1 /*
2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "gc_interface/collectedHeap.hpp"
36 #include "memory/barrierSet.hpp"
37 #include "memory/cardTableModRefBS.hpp"
38 #include "nativeInst_x86.hpp"
39 #include "oops/objArrayKlass.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "vmreg_x86.inline.hpp"
42
43
44 // These masks are used to provide 128-bit aligned bitmasks to the XMM
45 // instructions, to allow sign-masking or sign-bit flipping. They allow
46 // fast versions of NegF/NegD and AbsF/AbsD.
47
48 // Note: 'double' and 'long long' have 32-bits alignment on x86.
49 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
50 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
51 // of 128-bits operands for SSE instructions.
52 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
53 // Store the value to a 128-bits operand.
54 operand[0] = lo;
55 operand[1] = hi;
56 return operand;
57 }
58
59 // Buffer for 128-bits masks used by SSE instructions.
60 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
61
62 // Static initialization during VM startup.
63 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
64 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
65 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
66 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
67
68
69
70 NEEDS_CLEANUP // remove this definitions ?
71 const Register IC_Klass = rax; // where the IC klass is cached
72 const Register SYNC_header = rax; // synchronization header
73 const Register SHIFT_count = rcx; // where count for shift operations must be
74
75 #define __ _masm->
76
77
78 static void select_different_registers(Register preserve,
79 Register extra,
80 Register &tmp1,
81 Register &tmp2) {
82 if (tmp1 == preserve) {
83 assert_different_registers(tmp1, tmp2, extra);
84 tmp1 = extra;
85 } else if (tmp2 == preserve) {
86 assert_different_registers(tmp1, tmp2, extra);
87 tmp2 = extra;
88 }
89 assert_different_registers(preserve, tmp1, tmp2);
90 }
91
92
93
94 static void select_different_registers(Register preserve,
95 Register extra,
96 Register &tmp1,
97 Register &tmp2,
98 Register &tmp3) {
99 if (tmp1 == preserve) {
100 assert_different_registers(tmp1, tmp2, tmp3, extra);
101 tmp1 = extra;
102 } else if (tmp2 == preserve) {
103 assert_different_registers(tmp1, tmp2, tmp3, extra);
104 tmp2 = extra;
105 } else if (tmp3 == preserve) {
106 assert_different_registers(tmp1, tmp2, tmp3, extra);
107 tmp3 = extra;
108 }
109 assert_different_registers(preserve, tmp1, tmp2, tmp3);
110 }
111
112
113
114 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
115 if (opr->is_constant()) {
116 LIR_Const* constant = opr->as_constant_ptr();
117 switch (constant->type()) {
118 case T_INT: {
119 return true;
120 }
121
122 default:
123 return false;
124 }
125 }
126 return false;
127 }
128
129
130 LIR_Opr LIR_Assembler::receiverOpr() {
131 return FrameMap::receiver_opr;
132 }
133
134 LIR_Opr LIR_Assembler::osrBufferPointer() {
135 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
136 }
137
138 //--------------fpu register translations-----------------------
139
140
141 address LIR_Assembler::float_constant(float f) {
142 address const_addr = __ float_constant(f);
143 if (const_addr == NULL) {
144 bailout("const section overflow");
145 return __ code()->consts()->start();
146 } else {
147 return const_addr;
148 }
149 }
150
151
152 address LIR_Assembler::double_constant(double d) {
153 address const_addr = __ double_constant(d);
154 if (const_addr == NULL) {
155 bailout("const section overflow");
156 return __ code()->consts()->start();
157 } else {
158 return const_addr;
159 }
160 }
161
162
163 void LIR_Assembler::set_24bit_FPU() {
164 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
165 }
166
167 void LIR_Assembler::reset_FPU() {
168 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
169 }
170
171 void LIR_Assembler::fpop() {
172 __ fpop();
173 }
174
175 void LIR_Assembler::fxch(int i) {
176 __ fxch(i);
177 }
178
179 void LIR_Assembler::fld(int i) {
180 __ fld_s(i);
181 }
182
183 void LIR_Assembler::ffree(int i) {
184 __ ffree(i);
185 }
186
187 void LIR_Assembler::breakpoint() {
188 __ int3();
189 }
190
191 void LIR_Assembler::push(LIR_Opr opr) {
192 if (opr->is_single_cpu()) {
193 __ push_reg(opr->as_register());
194 } else if (opr->is_double_cpu()) {
195 NOT_LP64(__ push_reg(opr->as_register_hi()));
196 __ push_reg(opr->as_register_lo());
197 } else if (opr->is_stack()) {
198 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
199 } else if (opr->is_constant()) {
200 LIR_Const* const_opr = opr->as_constant_ptr();
201 if (const_opr->type() == T_OBJECT) {
202 __ push_oop(const_opr->as_jobject());
203 } else if (const_opr->type() == T_INT) {
204 __ push_jint(const_opr->as_jint());
205 } else {
206 ShouldNotReachHere();
207 }
208
209 } else {
210 ShouldNotReachHere();
211 }
212 }
213
214 void LIR_Assembler::pop(LIR_Opr opr) {
215 if (opr->is_single_cpu()) {
216 __ pop_reg(opr->as_register());
217 } else {
218 ShouldNotReachHere();
219 }
220 }
221
222 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
223 return addr->base()->is_illegal() && addr->index()->is_illegal();
224 }
225
226 //-------------------------------------------
227
228 Address LIR_Assembler::as_Address(LIR_Address* addr) {
229 return as_Address(addr, rscratch1);
230 }
231
232 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
233 if (addr->base()->is_illegal()) {
234 assert(addr->index()->is_illegal(), "must be illegal too");
235 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
236 if (! __ reachable(laddr)) {
237 __ movptr(tmp, laddr.addr());
238 Address res(tmp, 0);
239 return res;
240 } else {
241 return __ as_Address(laddr);
242 }
243 }
244
245 Register base = addr->base()->as_pointer_register();
246
247 if (addr->index()->is_illegal()) {
248 return Address( base, addr->disp());
249 } else if (addr->index()->is_cpu_register()) {
250 Register index = addr->index()->as_pointer_register();
251 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
252 } else if (addr->index()->is_constant()) {
253 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
254 assert(Assembler::is_simm32(addr_offset), "must be");
255
256 return Address(base, addr_offset);
257 } else {
258 Unimplemented();
259 return Address();
260 }
261 }
262
263
264 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
265 Address base = as_Address(addr);
266 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
267 }
268
269
270 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
271 return as_Address(addr);
272 }
273
274
275 void LIR_Assembler::osr_entry() {
276 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
277 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
278 ValueStack* entry_state = osr_entry->state();
279 int number_of_locks = entry_state->locks_size();
280
281 // we jump here if osr happens with the interpreter
282 // state set up to continue at the beginning of the
283 // loop that triggered osr - in particular, we have
284 // the following registers setup:
285 //
286 // rcx: osr buffer
287 //
288
289 // build frame
290 ciMethod* m = compilation()->method();
291 __ build_frame(initial_frame_size_in_bytes());
292
293 // OSR buffer is
294 //
295 // locals[nlocals-1..0]
296 // monitors[0..number_of_locks]
297 //
298 // locals is a direct copy of the interpreter frame so in the osr buffer
299 // so first slot in the local array is the last local from the interpreter
300 // and last slot is local[0] (receiver) from the interpreter
301 //
302 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
303 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
304 // in the interpreter frame (the method lock if a sync method)
305
306 // Initialize monitors in the compiled activation.
307 // rcx: pointer to osr buffer
308 //
309 // All other registers are dead at this point and the locals will be
310 // copied into place by code emitted in the IR.
311
312 Register OSR_buf = osrBufferPointer()->as_pointer_register();
313 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
314 int monitor_offset = BytesPerWord * method()->max_locals() +
315 (2 * BytesPerWord) * (number_of_locks - 1);
316 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
317 // the OSR buffer using 2 word entries: first the lock and then
318 // the oop.
319 for (int i = 0; i < number_of_locks; i++) {
320 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
321 #ifdef ASSERT
322 // verify the interpreter's monitor has a non-null object
323 {
324 Label L;
325 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
326 __ jcc(Assembler::notZero, L);
327 __ stop("locked object is NULL");
328 __ bind(L);
329 }
330 #endif
331 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
332 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
333 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
334 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
335 }
336 }
337 }
338
339
340 // inline cache check; done before the frame is built.
341 int LIR_Assembler::check_icache() {
342 Register receiver = FrameMap::receiver_opr->as_register();
343 Register ic_klass = IC_Klass;
344 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
345 const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
346 if (!do_post_padding) {
347 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
348 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) {
349 __ nop();
350 }
351 }
352 int offset = __ offset();
353 __ inline_cache_check(receiver, IC_Klass);
354 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
355 if (do_post_padding) {
356 // force alignment after the cache check.
357 // It's been verified to be aligned if !VerifyOops
358 __ align(CodeEntryAlignment);
359 }
360 return offset;
361 }
362
363
364 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
365 jobject o = NULL;
366 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
367 __ movoop(reg, o);
368 patching_epilog(patch, lir_patch_normal, reg, info);
369 }
370
371 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
372 Metadata* o = NULL;
373 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
374 __ mov_metadata(reg, o);
375 patching_epilog(patch, lir_patch_normal, reg, info);
376 }
377
378 // This specifies the rsp decrement needed to build the frame
379 int LIR_Assembler::initial_frame_size_in_bytes() {
380 // if rounding, must let FrameMap know!
381
382 // The frame_map records size in slots (32bit word)
383
384 // subtract two words to account for return address and link
385 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
386 }
387
388
389 int LIR_Assembler::emit_exception_handler() {
390 // if the last instruction is a call (typically to do a throw which
391 // is coming at the end after block reordering) the return address
392 // must still point into the code area in order to avoid assertion
393 // failures when searching for the corresponding bci => add a nop
394 // (was bug 5/14/1999 - gri)
395 __ nop();
396
397 // generate code for exception handler
398 address handler_base = __ start_a_stub(exception_handler_size);
399 if (handler_base == NULL) {
400 // not enough space left for the handler
401 bailout("exception handler overflow");
402 return -1;
403 }
404
405 int offset = code_offset();
406
407 // the exception oop and pc are in rax, and rdx
408 // no other registers need to be preserved, so invalidate them
409 __ invalidate_registers(false, true, true, false, true, true);
410
411 // check that there is really an exception
412 __ verify_not_null_oop(rax);
413
414 // search an exception handler (rax: exception oop, rdx: throwing pc)
415 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
416 __ should_not_reach_here();
417 guarantee(code_offset() - offset <= exception_handler_size, "overflow");
418 __ end_a_stub();
419
420 return offset;
421 }
422
423
424 // Emit the code to remove the frame from the stack in the exception
425 // unwind path.
426 int LIR_Assembler::emit_unwind_handler() {
427 #ifndef PRODUCT
428 if (CommentedAssembly) {
429 _masm->block_comment("Unwind handler");
430 }
431 #endif
432
433 int offset = code_offset();
434
435 // Fetch the exception from TLS and clear out exception related thread state
436 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
437 NOT_LP64(__ get_thread(rsi));
438 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
439 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
440 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
441
442 __ bind(_unwind_handler_entry);
443 __ verify_not_null_oop(rax);
444 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
445 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
446 }
447
448 // Preform needed unlocking
449 MonitorExitStub* stub = NULL;
450 if (method()->is_synchronized()) {
451 monitor_address(0, FrameMap::rax_opr);
452 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
453 __ unlock_object(rdi, rsi, rax, *stub->entry());
454 __ bind(*stub->continuation());
455 }
456
457 if (compilation()->env()->dtrace_method_probes()) {
458 #ifdef _LP64
459 __ mov(rdi, r15_thread);
460 __ mov_metadata(rsi, method()->constant_encoding());
461 #else
462 __ get_thread(rax);
463 __ movptr(Address(rsp, 0), rax);
464 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
465 #endif
466 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
467 }
468
469 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
470 __ mov(rax, rbx); // Restore the exception
471 }
472
473 // remove the activation and dispatch to the unwind handler
474 __ remove_frame(initial_frame_size_in_bytes());
475 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
476
477 // Emit the slow path assembly
478 if (stub != NULL) {
479 stub->emit_code(this);
480 }
481
482 return offset;
483 }
484
485
486 int LIR_Assembler::emit_deopt_handler() {
487 // if the last instruction is a call (typically to do a throw which
488 // is coming at the end after block reordering) the return address
489 // must still point into the code area in order to avoid assertion
490 // failures when searching for the corresponding bci => add a nop
491 // (was bug 5/14/1999 - gri)
492 __ nop();
493
494 // generate code for exception handler
495 address handler_base = __ start_a_stub(deopt_handler_size);
496 if (handler_base == NULL) {
497 // not enough space left for the handler
498 bailout("deopt handler overflow");
499 return -1;
500 }
501
502 int offset = code_offset();
503 InternalAddress here(__ pc());
504
505 __ pushptr(here.addr());
506 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
507 guarantee(code_offset() - offset <= deopt_handler_size, "overflow");
508 __ end_a_stub();
509
510 return offset;
511 }
512
513
514 // This is the fast version of java.lang.String.compare; it has not
515 // OSR-entry and therefore, we generate a slow version for OSR's
516 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) {
517 __ movptr (rbx, rcx); // receiver is in rcx
518 __ movptr (rax, arg1->as_register());
519
520 // Get addresses of first characters from both Strings
521 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes()));
522 if (java_lang_String::has_offset_field()) {
523 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes()));
524 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes()));
525 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
526 } else {
527 __ movl (rax, Address(rsi, arrayOopDesc::length_offset_in_bytes()));
528 __ lea (rsi, Address(rsi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
529 }
530
531 // rbx, may be NULL
532 add_debug_info_for_null_check_here(info);
533 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes()));
534 if (java_lang_String::has_offset_field()) {
535 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes()));
536 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes()));
537 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
538 } else {
539 __ movl (rbx, Address(rdi, arrayOopDesc::length_offset_in_bytes()));
540 __ lea (rdi, Address(rdi, arrayOopDesc::base_offset_in_bytes(T_CHAR)));
541 }
542
543 // compute minimum length (in rax) and difference of lengths (on top of stack)
544 __ mov (rcx, rbx);
545 __ subptr(rbx, rax); // subtract lengths
546 __ push (rbx); // result
547 __ cmov (Assembler::lessEqual, rax, rcx);
548
549 // is minimum length 0?
550 Label noLoop, haveResult;
551 __ testptr (rax, rax);
552 __ jcc (Assembler::zero, noLoop);
553
554 // compare first characters
555 __ load_unsigned_short(rcx, Address(rdi, 0));
556 __ load_unsigned_short(rbx, Address(rsi, 0));
557 __ subl(rcx, rbx);
558 __ jcc(Assembler::notZero, haveResult);
559 // starting loop
560 __ decrement(rax); // we already tested index: skip one
561 __ jcc(Assembler::zero, noLoop);
562
563 // set rsi.edi to the end of the arrays (arrays have same length)
564 // negate the index
565
566 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR)));
567 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR)));
568 __ negptr(rax);
569
570 // compare the strings in a loop
571
572 Label loop;
573 __ align(wordSize);
574 __ bind(loop);
575 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0));
576 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0));
577 __ subl(rcx, rbx);
578 __ jcc(Assembler::notZero, haveResult);
579 __ increment(rax);
580 __ jcc(Assembler::notZero, loop);
581
582 // strings are equal up to min length
583
584 __ bind(noLoop);
585 __ pop(rax);
586 return_op(LIR_OprFact::illegalOpr);
587
588 __ bind(haveResult);
589 // leave instruction is going to discard the TOS value
590 __ mov (rax, rcx); // result of call is in rax,
591 }
592
593
594 void LIR_Assembler::return_op(LIR_Opr result) {
595 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
596 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
597 assert(result->fpu() == 0, "result must already be on TOS");
598 }
599
600 // Pop the stack before the safepoint code
601 __ remove_frame(initial_frame_size_in_bytes());
602
603 bool result_is_oop = result->is_valid() ? result->is_oop() : false;
604
605 // Note: we do not need to round double result; float result has the right precision
606 // the poll sets the condition code, but no data registers
607 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
608
609 if (Assembler::is_polling_page_far()) {
610 __ lea(rscratch1, polling_page);
611 __ relocate(relocInfo::poll_return_type);
612 __ testl(rax, Address(rscratch1, 0));
613 } else {
614 __ testl(rax, polling_page);
615 }
616 __ ret(0);
617 }
618
619
620 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
621 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
622 guarantee(info != NULL, "Shouldn't be NULL");
623 int offset = __ offset();
624 if (Assembler::is_polling_page_far()) {
625 __ lea(rscratch1, polling_page);
626 offset = __ offset();
627 add_debug_info_for_branch(info);
628 __ testl(rax, Address(rscratch1, 0));
629 } else {
630 add_debug_info_for_branch(info);
631 __ testl(rax, polling_page);
632 }
633 return offset;
634 }
635
636
637 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
638 if (from_reg != to_reg) __ mov(to_reg, from_reg);
639 }
640
641 void LIR_Assembler::swap_reg(Register a, Register b) {
642 __ xchgptr(a, b);
643 }
644
645
646 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
647 assert(src->is_constant(), "should not call otherwise");
648 assert(dest->is_register(), "should not call otherwise");
649 LIR_Const* c = src->as_constant_ptr();
650
651 switch (c->type()) {
652 case T_INT: {
653 assert(patch_code == lir_patch_none, "no patching handled here");
654 __ movl(dest->as_register(), c->as_jint());
655 break;
656 }
657
658 case T_ADDRESS: {
659 assert(patch_code == lir_patch_none, "no patching handled here");
660 __ movptr(dest->as_register(), c->as_jint());
661 break;
662 }
663
664 case T_LONG: {
665 assert(patch_code == lir_patch_none, "no patching handled here");
666 #ifdef _LP64
667 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
668 #else
669 __ movptr(dest->as_register_lo(), c->as_jint_lo());
670 __ movptr(dest->as_register_hi(), c->as_jint_hi());
671 #endif // _LP64
672 break;
673 }
674
675 case T_OBJECT: {
676 if (patch_code != lir_patch_none) {
677 jobject2reg_with_patching(dest->as_register(), info);
678 } else {
679 __ movoop(dest->as_register(), c->as_jobject());
680 }
681 break;
682 }
683
684 case T_METADATA: {
685 if (patch_code != lir_patch_none) {
686 klass2reg_with_patching(dest->as_register(), info);
687 } else {
688 __ mov_metadata(dest->as_register(), c->as_metadata());
689 }
690 break;
691 }
692
693 case T_FLOAT: {
694 if (dest->is_single_xmm()) {
695 if (c->is_zero_float()) {
696 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
697 } else {
698 __ movflt(dest->as_xmm_float_reg(),
699 InternalAddress(float_constant(c->as_jfloat())));
700 }
701 } else {
702 assert(dest->is_single_fpu(), "must be");
703 assert(dest->fpu_regnr() == 0, "dest must be TOS");
704 if (c->is_zero_float()) {
705 __ fldz();
706 } else if (c->is_one_float()) {
707 __ fld1();
708 } else {
709 __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
710 }
711 }
712 break;
713 }
714
715 case T_DOUBLE: {
716 if (dest->is_double_xmm()) {
717 if (c->is_zero_double()) {
718 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
719 } else {
720 __ movdbl(dest->as_xmm_double_reg(),
721 InternalAddress(double_constant(c->as_jdouble())));
722 }
723 } else {
724 assert(dest->is_double_fpu(), "must be");
725 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
726 if (c->is_zero_double()) {
727 __ fldz();
728 } else if (c->is_one_double()) {
729 __ fld1();
730 } else {
731 __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
732 }
733 }
734 break;
735 }
736
737 default:
738 ShouldNotReachHere();
739 }
740 }
741
742 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
743 assert(src->is_constant(), "should not call otherwise");
744 assert(dest->is_stack(), "should not call otherwise");
745 LIR_Const* c = src->as_constant_ptr();
746
747 switch (c->type()) {
748 case T_INT: // fall through
749 case T_FLOAT:
750 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
751 break;
752
753 case T_ADDRESS:
754 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
755 break;
756
757 case T_OBJECT:
758 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
759 break;
760
761 case T_LONG: // fall through
762 case T_DOUBLE:
763 #ifdef _LP64
764 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
765 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
766 #else
767 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
768 lo_word_offset_in_bytes), c->as_jint_lo_bits());
769 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
770 hi_word_offset_in_bytes), c->as_jint_hi_bits());
771 #endif // _LP64
772 break;
773
774 default:
775 ShouldNotReachHere();
776 }
777 }
778
779 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
780 assert(src->is_constant(), "should not call otherwise");
781 assert(dest->is_address(), "should not call otherwise");
782 LIR_Const* c = src->as_constant_ptr();
783 LIR_Address* addr = dest->as_address_ptr();
784
785 int null_check_here = code_offset();
786 switch (type) {
787 case T_INT: // fall through
788 case T_FLOAT:
789 __ movl(as_Address(addr), c->as_jint_bits());
790 break;
791
792 case T_ADDRESS:
793 __ movptr(as_Address(addr), c->as_jint_bits());
794 break;
795
796 case T_OBJECT: // fall through
797 case T_ARRAY:
798 if (c->as_jobject() == NULL) {
799 if (UseCompressedOops && !wide) {
800 __ movl(as_Address(addr), (int32_t)NULL_WORD);
801 } else {
802 __ movptr(as_Address(addr), NULL_WORD);
803 }
804 } else {
805 if (is_literal_address(addr)) {
806 ShouldNotReachHere();
807 __ movoop(as_Address(addr, noreg), c->as_jobject());
808 } else {
809 #ifdef _LP64
810 __ movoop(rscratch1, c->as_jobject());
811 if (UseCompressedOops && !wide) {
812 __ encode_heap_oop(rscratch1);
813 null_check_here = code_offset();
814 __ movl(as_Address_lo(addr), rscratch1);
815 } else {
816 null_check_here = code_offset();
817 __ movptr(as_Address_lo(addr), rscratch1);
818 }
819 #else
820 __ movoop(as_Address(addr), c->as_jobject());
821 #endif
822 }
823 }
824 break;
825
826 case T_LONG: // fall through
827 case T_DOUBLE:
828 #ifdef _LP64
829 if (is_literal_address(addr)) {
830 ShouldNotReachHere();
831 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
832 } else {
833 __ movptr(r10, (intptr_t)c->as_jlong_bits());
834 null_check_here = code_offset();
835 __ movptr(as_Address_lo(addr), r10);
836 }
837 #else
838 // Always reachable in 32bit so this doesn't produce useless move literal
839 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
840 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
841 #endif // _LP64
842 break;
843
844 case T_BOOLEAN: // fall through
845 case T_BYTE:
846 __ movb(as_Address(addr), c->as_jint() & 0xFF);
847 break;
848
849 case T_CHAR: // fall through
850 case T_SHORT:
851 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
852 break;
853
854 default:
855 ShouldNotReachHere();
856 };
857
858 if (info != NULL) {
859 add_debug_info_for_null_check(null_check_here, info);
860 }
861 }
862
863
864 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
865 assert(src->is_register(), "should not call otherwise");
866 assert(dest->is_register(), "should not call otherwise");
867
868 // move between cpu-registers
869 if (dest->is_single_cpu()) {
870 #ifdef _LP64
871 if (src->type() == T_LONG) {
872 // Can do LONG -> OBJECT
873 move_regs(src->as_register_lo(), dest->as_register());
874 return;
875 }
876 #endif
877 assert(src->is_single_cpu(), "must match");
878 if (src->type() == T_OBJECT) {
879 __ verify_oop(src->as_register());
880 }
881 move_regs(src->as_register(), dest->as_register());
882
883 } else if (dest->is_double_cpu()) {
884 #ifdef _LP64
885 if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
886 // Surprising to me but we can see move of a long to t_object
887 __ verify_oop(src->as_register());
888 move_regs(src->as_register(), dest->as_register_lo());
889 return;
890 }
891 #endif
892 assert(src->is_double_cpu(), "must match");
893 Register f_lo = src->as_register_lo();
894 Register f_hi = src->as_register_hi();
895 Register t_lo = dest->as_register_lo();
896 Register t_hi = dest->as_register_hi();
897 #ifdef _LP64
898 assert(f_hi == f_lo, "must be same");
899 assert(t_hi == t_lo, "must be same");
900 move_regs(f_lo, t_lo);
901 #else
902 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
903
904
905 if (f_lo == t_hi && f_hi == t_lo) {
906 swap_reg(f_lo, f_hi);
907 } else if (f_hi == t_lo) {
908 assert(f_lo != t_hi, "overwriting register");
909 move_regs(f_hi, t_hi);
910 move_regs(f_lo, t_lo);
911 } else {
912 assert(f_hi != t_lo, "overwriting register");
913 move_regs(f_lo, t_lo);
914 move_regs(f_hi, t_hi);
915 }
916 #endif // LP64
917
918 // special moves from fpu-register to xmm-register
919 // necessary for method results
920 } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
921 __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
922 __ fld_s(Address(rsp, 0));
923 } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
924 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
925 __ fld_d(Address(rsp, 0));
926 } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
927 __ fstp_s(Address(rsp, 0));
928 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
929 } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
930 __ fstp_d(Address(rsp, 0));
931 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
932
933 // move between xmm-registers
934 } else if (dest->is_single_xmm()) {
935 assert(src->is_single_xmm(), "must match");
936 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
937 } else if (dest->is_double_xmm()) {
938 assert(src->is_double_xmm(), "must match");
939 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
940
941 // move between fpu-registers (no instruction necessary because of fpu-stack)
942 } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
943 assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
944 assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
945 } else {
946 ShouldNotReachHere();
947 }
948 }
949
950 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
951 assert(src->is_register(), "should not call otherwise");
952 assert(dest->is_stack(), "should not call otherwise");
953
954 if (src->is_single_cpu()) {
955 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
956 if (type == T_OBJECT || type == T_ARRAY) {
957 __ verify_oop(src->as_register());
958 __ movptr (dst, src->as_register());
959 } else if (type == T_METADATA) {
960 __ movptr (dst, src->as_register());
961 } else {
962 __ movl (dst, src->as_register());
963 }
964
965 } else if (src->is_double_cpu()) {
966 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
967 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
968 __ movptr (dstLO, src->as_register_lo());
969 NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
970
971 } else if (src->is_single_xmm()) {
972 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
973 __ movflt(dst_addr, src->as_xmm_float_reg());
974
975 } else if (src->is_double_xmm()) {
976 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
977 __ movdbl(dst_addr, src->as_xmm_double_reg());
978
979 } else if (src->is_single_fpu()) {
980 assert(src->fpu_regnr() == 0, "argument must be on TOS");
981 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
982 if (pop_fpu_stack) __ fstp_s (dst_addr);
983 else __ fst_s (dst_addr);
984
985 } else if (src->is_double_fpu()) {
986 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
987 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
988 if (pop_fpu_stack) __ fstp_d (dst_addr);
989 else __ fst_d (dst_addr);
990
991 } else {
992 ShouldNotReachHere();
993 }
994 }
995
996
997 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
998 LIR_Address* to_addr = dest->as_address_ptr();
999 PatchingStub* patch = NULL;
1000 Register compressed_src = rscratch1;
1001
1002 if (type == T_ARRAY || type == T_OBJECT) {
1003 __ verify_oop(src->as_register());
1004 #ifdef _LP64
1005 if (UseCompressedOops && !wide) {
1006 __ movptr(compressed_src, src->as_register());
1007 __ encode_heap_oop(compressed_src);
1008 if (patch_code != lir_patch_none) {
1009 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
1010 }
1011 }
1012 #endif
1013 }
1014
1015 if (patch_code != lir_patch_none) {
1016 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1017 Address toa = as_Address(to_addr);
1018 assert(toa.disp() != 0, "must have");
1019 }
1020
1021 int null_check_here = code_offset();
1022 switch (type) {
1023 case T_FLOAT: {
1024 if (src->is_single_xmm()) {
1025 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1026 } else {
1027 assert(src->is_single_fpu(), "must be");
1028 assert(src->fpu_regnr() == 0, "argument must be on TOS");
1029 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr));
1030 else __ fst_s (as_Address(to_addr));
1031 }
1032 break;
1033 }
1034
1035 case T_DOUBLE: {
1036 if (src->is_double_xmm()) {
1037 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1038 } else {
1039 assert(src->is_double_fpu(), "must be");
1040 assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1041 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr));
1042 else __ fst_d (as_Address(to_addr));
1043 }
1044 break;
1045 }
1046
1047 case T_ARRAY: // fall through
1048 case T_OBJECT: // fall through
1049 if (UseCompressedOops && !wide) {
1050 __ movl(as_Address(to_addr), compressed_src);
1051 } else {
1052 __ movptr(as_Address(to_addr), src->as_register());
1053 }
1054 break;
1055 case T_METADATA:
1056 // We get here to store a method pointer to the stack to pass to
1057 // a dtrace runtime call. This can't work on 64 bit with
1058 // compressed klass ptrs: T_METADATA can be a compressed klass
1059 // ptr or a 64 bit method pointer.
1060 LP64_ONLY(ShouldNotReachHere());
1061 __ movptr(as_Address(to_addr), src->as_register());
1062 break;
1063 case T_ADDRESS:
1064 __ movptr(as_Address(to_addr), src->as_register());
1065 break;
1066 case T_INT:
1067 __ movl(as_Address(to_addr), src->as_register());
1068 break;
1069
1070 case T_LONG: {
1071 Register from_lo = src->as_register_lo();
1072 Register from_hi = src->as_register_hi();
1073 #ifdef _LP64
1074 __ movptr(as_Address_lo(to_addr), from_lo);
1075 #else
1076 Register base = to_addr->base()->as_register();
1077 Register index = noreg;
1078 if (to_addr->index()->is_register()) {
1079 index = to_addr->index()->as_register();
1080 }
1081 if (base == from_lo || index == from_lo) {
1082 assert(base != from_hi, "can't be");
1083 assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1084 __ movl(as_Address_hi(to_addr), from_hi);
1085 if (patch != NULL) {
1086 patching_epilog(patch, lir_patch_high, base, info);
1087 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1088 patch_code = lir_patch_low;
1089 }
1090 __ movl(as_Address_lo(to_addr), from_lo);
1091 } else {
1092 assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1093 __ movl(as_Address_lo(to_addr), from_lo);
1094 if (patch != NULL) {
1095 patching_epilog(patch, lir_patch_low, base, info);
1096 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1097 patch_code = lir_patch_high;
1098 }
1099 __ movl(as_Address_hi(to_addr), from_hi);
1100 }
1101 #endif // _LP64
1102 break;
1103 }
1104
1105 case T_BYTE: // fall through
1106 case T_BOOLEAN: {
1107 Register src_reg = src->as_register();
1108 Address dst_addr = as_Address(to_addr);
1109 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1110 __ movb(dst_addr, src_reg);
1111 break;
1112 }
1113
1114 case T_CHAR: // fall through
1115 case T_SHORT:
1116 __ movw(as_Address(to_addr), src->as_register());
1117 break;
1118
1119 default:
1120 ShouldNotReachHere();
1121 }
1122 if (info != NULL) {
1123 add_debug_info_for_null_check(null_check_here, info);
1124 }
1125
1126 if (patch_code != lir_patch_none) {
1127 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1128 }
1129 }
1130
1131
1132 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1133 assert(src->is_stack(), "should not call otherwise");
1134 assert(dest->is_register(), "should not call otherwise");
1135
1136 if (dest->is_single_cpu()) {
1137 if (type == T_ARRAY || type == T_OBJECT) {
1138 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1139 __ verify_oop(dest->as_register());
1140 } else if (type == T_METADATA) {
1141 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1142 } else {
1143 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1144 }
1145
1146 } else if (dest->is_double_cpu()) {
1147 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1148 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1149 __ movptr(dest->as_register_lo(), src_addr_LO);
1150 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1151
1152 } else if (dest->is_single_xmm()) {
1153 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1154 __ movflt(dest->as_xmm_float_reg(), src_addr);
1155
1156 } else if (dest->is_double_xmm()) {
1157 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1158 __ movdbl(dest->as_xmm_double_reg(), src_addr);
1159
1160 } else if (dest->is_single_fpu()) {
1161 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1162 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1163 __ fld_s(src_addr);
1164
1165 } else if (dest->is_double_fpu()) {
1166 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1167 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1168 __ fld_d(src_addr);
1169
1170 } else {
1171 ShouldNotReachHere();
1172 }
1173 }
1174
1175
1176 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1177 if (src->is_single_stack()) {
1178 if (type == T_OBJECT || type == T_ARRAY) {
1179 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1180 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1181 } else {
1182 #ifndef _LP64
1183 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1184 __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1185 #else
1186 //no pushl on 64bits
1187 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1188 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1189 #endif
1190 }
1191
1192 } else if (src->is_double_stack()) {
1193 #ifdef _LP64
1194 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1195 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1196 #else
1197 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1198 // push and pop the part at src + wordSize, adding wordSize for the previous push
1199 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1200 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1201 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1202 #endif // _LP64
1203
1204 } else {
1205 ShouldNotReachHere();
1206 }
1207 }
1208
1209
1210 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1211 assert(src->is_address(), "should not call otherwise");
1212 assert(dest->is_register(), "should not call otherwise");
1213
1214 LIR_Address* addr = src->as_address_ptr();
1215 Address from_addr = as_Address(addr);
1216
1217 if (addr->base()->type() == T_OBJECT) {
1218 __ verify_oop(addr->base()->as_pointer_register());
1219 }
1220
1221 switch (type) {
1222 case T_BOOLEAN: // fall through
1223 case T_BYTE: // fall through
1224 case T_CHAR: // fall through
1225 case T_SHORT:
1226 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1227 // on pre P6 processors we may get partial register stalls
1228 // so blow away the value of to_rinfo before loading a
1229 // partial word into it. Do it here so that it precedes
1230 // the potential patch point below.
1231 __ xorptr(dest->as_register(), dest->as_register());
1232 }
1233 break;
1234 }
1235
1236 PatchingStub* patch = NULL;
1237 if (patch_code != lir_patch_none) {
1238 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1239 assert(from_addr.disp() != 0, "must have");
1240 }
1241 if (info != NULL) {
1242 add_debug_info_for_null_check_here(info);
1243 }
1244
1245 switch (type) {
1246 case T_FLOAT: {
1247 if (dest->is_single_xmm()) {
1248 __ movflt(dest->as_xmm_float_reg(), from_addr);
1249 } else {
1250 assert(dest->is_single_fpu(), "must be");
1251 assert(dest->fpu_regnr() == 0, "dest must be TOS");
1252 __ fld_s(from_addr);
1253 }
1254 break;
1255 }
1256
1257 case T_DOUBLE: {
1258 if (dest->is_double_xmm()) {
1259 __ movdbl(dest->as_xmm_double_reg(), from_addr);
1260 } else {
1261 assert(dest->is_double_fpu(), "must be");
1262 assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1263 __ fld_d(from_addr);
1264 }
1265 break;
1266 }
1267
1268 case T_OBJECT: // fall through
1269 case T_ARRAY: // fall through
1270 if (UseCompressedOops && !wide) {
1271 __ movl(dest->as_register(), from_addr);
1272 } else {
1273 __ movptr(dest->as_register(), from_addr);
1274 }
1275 break;
1276
1277 case T_ADDRESS:
1278 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1279 __ movl(dest->as_register(), from_addr);
1280 } else {
1281 __ movptr(dest->as_register(), from_addr);
1282 }
1283 break;
1284 case T_INT:
1285 __ movl(dest->as_register(), from_addr);
1286 break;
1287
1288 case T_LONG: {
1289 Register to_lo = dest->as_register_lo();
1290 Register to_hi = dest->as_register_hi();
1291 #ifdef _LP64
1292 __ movptr(to_lo, as_Address_lo(addr));
1293 #else
1294 Register base = addr->base()->as_register();
1295 Register index = noreg;
1296 if (addr->index()->is_register()) {
1297 index = addr->index()->as_register();
1298 }
1299 if ((base == to_lo && index == to_hi) ||
1300 (base == to_hi && index == to_lo)) {
1301 // addresses with 2 registers are only formed as a result of
1302 // array access so this code will never have to deal with
1303 // patches or null checks.
1304 assert(info == NULL && patch == NULL, "must be");
1305 __ lea(to_hi, as_Address(addr));
1306 __ movl(to_lo, Address(to_hi, 0));
1307 __ movl(to_hi, Address(to_hi, BytesPerWord));
1308 } else if (base == to_lo || index == to_lo) {
1309 assert(base != to_hi, "can't be");
1310 assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1311 __ movl(to_hi, as_Address_hi(addr));
1312 if (patch != NULL) {
1313 patching_epilog(patch, lir_patch_high, base, info);
1314 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1315 patch_code = lir_patch_low;
1316 }
1317 __ movl(to_lo, as_Address_lo(addr));
1318 } else {
1319 assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1320 __ movl(to_lo, as_Address_lo(addr));
1321 if (patch != NULL) {
1322 patching_epilog(patch, lir_patch_low, base, info);
1323 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1324 patch_code = lir_patch_high;
1325 }
1326 __ movl(to_hi, as_Address_hi(addr));
1327 }
1328 #endif // _LP64
1329 break;
1330 }
1331
1332 case T_BOOLEAN: // fall through
1333 case T_BYTE: {
1334 Register dest_reg = dest->as_register();
1335 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1336 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1337 __ movsbl(dest_reg, from_addr);
1338 } else {
1339 __ movb(dest_reg, from_addr);
1340 __ shll(dest_reg, 24);
1341 __ sarl(dest_reg, 24);
1342 }
1343 break;
1344 }
1345
1346 case T_CHAR: {
1347 Register dest_reg = dest->as_register();
1348 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1349 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1350 __ movzwl(dest_reg, from_addr);
1351 } else {
1352 __ movw(dest_reg, from_addr);
1353 }
1354 break;
1355 }
1356
1357 case T_SHORT: {
1358 Register dest_reg = dest->as_register();
1359 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1360 __ movswl(dest_reg, from_addr);
1361 } else {
1362 __ movw(dest_reg, from_addr);
1363 __ shll(dest_reg, 16);
1364 __ sarl(dest_reg, 16);
1365 }
1366 break;
1367 }
1368
1369 default:
1370 ShouldNotReachHere();
1371 }
1372
1373 if (patch != NULL) {
1374 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1375 }
1376
1377 if (type == T_ARRAY || type == T_OBJECT) {
1378 #ifdef _LP64
1379 if (UseCompressedOops && !wide) {
1380 __ decode_heap_oop(dest->as_register());
1381 }
1382 #endif
1383 __ verify_oop(dest->as_register());
1384 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1385 #ifdef _LP64
1386 if (UseCompressedClassPointers) {
1387 __ decode_klass_not_null(dest->as_register());
1388 }
1389 #endif
1390 }
1391 }
1392
1393
1394 void LIR_Assembler::prefetchr(LIR_Opr src) {
1395 LIR_Address* addr = src->as_address_ptr();
1396 Address from_addr = as_Address(addr);
1397
1398 if (VM_Version::supports_sse()) {
1399 switch (ReadPrefetchInstr) {
1400 case 0:
1401 __ prefetchnta(from_addr); break;
1402 case 1:
1403 __ prefetcht0(from_addr); break;
1404 case 2:
1405 __ prefetcht2(from_addr); break;
1406 default:
1407 ShouldNotReachHere(); break;
1408 }
1409 } else if (VM_Version::supports_3dnow_prefetch()) {
1410 __ prefetchr(from_addr);
1411 }
1412 }
1413
1414
1415 void LIR_Assembler::prefetchw(LIR_Opr src) {
1416 LIR_Address* addr = src->as_address_ptr();
1417 Address from_addr = as_Address(addr);
1418
1419 if (VM_Version::supports_sse()) {
1420 switch (AllocatePrefetchInstr) {
1421 case 0:
1422 __ prefetchnta(from_addr); break;
1423 case 1:
1424 __ prefetcht0(from_addr); break;
1425 case 2:
1426 __ prefetcht2(from_addr); break;
1427 case 3:
1428 __ prefetchw(from_addr); break;
1429 default:
1430 ShouldNotReachHere(); break;
1431 }
1432 } else if (VM_Version::supports_3dnow_prefetch()) {
1433 __ prefetchw(from_addr);
1434 }
1435 }
1436
1437
1438 NEEDS_CLEANUP; // This could be static?
1439 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1440 int elem_size = type2aelembytes(type);
1441 switch (elem_size) {
1442 case 1: return Address::times_1;
1443 case 2: return Address::times_2;
1444 case 4: return Address::times_4;
1445 case 8: return Address::times_8;
1446 }
1447 ShouldNotReachHere();
1448 return Address::no_scale;
1449 }
1450
1451
1452 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1453 switch (op->code()) {
1454 case lir_idiv:
1455 case lir_irem:
1456 arithmetic_idiv(op->code(),
1457 op->in_opr1(),
1458 op->in_opr2(),
1459 op->in_opr3(),
1460 op->result_opr(),
1461 op->info());
1462 break;
1463 default: ShouldNotReachHere(); break;
1464 }
1465 }
1466
1467 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1468 #ifdef ASSERT
1469 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1470 if (op->block() != NULL) _branch_target_blocks.append(op->block());
1471 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1472 #endif
1473
1474 if (op->cond() == lir_cond_always) {
1475 if (op->info() != NULL) add_debug_info_for_branch(op->info());
1476 __ jmp (*(op->label()));
1477 } else {
1478 Assembler::Condition acond = Assembler::zero;
1479 if (op->code() == lir_cond_float_branch) {
1480 assert(op->ublock() != NULL, "must have unordered successor");
1481 __ jcc(Assembler::parity, *(op->ublock()->label()));
1482 switch(op->cond()) {
1483 case lir_cond_equal: acond = Assembler::equal; break;
1484 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1485 case lir_cond_less: acond = Assembler::below; break;
1486 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1487 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1488 case lir_cond_greater: acond = Assembler::above; break;
1489 default: ShouldNotReachHere();
1490 }
1491 } else {
1492 switch (op->cond()) {
1493 case lir_cond_equal: acond = Assembler::equal; break;
1494 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1495 case lir_cond_less: acond = Assembler::less; break;
1496 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1497 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1498 case lir_cond_greater: acond = Assembler::greater; break;
1499 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1500 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1501 default: ShouldNotReachHere();
1502 }
1503 }
1504 __ jcc(acond,*(op->label()));
1505 }
1506 }
1507
1508 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1509 LIR_Opr src = op->in_opr();
1510 LIR_Opr dest = op->result_opr();
1511
1512 switch (op->bytecode()) {
1513 case Bytecodes::_i2l:
1514 #ifdef _LP64
1515 __ movl2ptr(dest->as_register_lo(), src->as_register());
1516 #else
1517 move_regs(src->as_register(), dest->as_register_lo());
1518 move_regs(src->as_register(), dest->as_register_hi());
1519 __ sarl(dest->as_register_hi(), 31);
1520 #endif // LP64
1521 break;
1522
1523 case Bytecodes::_l2i:
1524 #ifdef _LP64
1525 __ movl(dest->as_register(), src->as_register_lo());
1526 #else
1527 move_regs(src->as_register_lo(), dest->as_register());
1528 #endif
1529 break;
1530
1531 case Bytecodes::_i2b:
1532 move_regs(src->as_register(), dest->as_register());
1533 __ sign_extend_byte(dest->as_register());
1534 break;
1535
1536 case Bytecodes::_i2c:
1537 move_regs(src->as_register(), dest->as_register());
1538 __ andl(dest->as_register(), 0xFFFF);
1539 break;
1540
1541 case Bytecodes::_i2s:
1542 move_regs(src->as_register(), dest->as_register());
1543 __ sign_extend_short(dest->as_register());
1544 break;
1545
1546
1547 case Bytecodes::_f2d:
1548 case Bytecodes::_d2f:
1549 if (dest->is_single_xmm()) {
1550 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1551 } else if (dest->is_double_xmm()) {
1552 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1553 } else {
1554 assert(src->fpu() == dest->fpu(), "register must be equal");
1555 // do nothing (float result is rounded later through spilling)
1556 }
1557 break;
1558
1559 case Bytecodes::_i2f:
1560 case Bytecodes::_i2d:
1561 if (dest->is_single_xmm()) {
1562 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1563 } else if (dest->is_double_xmm()) {
1564 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1565 } else {
1566 assert(dest->fpu() == 0, "result must be on TOS");
1567 __ movl(Address(rsp, 0), src->as_register());
1568 __ fild_s(Address(rsp, 0));
1569 }
1570 break;
1571
1572 case Bytecodes::_f2i:
1573 case Bytecodes::_d2i:
1574 if (src->is_single_xmm()) {
1575 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1576 } else if (src->is_double_xmm()) {
1577 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1578 } else {
1579 assert(src->fpu() == 0, "input must be on TOS");
1580 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1581 __ fist_s(Address(rsp, 0));
1582 __ movl(dest->as_register(), Address(rsp, 0));
1583 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1584 }
1585
1586 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1587 assert(op->stub() != NULL, "stub required");
1588 __ cmpl(dest->as_register(), 0x80000000);
1589 __ jcc(Assembler::equal, *op->stub()->entry());
1590 __ bind(*op->stub()->continuation());
1591 break;
1592
1593 case Bytecodes::_l2f:
1594 case Bytecodes::_l2d:
1595 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1596 assert(dest->fpu() == 0, "result must be on TOS");
1597
1598 __ movptr(Address(rsp, 0), src->as_register_lo());
1599 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1600 __ fild_d(Address(rsp, 0));
1601 // float result is rounded later through spilling
1602 break;
1603
1604 case Bytecodes::_f2l:
1605 case Bytecodes::_d2l:
1606 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1607 assert(src->fpu() == 0, "input must be on TOS");
1608 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1609
1610 // instruction sequence too long to inline it here
1611 {
1612 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1613 }
1614 break;
1615
1616 default: ShouldNotReachHere();
1617 }
1618 }
1619
1620 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1621 if (op->init_check()) {
1622 __ cmpb(Address(op->klass()->as_register(),
1623 InstanceKlass::init_state_offset()),
1624 InstanceKlass::fully_initialized);
1625 add_debug_info_for_null_check_here(op->stub()->info());
1626 __ jcc(Assembler::notEqual, *op->stub()->entry());
1627 }
1628 __ allocate_object(op->obj()->as_register(),
1629 op->tmp1()->as_register(),
1630 op->tmp2()->as_register(),
1631 op->header_size(),
1632 op->object_size(),
1633 op->klass()->as_register(),
1634 *op->stub()->entry());
1635 __ bind(*op->stub()->continuation());
1636 }
1637
1638 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1639 Register len = op->len()->as_register();
1640 LP64_ONLY( __ movslq(len, len); )
1641
1642 if (UseSlowPath ||
1643 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1644 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1645 __ jmp(*op->stub()->entry());
1646 } else {
1647 Register tmp1 = op->tmp1()->as_register();
1648 Register tmp2 = op->tmp2()->as_register();
1649 Register tmp3 = op->tmp3()->as_register();
1650 if (len == tmp1) {
1651 tmp1 = tmp3;
1652 } else if (len == tmp2) {
1653 tmp2 = tmp3;
1654 } else if (len == tmp3) {
1655 // everything is ok
1656 } else {
1657 __ mov(tmp3, len);
1658 }
1659 __ allocate_array(op->obj()->as_register(),
1660 len,
1661 tmp1,
1662 tmp2,
1663 arrayOopDesc::header_size(op->type()),
1664 array_element_size(op->type()),
1665 op->klass()->as_register(),
1666 *op->stub()->entry());
1667 }
1668 __ bind(*op->stub()->continuation());
1669 }
1670
1671 void LIR_Assembler::type_profile_helper(Register mdo,
1672 ciMethodData *md, ciProfileData *data,
1673 Register recv, Label* update_done) {
1674 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1675 Label next_test;
1676 // See if the receiver is receiver[n].
1677 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1678 __ jccb(Assembler::notEqual, next_test);
1679 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1680 __ addptr(data_addr, DataLayout::counter_increment);
1681 __ jmp(*update_done);
1682 __ bind(next_test);
1683 }
1684
1685 // Didn't find receiver; find next empty slot and fill it in
1686 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1687 Label next_test;
1688 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1689 __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1690 __ jccb(Assembler::notEqual, next_test);
1691 __ movptr(recv_addr, recv);
1692 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1693 __ jmp(*update_done);
1694 __ bind(next_test);
1695 }
1696 }
1697
1698 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1699 // we always need a stub for the failure case.
1700 CodeStub* stub = op->stub();
1701 Register obj = op->object()->as_register();
1702 Register k_RInfo = op->tmp1()->as_register();
1703 Register klass_RInfo = op->tmp2()->as_register();
1704 Register dst = op->result_opr()->as_register();
1705 ciKlass* k = op->klass();
1706 Register Rtmp1 = noreg;
1707
1708 // check if it needs to be profiled
1709 ciMethodData* md;
1710 ciProfileData* data;
1711
1712 if (op->should_profile()) {
1713 ciMethod* method = op->profiled_method();
1714 assert(method != NULL, "Should have method");
1715 int bci = op->profiled_bci();
1716 md = method->method_data_or_null();
1717 assert(md != NULL, "Sanity");
1718 data = md->bci_to_data(bci);
1719 assert(data != NULL, "need data for type check");
1720 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1721 }
1722 Label profile_cast_success, profile_cast_failure;
1723 Label *success_target = op->should_profile() ? &profile_cast_success : success;
1724 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1725
1726 if (obj == k_RInfo) {
1727 k_RInfo = dst;
1728 } else if (obj == klass_RInfo) {
1729 klass_RInfo = dst;
1730 }
1731 if (k->is_loaded() && !UseCompressedClassPointers) {
1732 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1733 } else {
1734 Rtmp1 = op->tmp3()->as_register();
1735 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1736 }
1737
1738 assert_different_registers(obj, k_RInfo, klass_RInfo);
1739
1740 __ cmpptr(obj, (int32_t)NULL_WORD);
1741 if (op->should_profile()) {
1742 Label not_null;
1743 __ jccb(Assembler::notEqual, not_null);
1744 // Object is null; update MDO and exit
1745 Register mdo = klass_RInfo;
1746 __ mov_metadata(mdo, md->constant_encoding());
1747 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1748 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1749 __ orl(data_addr, header_bits);
1750 __ jmp(*obj_is_null);
1751 __ bind(not_null);
1752 } else {
1753 __ jcc(Assembler::equal, *obj_is_null);
1754 }
1755
1756 if (!k->is_loaded()) {
1757 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1758 } else {
1759 #ifdef _LP64
1760 __ mov_metadata(k_RInfo, k->constant_encoding());
1761 #endif // _LP64
1762 }
1763 __ verify_oop(obj);
1764
1765 if (op->fast_check()) {
1766 // get object class
1767 // not a safepoint as obj null check happens earlier
1768 #ifdef _LP64
1769 if (UseCompressedClassPointers) {
1770 __ load_klass(Rtmp1, obj);
1771 __ cmpptr(k_RInfo, Rtmp1);
1772 } else {
1773 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1774 }
1775 #else
1776 if (k->is_loaded()) {
1777 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1778 } else {
1779 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1780 }
1781 #endif
1782 __ jcc(Assembler::notEqual, *failure_target);
1783 // successful cast, fall through to profile or jump
1784 } else {
1785 // get object class
1786 // not a safepoint as obj null check happens earlier
1787 __ load_klass(klass_RInfo, obj);
1788 if (k->is_loaded()) {
1789 // See if we get an immediate positive hit
1790 #ifdef _LP64
1791 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1792 #else
1793 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1794 #endif // _LP64
1795 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1796 __ jcc(Assembler::notEqual, *failure_target);
1797 // successful cast, fall through to profile or jump
1798 } else {
1799 // See if we get an immediate positive hit
1800 __ jcc(Assembler::equal, *success_target);
1801 // check for self
1802 #ifdef _LP64
1803 __ cmpptr(klass_RInfo, k_RInfo);
1804 #else
1805 __ cmpklass(klass_RInfo, k->constant_encoding());
1806 #endif // _LP64
1807 __ jcc(Assembler::equal, *success_target);
1808
1809 __ push(klass_RInfo);
1810 #ifdef _LP64
1811 __ push(k_RInfo);
1812 #else
1813 __ pushklass(k->constant_encoding());
1814 #endif // _LP64
1815 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1816 __ pop(klass_RInfo);
1817 __ pop(klass_RInfo);
1818 // result is a boolean
1819 __ cmpl(klass_RInfo, 0);
1820 __ jcc(Assembler::equal, *failure_target);
1821 // successful cast, fall through to profile or jump
1822 }
1823 } else {
1824 // perform the fast part of the checking logic
1825 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1826 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1827 __ push(klass_RInfo);
1828 __ push(k_RInfo);
1829 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1830 __ pop(klass_RInfo);
1831 __ pop(k_RInfo);
1832 // result is a boolean
1833 __ cmpl(k_RInfo, 0);
1834 __ jcc(Assembler::equal, *failure_target);
1835 // successful cast, fall through to profile or jump
1836 }
1837 }
1838 if (op->should_profile()) {
1839 Register mdo = klass_RInfo, recv = k_RInfo;
1840 __ bind(profile_cast_success);
1841 __ mov_metadata(mdo, md->constant_encoding());
1842 __ load_klass(recv, obj);
1843 Label update_done;
1844 type_profile_helper(mdo, md, data, recv, success);
1845 __ jmp(*success);
1846
1847 __ bind(profile_cast_failure);
1848 __ mov_metadata(mdo, md->constant_encoding());
1849 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1850 __ subptr(counter_addr, DataLayout::counter_increment);
1851 __ jmp(*failure);
1852 }
1853 __ jmp(*success);
1854 }
1855
1856
1857 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1858 LIR_Code code = op->code();
1859 if (code == lir_store_check) {
1860 Register value = op->object()->as_register();
1861 Register array = op->array()->as_register();
1862 Register k_RInfo = op->tmp1()->as_register();
1863 Register klass_RInfo = op->tmp2()->as_register();
1864 Register Rtmp1 = op->tmp3()->as_register();
1865
1866 CodeStub* stub = op->stub();
1867
1868 // check if it needs to be profiled
1869 ciMethodData* md;
1870 ciProfileData* data;
1871
1872 if (op->should_profile()) {
1873 ciMethod* method = op->profiled_method();
1874 assert(method != NULL, "Should have method");
1875 int bci = op->profiled_bci();
1876 md = method->method_data_or_null();
1877 assert(md != NULL, "Sanity");
1878 data = md->bci_to_data(bci);
1879 assert(data != NULL, "need data for type check");
1880 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1881 }
1882 Label profile_cast_success, profile_cast_failure, done;
1883 Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1884 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1885
1886 __ cmpptr(value, (int32_t)NULL_WORD);
1887 if (op->should_profile()) {
1888 Label not_null;
1889 __ jccb(Assembler::notEqual, not_null);
1890 // Object is null; update MDO and exit
1891 Register mdo = klass_RInfo;
1892 __ mov_metadata(mdo, md->constant_encoding());
1893 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
1894 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
1895 __ orl(data_addr, header_bits);
1896 __ jmp(done);
1897 __ bind(not_null);
1898 } else {
1899 __ jcc(Assembler::equal, done);
1900 }
1901
1902 add_debug_info_for_null_check_here(op->info_for_exception());
1903 __ load_klass(k_RInfo, array);
1904 __ load_klass(klass_RInfo, value);
1905
1906 // get instance klass (it's already uncompressed)
1907 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1908 // perform the fast part of the checking logic
1909 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1910 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1911 __ push(klass_RInfo);
1912 __ push(k_RInfo);
1913 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1914 __ pop(klass_RInfo);
1915 __ pop(k_RInfo);
1916 // result is a boolean
1917 __ cmpl(k_RInfo, 0);
1918 __ jcc(Assembler::equal, *failure_target);
1919 // fall through to the success case
1920
1921 if (op->should_profile()) {
1922 Register mdo = klass_RInfo, recv = k_RInfo;
1923 __ bind(profile_cast_success);
1924 __ mov_metadata(mdo, md->constant_encoding());
1925 __ load_klass(recv, value);
1926 Label update_done;
1927 type_profile_helper(mdo, md, data, recv, &done);
1928 __ jmpb(done);
1929
1930 __ bind(profile_cast_failure);
1931 __ mov_metadata(mdo, md->constant_encoding());
1932 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1933 __ subptr(counter_addr, DataLayout::counter_increment);
1934 __ jmp(*stub->entry());
1935 }
1936
1937 __ bind(done);
1938 } else
1939 if (code == lir_checkcast) {
1940 Register obj = op->object()->as_register();
1941 Register dst = op->result_opr()->as_register();
1942 Label success;
1943 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1944 __ bind(success);
1945 if (dst != obj) {
1946 __ mov(dst, obj);
1947 }
1948 } else
1949 if (code == lir_instanceof) {
1950 Register obj = op->object()->as_register();
1951 Register dst = op->result_opr()->as_register();
1952 Label success, failure, done;
1953 emit_typecheck_helper(op, &success, &failure, &failure);
1954 __ bind(failure);
1955 __ xorptr(dst, dst);
1956 __ jmpb(done);
1957 __ bind(success);
1958 __ movptr(dst, 1);
1959 __ bind(done);
1960 } else {
1961 ShouldNotReachHere();
1962 }
1963
1964 }
1965
1966
1967 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1968 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1969 assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1970 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1971 assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1972 assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1973 Register addr = op->addr()->as_register();
1974 if (os::is_MP()) {
1975 __ lock();
1976 }
1977 NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1978
1979 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1980 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1981 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1982 Register newval = op->new_value()->as_register();
1983 Register cmpval = op->cmp_value()->as_register();
1984 assert(cmpval == rax, "wrong register");
1985 assert(newval != NULL, "new val must be register");
1986 assert(cmpval != newval, "cmp and new values must be in different registers");
1987 assert(cmpval != addr, "cmp and addr must be in different registers");
1988 assert(newval != addr, "new value and addr must be in different registers");
1989
1990 if ( op->code() == lir_cas_obj) {
1991 #ifdef _LP64
1992 if (UseCompressedOops) {
1993 __ encode_heap_oop(cmpval);
1994 __ mov(rscratch1, newval);
1995 __ encode_heap_oop(rscratch1);
1996 if (os::is_MP()) {
1997 __ lock();
1998 }
1999 // cmpval (rax) is implicitly used by this instruction
2000 __ cmpxchgl(rscratch1, Address(addr, 0));
2001 } else
2002 #endif
2003 {
2004 if (os::is_MP()) {
2005 __ lock();
2006 }
2007 __ cmpxchgptr(newval, Address(addr, 0));
2008 }
2009 } else {
2010 assert(op->code() == lir_cas_int, "lir_cas_int expected");
2011 if (os::is_MP()) {
2012 __ lock();
2013 }
2014 __ cmpxchgl(newval, Address(addr, 0));
2015 }
2016 #ifdef _LP64
2017 } else if (op->code() == lir_cas_long) {
2018 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
2019 Register newval = op->new_value()->as_register_lo();
2020 Register cmpval = op->cmp_value()->as_register_lo();
2021 assert(cmpval == rax, "wrong register");
2022 assert(newval != NULL, "new val must be register");
2023 assert(cmpval != newval, "cmp and new values must be in different registers");
2024 assert(cmpval != addr, "cmp and addr must be in different registers");
2025 assert(newval != addr, "new value and addr must be in different registers");
2026 if (os::is_MP()) {
2027 __ lock();
2028 }
2029 __ cmpxchgq(newval, Address(addr, 0));
2030 #endif // _LP64
2031 } else {
2032 Unimplemented();
2033 }
2034 }
2035
2036 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
2037 Assembler::Condition acond, ncond;
2038 switch (condition) {
2039 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
2040 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
2041 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
2042 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
2043 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
2044 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
2045 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
2046 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
2047 default: ShouldNotReachHere();
2048 }
2049
2050 if (opr1->is_cpu_register()) {
2051 reg2reg(opr1, result);
2052 } else if (opr1->is_stack()) {
2053 stack2reg(opr1, result, result->type());
2054 } else if (opr1->is_constant()) {
2055 const2reg(opr1, result, lir_patch_none, NULL);
2056 } else {
2057 ShouldNotReachHere();
2058 }
2059
2060 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2061 // optimized version that does not require a branch
2062 if (opr2->is_single_cpu()) {
2063 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2064 __ cmov(ncond, result->as_register(), opr2->as_register());
2065 } else if (opr2->is_double_cpu()) {
2066 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2067 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2068 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2069 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2070 } else if (opr2->is_single_stack()) {
2071 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2072 } else if (opr2->is_double_stack()) {
2073 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2074 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2075 } else {
2076 ShouldNotReachHere();
2077 }
2078
2079 } else {
2080 Label skip;
2081 __ jcc (acond, skip);
2082 if (opr2->is_cpu_register()) {
2083 reg2reg(opr2, result);
2084 } else if (opr2->is_stack()) {
2085 stack2reg(opr2, result, result->type());
2086 } else if (opr2->is_constant()) {
2087 const2reg(opr2, result, lir_patch_none, NULL);
2088 } else {
2089 ShouldNotReachHere();
2090 }
2091 __ bind(skip);
2092 }
2093 }
2094
2095
2096 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2097 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2098
2099 if (left->is_single_cpu()) {
2100 assert(left == dest, "left and dest must be equal");
2101 Register lreg = left->as_register();
2102
2103 if (right->is_single_cpu()) {
2104 // cpu register - cpu register
2105 Register rreg = right->as_register();
2106 switch (code) {
2107 case lir_add: __ addl (lreg, rreg); break;
2108 case lir_sub: __ subl (lreg, rreg); break;
2109 case lir_mul: __ imull(lreg, rreg); break;
2110 default: ShouldNotReachHere();
2111 }
2112
2113 } else if (right->is_stack()) {
2114 // cpu register - stack
2115 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2116 switch (code) {
2117 case lir_add: __ addl(lreg, raddr); break;
2118 case lir_sub: __ subl(lreg, raddr); break;
2119 default: ShouldNotReachHere();
2120 }
2121
2122 } else if (right->is_constant()) {
2123 // cpu register - constant
2124 jint c = right->as_constant_ptr()->as_jint();
2125 switch (code) {
2126 case lir_add: {
2127 __ incrementl(lreg, c);
2128 break;
2129 }
2130 case lir_sub: {
2131 __ decrementl(lreg, c);
2132 break;
2133 }
2134 default: ShouldNotReachHere();
2135 }
2136
2137 } else {
2138 ShouldNotReachHere();
2139 }
2140
2141 } else if (left->is_double_cpu()) {
2142 assert(left == dest, "left and dest must be equal");
2143 Register lreg_lo = left->as_register_lo();
2144 Register lreg_hi = left->as_register_hi();
2145
2146 if (right->is_double_cpu()) {
2147 // cpu register - cpu register
2148 Register rreg_lo = right->as_register_lo();
2149 Register rreg_hi = right->as_register_hi();
2150 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2151 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2152 switch (code) {
2153 case lir_add:
2154 __ addptr(lreg_lo, rreg_lo);
2155 NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2156 break;
2157 case lir_sub:
2158 __ subptr(lreg_lo, rreg_lo);
2159 NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2160 break;
2161 case lir_mul:
2162 #ifdef _LP64
2163 __ imulq(lreg_lo, rreg_lo);
2164 #else
2165 assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2166 __ imull(lreg_hi, rreg_lo);
2167 __ imull(rreg_hi, lreg_lo);
2168 __ addl (rreg_hi, lreg_hi);
2169 __ mull (rreg_lo);
2170 __ addl (lreg_hi, rreg_hi);
2171 #endif // _LP64
2172 break;
2173 default:
2174 ShouldNotReachHere();
2175 }
2176
2177 } else if (right->is_constant()) {
2178 // cpu register - constant
2179 #ifdef _LP64
2180 jlong c = right->as_constant_ptr()->as_jlong_bits();
2181 __ movptr(r10, (intptr_t) c);
2182 switch (code) {
2183 case lir_add:
2184 __ addptr(lreg_lo, r10);
2185 break;
2186 case lir_sub:
2187 __ subptr(lreg_lo, r10);
2188 break;
2189 default:
2190 ShouldNotReachHere();
2191 }
2192 #else
2193 jint c_lo = right->as_constant_ptr()->as_jint_lo();
2194 jint c_hi = right->as_constant_ptr()->as_jint_hi();
2195 switch (code) {
2196 case lir_add:
2197 __ addptr(lreg_lo, c_lo);
2198 __ adcl(lreg_hi, c_hi);
2199 break;
2200 case lir_sub:
2201 __ subptr(lreg_lo, c_lo);
2202 __ sbbl(lreg_hi, c_hi);
2203 break;
2204 default:
2205 ShouldNotReachHere();
2206 }
2207 #endif // _LP64
2208
2209 } else {
2210 ShouldNotReachHere();
2211 }
2212
2213 } else if (left->is_single_xmm()) {
2214 assert(left == dest, "left and dest must be equal");
2215 XMMRegister lreg = left->as_xmm_float_reg();
2216
2217 if (right->is_single_xmm()) {
2218 XMMRegister rreg = right->as_xmm_float_reg();
2219 switch (code) {
2220 case lir_add: __ addss(lreg, rreg); break;
2221 case lir_sub: __ subss(lreg, rreg); break;
2222 case lir_mul_strictfp: // fall through
2223 case lir_mul: __ mulss(lreg, rreg); break;
2224 case lir_div_strictfp: // fall through
2225 case lir_div: __ divss(lreg, rreg); break;
2226 default: ShouldNotReachHere();
2227 }
2228 } else {
2229 Address raddr;
2230 if (right->is_single_stack()) {
2231 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2232 } else if (right->is_constant()) {
2233 // hack for now
2234 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2235 } else {
2236 ShouldNotReachHere();
2237 }
2238 switch (code) {
2239 case lir_add: __ addss(lreg, raddr); break;
2240 case lir_sub: __ subss(lreg, raddr); break;
2241 case lir_mul_strictfp: // fall through
2242 case lir_mul: __ mulss(lreg, raddr); break;
2243 case lir_div_strictfp: // fall through
2244 case lir_div: __ divss(lreg, raddr); break;
2245 default: ShouldNotReachHere();
2246 }
2247 }
2248
2249 } else if (left->is_double_xmm()) {
2250 assert(left == dest, "left and dest must be equal");
2251
2252 XMMRegister lreg = left->as_xmm_double_reg();
2253 if (right->is_double_xmm()) {
2254 XMMRegister rreg = right->as_xmm_double_reg();
2255 switch (code) {
2256 case lir_add: __ addsd(lreg, rreg); break;
2257 case lir_sub: __ subsd(lreg, rreg); break;
2258 case lir_mul_strictfp: // fall through
2259 case lir_mul: __ mulsd(lreg, rreg); break;
2260 case lir_div_strictfp: // fall through
2261 case lir_div: __ divsd(lreg, rreg); break;
2262 default: ShouldNotReachHere();
2263 }
2264 } else {
2265 Address raddr;
2266 if (right->is_double_stack()) {
2267 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2268 } else if (right->is_constant()) {
2269 // hack for now
2270 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2271 } else {
2272 ShouldNotReachHere();
2273 }
2274 switch (code) {
2275 case lir_add: __ addsd(lreg, raddr); break;
2276 case lir_sub: __ subsd(lreg, raddr); break;
2277 case lir_mul_strictfp: // fall through
2278 case lir_mul: __ mulsd(lreg, raddr); break;
2279 case lir_div_strictfp: // fall through
2280 case lir_div: __ divsd(lreg, raddr); break;
2281 default: ShouldNotReachHere();
2282 }
2283 }
2284
2285 } else if (left->is_single_fpu()) {
2286 assert(dest->is_single_fpu(), "fpu stack allocation required");
2287
2288 if (right->is_single_fpu()) {
2289 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2290
2291 } else {
2292 assert(left->fpu_regnr() == 0, "left must be on TOS");
2293 assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2294
2295 Address raddr;
2296 if (right->is_single_stack()) {
2297 raddr = frame_map()->address_for_slot(right->single_stack_ix());
2298 } else if (right->is_constant()) {
2299 address const_addr = float_constant(right->as_jfloat());
2300 assert(const_addr != NULL, "incorrect float/double constant maintainance");
2301 // hack for now
2302 raddr = __ as_Address(InternalAddress(const_addr));
2303 } else {
2304 ShouldNotReachHere();
2305 }
2306
2307 switch (code) {
2308 case lir_add: __ fadd_s(raddr); break;
2309 case lir_sub: __ fsub_s(raddr); break;
2310 case lir_mul_strictfp: // fall through
2311 case lir_mul: __ fmul_s(raddr); break;
2312 case lir_div_strictfp: // fall through
2313 case lir_div: __ fdiv_s(raddr); break;
2314 default: ShouldNotReachHere();
2315 }
2316 }
2317
2318 } else if (left->is_double_fpu()) {
2319 assert(dest->is_double_fpu(), "fpu stack allocation required");
2320
2321 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2322 // Double values require special handling for strictfp mul/div on x86
2323 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2324 __ fmulp(left->fpu_regnrLo() + 1);
2325 }
2326
2327 if (right->is_double_fpu()) {
2328 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2329
2330 } else {
2331 assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2332 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2333
2334 Address raddr;
2335 if (right->is_double_stack()) {
2336 raddr = frame_map()->address_for_slot(right->double_stack_ix());
2337 } else if (right->is_constant()) {
2338 // hack for now
2339 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2340 } else {
2341 ShouldNotReachHere();
2342 }
2343
2344 switch (code) {
2345 case lir_add: __ fadd_d(raddr); break;
2346 case lir_sub: __ fsub_d(raddr); break;
2347 case lir_mul_strictfp: // fall through
2348 case lir_mul: __ fmul_d(raddr); break;
2349 case lir_div_strictfp: // fall through
2350 case lir_div: __ fdiv_d(raddr); break;
2351 default: ShouldNotReachHere();
2352 }
2353 }
2354
2355 if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2356 // Double values require special handling for strictfp mul/div on x86
2357 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2358 __ fmulp(dest->fpu_regnrLo() + 1);
2359 }
2360
2361 } else if (left->is_single_stack() || left->is_address()) {
2362 assert(left == dest, "left and dest must be equal");
2363
2364 Address laddr;
2365 if (left->is_single_stack()) {
2366 laddr = frame_map()->address_for_slot(left->single_stack_ix());
2367 } else if (left->is_address()) {
2368 laddr = as_Address(left->as_address_ptr());
2369 } else {
2370 ShouldNotReachHere();
2371 }
2372
2373 if (right->is_single_cpu()) {
2374 Register rreg = right->as_register();
2375 switch (code) {
2376 case lir_add: __ addl(laddr, rreg); break;
2377 case lir_sub: __ subl(laddr, rreg); break;
2378 default: ShouldNotReachHere();
2379 }
2380 } else if (right->is_constant()) {
2381 jint c = right->as_constant_ptr()->as_jint();
2382 switch (code) {
2383 case lir_add: {
2384 __ incrementl(laddr, c);
2385 break;
2386 }
2387 case lir_sub: {
2388 __ decrementl(laddr, c);
2389 break;
2390 }
2391 default: ShouldNotReachHere();
2392 }
2393 } else {
2394 ShouldNotReachHere();
2395 }
2396
2397 } else {
2398 ShouldNotReachHere();
2399 }
2400 }
2401
2402 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2403 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR");
2404 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2405 assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2406
2407 bool left_is_tos = (left_index == 0);
2408 bool dest_is_tos = (dest_index == 0);
2409 int non_tos_index = (left_is_tos ? right_index : left_index);
2410
2411 switch (code) {
2412 case lir_add:
2413 if (pop_fpu_stack) __ faddp(non_tos_index);
2414 else if (dest_is_tos) __ fadd (non_tos_index);
2415 else __ fadda(non_tos_index);
2416 break;
2417
2418 case lir_sub:
2419 if (left_is_tos) {
2420 if (pop_fpu_stack) __ fsubrp(non_tos_index);
2421 else if (dest_is_tos) __ fsub (non_tos_index);
2422 else __ fsubra(non_tos_index);
2423 } else {
2424 if (pop_fpu_stack) __ fsubp (non_tos_index);
2425 else if (dest_is_tos) __ fsubr (non_tos_index);
2426 else __ fsuba (non_tos_index);
2427 }
2428 break;
2429
2430 case lir_mul_strictfp: // fall through
2431 case lir_mul:
2432 if (pop_fpu_stack) __ fmulp(non_tos_index);
2433 else if (dest_is_tos) __ fmul (non_tos_index);
2434 else __ fmula(non_tos_index);
2435 break;
2436
2437 case lir_div_strictfp: // fall through
2438 case lir_div:
2439 if (left_is_tos) {
2440 if (pop_fpu_stack) __ fdivrp(non_tos_index);
2441 else if (dest_is_tos) __ fdiv (non_tos_index);
2442 else __ fdivra(non_tos_index);
2443 } else {
2444 if (pop_fpu_stack) __ fdivp (non_tos_index);
2445 else if (dest_is_tos) __ fdivr (non_tos_index);
2446 else __ fdiva (non_tos_index);
2447 }
2448 break;
2449
2450 case lir_rem:
2451 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2452 __ fremr(noreg);
2453 break;
2454
2455 default:
2456 ShouldNotReachHere();
2457 }
2458 }
2459
2460
2461 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
2462 if (value->is_double_xmm()) {
2463 switch(code) {
2464 case lir_abs :
2465 {
2466 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2467 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2468 }
2469 __ andpd(dest->as_xmm_double_reg(),
2470 ExternalAddress((address)double_signmask_pool));
2471 }
2472 break;
2473
2474 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2475 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2476 default : ShouldNotReachHere();
2477 }
2478
2479 } else if (value->is_double_fpu()) {
2480 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2481 switch(code) {
2482 case lir_log : __ flog() ; break;
2483 case lir_log10 : __ flog10() ; break;
2484 case lir_abs : __ fabs() ; break;
2485 case lir_sqrt : __ fsqrt(); break;
2486 case lir_sin :
2487 // Should consider not saving rbx, if not necessary
2488 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2489 break;
2490 case lir_cos :
2491 // Should consider not saving rbx, if not necessary
2492 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2493 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2494 break;
2495 case lir_tan :
2496 // Should consider not saving rbx, if not necessary
2497 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2498 break;
2499 case lir_exp :
2500 __ exp_with_fallback(op->as_Op2()->fpu_stack_size());
2501 break;
2502 case lir_pow :
2503 __ pow_with_fallback(op->as_Op2()->fpu_stack_size());
2504 break;
2505 default : ShouldNotReachHere();
2506 }
2507 } else {
2508 Unimplemented();
2509 }
2510 }
2511
2512 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2513 // assert(left->destroys_register(), "check");
2514 if (left->is_single_cpu()) {
2515 Register reg = left->as_register();
2516 if (right->is_constant()) {
2517 int val = right->as_constant_ptr()->as_jint();
2518 switch (code) {
2519 case lir_logic_and: __ andl (reg, val); break;
2520 case lir_logic_or: __ orl (reg, val); break;
2521 case lir_logic_xor: __ xorl (reg, val); break;
2522 default: ShouldNotReachHere();
2523 }
2524 } else if (right->is_stack()) {
2525 // added support for stack operands
2526 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2527 switch (code) {
2528 case lir_logic_and: __ andl (reg, raddr); break;
2529 case lir_logic_or: __ orl (reg, raddr); break;
2530 case lir_logic_xor: __ xorl (reg, raddr); break;
2531 default: ShouldNotReachHere();
2532 }
2533 } else {
2534 Register rright = right->as_register();
2535 switch (code) {
2536 case lir_logic_and: __ andptr (reg, rright); break;
2537 case lir_logic_or : __ orptr (reg, rright); break;
2538 case lir_logic_xor: __ xorptr (reg, rright); break;
2539 default: ShouldNotReachHere();
2540 }
2541 }
2542 move_regs(reg, dst->as_register());
2543 } else {
2544 Register l_lo = left->as_register_lo();
2545 Register l_hi = left->as_register_hi();
2546 if (right->is_constant()) {
2547 #ifdef _LP64
2548 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2549 switch (code) {
2550 case lir_logic_and:
2551 __ andq(l_lo, rscratch1);
2552 break;
2553 case lir_logic_or:
2554 __ orq(l_lo, rscratch1);
2555 break;
2556 case lir_logic_xor:
2557 __ xorq(l_lo, rscratch1);
2558 break;
2559 default: ShouldNotReachHere();
2560 }
2561 #else
2562 int r_lo = right->as_constant_ptr()->as_jint_lo();
2563 int r_hi = right->as_constant_ptr()->as_jint_hi();
2564 switch (code) {
2565 case lir_logic_and:
2566 __ andl(l_lo, r_lo);
2567 __ andl(l_hi, r_hi);
2568 break;
2569 case lir_logic_or:
2570 __ orl(l_lo, r_lo);
2571 __ orl(l_hi, r_hi);
2572 break;
2573 case lir_logic_xor:
2574 __ xorl(l_lo, r_lo);
2575 __ xorl(l_hi, r_hi);
2576 break;
2577 default: ShouldNotReachHere();
2578 }
2579 #endif // _LP64
2580 } else {
2581 #ifdef _LP64
2582 Register r_lo;
2583 if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2584 r_lo = right->as_register();
2585 } else {
2586 r_lo = right->as_register_lo();
2587 }
2588 #else
2589 Register r_lo = right->as_register_lo();
2590 Register r_hi = right->as_register_hi();
2591 assert(l_lo != r_hi, "overwriting registers");
2592 #endif
2593 switch (code) {
2594 case lir_logic_and:
2595 __ andptr(l_lo, r_lo);
2596 NOT_LP64(__ andptr(l_hi, r_hi);)
2597 break;
2598 case lir_logic_or:
2599 __ orptr(l_lo, r_lo);
2600 NOT_LP64(__ orptr(l_hi, r_hi);)
2601 break;
2602 case lir_logic_xor:
2603 __ xorptr(l_lo, r_lo);
2604 NOT_LP64(__ xorptr(l_hi, r_hi);)
2605 break;
2606 default: ShouldNotReachHere();
2607 }
2608 }
2609
2610 Register dst_lo = dst->as_register_lo();
2611 Register dst_hi = dst->as_register_hi();
2612
2613 #ifdef _LP64
2614 move_regs(l_lo, dst_lo);
2615 #else
2616 if (dst_lo == l_hi) {
2617 assert(dst_hi != l_lo, "overwriting registers");
2618 move_regs(l_hi, dst_hi);
2619 move_regs(l_lo, dst_lo);
2620 } else {
2621 assert(dst_lo != l_hi, "overwriting registers");
2622 move_regs(l_lo, dst_lo);
2623 move_regs(l_hi, dst_hi);
2624 }
2625 #endif // _LP64
2626 }
2627 }
2628
2629
2630 // we assume that rax, and rdx can be overwritten
2631 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2632
2633 assert(left->is_single_cpu(), "left must be register");
2634 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
2635 assert(result->is_single_cpu(), "result must be register");
2636
2637 // assert(left->destroys_register(), "check");
2638 // assert(right->destroys_register(), "check");
2639
2640 Register lreg = left->as_register();
2641 Register dreg = result->as_register();
2642
2643 if (right->is_constant()) {
2644 int divisor = right->as_constant_ptr()->as_jint();
2645 assert(divisor > 0 && is_power_of_2(divisor), "must be");
2646 if (code == lir_idiv) {
2647 assert(lreg == rax, "must be rax,");
2648 assert(temp->as_register() == rdx, "tmp register must be rdx");
2649 __ cdql(); // sign extend into rdx:rax
2650 if (divisor == 2) {
2651 __ subl(lreg, rdx);
2652 } else {
2653 __ andl(rdx, divisor - 1);
2654 __ addl(lreg, rdx);
2655 }
2656 __ sarl(lreg, log2_intptr(divisor));
2657 move_regs(lreg, dreg);
2658 } else if (code == lir_irem) {
2659 Label done;
2660 __ mov(dreg, lreg);
2661 __ andl(dreg, 0x80000000 | (divisor - 1));
2662 __ jcc(Assembler::positive, done);
2663 __ decrement(dreg);
2664 __ orl(dreg, ~(divisor - 1));
2665 __ increment(dreg);
2666 __ bind(done);
2667 } else {
2668 ShouldNotReachHere();
2669 }
2670 } else {
2671 Register rreg = right->as_register();
2672 assert(lreg == rax, "left register must be rax,");
2673 assert(rreg != rdx, "right register must not be rdx");
2674 assert(temp->as_register() == rdx, "tmp register must be rdx");
2675
2676 move_regs(lreg, rax);
2677
2678 int idivl_offset = __ corrected_idivl(rreg);
2679 add_debug_info_for_div0(idivl_offset, info);
2680 if (code == lir_irem) {
2681 move_regs(rdx, dreg); // result is in rdx
2682 } else {
2683 move_regs(rax, dreg);
2684 }
2685 }
2686 }
2687
2688
2689 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2690 if (opr1->is_single_cpu()) {
2691 Register reg1 = opr1->as_register();
2692 if (opr2->is_single_cpu()) {
2693 // cpu register - cpu register
2694 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2695 __ cmpptr(reg1, opr2->as_register());
2696 } else {
2697 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2698 __ cmpl(reg1, opr2->as_register());
2699 }
2700 } else if (opr2->is_stack()) {
2701 // cpu register - stack
2702 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2703 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2704 } else {
2705 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2706 }
2707 } else if (opr2->is_constant()) {
2708 // cpu register - constant
2709 LIR_Const* c = opr2->as_constant_ptr();
2710 if (c->type() == T_INT) {
2711 __ cmpl(reg1, c->as_jint());
2712 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2713 // In 64bit oops are single register
2714 jobject o = c->as_jobject();
2715 if (o == NULL) {
2716 __ cmpptr(reg1, (int32_t)NULL_WORD);
2717 } else {
2718 #ifdef _LP64
2719 __ movoop(rscratch1, o);
2720 __ cmpptr(reg1, rscratch1);
2721 #else
2722 __ cmpoop(reg1, c->as_jobject());
2723 #endif // _LP64
2724 }
2725 } else {
2726 fatal(err_msg("unexpected type: %s", basictype_to_str(c->type())));
2727 }
2728 // cpu register - address
2729 } else if (opr2->is_address()) {
2730 if (op->info() != NULL) {
2731 add_debug_info_for_null_check_here(op->info());
2732 }
2733 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2734 } else {
2735 ShouldNotReachHere();
2736 }
2737
2738 } else if(opr1->is_double_cpu()) {
2739 Register xlo = opr1->as_register_lo();
2740 Register xhi = opr1->as_register_hi();
2741 if (opr2->is_double_cpu()) {
2742 #ifdef _LP64
2743 __ cmpptr(xlo, opr2->as_register_lo());
2744 #else
2745 // cpu register - cpu register
2746 Register ylo = opr2->as_register_lo();
2747 Register yhi = opr2->as_register_hi();
2748 __ subl(xlo, ylo);
2749 __ sbbl(xhi, yhi);
2750 if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2751 __ orl(xhi, xlo);
2752 }
2753 #endif // _LP64
2754 } else if (opr2->is_constant()) {
2755 // cpu register - constant 0
2756 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2757 #ifdef _LP64
2758 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2759 #else
2760 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2761 __ orl(xhi, xlo);
2762 #endif // _LP64
2763 } else {
2764 ShouldNotReachHere();
2765 }
2766
2767 } else if (opr1->is_single_xmm()) {
2768 XMMRegister reg1 = opr1->as_xmm_float_reg();
2769 if (opr2->is_single_xmm()) {
2770 // xmm register - xmm register
2771 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2772 } else if (opr2->is_stack()) {
2773 // xmm register - stack
2774 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2775 } else if (opr2->is_constant()) {
2776 // xmm register - constant
2777 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2778 } else if (opr2->is_address()) {
2779 // xmm register - address
2780 if (op->info() != NULL) {
2781 add_debug_info_for_null_check_here(op->info());
2782 }
2783 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2784 } else {
2785 ShouldNotReachHere();
2786 }
2787
2788 } else if (opr1->is_double_xmm()) {
2789 XMMRegister reg1 = opr1->as_xmm_double_reg();
2790 if (opr2->is_double_xmm()) {
2791 // xmm register - xmm register
2792 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2793 } else if (opr2->is_stack()) {
2794 // xmm register - stack
2795 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2796 } else if (opr2->is_constant()) {
2797 // xmm register - constant
2798 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2799 } else if (opr2->is_address()) {
2800 // xmm register - address
2801 if (op->info() != NULL) {
2802 add_debug_info_for_null_check_here(op->info());
2803 }
2804 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2805 } else {
2806 ShouldNotReachHere();
2807 }
2808
2809 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2810 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2811 assert(opr2->is_fpu_register(), "both must be registers");
2812 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2813
2814 } else if (opr1->is_address() && opr2->is_constant()) {
2815 LIR_Const* c = opr2->as_constant_ptr();
2816 #ifdef _LP64
2817 if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2818 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2819 __ movoop(rscratch1, c->as_jobject());
2820 }
2821 #endif // LP64
2822 if (op->info() != NULL) {
2823 add_debug_info_for_null_check_here(op->info());
2824 }
2825 // special case: address - constant
2826 LIR_Address* addr = opr1->as_address_ptr();
2827 if (c->type() == T_INT) {
2828 __ cmpl(as_Address(addr), c->as_jint());
2829 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2830 #ifdef _LP64
2831 // %%% Make this explode if addr isn't reachable until we figure out a
2832 // better strategy by giving noreg as the temp for as_Address
2833 __ cmpptr(rscratch1, as_Address(addr, noreg));
2834 #else
2835 __ cmpoop(as_Address(addr), c->as_jobject());
2836 #endif // _LP64
2837 } else {
2838 ShouldNotReachHere();
2839 }
2840
2841 } else {
2842 ShouldNotReachHere();
2843 }
2844 }
2845
2846 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2847 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2848 if (left->is_single_xmm()) {
2849 assert(right->is_single_xmm(), "must match");
2850 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2851 } else if (left->is_double_xmm()) {
2852 assert(right->is_double_xmm(), "must match");
2853 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2854
2855 } else {
2856 assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2857 assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2858
2859 assert(left->fpu() == 0, "left must be on TOS");
2860 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2861 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2862 }
2863 } else {
2864 assert(code == lir_cmp_l2i, "check");
2865 #ifdef _LP64
2866 Label done;
2867 Register dest = dst->as_register();
2868 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2869 __ movl(dest, -1);
2870 __ jccb(Assembler::less, done);
2871 __ set_byte_if_not_zero(dest);
2872 __ movzbl(dest, dest);
2873 __ bind(done);
2874 #else
2875 __ lcmp2int(left->as_register_hi(),
2876 left->as_register_lo(),
2877 right->as_register_hi(),
2878 right->as_register_lo());
2879 move_regs(left->as_register_hi(), dst->as_register());
2880 #endif // _LP64
2881 }
2882 }
2883
2884
2885 void LIR_Assembler::align_call(LIR_Code code) {
2886 if (os::is_MP()) {
2887 // make sure that the displacement word of the call ends up word aligned
2888 int offset = __ offset();
2889 switch (code) {
2890 case lir_static_call:
2891 case lir_optvirtual_call:
2892 case lir_dynamic_call:
2893 offset += NativeCall::displacement_offset;
2894 break;
2895 case lir_icvirtual_call:
2896 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2897 break;
2898 case lir_virtual_call: // currently, sparc-specific for niagara
2899 default: ShouldNotReachHere();
2900 }
2901 while (offset++ % BytesPerWord != 0) {
2902 __ nop();
2903 }
2904 }
2905 }
2906
2907
2908 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2909 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2910 "must be aligned");
2911 __ call(AddressLiteral(op->addr(), rtype));
2912 add_call_info(code_offset(), op->info());
2913 }
2914
2915
2916 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2917 __ ic_call(op->addr());
2918 add_call_info(code_offset(), op->info());
2919 assert(!os::is_MP() ||
2920 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2921 "must be aligned");
2922 }
2923
2924
2925 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2926 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2927 ShouldNotReachHere();
2928 }
2929
2930
2931 void LIR_Assembler::emit_static_call_stub() {
2932 address call_pc = __ pc();
2933 address stub = __ start_a_stub(call_stub_size);
2934 if (stub == NULL) {
2935 bailout("static call stub overflow");
2936 return;
2937 }
2938
2939 int start = __ offset();
2940 if (os::is_MP()) {
2941 // make sure that the displacement word of the call ends up word aligned
2942 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset;
2943 while (offset++ % BytesPerWord != 0) {
2944 __ nop();
2945 }
2946 }
2947 __ relocate(static_stub_Relocation::spec(call_pc));
2948 __ mov_metadata(rbx, (Metadata*)NULL);
2949 // must be set to -1 at code generation time
2950 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP");
2951 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2952 __ jump(RuntimeAddress(__ pc()));
2953
2954 assert(__ offset() - start <= call_stub_size, "stub too big");
2955 __ end_a_stub();
2956 }
2957
2958
2959 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2960 assert(exceptionOop->as_register() == rax, "must match");
2961 assert(exceptionPC->as_register() == rdx, "must match");
2962
2963 // exception object is not added to oop map by LinearScan
2964 // (LinearScan assumes that no oops are in fixed registers)
2965 info->add_register_oop(exceptionOop);
2966 Runtime1::StubID unwind_id;
2967
2968 // get current pc information
2969 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2970 int pc_for_athrow_offset = __ offset();
2971 InternalAddress pc_for_athrow(__ pc());
2972 __ lea(exceptionPC->as_register(), pc_for_athrow);
2973 add_call_info(pc_for_athrow_offset, info); // for exception handler
2974
2975 __ verify_not_null_oop(rax);
2976 // search an exception handler (rax: exception oop, rdx: throwing pc)
2977 if (compilation()->has_fpu_code()) {
2978 unwind_id = Runtime1::handle_exception_id;
2979 } else {
2980 unwind_id = Runtime1::handle_exception_nofpu_id;
2981 }
2982 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2983
2984 // enough room for two byte trap
2985 __ nop();
2986 }
2987
2988
2989 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2990 assert(exceptionOop->as_register() == rax, "must match");
2991
2992 __ jmp(_unwind_handler_entry);
2993 }
2994
2995
2996 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2997
2998 // optimized version for linear scan:
2999 // * count must be already in ECX (guaranteed by LinearScan)
3000 // * left and dest must be equal
3001 // * tmp must be unused
3002 assert(count->as_register() == SHIFT_count, "count must be in ECX");
3003 assert(left == dest, "left and dest must be equal");
3004 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3005
3006 if (left->is_single_cpu()) {
3007 Register value = left->as_register();
3008 assert(value != SHIFT_count, "left cannot be ECX");
3009
3010 switch (code) {
3011 case lir_shl: __ shll(value); break;
3012 case lir_shr: __ sarl(value); break;
3013 case lir_ushr: __ shrl(value); break;
3014 default: ShouldNotReachHere();
3015 }
3016 } else if (left->is_double_cpu()) {
3017 Register lo = left->as_register_lo();
3018 Register hi = left->as_register_hi();
3019 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
3020 #ifdef _LP64
3021 switch (code) {
3022 case lir_shl: __ shlptr(lo); break;
3023 case lir_shr: __ sarptr(lo); break;
3024 case lir_ushr: __ shrptr(lo); break;
3025 default: ShouldNotReachHere();
3026 }
3027 #else
3028
3029 switch (code) {
3030 case lir_shl: __ lshl(hi, lo); break;
3031 case lir_shr: __ lshr(hi, lo, true); break;
3032 case lir_ushr: __ lshr(hi, lo, false); break;
3033 default: ShouldNotReachHere();
3034 }
3035 #endif // LP64
3036 } else {
3037 ShouldNotReachHere();
3038 }
3039 }
3040
3041
3042 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
3043 if (dest->is_single_cpu()) {
3044 // first move left into dest so that left is not destroyed by the shift
3045 Register value = dest->as_register();
3046 count = count & 0x1F; // Java spec
3047
3048 move_regs(left->as_register(), value);
3049 switch (code) {
3050 case lir_shl: __ shll(value, count); break;
3051 case lir_shr: __ sarl(value, count); break;
3052 case lir_ushr: __ shrl(value, count); break;
3053 default: ShouldNotReachHere();
3054 }
3055 } else if (dest->is_double_cpu()) {
3056 #ifndef _LP64
3057 Unimplemented();
3058 #else
3059 // first move left into dest so that left is not destroyed by the shift
3060 Register value = dest->as_register_lo();
3061 count = count & 0x1F; // Java spec
3062
3063 move_regs(left->as_register_lo(), value);
3064 switch (code) {
3065 case lir_shl: __ shlptr(value, count); break;
3066 case lir_shr: __ sarptr(value, count); break;
3067 case lir_ushr: __ shrptr(value, count); break;
3068 default: ShouldNotReachHere();
3069 }
3070 #endif // _LP64
3071 } else {
3072 ShouldNotReachHere();
3073 }
3074 }
3075
3076
3077 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3078 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3079 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3080 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3081 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3082 }
3083
3084
3085 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
3086 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3087 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3088 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3089 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3090 }
3091
3092
3093 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
3094 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3095 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3096 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3097 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3098 }
3099
3100
3101 // This code replaces a call to arraycopy; no exception may
3102 // be thrown in this code, they must be thrown in the System.arraycopy
3103 // activation frame; we could save some checks if this would not be the case
3104 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3105 ciArrayKlass* default_type = op->expected_type();
3106 Register src = op->src()->as_register();
3107 Register dst = op->dst()->as_register();
3108 Register src_pos = op->src_pos()->as_register();
3109 Register dst_pos = op->dst_pos()->as_register();
3110 Register length = op->length()->as_register();
3111 Register tmp = op->tmp()->as_register();
3112
3113 CodeStub* stub = op->stub();
3114 int flags = op->flags();
3115 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3116 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3117
3118 // if we don't know anything, just go through the generic arraycopy
3119 if (default_type == NULL) {
3120 Label done;
3121 // save outgoing arguments on stack in case call to System.arraycopy is needed
3122 // HACK ALERT. This code used to push the parameters in a hardwired fashion
3123 // for interpreter calling conventions. Now we have to do it in new style conventions.
3124 // For the moment until C1 gets the new register allocator I just force all the
3125 // args to the right place (except the register args) and then on the back side
3126 // reload the register args properly if we go slow path. Yuck
3127
3128 // These are proper for the calling convention
3129 store_parameter(length, 2);
3130 store_parameter(dst_pos, 1);
3131 store_parameter(dst, 0);
3132
3133 // these are just temporary placements until we need to reload
3134 store_parameter(src_pos, 3);
3135 store_parameter(src, 4);
3136 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3137
3138 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
3139
3140 address copyfunc_addr = StubRoutines::generic_arraycopy();
3141
3142 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3143 #ifdef _LP64
3144 // The arguments are in java calling convention so we can trivially shift them to C
3145 // convention
3146 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3147 __ mov(c_rarg0, j_rarg0);
3148 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3149 __ mov(c_rarg1, j_rarg1);
3150 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3151 __ mov(c_rarg2, j_rarg2);
3152 assert_different_registers(c_rarg3, j_rarg4);
3153 __ mov(c_rarg3, j_rarg3);
3154 #ifdef _WIN64
3155 // Allocate abi space for args but be sure to keep stack aligned
3156 __ subptr(rsp, 6*wordSize);
3157 store_parameter(j_rarg4, 4);
3158 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3159 __ call(RuntimeAddress(C_entry));
3160 } else {
3161 #ifndef PRODUCT
3162 if (PrintC1Statistics) {
3163 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3164 }
3165 #endif
3166 __ call(RuntimeAddress(copyfunc_addr));
3167 }
3168 __ addptr(rsp, 6*wordSize);
3169 #else
3170 __ mov(c_rarg4, j_rarg4);
3171 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3172 __ call(RuntimeAddress(C_entry));
3173 } else {
3174 #ifndef PRODUCT
3175 if (PrintC1Statistics) {
3176 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3177 }
3178 #endif
3179 __ call(RuntimeAddress(copyfunc_addr));
3180 }
3181 #endif // _WIN64
3182 #else
3183 __ push(length);
3184 __ push(dst_pos);
3185 __ push(dst);
3186 __ push(src_pos);
3187 __ push(src);
3188
3189 if (copyfunc_addr == NULL) { // Use C version if stub was not generated
3190 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack
3191 } else {
3192 #ifndef PRODUCT
3193 if (PrintC1Statistics) {
3194 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3195 }
3196 #endif
3197 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3198 }
3199
3200 #endif // _LP64
3201
3202 __ cmpl(rax, 0);
3203 __ jcc(Assembler::equal, *stub->continuation());
3204
3205 if (copyfunc_addr != NULL) {
3206 __ mov(tmp, rax);
3207 __ xorl(tmp, -1);
3208 }
3209
3210 // Reload values from the stack so they are where the stub
3211 // expects them.
3212 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3213 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3214 __ movptr (length, Address(rsp, 2*BytesPerWord));
3215 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3216 __ movptr (src, Address(rsp, 4*BytesPerWord));
3217
3218 if (copyfunc_addr != NULL) {
3219 __ subl(length, tmp);
3220 __ addl(src_pos, tmp);
3221 __ addl(dst_pos, tmp);
3222 }
3223 __ jmp(*stub->entry());
3224
3225 __ bind(*stub->continuation());
3226 return;
3227 }
3228
3229 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3230
3231 int elem_size = type2aelembytes(basic_type);
3232 int shift_amount;
3233 Address::ScaleFactor scale;
3234
3235 switch (elem_size) {
3236 case 1 :
3237 shift_amount = 0;
3238 scale = Address::times_1;
3239 break;
3240 case 2 :
3241 shift_amount = 1;
3242 scale = Address::times_2;
3243 break;
3244 case 4 :
3245 shift_amount = 2;
3246 scale = Address::times_4;
3247 break;
3248 case 8 :
3249 shift_amount = 3;
3250 scale = Address::times_8;
3251 break;
3252 default:
3253 ShouldNotReachHere();
3254 }
3255
3256 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3257 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3258 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3259 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3260
3261 // length and pos's are all sign extended at this point on 64bit
3262
3263 // test for NULL
3264 if (flags & LIR_OpArrayCopy::src_null_check) {
3265 __ testptr(src, src);
3266 __ jcc(Assembler::zero, *stub->entry());
3267 }
3268 if (flags & LIR_OpArrayCopy::dst_null_check) {
3269 __ testptr(dst, dst);
3270 __ jcc(Assembler::zero, *stub->entry());
3271 }
3272
3273 // check if negative
3274 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3275 __ testl(src_pos, src_pos);
3276 __ jcc(Assembler::less, *stub->entry());
3277 }
3278 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3279 __ testl(dst_pos, dst_pos);
3280 __ jcc(Assembler::less, *stub->entry());
3281 }
3282
3283 if (flags & LIR_OpArrayCopy::src_range_check) {
3284 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3285 __ cmpl(tmp, src_length_addr);
3286 __ jcc(Assembler::above, *stub->entry());
3287 }
3288 if (flags & LIR_OpArrayCopy::dst_range_check) {
3289 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3290 __ cmpl(tmp, dst_length_addr);
3291 __ jcc(Assembler::above, *stub->entry());
3292 }
3293
3294 if (flags & LIR_OpArrayCopy::length_positive_check) {
3295 __ testl(length, length);
3296 __ jcc(Assembler::less, *stub->entry());
3297 __ jcc(Assembler::zero, *stub->continuation());
3298 }
3299
3300 #ifdef _LP64
3301 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3302 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3303 #endif
3304
3305 if (flags & LIR_OpArrayCopy::type_check) {
3306 // We don't know the array types are compatible
3307 if (basic_type != T_OBJECT) {
3308 // Simple test for basic type arrays
3309 if (UseCompressedClassPointers) {
3310 __ movl(tmp, src_klass_addr);
3311 __ cmpl(tmp, dst_klass_addr);
3312 } else {
3313 __ movptr(tmp, src_klass_addr);
3314 __ cmpptr(tmp, dst_klass_addr);
3315 }
3316 __ jcc(Assembler::notEqual, *stub->entry());
3317 } else {
3318 // For object arrays, if src is a sub class of dst then we can
3319 // safely do the copy.
3320 Label cont, slow;
3321
3322 __ push(src);
3323 __ push(dst);
3324
3325 __ load_klass(src, src);
3326 __ load_klass(dst, dst);
3327
3328 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3329
3330 __ push(src);
3331 __ push(dst);
3332 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3333 __ pop(dst);
3334 __ pop(src);
3335
3336 __ cmpl(src, 0);
3337 __ jcc(Assembler::notEqual, cont);
3338
3339 __ bind(slow);
3340 __ pop(dst);
3341 __ pop(src);
3342
3343 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3344 if (copyfunc_addr != NULL) { // use stub if available
3345 // src is not a sub class of dst so we have to do a
3346 // per-element check.
3347
3348 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3349 if ((flags & mask) != mask) {
3350 // Check that at least both of them object arrays.
3351 assert(flags & mask, "one of the two should be known to be an object array");
3352
3353 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3354 __ load_klass(tmp, src);
3355 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3356 __ load_klass(tmp, dst);
3357 }
3358 int lh_offset = in_bytes(Klass::layout_helper_offset());
3359 Address klass_lh_addr(tmp, lh_offset);
3360 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3361 __ cmpl(klass_lh_addr, objArray_lh);
3362 __ jcc(Assembler::notEqual, *stub->entry());
3363 }
3364
3365 // Spill because stubs can use any register they like and it's
3366 // easier to restore just those that we care about.
3367 store_parameter(dst, 0);
3368 store_parameter(dst_pos, 1);
3369 store_parameter(length, 2);
3370 store_parameter(src_pos, 3);
3371 store_parameter(src, 4);
3372
3373 #ifndef _LP64
3374 __ movptr(tmp, dst_klass_addr);
3375 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3376 __ push(tmp);
3377 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3378 __ push(tmp);
3379 __ push(length);
3380 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3381 __ push(tmp);
3382 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3383 __ push(tmp);
3384
3385 __ call_VM_leaf(copyfunc_addr, 5);
3386 #else
3387 __ movl2ptr(length, length); //higher 32bits must be null
3388
3389 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3390 assert_different_registers(c_rarg0, dst, dst_pos, length);
3391 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3392 assert_different_registers(c_rarg1, dst, length);
3393
3394 __ mov(c_rarg2, length);
3395 assert_different_registers(c_rarg2, dst);
3396
3397 #ifdef _WIN64
3398 // Allocate abi space for args but be sure to keep stack aligned
3399 __ subptr(rsp, 6*wordSize);
3400 __ load_klass(c_rarg3, dst);
3401 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3402 store_parameter(c_rarg3, 4);
3403 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3404 __ call(RuntimeAddress(copyfunc_addr));
3405 __ addptr(rsp, 6*wordSize);
3406 #else
3407 __ load_klass(c_rarg4, dst);
3408 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3409 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3410 __ call(RuntimeAddress(copyfunc_addr));
3411 #endif
3412
3413 #endif
3414
3415 #ifndef PRODUCT
3416 if (PrintC1Statistics) {
3417 Label failed;
3418 __ testl(rax, rax);
3419 __ jcc(Assembler::notZero, failed);
3420 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3421 __ bind(failed);
3422 }
3423 #endif
3424
3425 __ testl(rax, rax);
3426 __ jcc(Assembler::zero, *stub->continuation());
3427
3428 #ifndef PRODUCT
3429 if (PrintC1Statistics) {
3430 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3431 }
3432 #endif
3433
3434 __ mov(tmp, rax);
3435
3436 __ xorl(tmp, -1);
3437
3438 // Restore previously spilled arguments
3439 __ movptr (dst, Address(rsp, 0*BytesPerWord));
3440 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
3441 __ movptr (length, Address(rsp, 2*BytesPerWord));
3442 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
3443 __ movptr (src, Address(rsp, 4*BytesPerWord));
3444
3445
3446 __ subl(length, tmp);
3447 __ addl(src_pos, tmp);
3448 __ addl(dst_pos, tmp);
3449 }
3450
3451 __ jmp(*stub->entry());
3452
3453 __ bind(cont);
3454 __ pop(dst);
3455 __ pop(src);
3456 }
3457 }
3458
3459 #ifdef ASSERT
3460 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3461 // Sanity check the known type with the incoming class. For the
3462 // primitive case the types must match exactly with src.klass and
3463 // dst.klass each exactly matching the default type. For the
3464 // object array case, if no type check is needed then either the
3465 // dst type is exactly the expected type and the src type is a
3466 // subtype which we can't check or src is the same array as dst
3467 // but not necessarily exactly of type default_type.
3468 Label known_ok, halt;
3469 __ mov_metadata(tmp, default_type->constant_encoding());
3470 #ifdef _LP64
3471 if (UseCompressedClassPointers) {
3472 __ encode_klass_not_null(tmp);
3473 }
3474 #endif
3475
3476 if (basic_type != T_OBJECT) {
3477
3478 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3479 else __ cmpptr(tmp, dst_klass_addr);
3480 __ jcc(Assembler::notEqual, halt);
3481 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr);
3482 else __ cmpptr(tmp, src_klass_addr);
3483 __ jcc(Assembler::equal, known_ok);
3484 } else {
3485 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr);
3486 else __ cmpptr(tmp, dst_klass_addr);
3487 __ jcc(Assembler::equal, known_ok);
3488 __ cmpptr(src, dst);
3489 __ jcc(Assembler::equal, known_ok);
3490 }
3491 __ bind(halt);
3492 __ stop("incorrect type information in arraycopy");
3493 __ bind(known_ok);
3494 }
3495 #endif
3496
3497 #ifndef PRODUCT
3498 if (PrintC1Statistics) {
3499 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3500 }
3501 #endif
3502
3503 #ifdef _LP64
3504 assert_different_registers(c_rarg0, dst, dst_pos, length);
3505 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3506 assert_different_registers(c_rarg1, length);
3507 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3508 __ mov(c_rarg2, length);
3509
3510 #else
3511 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3512 store_parameter(tmp, 0);
3513 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3514 store_parameter(tmp, 1);
3515 store_parameter(length, 2);
3516 #endif // _LP64
3517
3518 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3519 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3520 const char *name;
3521 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3522 __ call_VM_leaf(entry, 0);
3523
3524 __ bind(*stub->continuation());
3525 }
3526
3527 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3528 assert(op->crc()->is_single_cpu(), "crc must be register");
3529 assert(op->val()->is_single_cpu(), "byte value must be register");
3530 assert(op->result_opr()->is_single_cpu(), "result must be register");
3531 Register crc = op->crc()->as_register();
3532 Register val = op->val()->as_register();
3533 Register res = op->result_opr()->as_register();
3534
3535 assert_different_registers(val, crc, res);
3536
3537 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3538 __ notl(crc); // ~crc
3539 __ update_byte_crc32(crc, val, res);
3540 __ notl(crc); // ~crc
3541 __ mov(res, crc);
3542 }
3543
3544 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3545 Register obj = op->obj_opr()->as_register(); // may not be an oop
3546 Register hdr = op->hdr_opr()->as_register();
3547 Register lock = op->lock_opr()->as_register();
3548 if (!UseFastLocking) {
3549 __ jmp(*op->stub()->entry());
3550 } else if (op->code() == lir_lock) {
3551 Register scratch = noreg;
3552 if (UseBiasedLocking) {
3553 scratch = op->scratch_opr()->as_register();
3554 }
3555 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3556 // add debug info for NullPointerException only if one is possible
3557 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3558 if (op->info() != NULL) {
3559 add_debug_info_for_null_check(null_check_offset, op->info());
3560 }
3561 // done
3562 } else if (op->code() == lir_unlock) {
3563 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3564 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3565 } else {
3566 Unimplemented();
3567 }
3568 __ bind(*op->stub()->continuation());
3569 }
3570
3571
3572 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3573 ciMethod* method = op->profiled_method();
3574 int bci = op->profiled_bci();
3575 ciMethod* callee = op->profiled_callee();
3576
3577 // Update counter for all call types
3578 ciMethodData* md = method->method_data_or_null();
3579 assert(md != NULL, "Sanity");
3580 ciProfileData* data = md->bci_to_data(bci);
3581 assert(data->is_CounterData(), "need CounterData for calls");
3582 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
3583 Register mdo = op->mdo()->as_register();
3584 __ mov_metadata(mdo, md->constant_encoding());
3585 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3586 Bytecodes::Code bc = method->java_code_at_bci(bci);
3587 const bool callee_is_static = callee->is_loaded() && callee->is_static();
3588 // Perform additional virtual call profiling for invokevirtual and
3589 // invokeinterface bytecodes
3590 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
3591 !callee_is_static && // required for optimized MH invokes
3592 C1ProfileVirtualCalls) {
3593 assert(op->recv()->is_single_cpu(), "recv must be allocated");
3594 Register recv = op->recv()->as_register();
3595 assert_different_registers(mdo, recv);
3596 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3597 ciKlass* known_klass = op->known_holder();
3598 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3599 // We know the type that will be seen at this call site; we can
3600 // statically update the MethodData* rather than needing to do
3601 // dynamic tests on the receiver type
3602
3603 // NOTE: we should probably put a lock around this search to
3604 // avoid collisions by concurrent compilations
3605 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3606 uint i;
3607 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3608 ciKlass* receiver = vc_data->receiver(i);
3609 if (known_klass->equals(receiver)) {
3610 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3611 __ addptr(data_addr, DataLayout::counter_increment);
3612 return;
3613 }
3614 }
3615
3616 // Receiver type not found in profile data; select an empty slot
3617
3618 // Note that this is less efficient than it should be because it
3619 // always does a write to the receiver part of the
3620 // VirtualCallData rather than just the first time
3621 for (i = 0; i < VirtualCallData::row_limit(); i++) {
3622 ciKlass* receiver = vc_data->receiver(i);
3623 if (receiver == NULL) {
3624 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3625 __ mov_metadata(recv_addr, known_klass->constant_encoding());
3626 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3627 __ addptr(data_addr, DataLayout::counter_increment);
3628 return;
3629 }
3630 }
3631 } else {
3632 __ load_klass(recv, recv);
3633 Label update_done;
3634 type_profile_helper(mdo, md, data, recv, &update_done);
3635 // Receiver did not match any saved receiver and there is no empty row for it.
3636 // Increment total counter to indicate polymorphic case.
3637 __ addptr(counter_addr, DataLayout::counter_increment);
3638
3639 __ bind(update_done);
3640 }
3641 } else {
3642 // Static call
3643 __ addptr(counter_addr, DataLayout::counter_increment);
3644 }
3645 }
3646
3647 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3648 Register obj = op->obj()->as_register();
3649 Register tmp = op->tmp()->as_pointer_register();
3650 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3651 ciKlass* exact_klass = op->exact_klass();
3652 intptr_t current_klass = op->current_klass();
3653 bool not_null = op->not_null();
3654 bool no_conflict = op->no_conflict();
3655
3656 Label update, next, none;
3657
3658 bool do_null = !not_null;
3659 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3660 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3661
3662 assert(do_null || do_update, "why are we here?");
3663 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3664
3665 __ verify_oop(obj);
3666
3667 if (tmp != obj) {
3668 __ mov(tmp, obj);
3669 }
3670 if (do_null) {
3671 __ testptr(tmp, tmp);
3672 __ jccb(Assembler::notZero, update);
3673 if (!TypeEntries::was_null_seen(current_klass)) {
3674 __ orptr(mdo_addr, TypeEntries::null_seen);
3675 }
3676 if (do_update) {
3677 #ifndef ASSERT
3678 __ jmpb(next);
3679 }
3680 #else
3681 __ jmp(next);
3682 }
3683 } else {
3684 __ testptr(tmp, tmp);
3685 __ jccb(Assembler::notZero, update);
3686 __ stop("unexpect null obj");
3687 #endif
3688 }
3689
3690 __ bind(update);
3691
3692 if (do_update) {
3693 #ifdef ASSERT
3694 if (exact_klass != NULL) {
3695 Label ok;
3696 __ load_klass(tmp, tmp);
3697 __ push(tmp);
3698 __ mov_metadata(tmp, exact_klass->constant_encoding());
3699 __ cmpptr(tmp, Address(rsp, 0));
3700 __ jccb(Assembler::equal, ok);
3701 __ stop("exact klass and actual klass differ");
3702 __ bind(ok);
3703 __ pop(tmp);
3704 }
3705 #endif
3706 if (!no_conflict) {
3707 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3708 if (exact_klass != NULL) {
3709 __ mov_metadata(tmp, exact_klass->constant_encoding());
3710 } else {
3711 __ load_klass(tmp, tmp);
3712 }
3713
3714 __ xorptr(tmp, mdo_addr);
3715 __ testptr(tmp, TypeEntries::type_klass_mask);
3716 // klass seen before, nothing to do. The unknown bit may have been
3717 // set already but no need to check.
3718 __ jccb(Assembler::zero, next);
3719
3720 __ testptr(tmp, TypeEntries::type_unknown);
3721 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3722
3723 if (TypeEntries::is_type_none(current_klass)) {
3724 __ cmpptr(mdo_addr, 0);
3725 __ jccb(Assembler::equal, none);
3726 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3727 __ jccb(Assembler::equal, none);
3728 // There is a chance that the checks above (re-reading profiling
3729 // data from memory) fail if another thread has just set the
3730 // profiling to this obj's klass
3731 __ xorptr(tmp, mdo_addr);
3732 __ testptr(tmp, TypeEntries::type_klass_mask);
3733 __ jccb(Assembler::zero, next);
3734 }
3735 } else {
3736 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3737 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3738
3739 __ movptr(tmp, mdo_addr);
3740 __ testptr(tmp, TypeEntries::type_unknown);
3741 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3742 }
3743
3744 // different than before. Cannot keep accurate profile.
3745 __ orptr(mdo_addr, TypeEntries::type_unknown);
3746
3747 if (TypeEntries::is_type_none(current_klass)) {
3748 __ jmpb(next);
3749
3750 __ bind(none);
3751 // first time here. Set profile type.
3752 __ movptr(mdo_addr, tmp);
3753 }
3754 } else {
3755 // There's a single possible klass at this profile point
3756 assert(exact_klass != NULL, "should be");
3757 if (TypeEntries::is_type_none(current_klass)) {
3758 __ mov_metadata(tmp, exact_klass->constant_encoding());
3759 __ xorptr(tmp, mdo_addr);
3760 __ testptr(tmp, TypeEntries::type_klass_mask);
3761 #ifdef ASSERT
3762 __ jcc(Assembler::zero, next);
3763
3764 {
3765 Label ok;
3766 __ push(tmp);
3767 __ cmpptr(mdo_addr, 0);
3768 __ jcc(Assembler::equal, ok);
3769 __ cmpptr(mdo_addr, TypeEntries::null_seen);
3770 __ jcc(Assembler::equal, ok);
3771 // may have been set by another thread
3772 __ mov_metadata(tmp, exact_klass->constant_encoding());
3773 __ xorptr(tmp, mdo_addr);
3774 __ testptr(tmp, TypeEntries::type_mask);
3775 __ jcc(Assembler::zero, ok);
3776
3777 __ stop("unexpected profiling mismatch");
3778 __ bind(ok);
3779 __ pop(tmp);
3780 }
3781 #else
3782 __ jccb(Assembler::zero, next);
3783 #endif
3784 // first time here. Set profile type.
3785 __ movptr(mdo_addr, tmp);
3786 } else {
3787 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3788 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3789
3790 __ movptr(tmp, mdo_addr);
3791 __ testptr(tmp, TypeEntries::type_unknown);
3792 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3793
3794 __ orptr(mdo_addr, TypeEntries::type_unknown);
3795 }
3796 }
3797
3798 __ bind(next);
3799 }
3800 }
3801
3802 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3803 Unimplemented();
3804 }
3805
3806
3807 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3808 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3809 }
3810
3811
3812 void LIR_Assembler::align_backward_branch_target() {
3813 __ align(BytesPerWord);
3814 }
3815
3816
3817 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
3818 if (left->is_single_cpu()) {
3819 __ negl(left->as_register());
3820 move_regs(left->as_register(), dest->as_register());
3821
3822 } else if (left->is_double_cpu()) {
3823 Register lo = left->as_register_lo();
3824 #ifdef _LP64
3825 Register dst = dest->as_register_lo();
3826 __ movptr(dst, lo);
3827 __ negptr(dst);
3828 #else
3829 Register hi = left->as_register_hi();
3830 __ lneg(hi, lo);
3831 if (dest->as_register_lo() == hi) {
3832 assert(dest->as_register_hi() != lo, "destroying register");
3833 move_regs(hi, dest->as_register_hi());
3834 move_regs(lo, dest->as_register_lo());
3835 } else {
3836 move_regs(lo, dest->as_register_lo());
3837 move_regs(hi, dest->as_register_hi());
3838 }
3839 #endif // _LP64
3840
3841 } else if (dest->is_single_xmm()) {
3842 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3843 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3844 }
3845 __ xorps(dest->as_xmm_float_reg(),
3846 ExternalAddress((address)float_signflip_pool));
3847
3848 } else if (dest->is_double_xmm()) {
3849 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3850 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3851 }
3852 __ xorpd(dest->as_xmm_double_reg(),
3853 ExternalAddress((address)double_signflip_pool));
3854
3855 } else if (left->is_single_fpu() || left->is_double_fpu()) {
3856 assert(left->fpu() == 0, "arg must be on TOS");
3857 assert(dest->fpu() == 0, "dest must be TOS");
3858 __ fchs();
3859
3860 } else {
3861 ShouldNotReachHere();
3862 }
3863 }
3864
3865
3866 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) {
3867 assert(addr->is_address() && dest->is_register(), "check");
3868 Register reg;
3869 reg = dest->as_pointer_register();
3870 __ lea(reg, as_Address(addr->as_address_ptr()));
3871 }
3872
3873
3874
3875 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3876 assert(!tmp->is_valid(), "don't need temporary");
3877 __ call(RuntimeAddress(dest));
3878 if (info != NULL) {
3879 add_call_info_here(info);
3880 }
3881 }
3882
3883
3884 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3885 assert(type == T_LONG, "only for volatile long fields");
3886
3887 if (info != NULL) {
3888 add_debug_info_for_null_check_here(info);
3889 }
3890
3891 if (src->is_double_xmm()) {
3892 if (dest->is_double_cpu()) {
3893 #ifdef _LP64
3894 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3895 #else
3896 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3897 __ psrlq(src->as_xmm_double_reg(), 32);
3898 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3899 #endif // _LP64
3900 } else if (dest->is_double_stack()) {
3901 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3902 } else if (dest->is_address()) {
3903 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3904 } else {
3905 ShouldNotReachHere();
3906 }
3907
3908 } else if (dest->is_double_xmm()) {
3909 if (src->is_double_stack()) {
3910 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3911 } else if (src->is_address()) {
3912 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3913 } else {
3914 ShouldNotReachHere();
3915 }
3916
3917 } else if (src->is_double_fpu()) {
3918 assert(src->fpu_regnrLo() == 0, "must be TOS");
3919 if (dest->is_double_stack()) {
3920 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3921 } else if (dest->is_address()) {
3922 __ fistp_d(as_Address(dest->as_address_ptr()));
3923 } else {
3924 ShouldNotReachHere();
3925 }
3926
3927 } else if (dest->is_double_fpu()) {
3928 assert(dest->fpu_regnrLo() == 0, "must be TOS");
3929 if (src->is_double_stack()) {
3930 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3931 } else if (src->is_address()) {
3932 __ fild_d(as_Address(src->as_address_ptr()));
3933 } else {
3934 ShouldNotReachHere();
3935 }
3936 } else {
3937 ShouldNotReachHere();
3938 }
3939 }
3940
3941 #ifdef ASSERT
3942 // emit run-time assertion
3943 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3944 assert(op->code() == lir_assert, "must be");
3945
3946 if (op->in_opr1()->is_valid()) {
3947 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3948 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3949 } else {
3950 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3951 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3952 }
3953
3954 Label ok;
3955 if (op->condition() != lir_cond_always) {
3956 Assembler::Condition acond = Assembler::zero;
3957 switch (op->condition()) {
3958 case lir_cond_equal: acond = Assembler::equal; break;
3959 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3960 case lir_cond_less: acond = Assembler::less; break;
3961 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3962 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3963 case lir_cond_greater: acond = Assembler::greater; break;
3964 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3965 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3966 default: ShouldNotReachHere();
3967 }
3968 __ jcc(acond, ok);
3969 }
3970 if (op->halt()) {
3971 const char* str = __ code_string(op->msg());
3972 __ stop(str);
3973 } else {
3974 breakpoint();
3975 }
3976 __ bind(ok);
3977 }
3978 #endif
3979
3980 void LIR_Assembler::membar() {
3981 // QQQ sparc TSO uses this,
3982 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3983 }
3984
3985 void LIR_Assembler::membar_acquire() {
3986 // No x86 machines currently require load fences
3987 // __ load_fence();
3988 }
3989
3990 void LIR_Assembler::membar_release() {
3991 // No x86 machines currently require store fences
3992 // __ store_fence();
3993 }
3994
3995 void LIR_Assembler::membar_loadload() {
3996 // no-op
3997 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3998 }
3999
4000 void LIR_Assembler::membar_storestore() {
4001 // no-op
4002 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
4003 }
4004
4005 void LIR_Assembler::membar_loadstore() {
4006 // no-op
4007 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
4008 }
4009
4010 void LIR_Assembler::membar_storeload() {
4011 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4012 }
4013
4014 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4015 assert(result_reg->is_register(), "check");
4016 #ifdef _LP64
4017 // __ get_thread(result_reg->as_register_lo());
4018 __ mov(result_reg->as_register(), r15_thread);
4019 #else
4020 __ get_thread(result_reg->as_register());
4021 #endif // _LP64
4022 }
4023
4024
4025 void LIR_Assembler::peephole(LIR_List*) {
4026 // do nothing for now
4027 }
4028
4029 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4030 assert(data == dest, "xchg/xadd uses only 2 operands");
4031
4032 if (data->type() == T_INT) {
4033 if (code == lir_xadd) {
4034 if (os::is_MP()) {
4035 __ lock();
4036 }
4037 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4038 } else {
4039 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4040 }
4041 } else if (data->is_oop()) {
4042 assert (code == lir_xchg, "xadd for oops");
4043 Register obj = data->as_register();
4044 #ifdef _LP64
4045 if (UseCompressedOops) {
4046 __ encode_heap_oop(obj);
4047 __ xchgl(obj, as_Address(src->as_address_ptr()));
4048 __ decode_heap_oop(obj);
4049 } else {
4050 __ xchgptr(obj, as_Address(src->as_address_ptr()));
4051 }
4052 #else
4053 __ xchgl(obj, as_Address(src->as_address_ptr()));
4054 #endif
4055 } else if (data->type() == T_LONG) {
4056 #ifdef _LP64
4057 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4058 if (code == lir_xadd) {
4059 if (os::is_MP()) {
4060 __ lock();
4061 }
4062 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4063 } else {
4064 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4065 }
4066 #else
4067 ShouldNotReachHere();
4068 #endif
4069 } else {
4070 ShouldNotReachHere();
4071 }
4072 }
4073
4074 #undef __