*** old/src/cpu/sparc/vm/vm_version_sparc.cpp	Thu Sep  4 15:21:10 2014
--- new/src/cpu/sparc/vm/vm_version_sparc.cpp	Thu Sep  4 15:21:10 2014

*** 30,39 ****
--- 30,40 ----
  #include "runtime/stubCodeGenerator.hpp"
  #include "vm_version_sparc.hpp"
  
  int VM_Version::_features = VM_Version::unknown_m;
  const char* VM_Version::_features_str = "";
+ unsigned int VM_Version::_L2_cache_line_size = 0;
  
  void VM_Version::initialize() {
    _features = determine_features();
    PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
    PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();

*** 190,210 ****
--- 191,211 ----
      warning("CBCOND instruction is not available on this CPU");
      FLAG_SET_DEFAULT(UseCBCond, false);
    }
  
    assert(BlockZeroingLowLimit > 0, "invalid value");
!   if (has_block_zeroing() && cache_line_size > 0) {
      if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
        FLAG_SET_DEFAULT(UseBlockZeroing, true);
      }
    } else if (UseBlockZeroing) {
      warning("BIS zeroing instructions are not available on this CPU");
      FLAG_SET_DEFAULT(UseBlockZeroing, false);
    }
  
    assert(BlockCopyLowLimit > 0, "invalid value");
!   if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
      if (FLAG_IS_DEFAULT(UseBlockCopy)) {
        FLAG_SET_DEFAULT(UseBlockCopy, true);
      }
    } else if (UseBlockCopy) {
      warning("BIS instructions are not available or expensive on this CPU");

*** 250,302 ****
--- 251,260 ----
                 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
  
    // buf is started with ", " or is empty
    _features_str = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
  
    // There are three 64-bit SPARC families that do not overlap, e.g.,
    // both is_ultra3() and is_sparc64() cannot be true at the same time.
    // Within these families, there can be more than one chip, e.g.,
    // is_T4() and is_T7() machines are also is_niagara().
    if (is_ultra3()) {
      assert(_L1_data_cache_line_size == 0, "overlap with Ultra3 family");
      // Ref: UltraSPARC III Cu Processor
      _L1_data_cache_line_size = 64;
    }
    if (is_niagara()) {
      assert(_L1_data_cache_line_size == 0, "overlap with niagara family");
      // All Niagara's are sun4v's, but not all sun4v's are Niagaras, e.g.,
      // Fujitsu SPARC64 is sun4v, but we don't want it in this block.
      //
      // Ref: UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
      // Appendix F.1.3.1 Cacheable Accesses
      // -> 16-byte L1 cache line size
      //
      // Ref: UltraSPARC T2: A Highly-Threaded, Power-Efficient, SPARC SOC
      // Section III: SPARC Processor Core
      // -> 16-byte L1 cache line size
      //
      // Ref: Oracle's SPARC T4-1, SPARC T4-2, SPARC T4-4, and SPARC T4-1B Server Architecture
      // Section SPARC T4 Processor Cache Architecture
      // -> 32-byte L1 cache line size (no longer see that info on this ref)
      //
      // XXX - still need a T7 reference here
      //
      if (is_T7()) {  // T7 or newer
        _L1_data_cache_line_size = 64;
      } else if (is_T4()) {  // T4 or newer (until T7)
        _L1_data_cache_line_size = 32;
      } else {  // T1 or newer (until T4)
        _L1_data_cache_line_size = 16;
      }
    }
    if (is_sparc64()) {
      guarantee(_L1_data_cache_line_size == 0, "overlap with SPARC64 family");
      // Ref: Fujitsu SPARC64 VII Processor
      // Section 4 Cache System
      _L1_data_cache_line_size = 64;
    }
  
    // UseVIS is set to the smallest of what hardware supports and what
    // the command line requires.  I.e., you cannot set UseVIS to 3 on
    // older UltraSparc which do not support it.
    if (UseVIS > 3) UseVIS=3;
    if (UseVIS < 0) UseVIS=0;