79 T_family_m = 1 << T_family, 80 T1_model_m = 1 << T1_model, 81 sparc5_instructions_m = 1 << sparc5_instructions, 82 aes_instructions_m = 1 << aes_instructions, 83 sha1_instruction_m = 1 << sha1_instruction, 84 sha256_instruction_m = 1 << sha256_instruction, 85 sha512_instruction_m = 1 << sha512_instruction, 86 87 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m, 88 generic_v9_m = generic_v8_m | v9_instructions_m, 89 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m, 90 91 // Temporary until we have something more accurate 92 niagara1_unique_m = sun4v_m, 93 niagara1_m = generic_v9_m | niagara1_unique_m 94 }; 95 96 static int _features; 97 static const char* _features_str; 98 99 static void print_features(); 100 static int determine_features(); 101 static int platform_features(int features); 102 103 // Returns true if the platform is in the niagara line (T series) 104 static bool is_M_family(int features) { return (features & M_family_m) != 0; } 105 static bool is_T_family(int features) { return (features & T_family_m) != 0; } 106 static bool is_niagara() { return is_T_family(_features); } 107 #ifdef ASSERT 108 static bool is_niagara(int features) { 109 // 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as 110 // on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'. 111 return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0; 112 } 113 #endif 114 115 // Returns true if it is niagara1 (T1). 116 static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); } 117 118 static int maximum_niagara1_processor_count() { return 32; } 150 static bool is_T4() { return is_T_family(_features) && has_cbcond(); } 151 static bool is_T7() { return is_T_family(_features) && has_sparc5_instr(); } 152 153 // Fujitsu SPARC64 154 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; } 155 156 static bool is_sun4v() { return (_features & sun4v_m) != 0; } 157 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); } 158 159 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); } 160 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); } 161 162 // T4 and newer Sparc have fast RDPC instruction. 163 static bool has_fast_rdpc() { return is_T4(); } 164 165 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it. 166 static bool has_block_zeroing() { return has_blk_init() && is_T4(); } 167 168 static const char* cpu_features() { return _features_str; } 169 170 static intx prefetch_data_size() { 171 return is_T4() && !is_T7() ? 32 : 64; // default prefetch block size on sparc 172 } 173 174 // Prefetch 175 static intx prefetch_copy_interval_in_bytes() { 176 intx interval = PrefetchCopyIntervalInBytes; 177 return interval >= 0 ? interval : (has_v9() ? 512 : 0); 178 } 179 static intx prefetch_scan_interval_in_bytes() { 180 intx interval = PrefetchScanIntervalInBytes; 181 return interval >= 0 ? interval : (has_v9() ? 512 : 0); 182 } 183 static intx prefetch_fields_ahead() { 184 intx count = PrefetchFieldsAhead; 185 return count >= 0 ? count : (is_ultra3() ? 1 : 0); 186 } 187 188 static intx allocate_prefetch_distance() { 189 // This method should be called before allocate_prefetch_style(). 190 intx count = AllocatePrefetchDistance; 191 if (count < 0) { // default is not defined ? 192 count = 512; | 79 T_family_m = 1 << T_family, 80 T1_model_m = 1 << T1_model, 81 sparc5_instructions_m = 1 << sparc5_instructions, 82 aes_instructions_m = 1 << aes_instructions, 83 sha1_instruction_m = 1 << sha1_instruction, 84 sha256_instruction_m = 1 << sha256_instruction, 85 sha512_instruction_m = 1 << sha512_instruction, 86 87 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m, 88 generic_v9_m = generic_v8_m | v9_instructions_m, 89 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m, 90 91 // Temporary until we have something more accurate 92 niagara1_unique_m = sun4v_m, 93 niagara1_m = generic_v9_m | niagara1_unique_m 94 }; 95 96 static int _features; 97 static const char* _features_str; 98 99 static unsigned int _L2_cache_line_size; 100 static unsigned int L2_cache_line_size() { return _L2_cache_line_size; } 101 102 static void print_features(); 103 static int determine_features(); 104 static int platform_features(int features); 105 106 // Returns true if the platform is in the niagara line (T series) 107 static bool is_M_family(int features) { return (features & M_family_m) != 0; } 108 static bool is_T_family(int features) { return (features & T_family_m) != 0; } 109 static bool is_niagara() { return is_T_family(_features); } 110 #ifdef ASSERT 111 static bool is_niagara(int features) { 112 // 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as 113 // on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'. 114 return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0; 115 } 116 #endif 117 118 // Returns true if it is niagara1 (T1). 119 static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); } 120 121 static int maximum_niagara1_processor_count() { return 32; } 153 static bool is_T4() { return is_T_family(_features) && has_cbcond(); } 154 static bool is_T7() { return is_T_family(_features) && has_sparc5_instr(); } 155 156 // Fujitsu SPARC64 157 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; } 158 159 static bool is_sun4v() { return (_features & sun4v_m) != 0; } 160 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); } 161 162 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); } 163 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); } 164 165 // T4 and newer Sparc have fast RDPC instruction. 166 static bool has_fast_rdpc() { return is_T4(); } 167 168 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it. 169 static bool has_block_zeroing() { return has_blk_init() && is_T4(); } 170 171 static const char* cpu_features() { return _features_str; } 172 173 // default prefetch block size on sparc 174 static intx prefetch_data_size() { return L2_cache_line_size(); } 175 176 // Prefetch 177 static intx prefetch_copy_interval_in_bytes() { 178 intx interval = PrefetchCopyIntervalInBytes; 179 return interval >= 0 ? interval : (has_v9() ? 512 : 0); 180 } 181 static intx prefetch_scan_interval_in_bytes() { 182 intx interval = PrefetchScanIntervalInBytes; 183 return interval >= 0 ? interval : (has_v9() ? 512 : 0); 184 } 185 static intx prefetch_fields_ahead() { 186 intx count = PrefetchFieldsAhead; 187 return count >= 0 ? count : (is_ultra3() ? 1 : 0); 188 } 189 190 static intx allocate_prefetch_distance() { 191 // This method should be called before allocate_prefetch_style(). 192 intx count = AllocatePrefetchDistance; 193 if (count < 0) { // default is not defined ? 194 count = 512; |