*** old/src/cpu/sparc/vm/vm_version_sparc.hpp	Thu Sep  4 21:04:39 2014
--- new/src/cpu/sparc/vm/vm_version_sparc.hpp	Thu Sep  4 21:04:39 2014

*** 94,103 ****
--- 94,106 ----
    };
  
    static int  _features;
    static const char* _features_str;
  
+   static unsigned int _L2_cache_line_size;
+   static unsigned int L2_cache_line_size() { return _L2_cache_line_size; }
+ 
    static void print_features();
    static int  determine_features();
    static int  platform_features(int features);
  
    // Returns true if the platform is in the niagara line (T series)

*** 165,177 ****
--- 168,179 ----
    // On T4 and newer Sparc BIS to the beginning of cache line always zeros it.
    static bool has_block_zeroing()       { return has_blk_init() && is_T4(); }
  
    static const char* cpu_features()     { return _features_str; }
  
    static intx prefetch_data_size()  {
      return is_T4() && !is_T7() ? 32 : 64;  // default prefetch block size on sparc
    }
+   // default prefetch block size on sparc
+   static intx prefetch_data_size()      { return L2_cache_line_size();  }
  
    // Prefetch
    static intx prefetch_copy_interval_in_bytes() {
      intx interval = PrefetchCopyIntervalInBytes;
      return interval >= 0 ? interval : (has_v9() ? 512 : 0);