src/share/vm/c1/c1_LIRGenerator.cpp
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src/share/vm/c1/c1_LIRGenerator.cpp

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2028   }
2029 }
2030 
2031 
2032 void LIRGenerator::do_RoundFP(RoundFP* x) {
2033   LIRItem input(x->input(), this);
2034   input.load_item();
2035   LIR_Opr input_opr = input.result();
2036   assert(input_opr->is_register(), "why round if value is not in a register?");
2037   assert(input_opr->is_single_fpu() || input_opr->is_double_fpu(), "input should be floating-point value");
2038   if (input_opr->is_single_fpu()) {
2039     set_result(x, round_item(input_opr)); // This code path not currently taken
2040   } else {
2041     LIR_Opr result = new_register(T_DOUBLE);
2042     set_vreg_flag(result, must_start_in_memory);
2043     __ roundfp(input_opr, LIR_OprFact::illegalOpr, result);
2044     set_result(x, result);
2045   }
2046 }
2047 


2048 void LIRGenerator::do_UnsafeGetRaw(UnsafeGetRaw* x) {
2049   LIRItem base(x->base(), this);
2050   LIRItem idx(this);
2051 
2052   base.load_item();
2053   if (x->has_index()) {
2054     idx.set_instruction(x->index());
2055     idx.load_nonconstant();
2056   }
2057 
2058   LIR_Opr reg = rlock_result(x, x->basic_type());
2059 
2060   int   log2_scale = 0;
2061   if (x->has_index()) {
2062     assert(x->index()->type()->tag() == intTag, "should not find non-int index");
2063     log2_scale = x->log2_scale();
2064   }
2065 
2066   assert(!x->has_index() || idx.value() == x->index(), "should match");
2067 
2068   LIR_Opr base_op = base.result();

2069 #ifndef _LP64
2070   if (x->base()->type()->tag() == longTag) {
2071     base_op = new_register(T_INT);
2072     __ convert(Bytecodes::_l2i, base.result(), base_op);










2073   } else {
2074     assert(x->base()->type()->tag() == intTag, "must be");

2075   }























2076 #endif
2077 
2078   BasicType dst_type = x->basic_type();
2079   LIR_Opr index_op = idx.result();
2080 
2081   LIR_Address* addr;
2082   if (index_op->is_constant()) {
2083     assert(log2_scale == 0, "must not have a scale");

2084     addr = new LIR_Address(base_op, index_op->as_jint(), dst_type);
2085   } else {
2086 #ifdef X86
2087 #ifdef _LP64
2088     if (!index_op->is_illegal() && index_op->type() == T_INT) {
2089       LIR_Opr tmp = new_pointer_register();
2090       __ convert(Bytecodes::_i2l, index_op, tmp);
2091       index_op = tmp;
2092     }
2093 #endif
2094     addr = new LIR_Address(base_op, index_op, LIR_Address::Scale(log2_scale), 0, dst_type);
2095 #elif defined(ARM)
2096     addr = generate_address(base_op, index_op, log2_scale, 0, dst_type);
2097 #else
2098     if (index_op->is_illegal() || log2_scale == 0) {
2099 #ifdef _LP64
2100       if (!index_op->is_illegal() && index_op->type() == T_INT) {
2101         LIR_Opr tmp = new_pointer_register();
2102         __ convert(Bytecodes::_i2l, index_op, tmp);
2103         index_op = tmp;
2104       }
2105 #endif
2106       addr = new LIR_Address(base_op, index_op, dst_type);
2107     } else {
2108       LIR_Opr tmp = new_pointer_register();
2109       __ shift_left(index_op, log2_scale, tmp);
2110       addr = new LIR_Address(base_op, tmp, dst_type);
2111     }
2112 #endif
2113   }
2114 
2115   if (x->may_be_unaligned() && (dst_type == T_LONG || dst_type == T_DOUBLE)) {
2116     __ unaligned_move(addr, reg);
2117   } else {
2118     if (dst_type == T_OBJECT && x->is_wide()) {
2119       __ move_wide(addr, reg);
2120     } else {
2121       __ move(addr, reg);
2122     }
2123   }
2124 }
2125 
2126 
2127 void LIRGenerator::do_UnsafePutRaw(UnsafePutRaw* x) {
2128   int  log2_scale = 0;
2129   BasicType type = x->basic_type();
2130 
2131   if (x->has_index()) {
2132     assert(x->index()->type()->tag() == intTag, "should not find non-int index");
2133     log2_scale = x->log2_scale();
2134   }
2135 
2136   LIRItem base(x->base(), this);
2137   LIRItem value(x->value(), this);
2138   LIRItem idx(this);
2139 
2140   base.load_item();
2141   if (x->has_index()) {
2142     idx.set_instruction(x->index());
2143     idx.load_item();
2144   }
2145 
2146   if (type == T_BYTE || type == T_BOOLEAN) {
2147     value.load_byte_item();
2148   } else {
2149     value.load_item();
2150   }
2151 
2152   set_no_result(x);
2153 
2154   LIR_Opr base_op = base.result();


2155 #ifndef _LP64
2156   if (x->base()->type()->tag() == longTag) {
2157     base_op = new_register(T_INT);
2158     __ convert(Bytecodes::_l2i, base.result(), base_op);
2159   } else {
2160     assert(x->base()->type()->tag() == intTag, "must be");
2161   }



















2162 #endif
2163 
2164   LIR_Opr index_op = idx.result();
2165   if (log2_scale != 0) {
2166     // temporary fix (platform dependent code without shift on Intel would be better)
2167     index_op = new_pointer_register();
2168 #ifdef _LP64
2169     if(idx.result()->type() == T_INT) {
2170       __ convert(Bytecodes::_i2l, idx.result(), index_op);
2171     } else {
2172 #endif
2173       // TODO: ARM also allows embedded shift in the address
2174       __ move(idx.result(), index_op);
2175 #ifdef _LP64
2176     }
2177 #endif
2178     __ shift_left(index_op, log2_scale, index_op);
2179   }
2180 #ifdef _LP64
2181   else if(!index_op->is_illegal() && index_op->type() == T_INT) {
2182     LIR_Opr tmp = new_pointer_register();
2183     __ convert(Bytecodes::_i2l, index_op, tmp);
2184     index_op = tmp;
2185   }
2186 #endif
2187 
2188   LIR_Address* addr = new LIR_Address(base_op, index_op, x->basic_type());
2189   __ move(value.result(), addr);
2190 }
2191 
2192 
2193 void LIRGenerator::do_UnsafeGetObject(UnsafeGetObject* x) {
2194   BasicType type = x->basic_type();
2195   LIRItem src(x->object(), this);
2196   LIRItem off(x->offset(), this);
2197 
2198   off.load_item();
2199   src.load_item();
2200 
2201   LIR_Opr value = rlock_result(x, x->basic_type());
2202 
2203   get_Object_unsafe(value, src.result(), off.result(), type, x->is_volatile());
2204 
2205 #if INCLUDE_ALL_GCS
2206   // We might be reading the value of the referent field of a




2028   }
2029 }
2030 
2031 
2032 void LIRGenerator::do_RoundFP(RoundFP* x) {
2033   LIRItem input(x->input(), this);
2034   input.load_item();
2035   LIR_Opr input_opr = input.result();
2036   assert(input_opr->is_register(), "why round if value is not in a register?");
2037   assert(input_opr->is_single_fpu() || input_opr->is_double_fpu(), "input should be floating-point value");
2038   if (input_opr->is_single_fpu()) {
2039     set_result(x, round_item(input_opr)); // This code path not currently taken
2040   } else {
2041     LIR_Opr result = new_register(T_DOUBLE);
2042     set_vreg_flag(result, must_start_in_memory);
2043     __ roundfp(input_opr, LIR_OprFact::illegalOpr, result);
2044     set_result(x, result);
2045   }
2046 }
2047 
2048 // Here UnsafeGetRaw may have x->base() and x->index() be int or long
2049 // on both 64 and 32 bits. Expecting x->base() to be always long on 64bit.
2050 void LIRGenerator::do_UnsafeGetRaw(UnsafeGetRaw* x) {
2051   LIRItem base(x->base(), this);
2052   LIRItem idx(this);
2053 
2054   base.load_item();
2055   if (x->has_index()) {
2056     idx.set_instruction(x->index());
2057     idx.load_nonconstant();
2058   }
2059 
2060   LIR_Opr reg = rlock_result(x, x->basic_type());
2061 
2062   int   log2_scale = 0;
2063   if (x->has_index()) {

2064     log2_scale = x->log2_scale();
2065   }
2066 
2067   assert(!x->has_index() || idx.value() == x->index(), "should match");
2068 
2069   LIR_Opr base_op = base.result();
2070   LIR_Opr index_op = idx.result();
2071 #ifndef _LP64
2072   if (x->base()->type()->tag() == longTag) {
2073     base_op = new_register(T_INT);
2074     __ convert(Bytecodes::_l2i, base.result(), base_op);
2075   }
2076   if (x->has_index()) {
2077     if (x->index()->type()->tag() == longTag) {
2078       LIR_Opr long_index_op = index_op;
2079       if (x->index()->type()->is_constant()) {
2080         long_index_op = new_register(T_LONG);
2081         __ move(index_op, long_index_op);
2082       }
2083       index_op = new_register(T_INT);
2084       __ convert(Bytecodes::_l2i, long_index_op, index_op);
2085     } else {
2086       assert(x->index()->type()->tag() == intTag, "must be");
2087     }
2088   }
2089   // At this point base and index should be all ints.
2090   assert(base_op->type() == T_INT && !base_op->is_constant(), "base should be an non-constant int");
2091   assert(!x->has_index() || index_op->type() == T_INT, "index should be an int");
2092 #else
2093   if (x->has_index()) {
2094     if (x->index()->type()->tag() == intTag) {
2095       if (!x->index()->type()->is_constant()) {
2096         index_op = new_register(T_LONG);
2097         __ convert(Bytecodes::_i2l, idx.result(), index_op);
2098       }
2099     } else {
2100       assert(x->index()->type()->tag() == longTag, "must be");
2101       if (x->index()->type()->is_constant()) {
2102         index_op = new_register(T_LONG);
2103         __ move(idx.result(), index_op);
2104       }
2105     }
2106   }
2107   // At this point base is a long non-constant
2108   // Index is a long register or a int constant
2109   assert(base_op->type() == T_LONG && !base_op->is_constant(), "base must be a long non-constant");
2110   assert(!x->has_index() || (index_op->type() == T_INT && index_op->is_constant()) ||
2111                             (index_op->type() == T_LONG && !index_op->is_constant()), "unexpected index type");
2112 #endif
2113 
2114   BasicType dst_type = x->basic_type();

2115 
2116   LIR_Address* addr;
2117   if (index_op->is_constant()) {
2118     assert(log2_scale == 0, "must not have a scale");
2119     assert(index_op->type() == T_INT, "only int constants supported");
2120     addr = new LIR_Address(base_op, index_op->as_jint(), dst_type);
2121   } else {
2122 #ifdef X86







2123     addr = new LIR_Address(base_op, index_op, LIR_Address::Scale(log2_scale), 0, dst_type);
2124 #elif defined(ARM)
2125     addr = generate_address(base_op, index_op, log2_scale, 0, dst_type);
2126 #else
2127     if (index_op->is_illegal() || log2_scale == 0) {







2128       addr = new LIR_Address(base_op, index_op, dst_type);
2129     } else {
2130       LIR_Opr tmp = new_pointer_register();
2131       __ shift_left(index_op, log2_scale, tmp);
2132       addr = new LIR_Address(base_op, tmp, dst_type);
2133     }
2134 #endif
2135   }
2136 
2137   if (x->may_be_unaligned() && (dst_type == T_LONG || dst_type == T_DOUBLE)) {
2138     __ unaligned_move(addr, reg);
2139   } else {
2140     if (dst_type == T_OBJECT && x->is_wide()) {
2141       __ move_wide(addr, reg);
2142     } else {
2143       __ move(addr, reg);
2144     }
2145   }
2146 }
2147 
2148 
2149 void LIRGenerator::do_UnsafePutRaw(UnsafePutRaw* x) {
2150   int  log2_scale = 0;
2151   BasicType type = x->basic_type();
2152 
2153   if (x->has_index()) {

2154     log2_scale = x->log2_scale();
2155   }
2156 
2157   LIRItem base(x->base(), this);
2158   LIRItem value(x->value(), this);
2159   LIRItem idx(this);
2160 
2161   base.load_item();
2162   if (x->has_index()) {
2163     idx.set_instruction(x->index());
2164     idx.load_item();
2165   }
2166 
2167   if (type == T_BYTE || type == T_BOOLEAN) {
2168     value.load_byte_item();
2169   } else {
2170     value.load_item();
2171   }
2172 
2173   set_no_result(x);
2174 
2175   LIR_Opr base_op = base.result();
2176   LIR_Opr index_op = idx.result();
2177 
2178 #ifndef _LP64
2179   if (x->base()->type()->tag() == longTag) {
2180     base_op = new_register(T_INT);
2181     __ convert(Bytecodes::_l2i, base.result(), base_op);


2182   }
2183   if (x->has_index()) {
2184     if (x->index()->type()->tag() == longTag) {
2185       index_op = new_register(T_INT);
2186       __ convert(Bytecodes::_l2i, idx.result(), index_op);
2187     }
2188   }
2189   // At this point base and index should be all ints and not constants
2190   assert(base_op->type() == T_INT && !base_op->is_constant(), "base should be an non-constant int");
2191   assert(!x->has_index() || (index_op->type() == T_INT && !index_op->is_constant()), "index should be an non-constant int");
2192 #else
2193   if (x->has_index()) {
2194     if (x->index()->type()->tag() == intTag) {
2195       index_op = new_register(T_LONG);
2196       __ convert(Bytecodes::_i2l, idx.result(), index_op);
2197     }
2198   }
2199   // At this point base and index are long and non-constant
2200   assert(base_op->type() == T_LONG && !base_op->is_constant(), "base must be a non-constant long");
2201   assert(!x->has_index() || (index_op->type() == T_LONG && !index_op->is_constant()), "index must be a non-constant long");
2202 #endif
2203 

2204   if (log2_scale != 0) {
2205     // temporary fix (platform dependent code without shift on Intel would be better)






2206     // TODO: ARM also allows embedded shift in the address




2207     __ shift_left(index_op, log2_scale, index_op);
2208   }







2209 
2210   LIR_Address* addr = new LIR_Address(base_op, index_op, x->basic_type());
2211   __ move(value.result(), addr);
2212 }
2213 
2214 
2215 void LIRGenerator::do_UnsafeGetObject(UnsafeGetObject* x) {
2216   BasicType type = x->basic_type();
2217   LIRItem src(x->object(), this);
2218   LIRItem off(x->offset(), this);
2219 
2220   off.load_item();
2221   src.load_item();
2222 
2223   LIR_Opr value = rlock_result(x, x->basic_type());
2224 
2225   get_Object_unsafe(value, src.result(), off.result(), type, x->is_volatile());
2226 
2227 #if INCLUDE_ALL_GCS
2228   // We might be reading the value of the referent field of a


src/share/vm/c1/c1_LIRGenerator.cpp
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