1 /*
   2  * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "compiler/compileLog.hpp"
  27 #include "compiler/oopMap.hpp"
  28 #include "memory/allocation.inline.hpp"
  29 #include "opto/addnode.hpp"
  30 #include "opto/block.hpp"
  31 #include "opto/callnode.hpp"
  32 #include "opto/cfgnode.hpp"
  33 #include "opto/chaitin.hpp"
  34 #include "opto/coalesce.hpp"
  35 #include "opto/connode.hpp"
  36 #include "opto/idealGraphPrinter.hpp"
  37 #include "opto/indexSet.hpp"
  38 #include "opto/machnode.hpp"
  39 #include "opto/memnode.hpp"
  40 #include "opto/movenode.hpp"
  41 #include "opto/opcodes.hpp"
  42 #include "opto/rootnode.hpp"
  43 
  44 #ifndef PRODUCT
  45 void LRG::dump() const {
  46   ttyLocker ttyl;
  47   tty->print("%d ",num_regs());
  48   _mask.dump();
  49   if( _msize_valid ) {
  50     if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size);
  51     else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size());
  52   } else {
  53     tty->print(", #?(%d) ",_mask.Size());
  54   }
  55 
  56   tty->print("EffDeg: ");
  57   if( _degree_valid ) tty->print( "%d ", _eff_degree );
  58   else tty->print("? ");
  59 
  60   if( is_multidef() ) {
  61     tty->print("MultiDef ");
  62     if (_defs != NULL) {
  63       tty->print("(");
  64       for (int i = 0; i < _defs->length(); i++) {
  65         tty->print("N%d ", _defs->at(i)->_idx);
  66       }
  67       tty->print(") ");
  68     }
  69   }
  70   else if( _def == 0 ) tty->print("Dead ");
  71   else tty->print("Def: N%d ",_def->_idx);
  72 
  73   tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score());
  74   // Flags
  75   if( _is_oop ) tty->print("Oop ");
  76   if( _is_float ) tty->print("Float ");
  77   if( _is_vector ) tty->print("Vector ");
  78   if( _was_spilled1 ) tty->print("Spilled ");
  79   if( _was_spilled2 ) tty->print("Spilled2 ");
  80   if( _direct_conflict ) tty->print("Direct_conflict ");
  81   if( _fat_proj ) tty->print("Fat ");
  82   if( _was_lo ) tty->print("Lo ");
  83   if( _has_copy ) tty->print("Copy ");
  84   if( _at_risk ) tty->print("Risk ");
  85 
  86   if( _must_spill ) tty->print("Must_spill ");
  87   if( _is_bound ) tty->print("Bound ");
  88   if( _msize_valid ) {
  89     if( _degree_valid && lo_degree() ) tty->print("Trivial ");
  90   }
  91 
  92   tty->cr();
  93 }
  94 #endif
  95 
  96 // Compute score from cost and area.  Low score is best to spill.
  97 static double raw_score( double cost, double area ) {
  98   return cost - (area*RegisterCostAreaRatio) * 1.52588e-5;
  99 }
 100 
 101 double LRG::score() const {
 102   // Scale _area by RegisterCostAreaRatio/64K then subtract from cost.
 103   // Bigger area lowers score, encourages spilling this live range.
 104   // Bigger cost raise score, prevents spilling this live range.
 105   // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer
 106   // to turn a divide by a constant into a multiply by the reciprical).
 107   double score = raw_score( _cost, _area);
 108 
 109   // Account for area.  Basically, LRGs covering large areas are better
 110   // to spill because more other LRGs get freed up.
 111   if( _area == 0.0 )            // No area?  Then no progress to spill
 112     return 1e35;
 113 
 114   if( _was_spilled2 )           // If spilled once before, we are unlikely
 115     return score + 1e30;        // to make progress again.
 116 
 117   if( _cost >= _area*3.0 )      // Tiny area relative to cost
 118     return score + 1e17;        // Probably no progress to spill
 119 
 120   if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost
 121     return score + 1e10;        // Likely no progress to spill
 122 
 123   return score;
 124 }
 125 
 126 #define NUMBUCKS 3
 127 
 128 // Straight out of Tarjan's union-find algorithm
 129 uint LiveRangeMap::find_compress(uint lrg) {
 130   uint cur = lrg;
 131   uint next = _uf_map.at(cur);
 132   while (next != cur) { // Scan chain of equivalences
 133     assert( next < cur, "always union smaller");
 134     cur = next; // until find a fixed-point
 135     next = _uf_map.at(cur);
 136   }
 137 
 138   // Core of union-find algorithm: update chain of
 139   // equivalences to be equal to the root.
 140   while (lrg != next) {
 141     uint tmp = _uf_map.at(lrg);
 142     _uf_map.at_put(lrg, next);
 143     lrg = tmp;
 144   }
 145   return lrg;
 146 }
 147 
 148 // Reset the Union-Find map to identity
 149 void LiveRangeMap::reset_uf_map(uint max_lrg_id) {
 150   _max_lrg_id= max_lrg_id;
 151   // Force the Union-Find mapping to be at least this large
 152   _uf_map.at_put_grow(_max_lrg_id, 0);
 153   // Initialize it to be the ID mapping.
 154   for (uint i = 0; i < _max_lrg_id; ++i) {
 155     _uf_map.at_put(i, i);
 156   }
 157 }
 158 
 159 // Make all Nodes map directly to their final live range; no need for
 160 // the Union-Find mapping after this call.
 161 void LiveRangeMap::compress_uf_map_for_nodes() {
 162   // For all Nodes, compress mapping
 163   uint unique = _names.length();
 164   for (uint i = 0; i < unique; ++i) {
 165     uint lrg = _names.at(i);
 166     uint compressed_lrg = find(lrg);
 167     if (lrg != compressed_lrg) {
 168       _names.at_put(i, compressed_lrg);
 169     }
 170   }
 171 }
 172 
 173 // Like Find above, but no path compress, so bad asymptotic behavior
 174 uint LiveRangeMap::find_const(uint lrg) const {
 175   if (!lrg) {
 176     return lrg; // Ignore the zero LRG
 177   }
 178 
 179   // Off the end?  This happens during debugging dumps when you got
 180   // brand new live ranges but have not told the allocator yet.
 181   if (lrg >= _max_lrg_id) {
 182     return lrg;
 183   }
 184 
 185   uint next = _uf_map.at(lrg);
 186   while (next != lrg) { // Scan chain of equivalences
 187     assert(next < lrg, "always union smaller");
 188     lrg = next; // until find a fixed-point
 189     next = _uf_map.at(lrg);
 190   }
 191   return next;
 192 }
 193 
 194 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher)
 195   : PhaseRegAlloc(unique, cfg, matcher,
 196 #ifndef PRODUCT
 197        print_chaitin_statistics
 198 #else
 199        NULL
 200 #endif
 201        )
 202   , _lrg_map(Thread::current()->resource_area(), unique)
 203   , _live(0)
 204   , _spilled_once(Thread::current()->resource_area())
 205   , _spilled_twice(Thread::current()->resource_area())
 206   , _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0)
 207   , _oldphi(unique)
 208 #ifndef PRODUCT
 209   , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling"))
 210 #endif
 211 {
 212   Compile::TracePhase tp("ctorChaitin", &timers[_t_ctorChaitin]);
 213 
 214   _high_frequency_lrg = MIN2(double(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency());
 215 
 216   // Build a list of basic blocks, sorted by frequency
 217   _blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
 218   // Experiment with sorting strategies to speed compilation
 219   double  cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket
 220   Block **buckets[NUMBUCKS];             // Array of buckets
 221   uint    buckcnt[NUMBUCKS];             // Array of bucket counters
 222   double  buckval[NUMBUCKS];             // Array of bucket value cutoffs
 223   for (uint i = 0; i < NUMBUCKS; i++) {
 224     buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
 225     buckcnt[i] = 0;
 226     // Bump by three orders of magnitude each time
 227     cutoff *= 0.001;
 228     buckval[i] = cutoff;
 229     for (uint j = 0; j < _cfg.number_of_blocks(); j++) {
 230       buckets[i][j] = NULL;
 231     }
 232   }
 233   // Sort blocks into buckets
 234   for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
 235     for (uint j = 0; j < NUMBUCKS; j++) {
 236       if ((j == NUMBUCKS - 1) || (_cfg.get_block(i)->_freq > buckval[j])) {
 237         // Assign block to end of list for appropriate bucket
 238         buckets[j][buckcnt[j]++] = _cfg.get_block(i);
 239         break; // kick out of inner loop
 240       }
 241     }
 242   }
 243   // Dump buckets into final block array
 244   uint blkcnt = 0;
 245   for (uint i = 0; i < NUMBUCKS; i++) {
 246     for (uint j = 0; j < buckcnt[i]; j++) {
 247       _blks[blkcnt++] = buckets[i][j];
 248     }
 249   }
 250 
 251   assert(blkcnt == _cfg.number_of_blocks(), "Block array not totally filled");
 252 }
 253 
 254 // union 2 sets together.
 255 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) {
 256   uint src = _lrg_map.find(src_n);
 257   uint dst = _lrg_map.find(dst_n);
 258   assert(src, "");
 259   assert(dst, "");
 260   assert(src < _lrg_map.max_lrg_id(), "oob");
 261   assert(dst < _lrg_map.max_lrg_id(), "oob");
 262   assert(src < dst, "always union smaller");
 263   _lrg_map.uf_map(dst, src);
 264 }
 265 
 266 void PhaseChaitin::new_lrg(const Node *x, uint lrg) {
 267   // Make the Node->LRG mapping
 268   _lrg_map.extend(x->_idx,lrg);
 269   // Make the Union-Find mapping an identity function
 270   _lrg_map.uf_extend(lrg, lrg);
 271 }
 272 
 273 
 274 int PhaseChaitin::clone_projs(Block* b, uint idx, Node* orig, Node* copy, uint& max_lrg_id) {
 275   assert(b->find_node(copy) == (idx - 1), "incorrect insert index for copy kill projections");
 276   DEBUG_ONLY( Block* borig = _cfg.get_block_for_node(orig); )
 277   int found_projs = 0;
 278   uint cnt = orig->outcnt();
 279   for (uint i = 0; i < cnt; i++) {
 280     Node* proj = orig->raw_out(i);
 281     if (proj->is_MachProj()) {
 282       assert(proj->outcnt() == 0, "only kill projections are expected here");
 283       assert(_cfg.get_block_for_node(proj) == borig, "incorrect block for kill projections");
 284       found_projs++;
 285       // Copy kill projections after the cloned node
 286       Node* kills = proj->clone();
 287       kills->set_req(0, copy);
 288       b->insert_node(kills, idx++);
 289       _cfg.map_node_to_block(kills, b);
 290       new_lrg(kills, max_lrg_id++);
 291     }
 292   }
 293   return found_projs;
 294 }
 295 
 296 // Renumber the live ranges to compact them.  Makes the IFG smaller.
 297 void PhaseChaitin::compact() {
 298   Compile::TracePhase tp("chaitinCompact", &timers[_t_chaitinCompact]);
 299 
 300   // Current the _uf_map contains a series of short chains which are headed
 301   // by a self-cycle.  All the chains run from big numbers to little numbers.
 302   // The Find() call chases the chains & shortens them for the next Find call.
 303   // We are going to change this structure slightly.  Numbers above a moving
 304   // wave 'i' are unchanged.  Numbers below 'j' point directly to their
 305   // compacted live range with no further chaining.  There are no chains or
 306   // cycles below 'i', so the Find call no longer works.
 307   uint j=1;
 308   uint i;
 309   for (i = 1; i < _lrg_map.max_lrg_id(); i++) {
 310     uint lr = _lrg_map.uf_live_range_id(i);
 311     // Ignore unallocated live ranges
 312     if (!lr) {
 313       continue;
 314     }
 315     assert(lr <= i, "");
 316     _lrg_map.uf_map(i, ( lr == i ) ? j++ : _lrg_map.uf_live_range_id(lr));
 317   }
 318   // Now change the Node->LR mapping to reflect the compacted names
 319   uint unique = _lrg_map.size();
 320   for (i = 0; i < unique; i++) {
 321     uint lrg_id = _lrg_map.live_range_id(i);
 322     _lrg_map.map(i, _lrg_map.uf_live_range_id(lrg_id));
 323   }
 324 
 325   // Reset the Union-Find mapping
 326   _lrg_map.reset_uf_map(j);
 327 }
 328 
 329 void PhaseChaitin::Register_Allocate() {
 330 
 331   // Above the OLD FP (and in registers) are the incoming arguments.  Stack
 332   // slots in this area are called "arg_slots".  Above the NEW FP (and in
 333   // registers) is the outgoing argument area; above that is the spill/temp
 334   // area.  These are all "frame_slots".  Arg_slots start at the zero
 335   // stack_slots and count up to the known arg_size.  Frame_slots start at
 336   // the stack_slot #arg_size and go up.  After allocation I map stack
 337   // slots to actual offsets.  Stack-slots in the arg_slot area are biased
 338   // by the frame_size; stack-slots in the frame_slot area are biased by 0.
 339 
 340   _trip_cnt = 0;
 341   _alternate = 0;
 342   _matcher._allocation_started = true;
 343 
 344   ResourceArea split_arena;     // Arena for Split local resources
 345   ResourceArea live_arena;      // Arena for liveness & IFG info
 346   ResourceMark rm(&live_arena);
 347 
 348   // Need live-ness for the IFG; need the IFG for coalescing.  If the
 349   // liveness is JUST for coalescing, then I can get some mileage by renaming
 350   // all copy-related live ranges low and then using the max copy-related
 351   // live range as a cut-off for LIVE and the IFG.  In other words, I can
 352   // build a subset of LIVE and IFG just for copies.
 353   PhaseLive live(_cfg, _lrg_map.names(), &live_arena);
 354 
 355   // Need IFG for coalescing and coloring
 356   PhaseIFG ifg(&live_arena);
 357   _ifg = &ifg;
 358 
 359   // Come out of SSA world to the Named world.  Assign (virtual) registers to
 360   // Nodes.  Use the same register for all inputs and the output of PhiNodes
 361   // - effectively ending SSA form.  This requires either coalescing live
 362   // ranges or inserting copies.  For the moment, we insert "virtual copies"
 363   // - we pretend there is a copy prior to each Phi in predecessor blocks.
 364   // We will attempt to coalesce such "virtual copies" before we manifest
 365   // them for real.
 366   de_ssa();
 367 
 368 #ifdef ASSERT
 369   // Veify the graph before RA.
 370   verify(&live_arena);
 371 #endif
 372 
 373   {
 374     Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
 375     _live = NULL;                 // Mark live as being not available
 376     rm.reset_to_mark();           // Reclaim working storage
 377     IndexSet::reset_memory(C, &live_arena);
 378     ifg.init(_lrg_map.max_lrg_id()); // Empty IFG
 379     gather_lrg_masks( false );    // Collect LRG masks
 380     live.compute(_lrg_map.max_lrg_id()); // Compute liveness
 381     _live = &live;                // Mark LIVE as being available
 382   }
 383 
 384   // Base pointers are currently "used" by instructions which define new
 385   // derived pointers.  This makes base pointers live up to the where the
 386   // derived pointer is made, but not beyond.  Really, they need to be live
 387   // across any GC point where the derived value is live.  So this code looks
 388   // at all the GC points, and "stretches" the live range of any base pointer
 389   // to the GC point.
 390   if (stretch_base_pointer_live_ranges(&live_arena)) {
 391     Compile::TracePhase tp("computeLive (sbplr)", &timers[_t_computeLive]);
 392     // Since some live range stretched, I need to recompute live
 393     _live = NULL;
 394     rm.reset_to_mark();         // Reclaim working storage
 395     IndexSet::reset_memory(C, &live_arena);
 396     ifg.init(_lrg_map.max_lrg_id());
 397     gather_lrg_masks(false);
 398     live.compute(_lrg_map.max_lrg_id());
 399     _live = &live;
 400   }
 401   // Create the interference graph using virtual copies
 402   build_ifg_virtual();  // Include stack slots this time
 403 
 404   // The IFG is/was triangular.  I am 'squaring it up' so Union can run
 405   // faster.  Union requires a 'for all' operation which is slow on the
 406   // triangular adjacency matrix (quick reminder: the IFG is 'sparse' -
 407   // meaning I can visit all the Nodes neighbors less than a Node in time
 408   // O(# of neighbors), but I have to visit all the Nodes greater than a
 409   // given Node and search them for an instance, i.e., time O(#MaxLRG)).
 410   _ifg->SquareUp();
 411 
 412   // Aggressive (but pessimistic) copy coalescing.
 413   // This pass works on virtual copies.  Any virtual copies which are not
 414   // coalesced get manifested as actual copies
 415   {
 416     Compile::TracePhase tp("chaitinCoalesce1", &timers[_t_chaitinCoalesce1]);
 417 
 418     PhaseAggressiveCoalesce coalesce(*this);
 419     coalesce.coalesce_driver();
 420     // Insert un-coalesced copies.  Visit all Phis.  Where inputs to a Phi do
 421     // not match the Phi itself, insert a copy.
 422     coalesce.insert_copies(_matcher);
 423     if (C->failing()) {
 424       return;
 425     }
 426   }
 427 
 428   // After aggressive coalesce, attempt a first cut at coloring.
 429   // To color, we need the IFG and for that we need LIVE.
 430   {
 431     Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
 432     _live = NULL;
 433     rm.reset_to_mark();           // Reclaim working storage
 434     IndexSet::reset_memory(C, &live_arena);
 435     ifg.init(_lrg_map.max_lrg_id());
 436     gather_lrg_masks( true );
 437     live.compute(_lrg_map.max_lrg_id());
 438     _live = &live;
 439   }
 440 
 441   // Build physical interference graph
 442   uint must_spill = 0;
 443   must_spill = build_ifg_physical(&live_arena);
 444   // If we have a guaranteed spill, might as well spill now
 445   if (must_spill) {
 446     if(!_lrg_map.max_lrg_id()) {
 447       return;
 448     }
 449     // Bail out if unique gets too large (ie - unique > MaxNodeLimit)
 450     C->check_node_count(10*must_spill, "out of nodes before split");
 451     if (C->failing()) {
 452       return;
 453     }
 454 
 455     uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena);  // Split spilling LRG everywhere
 456     _lrg_map.set_max_lrg_id(new_max_lrg_id);
 457     // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
 458     // or we failed to split
 459     C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split");
 460     if (C->failing()) {
 461       return;
 462     }
 463 
 464     NOT_PRODUCT(C->verify_graph_edges();)
 465 
 466     compact();                  // Compact LRGs; return new lower max lrg
 467 
 468     {
 469       Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
 470       _live = NULL;
 471       rm.reset_to_mark();         // Reclaim working storage
 472       IndexSet::reset_memory(C, &live_arena);
 473       ifg.init(_lrg_map.max_lrg_id()); // Build a new interference graph
 474       gather_lrg_masks( true );   // Collect intersect mask
 475       live.compute(_lrg_map.max_lrg_id()); // Compute LIVE
 476       _live = &live;
 477     }
 478     build_ifg_physical(&live_arena);
 479     _ifg->SquareUp();
 480     _ifg->Compute_Effective_Degree();
 481     // Only do conservative coalescing if requested
 482     if (OptoCoalesce) {
 483       Compile::TracePhase tp("chaitinCoalesce2", &timers[_t_chaitinCoalesce2]);
 484       // Conservative (and pessimistic) copy coalescing of those spills
 485       PhaseConservativeCoalesce coalesce(*this);
 486       // If max live ranges greater than cutoff, don't color the stack.
 487       // This cutoff can be larger than below since it is only done once.
 488       coalesce.coalesce_driver();
 489     }
 490     _lrg_map.compress_uf_map_for_nodes();
 491 
 492 #ifdef ASSERT
 493     verify(&live_arena, true);
 494 #endif
 495   } else {
 496     ifg.SquareUp();
 497     ifg.Compute_Effective_Degree();
 498 #ifdef ASSERT
 499     set_was_low();
 500 #endif
 501   }
 502 
 503   // Prepare for Simplify & Select
 504   cache_lrg_info();           // Count degree of LRGs
 505 
 506   // Simplify the InterFerence Graph by removing LRGs of low degree.
 507   // LRGs of low degree are trivially colorable.
 508   Simplify();
 509 
 510   // Select colors by re-inserting LRGs back into the IFG in reverse order.
 511   // Return whether or not something spills.
 512   uint spills = Select( );
 513 
 514   // If we spill, split and recycle the entire thing
 515   while( spills ) {
 516     if( _trip_cnt++ > 24 ) {
 517       DEBUG_ONLY( dump_for_spill_split_recycle(); )
 518       if( _trip_cnt > 27 ) {
 519         C->record_method_not_compilable("failed spill-split-recycle sanity check");
 520         return;
 521       }
 522     }
 523 
 524     if (!_lrg_map.max_lrg_id()) {
 525       return;
 526     }
 527     uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena);  // Split spilling LRG everywhere
 528     _lrg_map.set_max_lrg_id(new_max_lrg_id);
 529     // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
 530     C->check_node_count(2 * NodeLimitFudgeFactor, "out of nodes after split");
 531     if (C->failing()) {
 532       return;
 533     }
 534 
 535     compact(); // Compact LRGs; return new lower max lrg
 536 
 537     // Nuke the live-ness and interference graph and LiveRanGe info
 538     {
 539       Compile::TracePhase tp("computeLive", &timers[_t_computeLive]);
 540       _live = NULL;
 541       rm.reset_to_mark();         // Reclaim working storage
 542       IndexSet::reset_memory(C, &live_arena);
 543       ifg.init(_lrg_map.max_lrg_id());
 544 
 545       // Create LiveRanGe array.
 546       // Intersect register masks for all USEs and DEFs
 547       gather_lrg_masks(true);
 548       live.compute(_lrg_map.max_lrg_id());
 549       _live = &live;
 550     }
 551     must_spill = build_ifg_physical(&live_arena);
 552     _ifg->SquareUp();
 553     _ifg->Compute_Effective_Degree();
 554 
 555     // Only do conservative coalescing if requested
 556     if (OptoCoalesce) {
 557       Compile::TracePhase tp("chaitinCoalesce3", &timers[_t_chaitinCoalesce3]);
 558       // Conservative (and pessimistic) copy coalescing
 559       PhaseConservativeCoalesce coalesce(*this);
 560       // Check for few live ranges determines how aggressive coalesce is.
 561       coalesce.coalesce_driver();
 562     }
 563     _lrg_map.compress_uf_map_for_nodes();
 564 #ifdef ASSERT
 565     verify(&live_arena, true);
 566 #endif
 567     cache_lrg_info();           // Count degree of LRGs
 568 
 569     // Simplify the InterFerence Graph by removing LRGs of low degree.
 570     // LRGs of low degree are trivially colorable.
 571     Simplify();
 572 
 573     // Select colors by re-inserting LRGs back into the IFG in reverse order.
 574     // Return whether or not something spills.
 575     spills = Select();
 576   }
 577 
 578   // Count number of Simplify-Select trips per coloring success.
 579   _allocator_attempts += _trip_cnt + 1;
 580   _allocator_successes += 1;
 581 
 582   // Peephole remove copies
 583   post_allocate_copy_removal();
 584 
 585 #ifdef ASSERT
 586   // Veify the graph after RA.
 587   verify(&live_arena);
 588 #endif
 589 
 590   // max_reg is past the largest *register* used.
 591   // Convert that to a frame_slot number.
 592   if (_max_reg <= _matcher._new_SP) {
 593     _framesize = C->out_preserve_stack_slots();
 594   }
 595   else {
 596     _framesize = _max_reg -_matcher._new_SP;
 597   }
 598   assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough");
 599 
 600   // This frame must preserve the required fp alignment
 601   _framesize = round_to(_framesize, Matcher::stack_alignment_in_slots());
 602   assert( _framesize >= 0 && _framesize <= 1000000, "sanity check" );
 603 #ifndef PRODUCT
 604   _total_framesize += _framesize;
 605   if ((int)_framesize > _max_framesize) {
 606     _max_framesize = _framesize;
 607   }
 608 #endif
 609 
 610   // Convert CISC spills
 611   fixup_spills();
 612 
 613   // Log regalloc results
 614   CompileLog* log = Compile::current()->log();
 615   if (log != NULL) {
 616     log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing());
 617   }
 618 
 619   if (C->failing()) {
 620     return;
 621   }
 622 
 623   NOT_PRODUCT(C->verify_graph_edges();)
 624 
 625   // Move important info out of the live_arena to longer lasting storage.
 626   alloc_node_regs(_lrg_map.size());
 627   for (uint i=0; i < _lrg_map.size(); i++) {
 628     if (_lrg_map.live_range_id(i)) { // Live range associated with Node?
 629       LRG &lrg = lrgs(_lrg_map.live_range_id(i));
 630       if (!lrg.alive()) {
 631         set_bad(i);
 632       } else if (lrg.num_regs() == 1) {
 633         set1(i, lrg.reg());
 634       } else {                  // Must be a register-set
 635         if (!lrg._fat_proj) {   // Must be aligned adjacent register set
 636           // Live ranges record the highest register in their mask.
 637           // We want the low register for the AD file writer's convenience.
 638           OptoReg::Name hi = lrg.reg(); // Get hi register
 639           OptoReg::Name lo = OptoReg::add(hi, (1-lrg.num_regs())); // Find lo
 640           // We have to use pair [lo,lo+1] even for wide vectors because
 641           // the rest of code generation works only with pairs. It is safe
 642           // since for registers encoding only 'lo' is used.
 643           // Second reg from pair is used in ScheduleAndBundle on SPARC where
 644           // vector max size is 8 which corresponds to registers pair.
 645           // It is also used in BuildOopMaps but oop operations are not
 646           // vectorized.
 647           set2(i, lo);
 648         } else {                // Misaligned; extract 2 bits
 649           OptoReg::Name hi = lrg.reg(); // Get hi register
 650           lrg.Remove(hi);       // Yank from mask
 651           int lo = lrg.mask().find_first_elem(); // Find lo
 652           set_pair(i, hi, lo);
 653         }
 654       }
 655       if( lrg._is_oop ) _node_oops.set(i);
 656     } else {
 657       set_bad(i);
 658     }
 659   }
 660 
 661   // Done!
 662   _live = NULL;
 663   _ifg = NULL;
 664   C->set_indexSet_arena(NULL);  // ResourceArea is at end of scope
 665 }
 666 
 667 void PhaseChaitin::de_ssa() {
 668   // Set initial Names for all Nodes.  Most Nodes get the virtual register
 669   // number.  A few get the ZERO live range number.  These do not
 670   // get allocated, but instead rely on correct scheduling to ensure that
 671   // only one instance is simultaneously live at a time.
 672   uint lr_counter = 1;
 673   for( uint i = 0; i < _cfg.number_of_blocks(); i++ ) {
 674     Block* block = _cfg.get_block(i);
 675     uint cnt = block->number_of_nodes();
 676 
 677     // Handle all the normal Nodes in the block
 678     for( uint j = 0; j < cnt; j++ ) {
 679       Node *n = block->get_node(j);
 680       // Pre-color to the zero live range, or pick virtual register
 681       const RegMask &rm = n->out_RegMask();
 682       _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0);
 683     }
 684   }
 685 
 686   // Reset the Union-Find mapping to be identity
 687   _lrg_map.reset_uf_map(lr_counter);
 688 }
 689 
 690 
 691 // Gather LiveRanGe information, including register masks.  Modification of
 692 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce.
 693 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
 694 
 695   // Nail down the frame pointer live range
 696   uint fp_lrg = _lrg_map.live_range_id(_cfg.get_root_node()->in(1)->in(TypeFunc::FramePtr));
 697   lrgs(fp_lrg)._cost += 1e12;   // Cost is infinite
 698 
 699   // For all blocks
 700   for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
 701     Block* block = _cfg.get_block(i);
 702 
 703     // For all instructions
 704     for (uint j = 1; j < block->number_of_nodes(); j++) {
 705       Node* n = block->get_node(j);
 706       uint input_edge_start =1; // Skip control most nodes
 707       if (n->is_Mach()) {
 708         input_edge_start = n->as_Mach()->oper_input_base();
 709       }
 710       uint idx = n->is_Copy();
 711 
 712       // Get virtual register number, same as LiveRanGe index
 713       uint vreg = _lrg_map.live_range_id(n);
 714       LRG& lrg = lrgs(vreg);
 715       if (vreg) {              // No vreg means un-allocable (e.g. memory)
 716 
 717         // Collect has-copy bit
 718         if (idx) {
 719           lrg._has_copy = 1;
 720           uint clidx = _lrg_map.live_range_id(n->in(idx));
 721           LRG& copy_src = lrgs(clidx);
 722           copy_src._has_copy = 1;
 723         }
 724 
 725         // Check for float-vs-int live range (used in register-pressure
 726         // calculations)
 727         const Type *n_type = n->bottom_type();
 728         if (n_type->is_floatingpoint()) {
 729           lrg._is_float = 1;
 730         }
 731 
 732         // Check for twice prior spilling.  Once prior spilling might have
 733         // spilled 'soft', 2nd prior spill should have spilled 'hard' and
 734         // further spilling is unlikely to make progress.
 735         if (_spilled_once.test(n->_idx)) {
 736           lrg._was_spilled1 = 1;
 737           if (_spilled_twice.test(n->_idx)) {
 738             lrg._was_spilled2 = 1;
 739           }
 740         }
 741 
 742 #ifndef PRODUCT
 743         if (trace_spilling() && lrg._def != NULL) {
 744           // collect defs for MultiDef printing
 745           if (lrg._defs == NULL) {
 746             lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL);
 747             lrg._defs->append(lrg._def);
 748           }
 749           lrg._defs->append(n);
 750         }
 751 #endif
 752 
 753         // Check for a single def LRG; these can spill nicely
 754         // via rematerialization.  Flag as NULL for no def found
 755         // yet, or 'n' for single def or -1 for many defs.
 756         lrg._def = lrg._def ? NodeSentinel : n;
 757 
 758         // Limit result register mask to acceptable registers
 759         const RegMask &rm = n->out_RegMask();
 760         lrg.AND( rm );
 761 
 762         int ireg = n->ideal_reg();
 763         assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
 764                 "oops must be in Op_RegP's" );
 765 
 766         // Check for vector live range (only if vector register is used).
 767         // On SPARC vector uses RegD which could be misaligned so it is not
 768         // processes as vector in RA.
 769         if (RegMask::is_vector(ireg))
 770           lrg._is_vector = 1;
 771         assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD || ireg == Op_RegL,
 772                "vector must be in vector registers");
 773 
 774         // Check for bound register masks
 775         const RegMask &lrgmask = lrg.mask();
 776         if (lrgmask.is_bound(ireg)) {
 777           lrg._is_bound = 1;
 778         }
 779 
 780         // Check for maximum frequency value
 781         if (lrg._maxfreq < block->_freq) {
 782           lrg._maxfreq = block->_freq;
 783         }
 784 
 785         // Check for oop-iness, or long/double
 786         // Check for multi-kill projection
 787         switch (ireg) {
 788         case MachProjNode::fat_proj:
 789           // Fat projections have size equal to number of registers killed
 790           lrg.set_num_regs(rm.Size());
 791           lrg.set_reg_pressure(lrg.num_regs());
 792           lrg._fat_proj = 1;
 793           lrg._is_bound = 1;
 794           break;
 795         case Op_RegP:
 796 #ifdef _LP64
 797           lrg.set_num_regs(2);  // Size is 2 stack words
 798 #else
 799           lrg.set_num_regs(1);  // Size is 1 stack word
 800 #endif
 801           // Register pressure is tracked relative to the maximum values
 802           // suggested for that platform, INTPRESSURE and FLOATPRESSURE,
 803           // and relative to other types which compete for the same regs.
 804           //
 805           // The following table contains suggested values based on the
 806           // architectures as defined in each .ad file.
 807           // INTPRESSURE and FLOATPRESSURE may be tuned differently for
 808           // compile-speed or performance.
 809           // Note1:
 810           // SPARC and SPARCV9 reg_pressures are at 2 instead of 1
 811           // since .ad registers are defined as high and low halves.
 812           // These reg_pressure values remain compatible with the code
 813           // in is_high_pressure() which relates get_invalid_mask_size(),
 814           // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE.
 815           // Note2:
 816           // SPARC -d32 has 24 registers available for integral values,
 817           // but only 10 of these are safe for 64-bit longs.
 818           // Using set_reg_pressure(2) for both int and long means
 819           // the allocator will believe it can fit 26 longs into
 820           // registers.  Using 2 for longs and 1 for ints means the
 821           // allocator will attempt to put 52 integers into registers.
 822           // The settings below limit this problem to methods with
 823           // many long values which are being run on 32-bit SPARC.
 824           //
 825           // ------------------- reg_pressure --------------------
 826           // Each entry is reg_pressure_per_value,number_of_regs
 827           //         RegL  RegI  RegFlags   RegF RegD    INTPRESSURE  FLOATPRESSURE
 828           // IA32     2     1     1          1    1          6           6
 829           // IA64     1     1     1          1    1         50          41
 830           // SPARC    2     2     2          2    2         48 (24)     52 (26)
 831           // SPARCV9  2     2     2          2    2         48 (24)     52 (26)
 832           // AMD64    1     1     1          1    1         14          15
 833           // -----------------------------------------------------
 834 #if defined(SPARC)
 835           lrg.set_reg_pressure(2);  // use for v9 as well
 836 #else
 837           lrg.set_reg_pressure(1);  // normally one value per register
 838 #endif
 839           if( n_type->isa_oop_ptr() ) {
 840             lrg._is_oop = 1;
 841           }
 842           break;
 843         case Op_RegL:           // Check for long or double
 844         case Op_RegD:
 845           lrg.set_num_regs(2);
 846           // Define platform specific register pressure
 847 #if defined(SPARC) || defined(ARM)
 848           lrg.set_reg_pressure(2);
 849 #elif defined(IA32)
 850           if( ireg == Op_RegL ) {
 851             lrg.set_reg_pressure(2);
 852           } else {
 853             lrg.set_reg_pressure(1);
 854           }
 855 #else
 856           lrg.set_reg_pressure(1);  // normally one value per register
 857 #endif
 858           // If this def of a double forces a mis-aligned double,
 859           // flag as '_fat_proj' - really flag as allowing misalignment
 860           // AND changes how we count interferences.  A mis-aligned
 861           // double can interfere with TWO aligned pairs, or effectively
 862           // FOUR registers!
 863           if (rm.is_misaligned_pair()) {
 864             lrg._fat_proj = 1;
 865             lrg._is_bound = 1;
 866           }
 867           break;
 868         case Op_RegF:
 869         case Op_RegI:
 870         case Op_RegN:
 871         case Op_RegFlags:
 872         case 0:                 // not an ideal register
 873           lrg.set_num_regs(1);
 874 #ifdef SPARC
 875           lrg.set_reg_pressure(2);
 876 #else
 877           lrg.set_reg_pressure(1);
 878 #endif
 879           break;
 880         case Op_VecS:
 881           assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");
 882           assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity");
 883           lrg.set_num_regs(RegMask::SlotsPerVecS);
 884           lrg.set_reg_pressure(1);
 885           break;
 886         case Op_VecD:
 887           assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
 888           assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
 889           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
 890           lrg.set_num_regs(RegMask::SlotsPerVecD);
 891           lrg.set_reg_pressure(1);
 892           break;
 893         case Op_VecX:
 894           assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
 895           assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
 896           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
 897           lrg.set_num_regs(RegMask::SlotsPerVecX);
 898           lrg.set_reg_pressure(1);
 899           break;
 900         case Op_VecY:
 901           assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity");
 902           assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity");
 903           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned");
 904           lrg.set_num_regs(RegMask::SlotsPerVecY);
 905           lrg.set_reg_pressure(1);
 906           break;
 907         default:
 908           ShouldNotReachHere();
 909         }
 910       }
 911 
 912       // Now do the same for inputs
 913       uint cnt = n->req();
 914       // Setup for CISC SPILLING
 915       uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
 916       if( UseCISCSpill && after_aggressive ) {
 917         inp = n->cisc_operand();
 918         if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
 919           // Convert operand number to edge index number
 920           inp = n->as_Mach()->operand_index(inp);
 921       }
 922       // Prepare register mask for each input
 923       for( uint k = input_edge_start; k < cnt; k++ ) {
 924         uint vreg = _lrg_map.live_range_id(n->in(k));
 925         if (!vreg) {
 926           continue;
 927         }
 928 
 929         // If this instruction is CISC Spillable, add the flags
 930         // bit to its appropriate input
 931         if( UseCISCSpill && after_aggressive && inp == k ) {
 932 #ifndef PRODUCT
 933           if( TraceCISCSpill ) {
 934             tty->print("  use_cisc_RegMask: ");
 935             n->dump();
 936           }
 937 #endif
 938           n->as_Mach()->use_cisc_RegMask();
 939         }
 940 
 941         LRG &lrg = lrgs(vreg);
 942         // // Testing for floating point code shape
 943         // Node *test = n->in(k);
 944         // if( test->is_Mach() ) {
 945         //   MachNode *m = test->as_Mach();
 946         //   int  op = m->ideal_Opcode();
 947         //   if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) {
 948         //     int zzz = 1;
 949         //   }
 950         // }
 951 
 952         // Limit result register mask to acceptable registers.
 953         // Do not limit registers from uncommon uses before
 954         // AggressiveCoalesce.  This effectively pre-virtual-splits
 955         // around uncommon uses of common defs.
 956         const RegMask &rm = n->in_RegMask(k);
 957         if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) {
 958           // Since we are BEFORE aggressive coalesce, leave the register
 959           // mask untrimmed by the call.  This encourages more coalescing.
 960           // Later, AFTER aggressive, this live range will have to spill
 961           // but the spiller handles slow-path calls very nicely.
 962         } else {
 963           lrg.AND( rm );
 964         }
 965 
 966         // Check for bound register masks
 967         const RegMask &lrgmask = lrg.mask();
 968         int kreg = n->in(k)->ideal_reg();
 969         bool is_vect = RegMask::is_vector(kreg);
 970         assert(n->in(k)->bottom_type()->isa_vect() == NULL ||
 971                is_vect || kreg == Op_RegD || kreg == Op_RegL,
 972                "vector must be in vector registers");
 973         if (lrgmask.is_bound(kreg))
 974           lrg._is_bound = 1;
 975 
 976         // If this use of a double forces a mis-aligned double,
 977         // flag as '_fat_proj' - really flag as allowing misalignment
 978         // AND changes how we count interferences.  A mis-aligned
 979         // double can interfere with TWO aligned pairs, or effectively
 980         // FOUR registers!
 981 #ifdef ASSERT
 982         if (is_vect) {
 983           assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned");
 984           assert(!lrg._fat_proj, "sanity");
 985           assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity");
 986         }
 987 #endif
 988         if (!is_vect && lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_pair()) {
 989           lrg._fat_proj = 1;
 990           lrg._is_bound = 1;
 991         }
 992         // if the LRG is an unaligned pair, we will have to spill
 993         // so clear the LRG's register mask if it is not already spilled
 994         if (!is_vect && !n->is_SpillCopy() &&
 995             (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) &&
 996             lrgmask.is_misaligned_pair()) {
 997           lrg.Clear();
 998         }
 999 
1000         // Check for maximum frequency value
1001         if (lrg._maxfreq < block->_freq) {
1002           lrg._maxfreq = block->_freq;
1003         }
1004 
1005       } // End for all allocated inputs
1006     } // end for all instructions
1007   } // end for all blocks
1008 
1009   // Final per-liverange setup
1010   for (uint i2 = 0; i2 < _lrg_map.max_lrg_id(); i2++) {
1011     LRG &lrg = lrgs(i2);
1012     assert(!lrg._is_vector || !lrg._fat_proj, "sanity");
1013     if (lrg.num_regs() > 1 && !lrg._fat_proj) {
1014       lrg.clear_to_sets();
1015     }
1016     lrg.compute_set_mask_size();
1017     if (lrg.not_free()) {      // Handle case where we lose from the start
1018       lrg.set_reg(OptoReg::Name(LRG::SPILL_REG));
1019       lrg._direct_conflict = 1;
1020     }
1021     lrg.set_degree(0);          // no neighbors in IFG yet
1022   }
1023 }
1024 
1025 // Set the was-lo-degree bit.  Conservative coalescing should not change the
1026 // colorability of the graph.  If any live range was of low-degree before
1027 // coalescing, it should Simplify.  This call sets the was-lo-degree bit.
1028 // The bit is checked in Simplify.
1029 void PhaseChaitin::set_was_low() {
1030 #ifdef ASSERT
1031   for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1032     int size = lrgs(i).num_regs();
1033     uint old_was_lo = lrgs(i)._was_lo;
1034     lrgs(i)._was_lo = 0;
1035     if( lrgs(i).lo_degree() ) {
1036       lrgs(i)._was_lo = 1;      // Trivially of low degree
1037     } else {                    // Else check the Brigg's assertion
1038       // Brigg's observation is that the lo-degree neighbors of a
1039       // hi-degree live range will not interfere with the color choices
1040       // of said hi-degree live range.  The Simplify reverse-stack-coloring
1041       // order takes care of the details.  Hence you do not have to count
1042       // low-degree neighbors when determining if this guy colors.
1043       int briggs_degree = 0;
1044       IndexSet *s = _ifg->neighbors(i);
1045       IndexSetIterator elements(s);
1046       uint lidx;
1047       while((lidx = elements.next()) != 0) {
1048         if( !lrgs(lidx).lo_degree() )
1049           briggs_degree += MAX2(size,lrgs(lidx).num_regs());
1050       }
1051       if( briggs_degree < lrgs(i).degrees_of_freedom() )
1052         lrgs(i)._was_lo = 1;    // Low degree via the briggs assertion
1053     }
1054     assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease");
1055   }
1056 #endif
1057 }
1058 
1059 #define REGISTER_CONSTRAINED 16
1060 
1061 // Compute cost/area ratio, in case we spill.  Build the lo-degree list.
1062 void PhaseChaitin::cache_lrg_info( ) {
1063   Compile::TracePhase tp("chaitinCacheLRG", &timers[_t_chaitinCacheLRG]);
1064 
1065   for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1066     LRG &lrg = lrgs(i);
1067 
1068     // Check for being of low degree: means we can be trivially colored.
1069     // Low degree, dead or must-spill guys just get to simplify right away
1070     if( lrg.lo_degree() ||
1071        !lrg.alive() ||
1072         lrg._must_spill ) {
1073       // Split low degree list into those guys that must get a
1074       // register and those that can go to register or stack.
1075       // The idea is LRGs that can go register or stack color first when
1076       // they have a good chance of getting a register.  The register-only
1077       // lo-degree live ranges always get a register.
1078       OptoReg::Name hi_reg = lrg.mask().find_last_elem();
1079       if( OptoReg::is_stack(hi_reg)) { // Can go to stack?
1080         lrg._next = _lo_stk_degree;
1081         _lo_stk_degree = i;
1082       } else {
1083         lrg._next = _lo_degree;
1084         _lo_degree = i;
1085       }
1086     } else {                    // Else high degree
1087       lrgs(_hi_degree)._prev = i;
1088       lrg._next = _hi_degree;
1089       lrg._prev = 0;
1090       _hi_degree = i;
1091     }
1092   }
1093 }
1094 
1095 // Simplify the IFG by removing LRGs of low degree that have NO copies
1096 void PhaseChaitin::Pre_Simplify( ) {
1097 
1098   // Warm up the lo-degree no-copy list
1099   int lo_no_copy = 0;
1100   for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1101     if ((lrgs(i).lo_degree() && !lrgs(i)._has_copy) ||
1102         !lrgs(i).alive() ||
1103         lrgs(i)._must_spill) {
1104       lrgs(i)._next = lo_no_copy;
1105       lo_no_copy = i;
1106     }
1107   }
1108 
1109   while( lo_no_copy ) {
1110     uint lo = lo_no_copy;
1111     lo_no_copy = lrgs(lo)._next;
1112     int size = lrgs(lo).num_regs();
1113 
1114     // Put the simplified guy on the simplified list.
1115     lrgs(lo)._next = _simplified;
1116     _simplified = lo;
1117 
1118     // Yank this guy from the IFG.
1119     IndexSet *adj = _ifg->remove_node( lo );
1120 
1121     // If any neighbors' degrees fall below their number of
1122     // allowed registers, then put that neighbor on the low degree
1123     // list.  Note that 'degree' can only fall and 'numregs' is
1124     // unchanged by this action.  Thus the two are equal at most once,
1125     // so LRGs hit the lo-degree worklists at most once.
1126     IndexSetIterator elements(adj);
1127     uint neighbor;
1128     while ((neighbor = elements.next()) != 0) {
1129       LRG *n = &lrgs(neighbor);
1130       assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
1131 
1132       // Check for just becoming of-low-degree
1133       if( n->just_lo_degree() && !n->_has_copy ) {
1134         assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
1135         // Put on lo-degree list
1136         n->_next = lo_no_copy;
1137         lo_no_copy = neighbor;
1138       }
1139     }
1140   } // End of while lo-degree no_copy worklist not empty
1141 
1142   // No more lo-degree no-copy live ranges to simplify
1143 }
1144 
1145 // Simplify the IFG by removing LRGs of low degree.
1146 void PhaseChaitin::Simplify( ) {
1147   Compile::TracePhase tp("chaitinSimplify", &timers[_t_chaitinSimplify]);
1148 
1149   while( 1 ) {                  // Repeat till simplified it all
1150     // May want to explore simplifying lo_degree before _lo_stk_degree.
1151     // This might result in more spills coloring into registers during
1152     // Select().
1153     while( _lo_degree || _lo_stk_degree ) {
1154       // If possible, pull from lo_stk first
1155       uint lo;
1156       if( _lo_degree ) {
1157         lo = _lo_degree;
1158         _lo_degree = lrgs(lo)._next;
1159       } else {
1160         lo = _lo_stk_degree;
1161         _lo_stk_degree = lrgs(lo)._next;
1162       }
1163 
1164       // Put the simplified guy on the simplified list.
1165       lrgs(lo)._next = _simplified;
1166       _simplified = lo;
1167       // If this guy is "at risk" then mark his current neighbors
1168       if( lrgs(lo)._at_risk ) {
1169         IndexSetIterator elements(_ifg->neighbors(lo));
1170         uint datum;
1171         while ((datum = elements.next()) != 0) {
1172           lrgs(datum)._risk_bias = lo;
1173         }
1174       }
1175 
1176       // Yank this guy from the IFG.
1177       IndexSet *adj = _ifg->remove_node( lo );
1178 
1179       // If any neighbors' degrees fall below their number of
1180       // allowed registers, then put that neighbor on the low degree
1181       // list.  Note that 'degree' can only fall and 'numregs' is
1182       // unchanged by this action.  Thus the two are equal at most once,
1183       // so LRGs hit the lo-degree worklist at most once.
1184       IndexSetIterator elements(adj);
1185       uint neighbor;
1186       while ((neighbor = elements.next()) != 0) {
1187         LRG *n = &lrgs(neighbor);
1188 #ifdef ASSERT
1189         if( VerifyOpto || VerifyRegisterAllocator ) {
1190           assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
1191         }
1192 #endif
1193 
1194         // Check for just becoming of-low-degree just counting registers.
1195         // _must_spill live ranges are already on the low degree list.
1196         if( n->just_lo_degree() && !n->_must_spill ) {
1197           assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
1198           // Pull from hi-degree list
1199           uint prev = n->_prev;
1200           uint next = n->_next;
1201           if( prev ) lrgs(prev)._next = next;
1202           else _hi_degree = next;
1203           lrgs(next)._prev = prev;
1204           n->_next = _lo_degree;
1205           _lo_degree = neighbor;
1206         }
1207       }
1208     } // End of while lo-degree/lo_stk_degree worklist not empty
1209 
1210     // Check for got everything: is hi-degree list empty?
1211     if( !_hi_degree ) break;
1212 
1213     // Time to pick a potential spill guy
1214     uint lo_score = _hi_degree;
1215     double score = lrgs(lo_score).score();
1216     double area = lrgs(lo_score)._area;
1217     double cost = lrgs(lo_score)._cost;
1218     bool bound = lrgs(lo_score)._is_bound;
1219 
1220     // Find cheapest guy
1221     debug_only( int lo_no_simplify=0; );
1222     for( uint i = _hi_degree; i; i = lrgs(i)._next ) {
1223       assert( !(*_ifg->_yanked)[i], "" );
1224       // It's just vaguely possible to move hi-degree to lo-degree without
1225       // going through a just-lo-degree stage: If you remove a double from
1226       // a float live range it's degree will drop by 2 and you can skip the
1227       // just-lo-degree stage.  It's very rare (shows up after 5000+ methods
1228       // in -Xcomp of Java2Demo).  So just choose this guy to simplify next.
1229       if( lrgs(i).lo_degree() ) {
1230         lo_score = i;
1231         break;
1232       }
1233       debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; );
1234       double iscore = lrgs(i).score();
1235       double iarea = lrgs(i)._area;
1236       double icost = lrgs(i)._cost;
1237       bool ibound = lrgs(i)._is_bound;
1238 
1239       // Compare cost/area of i vs cost/area of lo_score.  Smaller cost/area
1240       // wins.  Ties happen because all live ranges in question have spilled
1241       // a few times before and the spill-score adds a huge number which
1242       // washes out the low order bits.  We are choosing the lesser of 2
1243       // evils; in this case pick largest area to spill.
1244       // Ties also happen when live ranges are defined and used only inside
1245       // one block. In which case their area is 0 and score set to max.
1246       // In such case choose bound live range over unbound to free registers
1247       // or with smaller cost to spill.
1248       if( iscore < score ||
1249           (iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) ||
1250           (iscore == score && iarea == area &&
1251            ( (ibound && !bound) || ibound == bound && (icost < cost) )) ) {
1252         lo_score = i;
1253         score = iscore;
1254         area = iarea;
1255         cost = icost;
1256         bound = ibound;
1257       }
1258     }
1259     LRG *lo_lrg = &lrgs(lo_score);
1260     // The live range we choose for spilling is either hi-degree, or very
1261     // rarely it can be low-degree.  If we choose a hi-degree live range
1262     // there better not be any lo-degree choices.
1263     assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" );
1264 
1265     // Pull from hi-degree list
1266     uint prev = lo_lrg->_prev;
1267     uint next = lo_lrg->_next;
1268     if( prev ) lrgs(prev)._next = next;
1269     else _hi_degree = next;
1270     lrgs(next)._prev = prev;
1271     // Jam him on the lo-degree list, despite his high degree.
1272     // Maybe he'll get a color, and maybe he'll spill.
1273     // Only Select() will know.
1274     lrgs(lo_score)._at_risk = true;
1275     _lo_degree = lo_score;
1276     lo_lrg->_next = 0;
1277 
1278   } // End of while not simplified everything
1279 
1280 }
1281 
1282 // Is 'reg' register legal for 'lrg'?
1283 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) {
1284   if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) &&
1285       lrg.mask().Member(OptoReg::add(reg,-chunk))) {
1286     // RA uses OptoReg which represent the highest element of a registers set.
1287     // For example, vectorX (128bit) on x86 uses [XMM,XMMb,XMMc,XMMd] set
1288     // in which XMMd is used by RA to represent such vectors. A double value
1289     // uses [XMM,XMMb] pairs and XMMb is used by RA for it.
1290     // The register mask uses largest bits set of overlapping register sets.
1291     // On x86 with AVX it uses 8 bits for each XMM registers set.
1292     //
1293     // The 'lrg' already has cleared-to-set register mask (done in Select()
1294     // before calling choose_color()). Passing mask.Member(reg) check above
1295     // indicates that the size (num_regs) of 'reg' set is less or equal to
1296     // 'lrg' set size.
1297     // For set size 1 any register which is member of 'lrg' mask is legal.
1298     if (lrg.num_regs()==1)
1299       return true;
1300     // For larger sets only an aligned register with the same set size is legal.
1301     int mask = lrg.num_regs()-1;
1302     if ((reg&mask) == mask)
1303       return true;
1304   }
1305   return false;
1306 }
1307 
1308 // Choose a color using the biasing heuristic
1309 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
1310 
1311   // Check for "at_risk" LRG's
1312   uint risk_lrg = _lrg_map.find(lrg._risk_bias);
1313   if( risk_lrg != 0 ) {
1314     // Walk the colored neighbors of the "at_risk" candidate
1315     // Choose a color which is both legal and already taken by a neighbor
1316     // of the "at_risk" candidate in order to improve the chances of the
1317     // "at_risk" candidate of coloring
1318     IndexSetIterator elements(_ifg->neighbors(risk_lrg));
1319     uint datum;
1320     while ((datum = elements.next()) != 0) {
1321       OptoReg::Name reg = lrgs(datum).reg();
1322       // If this LRG's register is legal for us, choose it
1323       if (is_legal_reg(lrg, reg, chunk))
1324         return reg;
1325     }
1326   }
1327 
1328   uint copy_lrg = _lrg_map.find(lrg._copy_bias);
1329   if( copy_lrg != 0 ) {
1330     // If he has a color,
1331     if( !(*(_ifg->_yanked))[copy_lrg] ) {
1332       OptoReg::Name reg = lrgs(copy_lrg).reg();
1333       //  And it is legal for you,
1334       if (is_legal_reg(lrg, reg, chunk))
1335         return reg;
1336     } else if( chunk == 0 ) {
1337       // Choose a color which is legal for him
1338       RegMask tempmask = lrg.mask();
1339       tempmask.AND(lrgs(copy_lrg).mask());
1340       tempmask.clear_to_sets(lrg.num_regs());
1341       OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs());
1342       if (OptoReg::is_valid(reg))
1343         return reg;
1344     }
1345   }
1346 
1347   // If no bias info exists, just go with the register selection ordering
1348   if (lrg._is_vector || lrg.num_regs() == 2) {
1349     // Find an aligned set
1350     return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk);
1351   }
1352 
1353   // CNC - Fun hack.  Alternate 1st and 2nd selection.  Enables post-allocate
1354   // copy removal to remove many more copies, by preventing a just-assigned
1355   // register from being repeatedly assigned.
1356   OptoReg::Name reg = lrg.mask().find_first_elem();
1357   if( (++_alternate & 1) && OptoReg::is_valid(reg) ) {
1358     // This 'Remove; find; Insert' idiom is an expensive way to find the
1359     // SECOND element in the mask.
1360     lrg.Remove(reg);
1361     OptoReg::Name reg2 = lrg.mask().find_first_elem();
1362     lrg.Insert(reg);
1363     if( OptoReg::is_reg(reg2))
1364       reg = reg2;
1365   }
1366   return OptoReg::add( reg, chunk );
1367 }
1368 
1369 // Choose a color in the current chunk
1370 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) {
1371   assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)");
1372   assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)");
1373 
1374   if( lrg.num_regs() == 1 ||    // Common Case
1375       !lrg._fat_proj )          // Aligned+adjacent pairs ok
1376     // Use a heuristic to "bias" the color choice
1377     return bias_color(lrg, chunk);
1378 
1379   assert(!lrg._is_vector, "should be not vector here" );
1380   assert( lrg.num_regs() >= 2, "dead live ranges do not color" );
1381 
1382   // Fat-proj case or misaligned double argument.
1383   assert(lrg.compute_mask_size() == lrg.num_regs() ||
1384          lrg.num_regs() == 2,"fat projs exactly color" );
1385   assert( !chunk, "always color in 1st chunk" );
1386   // Return the highest element in the set.
1387   return lrg.mask().find_last_elem();
1388 }
1389 
1390 // Select colors by re-inserting LRGs back into the IFG.  LRGs are re-inserted
1391 // in reverse order of removal.  As long as nothing of hi-degree was yanked,
1392 // everything going back is guaranteed a color.  Select that color.  If some
1393 // hi-degree LRG cannot get a color then we record that we must spill.
1394 uint PhaseChaitin::Select( ) {
1395   Compile::TracePhase tp("chaitinSelect", &timers[_t_chaitinSelect]);
1396 
1397   uint spill_reg = LRG::SPILL_REG;
1398   _max_reg = OptoReg::Name(0);  // Past max register used
1399   while( _simplified ) {
1400     // Pull next LRG from the simplified list - in reverse order of removal
1401     uint lidx = _simplified;
1402     LRG *lrg = &lrgs(lidx);
1403     _simplified = lrg->_next;
1404 
1405 
1406 #ifndef PRODUCT
1407     if (trace_spilling()) {
1408       ttyLocker ttyl;
1409       tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(),
1410                     lrg->degrees_of_freedom());
1411       lrg->dump();
1412     }
1413 #endif
1414 
1415     // Re-insert into the IFG
1416     _ifg->re_insert(lidx);
1417     if( !lrg->alive() ) continue;
1418     // capture allstackedness flag before mask is hacked
1419     const int is_allstack = lrg->mask().is_AllStack();
1420 
1421     // Yeah, yeah, yeah, I know, I know.  I can refactor this
1422     // to avoid the GOTO, although the refactored code will not
1423     // be much clearer.  We arrive here IFF we have a stack-based
1424     // live range that cannot color in the current chunk, and it
1425     // has to move into the next free stack chunk.
1426     int chunk = 0;              // Current chunk is first chunk
1427     retry_next_chunk:
1428 
1429     // Remove neighbor colors
1430     IndexSet *s = _ifg->neighbors(lidx);
1431 
1432     debug_only(RegMask orig_mask = lrg->mask();)
1433     IndexSetIterator elements(s);
1434     uint neighbor;
1435     while ((neighbor = elements.next()) != 0) {
1436       // Note that neighbor might be a spill_reg.  In this case, exclusion
1437       // of its color will be a no-op, since the spill_reg chunk is in outer
1438       // space.  Also, if neighbor is in a different chunk, this exclusion
1439       // will be a no-op.  (Later on, if lrg runs out of possible colors in
1440       // its chunk, a new chunk of color may be tried, in which case
1441       // examination of neighbors is started again, at retry_next_chunk.)
1442       LRG &nlrg = lrgs(neighbor);
1443       OptoReg::Name nreg = nlrg.reg();
1444       // Only subtract masks in the same chunk
1445       if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) {
1446 #ifndef PRODUCT
1447         uint size = lrg->mask().Size();
1448         RegMask rm = lrg->mask();
1449 #endif
1450         lrg->SUBTRACT(nlrg.mask());
1451 #ifndef PRODUCT
1452         if (trace_spilling() && lrg->mask().Size() != size) {
1453           ttyLocker ttyl;
1454           tty->print("L%d ", lidx);
1455           rm.dump();
1456           tty->print(" intersected L%d ", neighbor);
1457           nlrg.mask().dump();
1458           tty->print(" removed ");
1459           rm.SUBTRACT(lrg->mask());
1460           rm.dump();
1461           tty->print(" leaving ");
1462           lrg->mask().dump();
1463           tty->cr();
1464         }
1465 #endif
1466       }
1467     }
1468     //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness");
1469     // Aligned pairs need aligned masks
1470     assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1471     if (lrg->num_regs() > 1 && !lrg->_fat_proj) {
1472       lrg->clear_to_sets();
1473     }
1474 
1475     // Check if a color is available and if so pick the color
1476     OptoReg::Name reg = choose_color( *lrg, chunk );
1477 #ifdef SPARC
1478     debug_only(lrg->compute_set_mask_size());
1479     assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned");
1480 #endif
1481 
1482     //---------------
1483     // If we fail to color and the AllStack flag is set, trigger
1484     // a chunk-rollover event
1485     if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) {
1486       // Bump register mask up to next stack chunk
1487       chunk += RegMask::CHUNK_SIZE;
1488       lrg->Set_All();
1489 
1490       goto retry_next_chunk;
1491     }
1492 
1493     //---------------
1494     // Did we get a color?
1495     else if( OptoReg::is_valid(reg)) {
1496 #ifndef PRODUCT
1497       RegMask avail_rm = lrg->mask();
1498 #endif
1499 
1500       // Record selected register
1501       lrg->set_reg(reg);
1502 
1503       if( reg >= _max_reg )     // Compute max register limit
1504         _max_reg = OptoReg::add(reg,1);
1505       // Fold reg back into normal space
1506       reg = OptoReg::add(reg,-chunk);
1507 
1508       // If the live range is not bound, then we actually had some choices
1509       // to make.  In this case, the mask has more bits in it than the colors
1510       // chosen.  Restrict the mask to just what was picked.
1511       int n_regs = lrg->num_regs();
1512       assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1513       if (n_regs == 1 || !lrg->_fat_proj) {
1514         assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecY, "sanity");
1515         lrg->Clear();           // Clear the mask
1516         lrg->Insert(reg);       // Set regmask to match selected reg
1517         // For vectors and pairs, also insert the low bit of the pair
1518         for (int i = 1; i < n_regs; i++)
1519           lrg->Insert(OptoReg::add(reg,-i));
1520         lrg->set_mask_size(n_regs);
1521       } else {                  // Else fatproj
1522         // mask must be equal to fatproj bits, by definition
1523       }
1524 #ifndef PRODUCT
1525       if (trace_spilling()) {
1526         ttyLocker ttyl;
1527         tty->print("L%d selected ", lidx);
1528         lrg->mask().dump();
1529         tty->print(" from ");
1530         avail_rm.dump();
1531         tty->cr();
1532       }
1533 #endif
1534       // Note that reg is the highest-numbered register in the newly-bound mask.
1535     } // end color available case
1536 
1537     //---------------
1538     // Live range is live and no colors available
1539     else {
1540       assert( lrg->alive(), "" );
1541       assert( !lrg->_fat_proj || lrg->is_multidef() ||
1542               lrg->_def->outcnt() > 0, "fat_proj cannot spill");
1543       assert( !orig_mask.is_AllStack(), "All Stack does not spill" );
1544 
1545       // Assign the special spillreg register
1546       lrg->set_reg(OptoReg::Name(spill_reg++));
1547       // Do not empty the regmask; leave mask_size lying around
1548       // for use during Spilling
1549 #ifndef PRODUCT
1550       if( trace_spilling() ) {
1551         ttyLocker ttyl;
1552         tty->print("L%d spilling with neighbors: ", lidx);
1553         s->dump();
1554         debug_only(tty->print(" original mask: "));
1555         debug_only(orig_mask.dump());
1556         dump_lrg(lidx);
1557       }
1558 #endif
1559     } // end spill case
1560 
1561   }
1562 
1563   return spill_reg-LRG::SPILL_REG;      // Return number of spills
1564 }
1565 
1566 // Copy 'was_spilled'-edness from the source Node to the dst Node.
1567 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) {
1568   if( _spilled_once.test(src->_idx) ) {
1569     _spilled_once.set(dst->_idx);
1570     lrgs(_lrg_map.find(dst))._was_spilled1 = 1;
1571     if( _spilled_twice.test(src->_idx) ) {
1572       _spilled_twice.set(dst->_idx);
1573       lrgs(_lrg_map.find(dst))._was_spilled2 = 1;
1574     }
1575   }
1576 }
1577 
1578 // Set the 'spilled_once' or 'spilled_twice' flag on a node.
1579 void PhaseChaitin::set_was_spilled( Node *n ) {
1580   if( _spilled_once.test_set(n->_idx) )
1581     _spilled_twice.set(n->_idx);
1582 }
1583 
1584 // Convert Ideal spill instructions into proper FramePtr + offset Loads and
1585 // Stores.  Use-def chains are NOT preserved, but Node->LRG->reg maps are.
1586 void PhaseChaitin::fixup_spills() {
1587   // This function does only cisc spill work.
1588   if( !UseCISCSpill ) return;
1589 
1590   Compile::TracePhase tp("fixupSpills", &timers[_t_fixupSpills]);
1591 
1592   // Grab the Frame Pointer
1593   Node *fp = _cfg.get_root_block()->head()->in(1)->in(TypeFunc::FramePtr);
1594 
1595   // For all blocks
1596   for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1597     Block* block = _cfg.get_block(i);
1598 
1599     // For all instructions in block
1600     uint last_inst = block->end_idx();
1601     for (uint j = 1; j <= last_inst; j++) {
1602       Node* n = block->get_node(j);
1603 
1604       // Dead instruction???
1605       assert( n->outcnt() != 0 ||// Nothing dead after post alloc
1606               C->top() == n ||  // Or the random TOP node
1607               n->is_Proj(),     // Or a fat-proj kill node
1608               "No dead instructions after post-alloc" );
1609 
1610       int inp = n->cisc_operand();
1611       if( inp != AdlcVMDeps::Not_cisc_spillable ) {
1612         // Convert operand number to edge index number
1613         MachNode *mach = n->as_Mach();
1614         inp = mach->operand_index(inp);
1615         Node *src = n->in(inp);   // Value to load or store
1616         LRG &lrg_cisc = lrgs(_lrg_map.find_const(src));
1617         OptoReg::Name src_reg = lrg_cisc.reg();
1618         // Doubles record the HIGH register of an adjacent pair.
1619         src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs());
1620         if( OptoReg::is_stack(src_reg) ) { // If input is on stack
1621           // This is a CISC Spill, get stack offset and construct new node
1622 #ifndef PRODUCT
1623           if( TraceCISCSpill ) {
1624             tty->print("    reg-instr:  ");
1625             n->dump();
1626           }
1627 #endif
1628           int stk_offset = reg2offset(src_reg);
1629           // Bailout if we might exceed node limit when spilling this instruction
1630           C->check_node_count(0, "out of nodes fixing spills");
1631           if (C->failing())  return;
1632           // Transform node
1633           MachNode *cisc = mach->cisc_version(stk_offset)->as_Mach();
1634           cisc->set_req(inp,fp);          // Base register is frame pointer
1635           if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) {
1636             assert( cisc->oper_input_base() == 2, "Only adding one edge");
1637             cisc->ins_req(1,src);         // Requires a memory edge
1638           }
1639           block->map_node(cisc, j);          // Insert into basic block
1640           n->subsume_by(cisc, C); // Correct graph
1641           //
1642           ++_used_cisc_instructions;
1643 #ifndef PRODUCT
1644           if( TraceCISCSpill ) {
1645             tty->print("    cisc-instr: ");
1646             cisc->dump();
1647           }
1648 #endif
1649         } else {
1650 #ifndef PRODUCT
1651           if( TraceCISCSpill ) {
1652             tty->print("    using reg-instr: ");
1653             n->dump();
1654           }
1655 #endif
1656           ++_unused_cisc_instructions;    // input can be on stack
1657         }
1658       }
1659 
1660     } // End of for all instructions
1661 
1662   } // End of for all blocks
1663 }
1664 
1665 // Helper to stretch above; recursively discover the base Node for a
1666 // given derived Node.  Easy for AddP-related machine nodes, but needs
1667 // to be recursive for derived Phis.
1668 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) {
1669   // See if already computed; if so return it
1670   if( derived_base_map[derived->_idx] )
1671     return derived_base_map[derived->_idx];
1672 
1673   // See if this happens to be a base.
1674   // NOTE: we use TypePtr instead of TypeOopPtr because we can have
1675   // pointers derived from NULL!  These are always along paths that
1676   // can't happen at run-time but the optimizer cannot deduce it so
1677   // we have to handle it gracefully.
1678   assert(!derived->bottom_type()->isa_narrowoop() ||
1679           derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1680   const TypePtr *tj = derived->bottom_type()->isa_ptr();
1681   // If its an OOP with a non-zero offset, then it is derived.
1682   if( tj == NULL || tj->_offset == 0 ) {
1683     derived_base_map[derived->_idx] = derived;
1684     return derived;
1685   }
1686   // Derived is NULL+offset?  Base is NULL!
1687   if( derived->is_Con() ) {
1688     Node *base = _matcher.mach_null();
1689     assert(base != NULL, "sanity");
1690     if (base->in(0) == NULL) {
1691       // Initialize it once and make it shared:
1692       // set control to _root and place it into Start block
1693       // (where top() node is placed).
1694       base->init_req(0, _cfg.get_root_node());
1695       Block *startb = _cfg.get_block_for_node(C->top());
1696       uint node_pos = startb->find_node(C->top());
1697       startb->insert_node(base, node_pos);
1698       _cfg.map_node_to_block(base, startb);
1699       assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet");
1700 
1701       // The loadConP0 might have projection nodes depending on architecture
1702       // Add the projection nodes to the CFG
1703       for (DUIterator_Fast imax, i = base->fast_outs(imax); i < imax; i++) {
1704         Node* use = base->fast_out(i);
1705         if (use->is_MachProj()) {
1706           startb->insert_node(use, ++node_pos);
1707           _cfg.map_node_to_block(use, startb);
1708           new_lrg(use, maxlrg++);
1709         }
1710       }
1711     }
1712     if (_lrg_map.live_range_id(base) == 0) {
1713       new_lrg(base, maxlrg++);
1714     }
1715     assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared");
1716     derived_base_map[derived->_idx] = base;
1717     return base;
1718   }
1719 
1720   // Check for AddP-related opcodes
1721   if (!derived->is_Phi()) {
1722     assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, err_msg_res("but is: %s", derived->Name()));
1723     Node *base = derived->in(AddPNode::Base);
1724     derived_base_map[derived->_idx] = base;
1725     return base;
1726   }
1727 
1728   // Recursively find bases for Phis.
1729   // First check to see if we can avoid a base Phi here.
1730   Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg);
1731   uint i;
1732   for( i = 2; i < derived->req(); i++ )
1733     if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg))
1734       break;
1735   // Went to the end without finding any different bases?
1736   if( i == derived->req() ) {   // No need for a base Phi here
1737     derived_base_map[derived->_idx] = base;
1738     return base;
1739   }
1740 
1741   // Now we see we need a base-Phi here to merge the bases
1742   const Type *t = base->bottom_type();
1743   base = new PhiNode( derived->in(0), t );
1744   for( i = 1; i < derived->req(); i++ ) {
1745     base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg));
1746     t = t->meet(base->in(i)->bottom_type());
1747   }
1748   base->as_Phi()->set_type(t);
1749 
1750   // Search the current block for an existing base-Phi
1751   Block *b = _cfg.get_block_for_node(derived);
1752   for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi
1753     Node *phi = b->get_node(i);
1754     if( !phi->is_Phi() ) {      // Found end of Phis with no match?
1755       b->insert_node(base,  i); // Must insert created Phi here as base
1756       _cfg.map_node_to_block(base, b);
1757       new_lrg(base,maxlrg++);
1758       break;
1759     }
1760     // See if Phi matches.
1761     uint j;
1762     for( j = 1; j < base->req(); j++ )
1763       if( phi->in(j) != base->in(j) &&
1764           !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs
1765         break;
1766     if( j == base->req() ) {    // All inputs match?
1767       base = phi;               // Then use existing 'phi' and drop 'base'
1768       break;
1769     }
1770   }
1771 
1772 
1773   // Cache info for later passes
1774   derived_base_map[derived->_idx] = base;
1775   return base;
1776 }
1777 
1778 // At each Safepoint, insert extra debug edges for each pair of derived value/
1779 // base pointer that is live across the Safepoint for oopmap building.  The
1780 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the
1781 // required edge set.
1782 bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) {
1783   int must_recompute_live = false;
1784   uint maxlrg = _lrg_map.max_lrg_id();
1785   Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique());
1786   memset( derived_base_map, 0, sizeof(Node*)*C->unique() );
1787 
1788   // For all blocks in RPO do...
1789   for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
1790     Block* block = _cfg.get_block(i);
1791     // Note use of deep-copy constructor.  I cannot hammer the original
1792     // liveout bits, because they are needed by the following coalesce pass.
1793     IndexSet liveout(_live->live(block));
1794 
1795     for (uint j = block->end_idx() + 1; j > 1; j--) {
1796       Node* n = block->get_node(j - 1);
1797 
1798       // Pre-split compares of loop-phis.  Loop-phis form a cycle we would
1799       // like to see in the same register.  Compare uses the loop-phi and so
1800       // extends its live range BUT cannot be part of the cycle.  If this
1801       // extended live range overlaps with the update of the loop-phi value
1802       // we need both alive at the same time -- which requires at least 1
1803       // copy.  But because Intel has only 2-address registers we end up with
1804       // at least 2 copies, one before the loop-phi update instruction and
1805       // one after.  Instead we split the input to the compare just after the
1806       // phi.
1807       if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) {
1808         Node *phi = n->in(1);
1809         if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
1810           Block *phi_block = _cfg.get_block_for_node(phi);
1811           if (_cfg.get_block_for_node(phi_block->pred(2)) == block) {
1812             const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
1813             Node *spill = new MachSpillCopyNode(MachSpillCopyNode::LoopPhiInput, phi, *mask, *mask);
1814             insert_proj( phi_block, 1, spill, maxlrg++ );
1815             n->set_req(1,spill);
1816             must_recompute_live = true;
1817           }
1818         }
1819       }
1820 
1821       // Get value being defined
1822       uint lidx = _lrg_map.live_range_id(n);
1823       // Ignore the occasional brand-new live range
1824       if (lidx && lidx < _lrg_map.max_lrg_id()) {
1825         // Remove from live-out set
1826         liveout.remove(lidx);
1827 
1828         // Copies do not define a new value and so do not interfere.
1829         // Remove the copies source from the liveout set before interfering.
1830         uint idx = n->is_Copy();
1831         if (idx) {
1832           liveout.remove(_lrg_map.live_range_id(n->in(idx)));
1833         }
1834       }
1835 
1836       // Found a safepoint?
1837       JVMState *jvms = n->jvms();
1838       if( jvms ) {
1839         // Now scan for a live derived pointer
1840         IndexSetIterator elements(&liveout);
1841         uint neighbor;
1842         while ((neighbor = elements.next()) != 0) {
1843           // Find reaching DEF for base and derived values
1844           // This works because we are still in SSA during this call.
1845           Node *derived = lrgs(neighbor)._def;
1846           const TypePtr *tj = derived->bottom_type()->isa_ptr();
1847           assert(!derived->bottom_type()->isa_narrowoop() ||
1848                   derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1849           // If its an OOP with a non-zero offset, then it is derived.
1850           if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) {
1851             Node *base = find_base_for_derived(derived_base_map, derived, maxlrg);
1852             assert(base->_idx < _lrg_map.size(), "");
1853             // Add reaching DEFs of derived pointer and base pointer as a
1854             // pair of inputs
1855             n->add_req(derived);
1856             n->add_req(base);
1857 
1858             // See if the base pointer is already live to this point.
1859             // Since I'm working on the SSA form, live-ness amounts to
1860             // reaching def's.  So if I find the base's live range then
1861             // I know the base's def reaches here.
1862             if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or
1863                  !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND
1864                  (_lrg_map.live_range_id(base) > 0) && // not a constant
1865                  _cfg.get_block_for_node(base) != block) { // base not def'd in blk)
1866               // Base pointer is not currently live.  Since I stretched
1867               // the base pointer to here and it crosses basic-block
1868               // boundaries, the global live info is now incorrect.
1869               // Recompute live.
1870               must_recompute_live = true;
1871             } // End of if base pointer is not live to debug info
1872           }
1873         } // End of scan all live data for derived ptrs crossing GC point
1874       } // End of if found a GC point
1875 
1876       // Make all inputs live
1877       if (!n->is_Phi()) {      // Phi function uses come from prior block
1878         for (uint k = 1; k < n->req(); k++) {
1879           uint lidx = _lrg_map.live_range_id(n->in(k));
1880           if (lidx < _lrg_map.max_lrg_id()) {
1881             liveout.insert(lidx);
1882           }
1883         }
1884       }
1885 
1886     } // End of forall instructions in block
1887     liveout.clear();  // Free the memory used by liveout.
1888 
1889   } // End of forall blocks
1890   _lrg_map.set_max_lrg_id(maxlrg);
1891 
1892   // If I created a new live range I need to recompute live
1893   if (maxlrg != _ifg->_maxlrg) {
1894     must_recompute_live = true;
1895   }
1896 
1897   return must_recompute_live != 0;
1898 }
1899 
1900 // Extend the node to LRG mapping
1901 
1902 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) {
1903   _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node));
1904 }
1905 
1906 #ifndef PRODUCT
1907 void PhaseChaitin::dump(const Node *n) const {
1908   uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0;
1909   tty->print("L%d",r);
1910   if (r && n->Opcode() != Op_Phi) {
1911     if( _node_regs ) {          // Got a post-allocation copy of allocation?
1912       tty->print("[");
1913       OptoReg::Name second = get_reg_second(n);
1914       if( OptoReg::is_valid(second) ) {
1915         if( OptoReg::is_reg(second) )
1916           tty->print("%s:",Matcher::regName[second]);
1917         else
1918           tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second));
1919       }
1920       OptoReg::Name first = get_reg_first(n);
1921       if( OptoReg::is_reg(first) )
1922         tty->print("%s]",Matcher::regName[first]);
1923       else
1924          tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first));
1925     } else
1926     n->out_RegMask().dump();
1927   }
1928   tty->print("/N%d\t",n->_idx);
1929   tty->print("%s === ", n->Name());
1930   uint k;
1931   for (k = 0; k < n->req(); k++) {
1932     Node *m = n->in(k);
1933     if (!m) {
1934       tty->print("_ ");
1935     }
1936     else {
1937       uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1938       tty->print("L%d",r);
1939       // Data MultiNode's can have projections with no real registers.
1940       // Don't die while dumping them.
1941       int op = n->Opcode();
1942       if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) {
1943         if( _node_regs ) {
1944           tty->print("[");
1945           OptoReg::Name second = get_reg_second(n->in(k));
1946           if( OptoReg::is_valid(second) ) {
1947             if( OptoReg::is_reg(second) )
1948               tty->print("%s:",Matcher::regName[second]);
1949             else
1950               tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer),
1951                          reg2offset_unchecked(second));
1952           }
1953           OptoReg::Name first = get_reg_first(n->in(k));
1954           if( OptoReg::is_reg(first) )
1955             tty->print("%s]",Matcher::regName[first]);
1956           else
1957             tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer),
1958                        reg2offset_unchecked(first));
1959         } else
1960           n->in_RegMask(k).dump();
1961       }
1962       tty->print("/N%d ",m->_idx);
1963     }
1964   }
1965   if( k < n->len() && n->in(k) ) tty->print("| ");
1966   for( ; k < n->len(); k++ ) {
1967     Node *m = n->in(k);
1968     if(!m) {
1969       break;
1970     }
1971     uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1972     tty->print("L%d",r);
1973     tty->print("/N%d ",m->_idx);
1974   }
1975   if( n->is_Mach() ) n->as_Mach()->dump_spec(tty);
1976   else n->dump_spec(tty);
1977   if( _spilled_once.test(n->_idx ) ) {
1978     tty->print(" Spill_1");
1979     if( _spilled_twice.test(n->_idx ) )
1980       tty->print(" Spill_2");
1981   }
1982   tty->print("\n");
1983 }
1984 
1985 void PhaseChaitin::dump(const Block *b) const {
1986   b->dump_head(&_cfg);
1987 
1988   // For all instructions
1989   for( uint j = 0; j < b->number_of_nodes(); j++ )
1990     dump(b->get_node(j));
1991   // Print live-out info at end of block
1992   if( _live ) {
1993     tty->print("Liveout: ");
1994     IndexSet *live = _live->live(b);
1995     IndexSetIterator elements(live);
1996     tty->print("{");
1997     uint i;
1998     while ((i = elements.next()) != 0) {
1999       tty->print("L%d ", _lrg_map.find_const(i));
2000     }
2001     tty->print_cr("}");
2002   }
2003   tty->print("\n");
2004 }
2005 
2006 void PhaseChaitin::dump() const {
2007   tty->print( "--- Chaitin -- argsize: %d  framesize: %d ---\n",
2008               _matcher._new_SP, _framesize );
2009 
2010   // For all blocks
2011   for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
2012     dump(_cfg.get_block(i));
2013   }
2014   // End of per-block dump
2015   tty->print("\n");
2016 
2017   if (!_ifg) {
2018     tty->print("(No IFG.)\n");
2019     return;
2020   }
2021 
2022   // Dump LRG array
2023   tty->print("--- Live RanGe Array ---\n");
2024   for (uint i2 = 1; i2 < _lrg_map.max_lrg_id(); i2++) {
2025     tty->print("L%d: ",i2);
2026     if (i2 < _ifg->_maxlrg) {
2027       lrgs(i2).dump();
2028     }
2029     else {
2030       tty->print_cr("new LRG");
2031     }
2032   }
2033   tty->cr();
2034 
2035   // Dump lo-degree list
2036   tty->print("Lo degree: ");
2037   for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next )
2038     tty->print("L%d ",i3);
2039   tty->cr();
2040 
2041   // Dump lo-stk-degree list
2042   tty->print("Lo stk degree: ");
2043   for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next )
2044     tty->print("L%d ",i4);
2045   tty->cr();
2046 
2047   // Dump lo-degree list
2048   tty->print("Hi degree: ");
2049   for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next )
2050     tty->print("L%d ",i5);
2051   tty->cr();
2052 }
2053 
2054 void PhaseChaitin::dump_degree_lists() const {
2055   // Dump lo-degree list
2056   tty->print("Lo degree: ");
2057   for( uint i = _lo_degree; i; i = lrgs(i)._next )
2058     tty->print("L%d ",i);
2059   tty->cr();
2060 
2061   // Dump lo-stk-degree list
2062   tty->print("Lo stk degree: ");
2063   for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next )
2064     tty->print("L%d ",i2);
2065   tty->cr();
2066 
2067   // Dump lo-degree list
2068   tty->print("Hi degree: ");
2069   for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next )
2070     tty->print("L%d ",i3);
2071   tty->cr();
2072 }
2073 
2074 void PhaseChaitin::dump_simplified() const {
2075   tty->print("Simplified: ");
2076   for( uint i = _simplified; i; i = lrgs(i)._next )
2077     tty->print("L%d ",i);
2078   tty->cr();
2079 }
2080 
2081 static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) {
2082   if ((int)reg < 0)
2083     sprintf(buf, "<OptoReg::%d>", (int)reg);
2084   else if (OptoReg::is_reg(reg))
2085     strcpy(buf, Matcher::regName[reg]);
2086   else
2087     sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer),
2088             pc->reg2offset(reg));
2089   return buf+strlen(buf);
2090 }
2091 
2092 // Dump a register name into a buffer.  Be intelligent if we get called
2093 // before allocation is complete.
2094 char *PhaseChaitin::dump_register( const Node *n, char *buf  ) const {
2095   if( !this ) {                 // Not got anything?
2096     sprintf(buf,"N%d",n->_idx); // Then use Node index
2097   } else if( _node_regs ) {
2098     // Post allocation, use direct mappings, no LRG info available
2099     print_reg( get_reg_first(n), this, buf );
2100   } else {
2101     uint lidx = _lrg_map.find_const(n); // Grab LRG number
2102     if( !_ifg ) {
2103       sprintf(buf,"L%d",lidx);  // No register binding yet
2104     } else if( !lidx ) {        // Special, not allocated value
2105       strcpy(buf,"Special");
2106     } else {
2107       if (lrgs(lidx)._is_vector) {
2108         if (lrgs(lidx).mask().is_bound_set(lrgs(lidx).num_regs()))
2109           print_reg( lrgs(lidx).reg(), this, buf ); // a bound machine register
2110         else
2111           sprintf(buf,"L%d",lidx); // No register binding yet
2112       } else if( (lrgs(lidx).num_regs() == 1)
2113                  ? lrgs(lidx).mask().is_bound1()
2114                  : lrgs(lidx).mask().is_bound_pair() ) {
2115         // Hah!  We have a bound machine register
2116         print_reg( lrgs(lidx).reg(), this, buf );
2117       } else {
2118         sprintf(buf,"L%d",lidx); // No register binding yet
2119       }
2120     }
2121   }
2122   return buf+strlen(buf);
2123 }
2124 
2125 void PhaseChaitin::dump_for_spill_split_recycle() const {
2126   if( WizardMode && (PrintCompilation || PrintOpto) ) {
2127     // Display which live ranges need to be split and the allocator's state
2128     tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt);
2129     for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) {
2130       if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) {
2131         tty->print("L%d: ", bidx);
2132         lrgs(bidx).dump();
2133       }
2134     }
2135     tty->cr();
2136     dump();
2137   }
2138 }
2139 
2140 void PhaseChaitin::dump_frame() const {
2141   const char *fp = OptoReg::regname(OptoReg::c_frame_pointer);
2142   const TypeTuple *domain = C->tf()->domain();
2143   const int        argcnt = domain->cnt() - TypeFunc::Parms;
2144 
2145   // Incoming arguments in registers dump
2146   for( int k = 0; k < argcnt; k++ ) {
2147     OptoReg::Name parmreg = _matcher._parm_regs[k].first();
2148     if( OptoReg::is_reg(parmreg))  {
2149       const char *reg_name = OptoReg::regname(parmreg);
2150       tty->print("#r%3.3d %s", parmreg, reg_name);
2151       parmreg = _matcher._parm_regs[k].second();
2152       if( OptoReg::is_reg(parmreg))  {
2153         tty->print(":%s", OptoReg::regname(parmreg));
2154       }
2155       tty->print("   : parm %d: ", k);
2156       domain->field_at(k + TypeFunc::Parms)->dump();
2157       tty->cr();
2158     }
2159   }
2160 
2161   // Check for un-owned padding above incoming args
2162   OptoReg::Name reg = _matcher._new_SP;
2163   if( reg > _matcher._in_arg_limit ) {
2164     reg = OptoReg::add(reg, -1);
2165     tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg));
2166   }
2167 
2168   // Incoming argument area dump
2169   OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots());
2170   while( reg > begin_in_arg ) {
2171     reg = OptoReg::add(reg, -1);
2172     tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
2173     int j;
2174     for( j = 0; j < argcnt; j++) {
2175       if( _matcher._parm_regs[j].first() == reg ||
2176           _matcher._parm_regs[j].second() == reg ) {
2177         tty->print("parm %d: ",j);
2178         domain->field_at(j + TypeFunc::Parms)->dump();
2179         tty->cr();
2180         break;
2181       }
2182     }
2183     if( j >= argcnt )
2184       tty->print_cr("HOLE, owned by SELF");
2185   }
2186 
2187   // Old outgoing preserve area
2188   while( reg > _matcher._old_SP ) {
2189     reg = OptoReg::add(reg, -1);
2190     tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg));
2191   }
2192 
2193   // Old SP
2194   tty->print_cr("# -- Old %s -- Framesize: %d --",fp,
2195     reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize);
2196 
2197   // Preserve area dump
2198   int fixed_slots = C->fixed_slots();
2199   OptoReg::Name begin_in_preserve = OptoReg::add(_matcher._old_SP, -(int)C->in_preserve_stack_slots());
2200   OptoReg::Name return_addr = _matcher.return_addr();
2201 
2202   reg = OptoReg::add(reg, -1);
2203   while (OptoReg::is_stack(reg)) {
2204     tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
2205     if (return_addr == reg) {
2206       tty->print_cr("return address");
2207     } else if (reg >= begin_in_preserve) {
2208       // Preserved slots are present on x86
2209       if (return_addr == OptoReg::add(reg, VMRegImpl::slots_per_word))
2210         tty->print_cr("saved fp register");
2211       else if (return_addr == OptoReg::add(reg, 2*VMRegImpl::slots_per_word) &&
2212                VerifyStackAtCalls)
2213         tty->print_cr("0xBADB100D   +VerifyStackAtCalls");
2214       else
2215         tty->print_cr("in_preserve");
2216     } else if ((int)OptoReg::reg2stack(reg) < fixed_slots) {
2217       tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg));
2218     } else {
2219       tty->print_cr("pad2, stack alignment");
2220     }
2221     reg = OptoReg::add(reg, -1);
2222   }
2223 
2224   // Spill area dump
2225   reg = OptoReg::add(_matcher._new_SP, _framesize );
2226   while( reg > _matcher._out_arg_limit ) {
2227     reg = OptoReg::add(reg, -1);
2228     tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg));
2229   }
2230 
2231   // Outgoing argument area dump
2232   while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) {
2233     reg = OptoReg::add(reg, -1);
2234     tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg));
2235   }
2236 
2237   // Outgoing new preserve area
2238   while( reg > _matcher._new_SP ) {
2239     reg = OptoReg::add(reg, -1);
2240     tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg));
2241   }
2242   tty->print_cr("#");
2243 }
2244 
2245 void PhaseChaitin::dump_bb( uint pre_order ) const {
2246   tty->print_cr("---dump of B%d---",pre_order);
2247   for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
2248     Block* block = _cfg.get_block(i);
2249     if (block->_pre_order == pre_order) {
2250       dump(block);
2251     }
2252   }
2253 }
2254 
2255 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const {
2256   tty->print_cr("---dump of L%d---",lidx);
2257 
2258   if (_ifg) {
2259     if (lidx >= _lrg_map.max_lrg_id()) {
2260       tty->print("Attempt to print live range index beyond max live range.\n");
2261       return;
2262     }
2263     tty->print("L%d: ",lidx);
2264     if (lidx < _ifg->_maxlrg) {
2265       lrgs(lidx).dump();
2266     } else {
2267       tty->print_cr("new LRG");
2268     }
2269   }
2270   if( _ifg && lidx < _ifg->_maxlrg) {
2271     tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx));
2272     _ifg->neighbors(lidx)->dump();
2273     tty->cr();
2274   }
2275   // For all blocks
2276   for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
2277     Block* block = _cfg.get_block(i);
2278     int dump_once = 0;
2279 
2280     // For all instructions
2281     for( uint j = 0; j < block->number_of_nodes(); j++ ) {
2282       Node *n = block->get_node(j);
2283       if (_lrg_map.find_const(n) == lidx) {
2284         if (!dump_once++) {
2285           tty->cr();
2286           block->dump_head(&_cfg);
2287         }
2288         dump(n);
2289         continue;
2290       }
2291       if (!defs_only) {
2292         uint cnt = n->req();
2293         for( uint k = 1; k < cnt; k++ ) {
2294           Node *m = n->in(k);
2295           if (!m)  {
2296             continue;  // be robust in the dumper
2297           }
2298           if (_lrg_map.find_const(m) == lidx) {
2299             if (!dump_once++) {
2300               tty->cr();
2301               block->dump_head(&_cfg);
2302             }
2303             dump(n);
2304           }
2305         }
2306       }
2307     }
2308   } // End of per-block dump
2309   tty->cr();
2310 }
2311 #endif // not PRODUCT
2312 
2313 int PhaseChaitin::_final_loads  = 0;
2314 int PhaseChaitin::_final_stores = 0;
2315 int PhaseChaitin::_final_memoves= 0;
2316 int PhaseChaitin::_final_copies = 0;
2317 double PhaseChaitin::_final_load_cost  = 0;
2318 double PhaseChaitin::_final_store_cost = 0;
2319 double PhaseChaitin::_final_memove_cost= 0;
2320 double PhaseChaitin::_final_copy_cost  = 0;
2321 int PhaseChaitin::_conserv_coalesce = 0;
2322 int PhaseChaitin::_conserv_coalesce_pair = 0;
2323 int PhaseChaitin::_conserv_coalesce_trie = 0;
2324 int PhaseChaitin::_conserv_coalesce_quad = 0;
2325 int PhaseChaitin::_post_alloc = 0;
2326 int PhaseChaitin::_lost_opp_pp_coalesce = 0;
2327 int PhaseChaitin::_lost_opp_cflow_coalesce = 0;
2328 int PhaseChaitin::_used_cisc_instructions   = 0;
2329 int PhaseChaitin::_unused_cisc_instructions = 0;
2330 int PhaseChaitin::_allocator_attempts       = 0;
2331 int PhaseChaitin::_allocator_successes      = 0;
2332 
2333 #ifndef PRODUCT
2334 uint PhaseChaitin::_high_pressure           = 0;
2335 uint PhaseChaitin::_low_pressure            = 0;
2336 
2337 void PhaseChaitin::print_chaitin_statistics() {
2338   tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies);
2339   tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost);
2340   tty->print_cr("Adjusted spill cost = %7.0f.",
2341                 _final_load_cost*4.0 + _final_store_cost  * 2.0 +
2342                 _final_copy_cost*1.0 + _final_memove_cost*12.0);
2343   tty->print("Conservatively coalesced %d copies, %d pairs",
2344                 _conserv_coalesce, _conserv_coalesce_pair);
2345   if( _conserv_coalesce_trie || _conserv_coalesce_quad )
2346     tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad);
2347   tty->print_cr(", %d post alloc.", _post_alloc);
2348   if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce )
2349     tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.",
2350                   _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce );
2351   if( _used_cisc_instructions || _unused_cisc_instructions )
2352     tty->print_cr("Used cisc instruction  %d,  remained in register %d",
2353                    _used_cisc_instructions, _unused_cisc_instructions);
2354   if( _allocator_successes != 0 )
2355     tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes);
2356   tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure);
2357 }
2358 #endif // not PRODUCT