1 /*
   2  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.inline.hpp"
  27 #include "memory/resourceArea.hpp"
  28 #include "runtime/java.hpp"
  29 #include "runtime/os.hpp"
  30 #include "runtime/stubCodeGenerator.hpp"
  31 #include "vm_version_sparc.hpp"
  32 
  33 unsigned int VM_Version::_L2_data_cache_line_size = 0;
  34 
  35 void VM_Version::initialize() {
  36   assert(_features != 0, "System pre-initialization is not complete.");
  37   guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
  38 
  39   PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
  40   PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
  41   PrefetchFieldsAhead         = prefetch_fields_ahead();
  42 
  43   // Allocation prefetch settings
  44   intx cache_line_size = prefetch_data_size();
  45   if( cache_line_size > AllocatePrefetchStepSize )
  46     AllocatePrefetchStepSize = cache_line_size;
  47 
  48   AllocatePrefetchDistance = allocate_prefetch_distance();
  49   AllocatePrefetchStyle    = allocate_prefetch_style();
  50 
  51   if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
  52     warning("BIS instructions are not available on this CPU");
  53     FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
  54   }
  55 
  56   UseSSE = 0; // Only on x86 and x64
  57 
  58   _supports_cx8 = has_v9();
  59   _supports_atomic_getset4 = true; // swap instruction
  60 
  61   if (is_niagara()) {
  62     // Indirect branch is the same cost as direct
  63     if (FLAG_IS_DEFAULT(UseInlineCaches)) {
  64       FLAG_SET_DEFAULT(UseInlineCaches, false);
  65     }
  66     // Align loops on a single instruction boundary.
  67     if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
  68       FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
  69     }
  70 #ifdef _LP64
  71     // 32-bit oops don't make sense for the 64-bit VM on sparc
  72     // since the 32-bit VM has the same registers and smaller objects.
  73     Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
  74     Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
  75 #endif // _LP64
  76 #ifdef COMPILER2
  77     // Indirect branch is the same cost as direct
  78     if (FLAG_IS_DEFAULT(UseJumpTables)) {
  79       FLAG_SET_DEFAULT(UseJumpTables, true);
  80     }
  81     // Single-issue, so entry and loop tops are
  82     // aligned on a single instruction boundary
  83     if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
  84       FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
  85     }
  86     if (is_niagara_plus()) {
  87       if (has_blk_init() && UseTLAB &&
  88           FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
  89         // Use BIS instruction for TLAB allocation prefetch.
  90         FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
  91         if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
  92           FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
  93         }
  94         if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
  95           // Use smaller prefetch distance with BIS
  96           FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
  97         }
  98       }
  99       if (is_T4()) {
 100         // Double number of prefetched cache lines on T4
 101         // since L2 cache line size is smaller (32 bytes).
 102         if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
 103           FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
 104         }
 105         if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
 106           FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
 107         }
 108       }
 109       if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
 110         // Use different prefetch distance without BIS
 111         FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
 112       }
 113       if (AllocatePrefetchInstr == 1) {
 114         // Need a space at the end of TLAB for BIS since it
 115         // will fault when accessing memory outside of heap.
 116 
 117         // +1 for rounding up to next cache line, +1 to be safe
 118         int lines = AllocatePrefetchLines + 2;
 119         int step_size = AllocatePrefetchStepSize;
 120         int distance = AllocatePrefetchDistance;
 121         _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
 122       }
 123     }
 124 #endif
 125   }
 126 
 127   // Use hardware population count instruction if available.
 128   if (has_hardware_popc()) {
 129     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
 130       FLAG_SET_DEFAULT(UsePopCountInstruction, true);
 131     }
 132   } else if (UsePopCountInstruction) {
 133     warning("POPC instruction is not available on this CPU");
 134     FLAG_SET_DEFAULT(UsePopCountInstruction, false);
 135   }
 136 
 137   // T4 and newer Sparc cpus have new compare and branch instruction.
 138   if (has_cbcond()) {
 139     if (FLAG_IS_DEFAULT(UseCBCond)) {
 140       FLAG_SET_DEFAULT(UseCBCond, true);
 141     }
 142   } else if (UseCBCond) {
 143     warning("CBCOND instruction is not available on this CPU");
 144     FLAG_SET_DEFAULT(UseCBCond, false);
 145   }
 146 
 147   assert(BlockZeroingLowLimit > 0, "invalid value");
 148   if (has_block_zeroing() && cache_line_size > 0) {
 149     if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
 150       FLAG_SET_DEFAULT(UseBlockZeroing, true);
 151     }
 152   } else if (UseBlockZeroing) {
 153     warning("BIS zeroing instructions are not available on this CPU");
 154     FLAG_SET_DEFAULT(UseBlockZeroing, false);
 155   }
 156 
 157   assert(BlockCopyLowLimit > 0, "invalid value");
 158   if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
 159     if (FLAG_IS_DEFAULT(UseBlockCopy)) {
 160       FLAG_SET_DEFAULT(UseBlockCopy, true);
 161     }
 162   } else if (UseBlockCopy) {
 163     warning("BIS instructions are not available or expensive on this CPU");
 164     FLAG_SET_DEFAULT(UseBlockCopy, false);
 165   }
 166 
 167 #ifdef COMPILER2
 168   // T4 and newer Sparc cpus have fast RDPC.
 169   if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
 170     FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
 171   }
 172 
 173   // Currently not supported anywhere.
 174   FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 175 
 176   MaxVectorSize = 8;
 177 
 178   assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 179 #endif
 180 
 181   assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 182   assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
 183 
 184   char buf[512];
 185   jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 186                (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
 187                (has_hardware_popc() ? ", popc" : ""),
 188                (has_vis1() ? ", vis1" : ""),
 189                (has_vis2() ? ", vis2" : ""),
 190                (has_vis3() ? ", vis3" : ""),
 191                (has_blk_init() ? ", blk_init" : ""),
 192                (has_cbcond() ? ", cbcond" : ""),
 193                (has_aes() ? ", aes" : ""),
 194                (has_sha1() ? ", sha1" : ""),
 195                (has_sha256() ? ", sha256" : ""),
 196                (has_sha512() ? ", sha512" : ""),
 197                (has_crc32c() ? ", crc32c" : ""),
 198                (is_ultra3() ? ", ultra3" : ""),
 199                (is_sun4v() ? ", sun4v" : ""),
 200                (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
 201                (is_sparc64() ? ", sparc64" : ""),
 202                (!has_hardware_mul32() ? ", no-mul32" : ""),
 203                (!has_hardware_div32() ? ", no-div32" : ""),
 204                (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
 205 
 206   // buf is started with ", " or is empty
 207   _features_string = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
 208 
 209   // UseVIS is set to the smallest of what hardware supports and what
 210   // the command line requires.  I.e., you cannot set UseVIS to 3 on
 211   // older UltraSparc which do not support it.
 212   if (UseVIS > 3) UseVIS=3;
 213   if (UseVIS < 0) UseVIS=0;
 214   if (!has_vis3()) // Drop to 2 if no VIS3 support
 215     UseVIS = MIN2((intx)2,UseVIS);
 216   if (!has_vis2()) // Drop to 1 if no VIS2 support
 217     UseVIS = MIN2((intx)1,UseVIS);
 218   if (!has_vis1()) // Drop to 0 if no VIS1 support
 219     UseVIS = 0;
 220 
 221   // SPARC T4 and above should have support for AES instructions
 222   if (has_aes()) {
 223     if (FLAG_IS_DEFAULT(UseAES)) {
 224       FLAG_SET_DEFAULT(UseAES, true);
 225     }
 226     if (!UseAES) {
 227       if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 228         warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
 229       }
 230       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 231     } else {
 232       // The AES intrinsic stubs require AES instruction support (of course)
 233       // but also require VIS3 mode or higher for instructions it use.
 234       if (UseVIS > 2) {
 235         if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 236           FLAG_SET_DEFAULT(UseAESIntrinsics, true);
 237         }
 238       } else {
 239         if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 240           warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
 241         }
 242         FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 243       }
 244     }
 245   } else if (UseAES || UseAESIntrinsics) {
 246     if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
 247       warning("AES instructions are not available on this CPU");
 248       FLAG_SET_DEFAULT(UseAES, false);
 249     }
 250     if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 251       warning("AES intrinsics are not available on this CPU");
 252       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 253     }
 254   }
 255 
 256   if (UseAESCTRIntrinsics) {
 257     warning("AES/CTR intrinsics are not available on this CPU");
 258     FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 259   }
 260 
 261   // GHASH/GCM intrinsics
 262   if (has_vis3() && (UseVIS > 2)) {
 263     if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
 264       UseGHASHIntrinsics = true;
 265     }
 266   } else if (UseGHASHIntrinsics) {
 267     if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
 268       warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
 269     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 270   }
 271 
 272   // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
 273   if (has_sha1() || has_sha256() || has_sha512()) {
 274     if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
 275       if (FLAG_IS_DEFAULT(UseSHA)) {
 276         FLAG_SET_DEFAULT(UseSHA, true);
 277       }
 278     } else {
 279       if (UseSHA) {
 280         warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
 281         FLAG_SET_DEFAULT(UseSHA, false);
 282       }
 283     }
 284   } else if (UseSHA) {
 285     warning("SHA instructions are not available on this CPU");
 286     FLAG_SET_DEFAULT(UseSHA, false);
 287   }
 288 
 289   if (UseSHA && has_sha1()) {
 290     if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
 291       FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
 292     }
 293   } else if (UseSHA1Intrinsics) {
 294     warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
 295     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 296   }
 297 
 298   if (UseSHA && has_sha256()) {
 299     if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
 300       FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
 301     }
 302   } else if (UseSHA256Intrinsics) {
 303     warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
 304     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 305   }
 306 
 307   if (UseSHA && has_sha512()) {
 308     if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
 309       FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
 310     }
 311   } else if (UseSHA512Intrinsics) {
 312     warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
 313     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 314   }
 315 
 316   if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
 317     FLAG_SET_DEFAULT(UseSHA, false);
 318   }
 319 
 320   // SPARC T4 and above should have support for CRC32C instruction
 321   if (has_crc32c()) {
 322     if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
 323       if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 324         FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
 325       }
 326     } else {
 327       if (UseCRC32CIntrinsics) {
 328         warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
 329         FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 330       }
 331     }
 332   } else if (UseCRC32CIntrinsics) {
 333     warning("CRC32C instruction is not available on this CPU");
 334     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 335   }
 336 
 337   if (UseVIS > 2) {
 338     if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
 339       FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
 340     }
 341   } else if (UseAdler32Intrinsics) {
 342     warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
 343     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
 344   }
 345 
 346   if (UseVIS > 2) {
 347     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 348       FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
 349     }
 350   } else if (UseCRC32Intrinsics) {
 351     warning("SPARC CRC32 intrinsics require VIS3 insructions support. Intriniscs will be disabled");
 352     FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
 353   }
 354 
 355   if (UseVectorizedMismatchIntrinsic) {
 356     warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
 357     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
 358   }
 359 
 360   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
 361     (cache_line_size > ContendedPaddingWidth))
 362     ContendedPaddingWidth = cache_line_size;
 363 
 364   // This machine does not allow unaligned memory accesses
 365   if (UseUnalignedAccesses) {
 366     if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
 367       warning("Unaligned memory access is not available on this CPU");
 368     FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
 369   }
 370 
 371   if (PrintMiscellaneous && Verbose) {
 372     tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
 373     tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
 374     tty->print("Allocation");
 375     if (AllocatePrefetchStyle <= 0) {
 376       tty->print_cr(": no prefetching");
 377     } else {
 378       tty->print(" prefetching: ");
 379       if (AllocatePrefetchInstr == 0) {
 380           tty->print("PREFETCH");
 381       } else if (AllocatePrefetchInstr == 1) {
 382           tty->print("BIS");
 383       }
 384       if (AllocatePrefetchLines > 1) {
 385         tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
 386       } else {
 387         tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
 388       }
 389     }
 390     if (PrefetchCopyIntervalInBytes > 0) {
 391       tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
 392     }
 393     if (PrefetchScanIntervalInBytes > 0) {
 394       tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
 395     }
 396     if (PrefetchFieldsAhead > 0) {
 397       tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
 398     }
 399     if (ContendedPaddingWidth > 0) {
 400       tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
 401     }
 402   }
 403 }
 404 
 405 void VM_Version::print_features() {
 406   tty->print_cr("Version:%s", _features);
 407 }
 408 
 409 int VM_Version::determine_features() {
 410   if (UseV8InstrsOnly) {
 411     if (PrintMiscellaneous && Verbose) { tty->print_cr("Version is Forced-V8"); }
 412     return generic_v8_m;
 413   }
 414 
 415   int features = platform_features(unknown_m); // platform_features() is os_arch specific
 416 
 417   if (features == unknown_m) {
 418     features = generic_v9_m;
 419     warning("Cannot recognize SPARC version. Default to V9");
 420   }
 421 
 422   assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
 423   if (UseNiagaraInstrs) { // Force code generation for Niagara
 424     if (is_T_family(features)) {
 425       // Happy to accomodate...
 426     } else {
 427       if (PrintMiscellaneous && Verbose) { tty->print_cr("Version is Forced-Niagara"); }
 428       features |= T_family_m;
 429     }
 430   } else {
 431     if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
 432       if (PrintMiscellaneous && Verbose) { tty->print_cr("Version is Forced-Not-Niagara"); }
 433       features &= ~(T_family_m | T1_model_m);
 434     } else {
 435       // Happy to accomodate...
 436     }
 437   }
 438 
 439   return features;
 440 }
 441 
 442 static uint64_t saved_features = 0;
 443 
 444 void VM_Version::allow_all() {
 445   saved_features = _features;
 446   _features      = all_features_m;
 447 }
 448 
 449 void VM_Version::revert() {
 450   _features = saved_features;
 451 }
 452 
 453 unsigned int VM_Version::calc_parallel_worker_threads() {
 454   unsigned int result;
 455   if (is_M_series()) {
 456     // for now, use same gc thread calculation for M-series as for niagara-plus
 457     // in future, we may want to tweak parameters for nof_parallel_worker_thread
 458     result = nof_parallel_worker_threads(5, 16, 8);
 459   } else if (is_niagara_plus()) {
 460     result = nof_parallel_worker_threads(5, 16, 8);
 461   } else {
 462     result = nof_parallel_worker_threads(5, 8, 8);
 463   }
 464   return result;
 465 }


































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