1 /*
   2  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP
  26 #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP
  27 
  28 #include "runtime/globals_extension.hpp"
  29 #include "runtime/vm_version.hpp"
  30 
  31 class VM_Version: public Abstract_VM_Version {
  32   friend class VMStructs;
  33   friend class JVMCIVMStructs;
  34 
  35 protected:
  36   enum Feature_Flag {
  37     v8_instructions      = 0,
  38     hardware_mul32       = 1,
  39     hardware_div32       = 2,
  40     hardware_fsmuld      = 3,
  41     hardware_popc        = 4,
  42     v9_instructions      = 5,
  43     vis1_instructions    = 6,
  44     vis2_instructions    = 7,
  45     sun4v_instructions   = 8,
  46     blk_init_instructions = 9,
  47     fmaf_instructions    = 10,
  48     fmau_instructions    = 11,
  49     vis3_instructions    = 12,
  50     cbcond_instructions  = 13,
  51     sparc64_family       = 14,
  52     M_family             = 15,
  53     T_family             = 16,
  54     T1_model             = 17,
  55     sparc5_instructions  = 18,
  56     aes_instructions     = 19,
  57     sha1_instruction     = 20,
  58     sha256_instruction   = 21,
  59     sha512_instruction   = 22,
  60     crc32c_instruction   = 23
  61   };
  62 
  63   enum Feature_Flag_Set {
  64     unknown_m           = 0,
  65     all_features_m      = -1,
  66 
  67     v8_instructions_m       = 1 << v8_instructions,
  68     hardware_mul32_m        = 1 << hardware_mul32,
  69     hardware_div32_m        = 1 << hardware_div32,
  70     hardware_fsmuld_m       = 1 << hardware_fsmuld,
  71     hardware_popc_m         = 1 << hardware_popc,
  72     v9_instructions_m       = 1 << v9_instructions,
  73     vis1_instructions_m     = 1 << vis1_instructions,
  74     vis2_instructions_m     = 1 << vis2_instructions,
  75     sun4v_m                 = 1 << sun4v_instructions,
  76     blk_init_instructions_m = 1 << blk_init_instructions,
  77     fmaf_instructions_m     = 1 << fmaf_instructions,
  78     fmau_instructions_m     = 1 << fmau_instructions,
  79     vis3_instructions_m     = 1 << vis3_instructions,
  80     cbcond_instructions_m   = 1 << cbcond_instructions,
  81     sparc64_family_m        = 1 << sparc64_family,
  82     M_family_m              = 1 << M_family,
  83     T_family_m              = 1 << T_family,
  84     T1_model_m              = 1 << T1_model,
  85     sparc5_instructions_m   = 1 << sparc5_instructions,
  86     aes_instructions_m      = 1 << aes_instructions,
  87     sha1_instruction_m      = 1 << sha1_instruction,
  88     sha256_instruction_m    = 1 << sha256_instruction,
  89     sha512_instruction_m    = 1 << sha512_instruction,
  90     crc32c_instruction_m    = 1 << crc32c_instruction,
  91 
  92     generic_v8_m        = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
  93     generic_v9_m        = generic_v8_m | v9_instructions_m,
  94     ultra3_m            = generic_v9_m | vis1_instructions_m | vis2_instructions_m,
  95 
  96     // Temporary until we have something more accurate
  97     niagara1_unique_m   = sun4v_m,
  98     niagara1_m          = generic_v9_m | niagara1_unique_m
  99   };
 100 
 101   static unsigned int _L2_data_cache_line_size;
 102   static unsigned int L2_data_cache_line_size() { return _L2_data_cache_line_size; }
 103 
 104   static void print_features();
 105   static int  determine_features();
 106   static int  platform_features(int features);
 107 
 108   // Returns true if the platform is in the niagara line (T series)
 109   static bool is_M_family(int features) { return (features & M_family_m) != 0; }
 110   static bool is_T_family(int features) { return (features & T_family_m) != 0; }
 111   static bool is_niagara() { return is_T_family(_features); }
 112 #ifdef ASSERT
 113   static bool is_niagara(int features)  {
 114     // 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as
 115     // on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'.
 116     return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0;
 117   }
 118 #endif
 119 
 120   // Returns true if it is niagara1 (T1).
 121   static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); }
 122 
 123   static int maximum_niagara1_processor_count() { return 32; }
 124 
 125 public:
 126   // Initialization
 127   static void initialize();
 128 
 129   static void init_before_ergo()        { _features = determine_features(); }
 130 
 131   // Instruction support
 132   static bool has_v8()                  { return (_features & v8_instructions_m) != 0; }
 133   static bool has_v9()                  { return (_features & v9_instructions_m) != 0; }
 134   static bool has_hardware_mul32()      { return (_features & hardware_mul32_m) != 0; }
 135   static bool has_hardware_div32()      { return (_features & hardware_div32_m) != 0; }
 136   static bool has_hardware_fsmuld()     { return (_features & hardware_fsmuld_m) != 0; }
 137   static bool has_hardware_popc()       { return (_features & hardware_popc_m) != 0; }
 138   static bool has_vis1()                { return (_features & vis1_instructions_m) != 0; }
 139   static bool has_vis2()                { return (_features & vis2_instructions_m) != 0; }
 140   static bool has_vis3()                { return (_features & vis3_instructions_m) != 0; }
 141   static bool has_blk_init()            { return (_features & blk_init_instructions_m) != 0; }
 142   static bool has_cbcond()              { return (_features & cbcond_instructions_m) != 0; }
 143   static bool has_sparc5_instr()        { return (_features & sparc5_instructions_m) != 0; }
 144   static bool has_aes()                 { return (_features & aes_instructions_m) != 0; }
 145   static bool has_sha1()                { return (_features & sha1_instruction_m) != 0; }
 146   static bool has_sha256()              { return (_features & sha256_instruction_m) != 0; }
 147   static bool has_sha512()              { return (_features & sha512_instruction_m) != 0; }
 148   static bool has_crc32c()              { return (_features & crc32c_instruction_m) != 0; }
 149 
 150   static bool supports_compare_and_exchange()
 151                                         { return has_v9(); }
 152 
 153   // Returns true if the platform is in the niagara line (T series)
 154   // and newer than the niagara1.
 155   static bool is_niagara_plus()         { return is_T_family(_features) && !is_T1_model(_features); }
 156 
 157   static bool is_M_series()             { return is_M_family(_features); }
 158   static bool is_T4()                   { return is_T_family(_features) && has_cbcond(); }
 159   static bool is_T7()                   { return is_T_family(_features) && has_sparc5_instr(); }
 160 
 161   // Fujitsu SPARC64
 162   static bool is_sparc64()              { return (_features & sparc64_family_m) != 0; }
 163 
 164   static bool is_sun4v()                { return (_features & sun4v_m) != 0; }
 165   static bool is_ultra3()               { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }
 166 
 167   static bool has_fast_fxtof()          { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
 168   static bool has_fast_idiv()           { return is_niagara_plus() || is_sparc64(); }
 169 
 170   // T4 and newer Sparc have fast RDPC instruction.
 171   static bool has_fast_rdpc()           { return is_T4(); }
 172 
 173   // On T4 and newer Sparc BIS to the beginning of cache line always zeros it.
 174   static bool has_block_zeroing()       { return has_blk_init() && is_T4(); }
 175 
 176   // default prefetch block size on sparc
 177   static intx prefetch_data_size()      { return L2_data_cache_line_size();  }
 178 
 179   // Prefetch
 180   static intx prefetch_copy_interval_in_bytes() {
 181     intx interval = PrefetchCopyIntervalInBytes;
 182     return interval >= 0 ? interval : (has_v9() ? 512 : 0);
 183   }
 184   static intx prefetch_scan_interval_in_bytes() {
 185     intx interval = PrefetchScanIntervalInBytes;
 186     return interval >= 0 ? interval : (has_v9() ? 512 : 0);
 187   }
 188   static intx prefetch_fields_ahead() {
 189     intx count = PrefetchFieldsAhead;
 190     return count >= 0 ? count : (is_ultra3() ? 1 : 0);
 191   }
 192 
 193   static intx allocate_prefetch_distance() {
 194     // This method should be called before allocate_prefetch_style().
 195     intx count = AllocatePrefetchDistance;
 196     if (count < 0) { // default is not defined ?
 197       count = 512;
 198     }
 199     return count;
 200   }
 201   static intx allocate_prefetch_style() {
 202     assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
 203     // Return 0 if AllocatePrefetchDistance was not defined.
 204     return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
 205   }
 206 
 207   // Assembler testing
 208   static void allow_all();
 209   static void revert();
 210 
 211   // Override the Abstract_VM_Version implementation.
 212   static uint page_size_count() { return is_sun4v() ? 4 : 2; }
 213 
 214   // Calculates the number of parallel threads
 215   static unsigned int calc_parallel_worker_threads();
 216 };
 217 
 218 #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP