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src/cpu/x86/vm/assembler_x86.cpp

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3031   assert(VM_Version::supports_sse4_1(), "");
3032   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ true,
3033                                       VEX_OPCODE_0F_3A, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3034   emit_int8(0x16);
3035   emit_int8((unsigned char)(0xC0 | encode));
3036   emit_int8(imm8);
3037 }
3038 
3039 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3040   assert(VM_Version::supports_sse4_1(), "");
3041   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, /* no_mask_reg */  true,
3042                                       VEX_OPCODE_0F_3A, /* rex_w */ true, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3043   emit_int8(0x16);
3044   emit_int8((unsigned char)(0xC0 | encode));
3045   emit_int8(imm8);
3046 }
3047 
3048 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3049   assert(VM_Version::supports_sse2(), "");
3050   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ true,
3051                                       VEX_OPCODE_0F_3A, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3052   emit_int8(0x15);
3053   emit_int8((unsigned char)(0xC0 | encode));
3054   emit_int8(imm8);
3055 }
3056 
3057 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3058   assert(VM_Version::supports_sse4_1(), "");
3059   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, /* no_mask_reg */ true,
3060                                       VEX_OPCODE_0F_3A, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3061   emit_int8(0x22);
3062   emit_int8((unsigned char)(0xC0 | encode));
3063   emit_int8(imm8);
3064 }
3065 
3066 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3067   assert(VM_Version::supports_sse4_1(), "");
3068   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, /* no_mask_reg */ true,
3069                                       VEX_OPCODE_0F_3A, /* rex_w */ true, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3070   emit_int8(0x22);
3071   emit_int8((unsigned char)(0xC0 | encode));
3072   emit_int8(imm8);




3031   assert(VM_Version::supports_sse4_1(), "");
3032   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ true,
3033                                       VEX_OPCODE_0F_3A, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3034   emit_int8(0x16);
3035   emit_int8((unsigned char)(0xC0 | encode));
3036   emit_int8(imm8);
3037 }
3038 
3039 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3040   assert(VM_Version::supports_sse4_1(), "");
3041   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, /* no_mask_reg */  true,
3042                                       VEX_OPCODE_0F_3A, /* rex_w */ true, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3043   emit_int8(0x16);
3044   emit_int8((unsigned char)(0xC0 | encode));
3045   emit_int8(imm8);
3046 }
3047 
3048 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3049   assert(VM_Version::supports_sse2(), "");
3050   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, /* no_mask_reg */ true,
3051                                       VEX_OPCODE_0F, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_bw);
3052   emit_int8((unsigned char)0xC5);
3053   emit_int8((unsigned char)(0xC0 | encode));
3054   emit_int8(imm8);
3055 }
3056 
3057 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3058   assert(VM_Version::supports_sse4_1(), "");
3059   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, /* no_mask_reg */ true,
3060                                       VEX_OPCODE_0F_3A, /* rex_w */ false, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3061   emit_int8(0x22);
3062   emit_int8((unsigned char)(0xC0 | encode));
3063   emit_int8(imm8);
3064 }
3065 
3066 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3067   assert(VM_Version::supports_sse4_1(), "");
3068   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, /* no_mask_reg */ true,
3069                                       VEX_OPCODE_0F_3A, /* rex_w */ true, AVX_128bit, /* legacy_mode */ _legacy_mode_dq);
3070   emit_int8(0x22);
3071   emit_int8((unsigned char)(0xC0 | encode));
3072   emit_int8(imm8);


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