1 /* 2 * Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2016, 2017, SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "c1/c1_Compilation.hpp" 28 #include "c1/c1_LIRAssembler.hpp" 29 #include "c1/c1_MacroAssembler.hpp" 30 #include "c1/c1_Runtime1.hpp" 31 #include "c1/c1_ValueStack.hpp" 32 #include "ci/ciArrayKlass.hpp" 33 #include "ci/ciInstance.hpp" 34 #include "gc/shared/collectedHeap.hpp" 35 #include "gc/shared/barrierSet.hpp" 36 #include "gc/shared/cardTableModRefBS.hpp" 37 #include "nativeInst_s390.hpp" 38 #include "oops/objArrayKlass.hpp" 39 #include "runtime/sharedRuntime.hpp" 40 #include "vmreg_s390.inline.hpp" 41 42 #define __ _masm-> 43 44 #ifndef PRODUCT 45 #undef __ 46 #define __ (Verbose ? (_masm->block_comment(FILE_AND_LINE),_masm) : _masm)-> 47 #endif 48 49 //------------------------------------------------------------ 50 51 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 52 // Not used on ZARCH_64 53 ShouldNotCallThis(); 54 return false; 55 } 56 57 LIR_Opr LIR_Assembler::receiverOpr() { 58 return FrameMap::Z_R2_oop_opr; 59 } 60 61 LIR_Opr LIR_Assembler::osrBufferPointer() { 62 return FrameMap::Z_R2_opr; 63 } 64 65 int LIR_Assembler::initial_frame_size_in_bytes() const { 66 return in_bytes(frame_map()->framesize_in_bytes()); 67 } 68 69 // Inline cache check: done before the frame is built. 70 // The inline cached class is in Z_inline_cache(Z_R9). 71 // We fetch the class of the receiver and compare it with the cached class. 72 // If they do not match we jump to the slow case. 73 int LIR_Assembler::check_icache() { 74 Register receiver = receiverOpr()->as_register(); 75 int offset = __ offset(); 76 __ inline_cache_check(receiver, Z_inline_cache); 77 return offset; 78 } 79 80 void LIR_Assembler::osr_entry() { 81 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp): 82 // 83 // 1. Create a new compiled activation. 84 // 2. Initialize local variables in the compiled activation. The expression stack must be empty 85 // at the osr_bci; it is not initialized. 86 // 3. Jump to the continuation address in compiled code to resume execution. 87 88 // OSR entry point 89 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 90 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 91 ValueStack* entry_state = osr_entry->end()->state(); 92 int number_of_locks = entry_state->locks_size(); 93 94 // Create a frame for the compiled activation. 95 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 96 97 // OSR buffer is 98 // 99 // locals[nlocals-1..0] 100 // monitors[number_of_locks-1..0] 101 // 102 // Locals is a direct copy of the interpreter frame so in the osr buffer 103 // the first slot in the local array is the last local from the interpreter 104 // and the last slot is local[0] (receiver) from the interpreter 105 // 106 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 107 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 108 // in the interpreter frame (the method lock if a sync method) 109 110 // Initialize monitors in the compiled activation. 111 // I0: pointer to osr buffer 112 // 113 // All other registers are dead at this point and the locals will be 114 // copied into place by code emitted in the IR. 115 116 Register OSR_buf = osrBufferPointer()->as_register(); 117 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 118 int monitor_offset = BytesPerWord * method()->max_locals() + 119 (2 * BytesPerWord) * (number_of_locks - 1); 120 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 121 // the OSR buffer using 2 word entries: first the lock and then 122 // the oop. 123 for (int i = 0; i < number_of_locks; i++) { 124 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 125 // Verify the interpreter's monitor has a non-null object. 126 __ asm_assert_mem8_isnot_zero(slot_offset + 1*BytesPerWord, OSR_buf, "locked object is NULL", __LINE__); 127 // Copy the lock field into the compiled activation. 128 __ z_lg(Z_R1_scratch, slot_offset + 0, OSR_buf); 129 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_lock(i)); 130 __ z_lg(Z_R1_scratch, slot_offset + 1*BytesPerWord, OSR_buf); 131 __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_object(i)); 132 } 133 } 134 } 135 136 // -------------------------------------------------------------------------------------------- 137 138 address LIR_Assembler::emit_call_c(address a) { 139 __ align_call_far_patchable(__ pc()); 140 address call_addr = __ call_c_opt(a); 141 if (call_addr == NULL) { 142 bailout("const section overflow"); 143 } 144 return call_addr; 145 } 146 147 int LIR_Assembler::emit_exception_handler() { 148 // If the last instruction is a call (typically to do a throw which 149 // is coming at the end after block reordering) the return address 150 // must still point into the code area in order to avoid assertion 151 // failures when searching for the corresponding bci. => Add a nop. 152 // (was bug 5/14/1999 - gri) 153 __ nop(); 154 155 // Generate code for exception handler. 156 address handler_base = __ start_a_stub(exception_handler_size()); 157 if (handler_base == NULL) { 158 // Not enough space left for the handler. 159 bailout("exception handler overflow"); 160 return -1; 161 } 162 163 int offset = code_offset(); 164 165 address a = Runtime1::entry_for (Runtime1::handle_exception_from_callee_id); 166 address call_addr = emit_call_c(a); 167 CHECK_BAILOUT_(-1); 168 __ should_not_reach_here(); 169 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 170 __ end_a_stub(); 171 172 return offset; 173 } 174 175 // Emit the code to remove the frame from the stack in the exception 176 // unwind path. 177 int LIR_Assembler::emit_unwind_handler() { 178 #ifndef PRODUCT 179 if (CommentedAssembly) { 180 _masm->block_comment("Unwind handler"); 181 } 182 #endif 183 184 int offset = code_offset(); 185 Register exception_oop_callee_saved = Z_R10; // Z_R10 is callee-saved. 186 Register Rtmp1 = Z_R11; 187 Register Rtmp2 = Z_R12; 188 189 // Fetch the exception from TLS and clear out exception related thread state. 190 Address exc_oop_addr = Address(Z_thread, JavaThread::exception_oop_offset()); 191 Address exc_pc_addr = Address(Z_thread, JavaThread::exception_pc_offset()); 192 __ z_lg(Z_EXC_OOP, exc_oop_addr); 193 __ clear_mem(exc_oop_addr, sizeof(oop)); 194 __ clear_mem(exc_pc_addr, sizeof(intptr_t)); 195 196 __ bind(_unwind_handler_entry); 197 __ verify_not_null_oop(Z_EXC_OOP); 198 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 199 __ lgr_if_needed(exception_oop_callee_saved, Z_EXC_OOP); // Preserve the exception. 200 } 201 202 // Preform needed unlocking. 203 MonitorExitStub* stub = NULL; 204 if (method()->is_synchronized()) { 205 // Runtime1::monitorexit_id expects lock address in Z_R1_scratch. 206 LIR_Opr lock = FrameMap::as_opr(Z_R1_scratch); 207 monitor_address(0, lock); 208 stub = new MonitorExitStub(lock, true, 0); 209 __ unlock_object(Rtmp1, Rtmp2, lock->as_register(), *stub->entry()); 210 __ bind(*stub->continuation()); 211 } 212 213 if (compilation()->env()->dtrace_method_probes()) { 214 ShouldNotReachHere(); // Not supported. 215 #if 0 216 __ mov(rdi, r15_thread); 217 __ mov_metadata(rsi, method()->constant_encoding()); 218 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 219 #endif 220 } 221 222 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 223 __ lgr_if_needed(Z_EXC_OOP, exception_oop_callee_saved); // Restore the exception. 224 } 225 226 // Remove the activation and dispatch to the unwind handler. 227 __ pop_frame(); 228 __ z_lg(Z_EXC_PC, _z_abi16(return_pc), Z_SP); 229 230 // Z_EXC_OOP: exception oop 231 // Z_EXC_PC: exception pc 232 233 // Dispatch to the unwind logic. 234 __ load_const_optimized(Z_R5, Runtime1::entry_for (Runtime1::unwind_exception_id)); 235 __ z_br(Z_R5); 236 237 // Emit the slow path assembly. 238 if (stub != NULL) { 239 stub->emit_code(this); 240 } 241 242 return offset; 243 } 244 245 int LIR_Assembler::emit_deopt_handler() { 246 // If the last instruction is a call (typically to do a throw which 247 // is coming at the end after block reordering) the return address 248 // must still point into the code area in order to avoid assertion 249 // failures when searching for the corresponding bci. => Add a nop. 250 // (was bug 5/14/1999 - gri) 251 __ nop(); 252 253 // Generate code for exception handler. 254 address handler_base = __ start_a_stub(deopt_handler_size()); 255 if (handler_base == NULL) { 256 // Not enough space left for the handler. 257 bailout("deopt handler overflow"); 258 return -1; 259 } int offset = code_offset(); 260 // Size must be constant (see HandlerImpl::emit_deopt_handler). 261 __ load_const(Z_R1_scratch, SharedRuntime::deopt_blob()->unpack()); 262 __ call(Z_R1_scratch); 263 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 264 __ end_a_stub(); 265 266 return offset; 267 } 268 269 void LIR_Assembler::jobject2reg(jobject o, Register reg) { 270 if (o == NULL) { 271 __ clear_reg(reg, true/*64bit*/, false/*set cc*/); // Must not kill cc set by cmove. 272 } else { 273 AddressLiteral a = __ allocate_oop_address(o); 274 bool success = __ load_oop_from_toc(reg, a, reg); 275 if (!success) { 276 bailout("const section overflow"); 277 } 278 } 279 } 280 281 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { 282 // Allocate a new index in table to hold the object once it's been patched. 283 int oop_index = __ oop_recorder()->allocate_oop_index(NULL); 284 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index); 285 286 AddressLiteral addrlit((intptr_t)0, oop_Relocation::spec(oop_index)); 287 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); 288 // The NULL will be dynamically patched later so the sequence to 289 // load the address literal must not be optimized. 290 __ load_const(reg, addrlit); 291 292 patching_epilog(patch, lir_patch_normal, reg, info); 293 } 294 295 void LIR_Assembler::metadata2reg(Metadata* md, Register reg) { 296 bool success = __ set_metadata_constant(md, reg); 297 if (!success) { 298 bailout("const section overflow"); 299 return; 300 } 301 } 302 303 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) { 304 // Allocate a new index in table to hold the klass once it's been patched. 305 int index = __ oop_recorder()->allocate_metadata_index(NULL); 306 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index); 307 AddressLiteral addrlit((intptr_t)0, metadata_Relocation::spec(index)); 308 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc"); 309 // The NULL will be dynamically patched later so the sequence to 310 // load the address literal must not be optimized. 311 __ load_const(reg, addrlit); 312 313 patching_epilog(patch, lir_patch_normal, reg, info); 314 } 315 316 void LIR_Assembler::emit_op3(LIR_Op3* op) { 317 switch (op->code()) { 318 case lir_idiv: 319 case lir_irem: 320 arithmetic_idiv(op->code(), 321 op->in_opr1(), 322 op->in_opr2(), 323 op->in_opr3(), 324 op->result_opr(), 325 op->info()); 326 break; 327 case lir_fmad: { 328 const FloatRegister opr1 = op->in_opr1()->as_double_reg(), 329 opr2 = op->in_opr2()->as_double_reg(), 330 opr3 = op->in_opr3()->as_double_reg(), 331 res = op->result_opr()->as_double_reg(); 332 __ z_madbr(opr3, opr1, opr2); 333 if (res != opr3) { __ z_ldr(res, opr3); } 334 } break; 335 case lir_fmaf: { 336 const FloatRegister opr1 = op->in_opr1()->as_float_reg(), 337 opr2 = op->in_opr2()->as_float_reg(), 338 opr3 = op->in_opr3()->as_float_reg(), 339 res = op->result_opr()->as_float_reg(); 340 __ z_maebr(opr3, opr1, opr2); 341 if (res != opr3) { __ z_ler(res, opr3); } 342 } break; 343 default: ShouldNotReachHere(); break; 344 } 345 } 346 347 348 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 349 #ifdef ASSERT 350 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 351 if (op->block() != NULL) { _branch_target_blocks.append(op->block()); } 352 if (op->ublock() != NULL) { _branch_target_blocks.append(op->ublock()); } 353 #endif 354 355 if (op->cond() == lir_cond_always) { 356 if (op->info() != NULL) { add_debug_info_for_branch(op->info()); } 357 __ branch_optimized(Assembler::bcondAlways, *(op->label())); 358 } else { 359 Assembler::branch_condition acond = Assembler::bcondZero; 360 if (op->code() == lir_cond_float_branch) { 361 assert(op->ublock() != NULL, "must have unordered successor"); 362 __ branch_optimized(Assembler::bcondNotOrdered, *(op->ublock()->label())); 363 } 364 switch (op->cond()) { 365 case lir_cond_equal: acond = Assembler::bcondEqual; break; 366 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; break; 367 case lir_cond_less: acond = Assembler::bcondLow; break; 368 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; break; 369 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; break; 370 case lir_cond_greater: acond = Assembler::bcondHigh; break; 371 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; break; 372 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; break; 373 default: ShouldNotReachHere(); 374 } 375 __ branch_optimized(acond,*(op->label())); 376 } 377 } 378 379 380 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 381 LIR_Opr src = op->in_opr(); 382 LIR_Opr dest = op->result_opr(); 383 384 switch (op->bytecode()) { 385 case Bytecodes::_i2l: 386 __ move_reg_if_needed(dest->as_register_lo(), T_LONG, src->as_register(), T_INT); 387 break; 388 389 case Bytecodes::_l2i: 390 __ move_reg_if_needed(dest->as_register(), T_INT, src->as_register_lo(), T_LONG); 391 break; 392 393 case Bytecodes::_i2b: 394 __ move_reg_if_needed(dest->as_register(), T_BYTE, src->as_register(), T_INT); 395 break; 396 397 case Bytecodes::_i2c: 398 __ move_reg_if_needed(dest->as_register(), T_CHAR, src->as_register(), T_INT); 399 break; 400 401 case Bytecodes::_i2s: 402 __ move_reg_if_needed(dest->as_register(), T_SHORT, src->as_register(), T_INT); 403 break; 404 405 case Bytecodes::_f2d: 406 assert(dest->is_double_fpu(), "check"); 407 __ move_freg_if_needed(dest->as_double_reg(), T_DOUBLE, src->as_float_reg(), T_FLOAT); 408 break; 409 410 case Bytecodes::_d2f: 411 assert(dest->is_single_fpu(), "check"); 412 __ move_freg_if_needed(dest->as_float_reg(), T_FLOAT, src->as_double_reg(), T_DOUBLE); 413 break; 414 415 case Bytecodes::_i2f: 416 __ z_cefbr(dest->as_float_reg(), src->as_register()); 417 break; 418 419 case Bytecodes::_i2d: 420 __ z_cdfbr(dest->as_double_reg(), src->as_register()); 421 break; 422 423 case Bytecodes::_l2f: 424 __ z_cegbr(dest->as_float_reg(), src->as_register_lo()); 425 break; 426 case Bytecodes::_l2d: 427 __ z_cdgbr(dest->as_double_reg(), src->as_register_lo()); 428 break; 429 430 case Bytecodes::_f2i: 431 case Bytecodes::_f2l: { 432 Label done; 433 FloatRegister Rsrc = src->as_float_reg(); 434 Register Rdst = (op->bytecode() == Bytecodes::_f2i ? dest->as_register() : dest->as_register_lo()); 435 __ clear_reg(Rdst, true, false); 436 __ z_cebr(Rsrc, Rsrc); 437 __ z_brno(done); // NaN -> 0 438 if (op->bytecode() == Bytecodes::_f2i) { 439 __ z_cfebr(Rdst, Rsrc, Assembler::to_zero); 440 } else { // op->bytecode() == Bytecodes::_f2l 441 __ z_cgebr(Rdst, Rsrc, Assembler::to_zero); 442 } 443 __ bind(done); 444 } 445 break; 446 447 case Bytecodes::_d2i: 448 case Bytecodes::_d2l: { 449 Label done; 450 FloatRegister Rsrc = src->as_double_reg(); 451 Register Rdst = (op->bytecode() == Bytecodes::_d2i ? dest->as_register() : dest->as_register_lo()); 452 __ clear_reg(Rdst, true, false); // Don't set CC. 453 __ z_cdbr(Rsrc, Rsrc); 454 __ z_brno(done); // NaN -> 0 455 if (op->bytecode() == Bytecodes::_d2i) { 456 __ z_cfdbr(Rdst, Rsrc, Assembler::to_zero); 457 } else { // Bytecodes::_d2l 458 __ z_cgdbr(Rdst, Rsrc, Assembler::to_zero); 459 } 460 __ bind(done); 461 } 462 break; 463 464 default: ShouldNotReachHere(); 465 } 466 } 467 468 void LIR_Assembler::align_call(LIR_Code code) { 469 // End of call instruction must be 4 byte aligned. 470 int offset = __ offset(); 471 switch (code) { 472 case lir_icvirtual_call: 473 offset += MacroAssembler::load_const_from_toc_size(); 474 // no break 475 case lir_static_call: 476 case lir_optvirtual_call: 477 case lir_dynamic_call: 478 offset += NativeCall::call_far_pcrelative_displacement_offset; 479 break; 480 case lir_virtual_call: // currently, sparc-specific for niagara 481 default: ShouldNotReachHere(); 482 } 483 if ((offset & (NativeCall::call_far_pcrelative_displacement_alignment-1)) != 0) { 484 __ nop(); 485 } 486 } 487 488 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 489 assert((__ offset() + NativeCall::call_far_pcrelative_displacement_offset) % NativeCall::call_far_pcrelative_displacement_alignment == 0, 490 "must be aligned (offset=%d)", __ offset()); 491 assert(rtype == relocInfo::none || 492 rtype == relocInfo::opt_virtual_call_type || 493 rtype == relocInfo::static_call_type, "unexpected rtype"); 494 // Prepend each BRASL with a nop. 495 __ relocate(rtype); 496 __ z_nop(); 497 __ z_brasl(Z_R14, op->addr()); 498 add_call_info(code_offset(), op->info()); 499 } 500 501 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 502 address virtual_call_oop_addr = NULL; 503 AddressLiteral empty_ic((address) Universe::non_oop_word()); 504 virtual_call_oop_addr = __ pc(); 505 bool success = __ load_const_from_toc(Z_inline_cache, empty_ic); 506 if (!success) { 507 bailout("const section overflow"); 508 return; 509 } 510 511 // CALL to fixup routine. Fixup routine uses ScopeDesc info 512 // to determine who we intended to call. 513 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); 514 call(op, relocInfo::none); 515 } 516 517 // not supported 518 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 519 ShouldNotReachHere(); 520 } 521 522 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 523 if (from_reg != to_reg) __ z_lgr(to_reg, from_reg); 524 } 525 526 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 527 assert(src->is_constant(), "should not call otherwise"); 528 assert(dest->is_stack(), "should not call otherwise"); 529 LIR_Const* c = src->as_constant_ptr(); 530 531 unsigned int lmem = 0; 532 unsigned int lcon = 0; 533 int64_t cbits = 0; 534 Address dest_addr; 535 switch (c->type()) { 536 case T_INT: // fall through 537 case T_FLOAT: 538 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 539 lmem = 4; lcon = 4; cbits = c->as_jint_bits(); 540 break; 541 542 case T_ADDRESS: 543 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 544 lmem = 8; lcon = 4; cbits = c->as_jint_bits(); 545 break; 546 547 case T_OBJECT: 548 dest_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 549 if (c->as_jobject() == NULL) { 550 __ store_const(dest_addr, (int64_t)NULL_WORD, 8, 8); 551 } else { 552 jobject2reg(c->as_jobject(), Z_R1_scratch); 553 __ reg2mem_opt(Z_R1_scratch, dest_addr, true); 554 } 555 return; 556 557 case T_LONG: // fall through 558 case T_DOUBLE: 559 dest_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 560 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits()); 561 break; 562 563 default: 564 ShouldNotReachHere(); 565 } 566 567 __ store_const(dest_addr, cbits, lmem, lcon); 568 } 569 570 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 571 assert(src->is_constant(), "should not call otherwise"); 572 assert(dest->is_address(), "should not call otherwise"); 573 // See special case in LIRGenerator::do_StoreIndexed. 574 // T_BYTE: Special case for card mark store. 575 assert(type == T_BYTE || !dest->as_address_ptr()->index()->is_valid(), "not supported"); 576 LIR_Const* c = src->as_constant_ptr(); 577 Address addr = as_Address(dest->as_address_ptr()); 578 579 int store_offset = -1; 580 unsigned int lmem = 0; 581 unsigned int lcon = 0; 582 int64_t cbits = 0; 583 switch (type) { 584 case T_INT: // fall through 585 case T_FLOAT: 586 lmem = 4; lcon = 4; cbits = c->as_jint_bits(); 587 break; 588 589 case T_ADDRESS: 590 lmem = 8; lcon = 4; cbits = c->as_jint_bits(); 591 break; 592 593 case T_OBJECT: // fall through 594 case T_ARRAY: 595 if (c->as_jobject() == NULL) { 596 if (UseCompressedOops && !wide) { 597 store_offset = __ store_const(addr, (int32_t)NULL_WORD, 4, 4); 598 } else { 599 store_offset = __ store_const(addr, (int64_t)NULL_WORD, 8, 8); 600 } 601 } else { 602 jobject2reg(c->as_jobject(), Z_R1_scratch); 603 if (UseCompressedOops && !wide) { 604 __ encode_heap_oop(Z_R1_scratch); 605 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false); 606 } else { 607 store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true); 608 } 609 } 610 assert(store_offset >= 0, "check"); 611 break; 612 613 case T_LONG: // fall through 614 case T_DOUBLE: 615 lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits()); 616 break; 617 618 case T_BOOLEAN: // fall through 619 case T_BYTE: 620 lmem = 1; lcon = 1; cbits = (int8_t)(c->as_jint()); 621 break; 622 623 case T_CHAR: // fall through 624 case T_SHORT: 625 lmem = 2; lcon = 2; cbits = (int16_t)(c->as_jint()); 626 break; 627 628 default: 629 ShouldNotReachHere(); 630 }; 631 632 // Index register is normally not supported, but for 633 // LIRGenerator::CardTableModRef_post_barrier we make an exception. 634 if (type == T_BYTE && dest->as_address_ptr()->index()->is_valid()) { 635 __ load_const_optimized(Z_R0_scratch, (int8_t)(c->as_jint())); 636 store_offset = __ offset(); 637 if (Immediate::is_uimm12(addr.disp())) { 638 __ z_stc(Z_R0_scratch, addr); 639 } else { 640 __ z_stcy(Z_R0_scratch, addr); 641 } 642 } 643 644 if (store_offset == -1) { 645 store_offset = __ store_const(addr, cbits, lmem, lcon); 646 assert(store_offset >= 0, "check"); 647 } 648 649 if (info != NULL) { 650 add_debug_info_for_null_check(store_offset, info); 651 } 652 } 653 654 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 655 assert(src->is_constant(), "should not call otherwise"); 656 assert(dest->is_register(), "should not call otherwise"); 657 LIR_Const* c = src->as_constant_ptr(); 658 659 switch (c->type()) { 660 case T_INT: { 661 assert(patch_code == lir_patch_none, "no patching handled here"); 662 __ load_const_optimized(dest->as_register(), c->as_jint()); 663 break; 664 } 665 666 case T_ADDRESS: { 667 assert(patch_code == lir_patch_none, "no patching handled here"); 668 __ load_const_optimized(dest->as_register(), c->as_jint()); 669 break; 670 } 671 672 case T_LONG: { 673 assert(patch_code == lir_patch_none, "no patching handled here"); 674 __ load_const_optimized(dest->as_register_lo(), (intptr_t)c->as_jlong()); 675 break; 676 } 677 678 case T_OBJECT: { 679 if (patch_code != lir_patch_none) { 680 jobject2reg_with_patching(dest->as_register(), info); 681 } else { 682 jobject2reg(c->as_jobject(), dest->as_register()); 683 } 684 break; 685 } 686 687 case T_METADATA: { 688 if (patch_code != lir_patch_none) { 689 klass2reg_with_patching(dest->as_register(), info); 690 } else { 691 metadata2reg(c->as_metadata(), dest->as_register()); 692 } 693 break; 694 } 695 696 case T_FLOAT: { 697 Register toc_reg = Z_R1_scratch; 698 __ load_toc(toc_reg); 699 address const_addr = __ float_constant(c->as_jfloat()); 700 if (const_addr == NULL) { 701 bailout("const section overflow"); 702 break; 703 } 704 int displ = const_addr - _masm->code()->consts()->start(); 705 if (dest->is_single_fpu()) { 706 __ z_ley(dest->as_float_reg(), displ, toc_reg); 707 } else { 708 assert(dest->is_single_cpu(), "Must be a cpu register."); 709 __ z_ly(dest->as_register(), displ, toc_reg); 710 } 711 } 712 break; 713 714 case T_DOUBLE: { 715 Register toc_reg = Z_R1_scratch; 716 __ load_toc(toc_reg); 717 address const_addr = __ double_constant(c->as_jdouble()); 718 if (const_addr == NULL) { 719 bailout("const section overflow"); 720 break; 721 } 722 int displ = const_addr - _masm->code()->consts()->start(); 723 if (dest->is_double_fpu()) { 724 __ z_ldy(dest->as_double_reg(), displ, toc_reg); 725 } else { 726 assert(dest->is_double_cpu(), "Must be a long register."); 727 __ z_lg(dest->as_register_lo(), displ, toc_reg); 728 } 729 } 730 break; 731 732 default: 733 ShouldNotReachHere(); 734 } 735 } 736 737 Address LIR_Assembler::as_Address(LIR_Address* addr) { 738 if (addr->base()->is_illegal()) { 739 Unimplemented(); 740 } 741 742 Register base = addr->base()->as_pointer_register(); 743 744 if (addr->index()->is_illegal()) { 745 return Address(base, addr->disp()); 746 } else if (addr->index()->is_cpu_register()) { 747 Register index = addr->index()->as_pointer_register(); 748 return Address(base, index, addr->disp()); 749 } else if (addr->index()->is_constant()) { 750 intptr_t addr_offset = addr->index()->as_constant_ptr()->as_jint() + addr->disp(); 751 return Address(base, addr_offset); 752 } else { 753 ShouldNotReachHere(); 754 return Address(); 755 } 756 } 757 758 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 759 switch (type) { 760 case T_INT: 761 case T_FLOAT: { 762 Register tmp = Z_R1_scratch; 763 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 764 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 765 __ mem2reg_opt(tmp, from, false); 766 __ reg2mem_opt(tmp, to, false); 767 break; 768 } 769 case T_ADDRESS: 770 case T_OBJECT: { 771 Register tmp = Z_R1_scratch; 772 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 773 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 774 __ mem2reg_opt(tmp, from, true); 775 __ reg2mem_opt(tmp, to, true); 776 break; 777 } 778 case T_LONG: 779 case T_DOUBLE: { 780 Register tmp = Z_R1_scratch; 781 Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); 782 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); 783 __ mem2reg_opt(tmp, from, true); 784 __ reg2mem_opt(tmp, to, true); 785 break; 786 } 787 788 default: 789 ShouldNotReachHere(); 790 } 791 } 792 793 // 4-byte accesses only! Don't use it to access 8 bytes! 794 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 795 ShouldNotCallThis(); 796 return 0; // unused 797 } 798 799 // 4-byte accesses only! Don't use it to access 8 bytes! 800 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 801 ShouldNotCallThis(); 802 return 0; // unused 803 } 804 805 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, 806 CodeEmitInfo* info, bool wide, bool unaligned) { 807 808 assert(type != T_METADATA, "load of metadata ptr not supported"); 809 LIR_Address* addr = src_opr->as_address_ptr(); 810 LIR_Opr to_reg = dest; 811 812 Register src = addr->base()->as_pointer_register(); 813 Register disp_reg = Z_R0; 814 int disp_value = addr->disp(); 815 bool needs_patching = (patch_code != lir_patch_none); 816 817 if (addr->base()->type() == T_OBJECT) { 818 __ verify_oop(src); 819 } 820 821 PatchingStub* patch = NULL; 822 if (needs_patching) { 823 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 824 assert(!to_reg->is_double_cpu() || 825 patch_code == lir_patch_none || 826 patch_code == lir_patch_normal, "patching doesn't match register"); 827 } 828 829 if (addr->index()->is_illegal()) { 830 if (!Immediate::is_simm20(disp_value)) { 831 if (needs_patching) { 832 __ load_const(Z_R1_scratch, (intptr_t)0); 833 } else { 834 __ load_const_optimized(Z_R1_scratch, disp_value); 835 } 836 disp_reg = Z_R1_scratch; 837 disp_value = 0; 838 } 839 } else { 840 if (!Immediate::is_simm20(disp_value)) { 841 __ load_const_optimized(Z_R1_scratch, disp_value); 842 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register()); 843 disp_reg = Z_R1_scratch; 844 disp_value = 0; 845 } 846 disp_reg = addr->index()->as_pointer_register(); 847 } 848 849 // Remember the offset of the load. The patching_epilog must be done 850 // before the call to add_debug_info, otherwise the PcDescs don't get 851 // entered in increasing order. 852 int offset = code_offset(); 853 854 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up"); 855 856 bool short_disp = Immediate::is_uimm12(disp_value); 857 858 switch (type) { 859 case T_BOOLEAN: // fall through 860 case T_BYTE : __ z_lb(dest->as_register(), disp_value, disp_reg, src); break; 861 case T_CHAR : __ z_llgh(dest->as_register(), disp_value, disp_reg, src); break; 862 case T_SHORT : 863 if (short_disp) { 864 __ z_lh(dest->as_register(), disp_value, disp_reg, src); 865 } else { 866 __ z_lhy(dest->as_register(), disp_value, disp_reg, src); 867 } 868 break; 869 case T_INT : 870 if (short_disp) { 871 __ z_l(dest->as_register(), disp_value, disp_reg, src); 872 } else { 873 __ z_ly(dest->as_register(), disp_value, disp_reg, src); 874 } 875 break; 876 case T_ADDRESS: 877 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) { 878 __ z_llgf(dest->as_register(), disp_value, disp_reg, src); 879 __ decode_klass_not_null(dest->as_register()); 880 } else { 881 __ z_lg(dest->as_register(), disp_value, disp_reg, src); 882 } 883 break; 884 case T_ARRAY : // fall through 885 case T_OBJECT: 886 { 887 if (UseCompressedOops && !wide) { 888 __ z_llgf(dest->as_register(), disp_value, disp_reg, src); 889 __ oop_decoder(dest->as_register(), dest->as_register(), true); 890 } else { 891 __ z_lg(dest->as_register(), disp_value, disp_reg, src); 892 } 893 break; 894 } 895 case T_FLOAT: 896 if (short_disp) { 897 __ z_le(dest->as_float_reg(), disp_value, disp_reg, src); 898 } else { 899 __ z_ley(dest->as_float_reg(), disp_value, disp_reg, src); 900 } 901 break; 902 case T_DOUBLE: 903 if (short_disp) { 904 __ z_ld(dest->as_double_reg(), disp_value, disp_reg, src); 905 } else { 906 __ z_ldy(dest->as_double_reg(), disp_value, disp_reg, src); 907 } 908 break; 909 case T_LONG : __ z_lg(dest->as_register_lo(), disp_value, disp_reg, src); break; 910 default : ShouldNotReachHere(); 911 } 912 if (type == T_ARRAY || type == T_OBJECT) { 913 __ verify_oop(dest->as_register()); 914 } 915 916 if (patch != NULL) { 917 patching_epilog(patch, patch_code, src, info); 918 } 919 if (info != NULL) add_debug_info_for_null_check(offset, info); 920 } 921 922 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 923 assert(src->is_stack(), "should not call otherwise"); 924 assert(dest->is_register(), "should not call otherwise"); 925 926 if (dest->is_single_cpu()) { 927 if (type == T_ARRAY || type == T_OBJECT) { 928 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true); 929 __ verify_oop(dest->as_register()); 930 } else if (type == T_METADATA) { 931 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true); 932 } else { 933 __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), false); 934 } 935 } else if (dest->is_double_cpu()) { 936 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix()); 937 __ mem2reg_opt(dest->as_register_lo(), src_addr_LO, true); 938 } else if (dest->is_single_fpu()) { 939 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 940 __ mem2freg_opt(dest->as_float_reg(), src_addr, false); 941 } else if (dest->is_double_fpu()) { 942 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 943 __ mem2freg_opt(dest->as_double_reg(), src_addr, true); 944 } else { 945 ShouldNotReachHere(); 946 } 947 } 948 949 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 950 assert(src->is_register(), "should not call otherwise"); 951 assert(dest->is_stack(), "should not call otherwise"); 952 953 if (src->is_single_cpu()) { 954 const Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 955 if (type == T_OBJECT || type == T_ARRAY) { 956 __ verify_oop(src->as_register()); 957 __ reg2mem_opt(src->as_register(), dst, true); 958 } else if (type == T_METADATA) { 959 __ reg2mem_opt(src->as_register(), dst, true); 960 } else { 961 __ reg2mem_opt(src->as_register(), dst, false); 962 } 963 } else if (src->is_double_cpu()) { 964 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix()); 965 __ reg2mem_opt(src->as_register_lo(), dstLO, true); 966 } else if (src->is_single_fpu()) { 967 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 968 __ freg2mem_opt(src->as_float_reg(), dst_addr, false); 969 } else if (src->is_double_fpu()) { 970 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 971 __ freg2mem_opt(src->as_double_reg(), dst_addr, true); 972 } else { 973 ShouldNotReachHere(); 974 } 975 } 976 977 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { 978 if (from_reg->is_float_kind() && to_reg->is_float_kind()) { 979 if (from_reg->is_double_fpu()) { 980 // double to double moves 981 assert(to_reg->is_double_fpu(), "should match"); 982 __ z_ldr(to_reg->as_double_reg(), from_reg->as_double_reg()); 983 } else { 984 // float to float moves 985 assert(to_reg->is_single_fpu(), "should match"); 986 __ z_ler(to_reg->as_float_reg(), from_reg->as_float_reg()); 987 } 988 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { 989 if (from_reg->is_double_cpu()) { 990 __ z_lgr(to_reg->as_pointer_register(), from_reg->as_pointer_register()); 991 } else if (to_reg->is_double_cpu()) { 992 // int to int moves 993 __ z_lgr(to_reg->as_register_lo(), from_reg->as_register()); 994 } else { 995 // int to int moves 996 __ z_lgr(to_reg->as_register(), from_reg->as_register()); 997 } 998 } else { 999 ShouldNotReachHere(); 1000 } 1001 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) { 1002 __ verify_oop(to_reg->as_register()); 1003 } 1004 } 1005 1006 void LIR_Assembler::reg2mem(LIR_Opr from, LIR_Opr dest_opr, BasicType type, 1007 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, 1008 bool wide, bool unaligned) { 1009 assert(type != T_METADATA, "store of metadata ptr not supported"); 1010 LIR_Address* addr = dest_opr->as_address_ptr(); 1011 1012 Register dest = addr->base()->as_pointer_register(); 1013 Register disp_reg = Z_R0; 1014 int disp_value = addr->disp(); 1015 bool needs_patching = (patch_code != lir_patch_none); 1016 1017 if (addr->base()->is_oop_register()) { 1018 __ verify_oop(dest); 1019 } 1020 1021 PatchingStub* patch = NULL; 1022 if (needs_patching) { 1023 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1024 assert(!from->is_double_cpu() || 1025 patch_code == lir_patch_none || 1026 patch_code == lir_patch_normal, "patching doesn't match register"); 1027 } 1028 1029 assert(!needs_patching || (!Immediate::is_simm20(disp_value) && addr->index()->is_illegal()), "assumption"); 1030 if (addr->index()->is_illegal()) { 1031 if (!Immediate::is_simm20(disp_value)) { 1032 if (needs_patching) { 1033 __ load_const(Z_R1_scratch, (intptr_t)0); 1034 } else { 1035 __ load_const_optimized(Z_R1_scratch, disp_value); 1036 } 1037 disp_reg = Z_R1_scratch; 1038 disp_value = 0; 1039 } 1040 } else { 1041 if (!Immediate::is_simm20(disp_value)) { 1042 __ load_const_optimized(Z_R1_scratch, disp_value); 1043 __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register()); 1044 disp_reg = Z_R1_scratch; 1045 disp_value = 0; 1046 } 1047 disp_reg = addr->index()->as_pointer_register(); 1048 } 1049 1050 assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up"); 1051 1052 if (type == T_ARRAY || type == T_OBJECT) { 1053 __ verify_oop(from->as_register()); 1054 } 1055 1056 bool short_disp = Immediate::is_uimm12(disp_value); 1057 1058 // Remember the offset of the store. The patching_epilog must be done 1059 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get 1060 // entered in increasing order. 1061 int offset = code_offset(); 1062 switch (type) { 1063 case T_BOOLEAN: // fall through 1064 case T_BYTE : 1065 if (short_disp) { 1066 __ z_stc(from->as_register(), disp_value, disp_reg, dest); 1067 } else { 1068 __ z_stcy(from->as_register(), disp_value, disp_reg, dest); 1069 } 1070 break; 1071 case T_CHAR : // fall through 1072 case T_SHORT : 1073 if (short_disp) { 1074 __ z_sth(from->as_register(), disp_value, disp_reg, dest); 1075 } else { 1076 __ z_sthy(from->as_register(), disp_value, disp_reg, dest); 1077 } 1078 break; 1079 case T_INT : 1080 if (short_disp) { 1081 __ z_st(from->as_register(), disp_value, disp_reg, dest); 1082 } else { 1083 __ z_sty(from->as_register(), disp_value, disp_reg, dest); 1084 } 1085 break; 1086 case T_LONG : __ z_stg(from->as_register_lo(), disp_value, disp_reg, dest); break; 1087 case T_ADDRESS: __ z_stg(from->as_register(), disp_value, disp_reg, dest); break; 1088 break; 1089 case T_ARRAY : // fall through 1090 case T_OBJECT: 1091 { 1092 if (UseCompressedOops && !wide) { 1093 Register compressed_src = Z_R14; 1094 __ oop_encoder(compressed_src, from->as_register(), true, (disp_reg != Z_R1) ? Z_R1 : Z_R0, -1, true); 1095 offset = code_offset(); 1096 if (short_disp) { 1097 __ z_st(compressed_src, disp_value, disp_reg, dest); 1098 } else { 1099 __ z_sty(compressed_src, disp_value, disp_reg, dest); 1100 } 1101 } else { 1102 __ z_stg(from->as_register(), disp_value, disp_reg, dest); 1103 } 1104 break; 1105 } 1106 case T_FLOAT : 1107 if (short_disp) { 1108 __ z_ste(from->as_float_reg(), disp_value, disp_reg, dest); 1109 } else { 1110 __ z_stey(from->as_float_reg(), disp_value, disp_reg, dest); 1111 } 1112 break; 1113 case T_DOUBLE: 1114 if (short_disp) { 1115 __ z_std(from->as_double_reg(), disp_value, disp_reg, dest); 1116 } else { 1117 __ z_stdy(from->as_double_reg(), disp_value, disp_reg, dest); 1118 } 1119 break; 1120 default: ShouldNotReachHere(); 1121 } 1122 1123 if (patch != NULL) { 1124 patching_epilog(patch, patch_code, dest, info); 1125 } 1126 1127 if (info != NULL) add_debug_info_for_null_check(offset, info); 1128 } 1129 1130 1131 void LIR_Assembler::return_op(LIR_Opr result) { 1132 assert(result->is_illegal() || 1133 (result->is_single_cpu() && result->as_register() == Z_R2) || 1134 (result->is_double_cpu() && result->as_register_lo() == Z_R2) || 1135 (result->is_single_fpu() && result->as_float_reg() == Z_F0) || 1136 (result->is_double_fpu() && result->as_double_reg() == Z_F0), "convention"); 1137 1138 AddressLiteral pp(os::get_polling_page()); 1139 __ load_const_optimized(Z_R1_scratch, pp); 1140 1141 // Pop the frame before the safepoint code. 1142 __ pop_frame_restore_retPC(initial_frame_size_in_bytes()); 1143 1144 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 1145 __ reserved_stack_check(Z_R14); 1146 } 1147 1148 // We need to mark the code position where the load from the safepoint 1149 // polling page was emitted as relocInfo::poll_return_type here. 1150 __ relocate(relocInfo::poll_return_type); 1151 __ load_from_polling_page(Z_R1_scratch); 1152 1153 __ z_br(Z_R14); // Return to caller. 1154 } 1155 1156 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 1157 AddressLiteral pp(os::get_polling_page()); 1158 __ load_const_optimized(tmp->as_register_lo(), pp); 1159 guarantee(info != NULL, "Shouldn't be NULL"); 1160 add_debug_info_for_branch(info); 1161 int offset = __ offset(); 1162 __ relocate(relocInfo::poll_type); 1163 __ load_from_polling_page(tmp->as_register_lo()); 1164 return offset; 1165 } 1166 1167 void LIR_Assembler::emit_static_call_stub() { 1168 1169 // Stub is fixed up when the corresponding call is converted from calling 1170 // compiled code to calling interpreted code. 1171 1172 address call_pc = __ pc(); 1173 address stub = __ start_a_stub(call_stub_size()); 1174 if (stub == NULL) { 1175 bailout("static call stub overflow"); 1176 return; 1177 } 1178 1179 int start = __ offset(); 1180 1181 __ relocate(static_stub_Relocation::spec(call_pc)); 1182 1183 // See also Matcher::interpreter_method_oop_reg(). 1184 AddressLiteral meta = __ allocate_metadata_address(NULL); 1185 bool success = __ load_const_from_toc(Z_method, meta); 1186 1187 __ set_inst_mark(); 1188 AddressLiteral a((address)-1); 1189 success = success && __ load_const_from_toc(Z_R1, a); 1190 if (!success) { 1191 bailout("const section overflow"); 1192 return; 1193 } 1194 1195 __ z_br(Z_R1); 1196 assert(__ offset() - start <= call_stub_size(), "stub too big"); 1197 __ end_a_stub(); // Update current stubs pointer and restore insts_end. 1198 } 1199 1200 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 1201 bool unsigned_comp = condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual; 1202 if (opr1->is_single_cpu()) { 1203 Register reg1 = opr1->as_register(); 1204 if (opr2->is_single_cpu()) { 1205 // cpu register - cpu register 1206 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 1207 __ z_clgr(reg1, opr2->as_register()); 1208 } else { 1209 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); 1210 if (unsigned_comp) { 1211 __ z_clr(reg1, opr2->as_register()); 1212 } else { 1213 __ z_cr(reg1, opr2->as_register()); 1214 } 1215 } 1216 } else if (opr2->is_stack()) { 1217 // cpu register - stack 1218 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 1219 __ z_cg(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 1220 } else { 1221 if (unsigned_comp) { 1222 __ z_cly(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 1223 } else { 1224 __ z_cy(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 1225 } 1226 } 1227 } else if (opr2->is_constant()) { 1228 // cpu register - constant 1229 LIR_Const* c = opr2->as_constant_ptr(); 1230 if (c->type() == T_INT) { 1231 if (unsigned_comp) { 1232 __ z_clfi(reg1, c->as_jint()); 1233 } else { 1234 __ z_cfi(reg1, c->as_jint()); 1235 } 1236 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 1237 // In 64bit oops are single register. 1238 jobject o = c->as_jobject(); 1239 if (o == NULL) { 1240 __ z_ltgr(reg1, reg1); 1241 } else { 1242 jobject2reg(o, Z_R1_scratch); 1243 __ z_cgr(reg1, Z_R1_scratch); 1244 } 1245 } else { 1246 fatal("unexpected type: %s", basictype_to_str(c->type())); 1247 } 1248 // cpu register - address 1249 } else if (opr2->is_address()) { 1250 if (op->info() != NULL) { 1251 add_debug_info_for_null_check_here(op->info()); 1252 } 1253 if (unsigned_comp) { 1254 __ z_cly(reg1, as_Address(opr2->as_address_ptr())); 1255 } else { 1256 __ z_cy(reg1, as_Address(opr2->as_address_ptr())); 1257 } 1258 } else { 1259 ShouldNotReachHere(); 1260 } 1261 1262 } else if (opr1->is_double_cpu()) { 1263 assert(!unsigned_comp, "unexpected"); 1264 Register xlo = opr1->as_register_lo(); 1265 Register xhi = opr1->as_register_hi(); 1266 if (opr2->is_double_cpu()) { 1267 __ z_cgr(xlo, opr2->as_register_lo()); 1268 } else if (opr2->is_constant()) { 1269 // cpu register - constant 0 1270 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 1271 __ z_ltgr(xlo, xlo); 1272 } else { 1273 ShouldNotReachHere(); 1274 } 1275 1276 } else if (opr1->is_single_fpu()) { 1277 if (opr2->is_single_fpu()) { 1278 __ z_cebr(opr1->as_float_reg(), opr2->as_float_reg()); 1279 } else { 1280 // stack slot 1281 Address addr = frame_map()->address_for_slot(opr2->single_stack_ix()); 1282 if (Immediate::is_uimm12(addr.disp())) { 1283 __ z_ceb(opr1->as_float_reg(), addr); 1284 } else { 1285 __ z_ley(Z_fscratch_1, addr); 1286 __ z_cebr(opr1->as_float_reg(), Z_fscratch_1); 1287 } 1288 } 1289 } else if (opr1->is_double_fpu()) { 1290 if (opr2->is_double_fpu()) { 1291 __ z_cdbr(opr1->as_double_reg(), opr2->as_double_reg()); 1292 } else { 1293 // stack slot 1294 Address addr = frame_map()->address_for_slot(opr2->double_stack_ix()); 1295 if (Immediate::is_uimm12(addr.disp())) { 1296 __ z_cdb(opr1->as_double_reg(), addr); 1297 } else { 1298 __ z_ldy(Z_fscratch_1, addr); 1299 __ z_cdbr(opr1->as_double_reg(), Z_fscratch_1); 1300 } 1301 } 1302 } else { 1303 ShouldNotReachHere(); 1304 } 1305 } 1306 1307 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 1308 Label done; 1309 Register dreg = dst->as_register(); 1310 1311 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 1312 assert((left->is_single_fpu() && right->is_single_fpu()) || 1313 (left->is_double_fpu() && right->is_double_fpu()), "unexpected operand types"); 1314 bool is_single = left->is_single_fpu(); 1315 bool is_unordered_less = (code == lir_ucmp_fd2i); 1316 FloatRegister lreg = is_single ? left->as_float_reg() : left->as_double_reg(); 1317 FloatRegister rreg = is_single ? right->as_float_reg() : right->as_double_reg(); 1318 if (is_single) { 1319 __ z_cebr(lreg, rreg); 1320 } else { 1321 __ z_cdbr(lreg, rreg); 1322 } 1323 if (VM_Version::has_LoadStoreConditional()) { 1324 Register one = Z_R0_scratch; 1325 Register minus_one = Z_R1_scratch; 1326 __ z_lghi(minus_one, -1); 1327 __ z_lghi(one, 1); 1328 __ z_lghi(dreg, 0); 1329 __ z_locgr(dreg, one, is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered); 1330 __ z_locgr(dreg, minus_one, is_unordered_less ? Assembler::bcondLowOrNotOrdered : Assembler::bcondLow); 1331 } else { 1332 __ clear_reg(dreg, true, false); 1333 __ z_bre(done); // if (left == right) dst = 0 1334 1335 // if (left > right || ((code ~= cmpg) && (left <> right)) dst := 1 1336 __ z_lhi(dreg, 1); 1337 __ z_brc(is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered, done); 1338 1339 // if (left < right || ((code ~= cmpl) && (left <> right)) dst := -1 1340 __ z_lhi(dreg, -1); 1341 } 1342 } else { 1343 assert(code == lir_cmp_l2i, "check"); 1344 if (VM_Version::has_LoadStoreConditional()) { 1345 Register one = Z_R0_scratch; 1346 Register minus_one = Z_R1_scratch; 1347 __ z_cgr(left->as_register_lo(), right->as_register_lo()); 1348 __ z_lghi(minus_one, -1); 1349 __ z_lghi(one, 1); 1350 __ z_lghi(dreg, 0); 1351 __ z_locgr(dreg, one, Assembler::bcondHigh); 1352 __ z_locgr(dreg, minus_one, Assembler::bcondLow); 1353 } else { 1354 __ z_cgr(left->as_register_lo(), right->as_register_lo()); 1355 __ z_lghi(dreg, 0); // eq value 1356 __ z_bre(done); 1357 __ z_lghi(dreg, 1); // gt value 1358 __ z_brh(done); 1359 __ z_lghi(dreg, -1); // lt value 1360 } 1361 } 1362 __ bind(done); 1363 } 1364 1365 // result = condition ? opr1 : opr2 1366 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1367 Assembler::branch_condition acond = Assembler::bcondEqual, ncond = Assembler::bcondNotEqual; 1368 switch (condition) { 1369 case lir_cond_equal: acond = Assembler::bcondEqual; ncond = Assembler::bcondNotEqual; break; 1370 case lir_cond_notEqual: acond = Assembler::bcondNotEqual; ncond = Assembler::bcondEqual; break; 1371 case lir_cond_less: acond = Assembler::bcondLow; ncond = Assembler::bcondNotLow; break; 1372 case lir_cond_lessEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break; 1373 case lir_cond_greaterEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break; 1374 case lir_cond_greater: acond = Assembler::bcondHigh; ncond = Assembler::bcondNotHigh; break; 1375 case lir_cond_belowEqual: acond = Assembler::bcondNotHigh; ncond = Assembler::bcondHigh; break; 1376 case lir_cond_aboveEqual: acond = Assembler::bcondNotLow; ncond = Assembler::bcondLow; break; 1377 default: ShouldNotReachHere(); 1378 } 1379 1380 if (opr1->is_cpu_register()) { 1381 reg2reg(opr1, result); 1382 } else if (opr1->is_stack()) { 1383 stack2reg(opr1, result, result->type()); 1384 } else if (opr1->is_constant()) { 1385 const2reg(opr1, result, lir_patch_none, NULL); 1386 } else { 1387 ShouldNotReachHere(); 1388 } 1389 1390 if (VM_Version::has_LoadStoreConditional() && !opr2->is_constant()) { 1391 // Optimized version that does not require a branch. 1392 if (opr2->is_single_cpu()) { 1393 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 1394 __ z_locgr(result->as_register(), opr2->as_register(), ncond); 1395 } else if (opr2->is_double_cpu()) { 1396 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1397 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1398 __ z_locgr(result->as_register_lo(), opr2->as_register_lo(), ncond); 1399 } else if (opr2->is_single_stack()) { 1400 __ z_loc(result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()), ncond); 1401 } else if (opr2->is_double_stack()) { 1402 __ z_locg(result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix()), ncond); 1403 } else { 1404 ShouldNotReachHere(); 1405 } 1406 } else { 1407 Label skip; 1408 __ z_brc(acond, skip); 1409 if (opr2->is_cpu_register()) { 1410 reg2reg(opr2, result); 1411 } else if (opr2->is_stack()) { 1412 stack2reg(opr2, result, result->type()); 1413 } else if (opr2->is_constant()) { 1414 const2reg(opr2, result, lir_patch_none, NULL); 1415 } else { 1416 ShouldNotReachHere(); 1417 } 1418 __ bind(skip); 1419 } 1420 } 1421 1422 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, 1423 CodeEmitInfo* info, bool pop_fpu_stack) { 1424 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 1425 1426 if (left->is_single_cpu()) { 1427 assert(left == dest, "left and dest must be equal"); 1428 Register lreg = left->as_register(); 1429 1430 if (right->is_single_cpu()) { 1431 // cpu register - cpu register 1432 Register rreg = right->as_register(); 1433 switch (code) { 1434 case lir_add: __ z_ar (lreg, rreg); break; 1435 case lir_sub: __ z_sr (lreg, rreg); break; 1436 case lir_mul: __ z_msr(lreg, rreg); break; 1437 default: ShouldNotReachHere(); 1438 } 1439 1440 } else if (right->is_stack()) { 1441 // cpu register - stack 1442 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 1443 switch (code) { 1444 case lir_add: __ z_ay(lreg, raddr); break; 1445 case lir_sub: __ z_sy(lreg, raddr); break; 1446 default: ShouldNotReachHere(); 1447 } 1448 1449 } else if (right->is_constant()) { 1450 // cpu register - constant 1451 jint c = right->as_constant_ptr()->as_jint(); 1452 switch (code) { 1453 case lir_add: __ z_agfi(lreg, c); break; 1454 case lir_sub: __ z_agfi(lreg, -c); break; // note: -min_jint == min_jint 1455 case lir_mul: __ z_msfi(lreg, c); break; 1456 default: ShouldNotReachHere(); 1457 } 1458 1459 } else { 1460 ShouldNotReachHere(); 1461 } 1462 1463 } else if (left->is_double_cpu()) { 1464 assert(left == dest, "left and dest must be equal"); 1465 Register lreg_lo = left->as_register_lo(); 1466 Register lreg_hi = left->as_register_hi(); 1467 1468 if (right->is_double_cpu()) { 1469 // cpu register - cpu register 1470 Register rreg_lo = right->as_register_lo(); 1471 Register rreg_hi = right->as_register_hi(); 1472 assert_different_registers(lreg_lo, rreg_lo); 1473 switch (code) { 1474 case lir_add: 1475 __ z_agr(lreg_lo, rreg_lo); 1476 break; 1477 case lir_sub: 1478 __ z_sgr(lreg_lo, rreg_lo); 1479 break; 1480 case lir_mul: 1481 __ z_msgr(lreg_lo, rreg_lo); 1482 break; 1483 default: 1484 ShouldNotReachHere(); 1485 } 1486 1487 } else if (right->is_constant()) { 1488 // cpu register - constant 1489 jlong c = right->as_constant_ptr()->as_jlong_bits(); 1490 switch (code) { 1491 case lir_add: __ z_agfi(lreg_lo, c); break; 1492 case lir_sub: 1493 if (c != min_jint) { 1494 __ z_agfi(lreg_lo, -c); 1495 } else { 1496 // -min_jint cannot be represented as simm32 in z_agfi 1497 // min_jint sign extended: 0xffffffff80000000 1498 // -min_jint as 64 bit integer: 0x0000000080000000 1499 // 0x80000000 can be represented as uimm32 in z_algfi 1500 // lreg_lo := lreg_lo + -min_jint == lreg_lo + 0x80000000 1501 __ z_algfi(lreg_lo, UCONST64(0x80000000)); 1502 } 1503 break; 1504 case lir_mul: __ z_msgfi(lreg_lo, c); break; 1505 default: 1506 ShouldNotReachHere(); 1507 } 1508 1509 } else { 1510 ShouldNotReachHere(); 1511 } 1512 1513 } else if (left->is_single_fpu()) { 1514 assert(left == dest, "left and dest must be equal"); 1515 FloatRegister lreg = left->as_float_reg(); 1516 FloatRegister rreg = right->is_single_fpu() ? right->as_float_reg() : fnoreg; 1517 Address raddr; 1518 1519 if (rreg == fnoreg) { 1520 assert(right->is_single_stack(), "constants should be loaded into register"); 1521 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 1522 if (!Immediate::is_uimm12(raddr.disp())) { 1523 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, false); 1524 } 1525 } 1526 1527 if (rreg != fnoreg) { 1528 switch (code) { 1529 case lir_add: __ z_aebr(lreg, rreg); break; 1530 case lir_sub: __ z_sebr(lreg, rreg); break; 1531 case lir_mul_strictfp: // fall through 1532 case lir_mul: __ z_meebr(lreg, rreg); break; 1533 case lir_div_strictfp: // fall through 1534 case lir_div: __ z_debr(lreg, rreg); break; 1535 default: ShouldNotReachHere(); 1536 } 1537 } else { 1538 switch (code) { 1539 case lir_add: __ z_aeb(lreg, raddr); break; 1540 case lir_sub: __ z_seb(lreg, raddr); break; 1541 case lir_mul_strictfp: // fall through 1542 case lir_mul: __ z_meeb(lreg, raddr); break; 1543 case lir_div_strictfp: // fall through 1544 case lir_div: __ z_deb(lreg, raddr); break; 1545 default: ShouldNotReachHere(); 1546 } 1547 } 1548 } else if (left->is_double_fpu()) { 1549 assert(left == dest, "left and dest must be equal"); 1550 FloatRegister lreg = left->as_double_reg(); 1551 FloatRegister rreg = right->is_double_fpu() ? right->as_double_reg() : fnoreg; 1552 Address raddr; 1553 1554 if (rreg == fnoreg) { 1555 assert(right->is_double_stack(), "constants should be loaded into register"); 1556 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 1557 if (!Immediate::is_uimm12(raddr.disp())) { 1558 __ mem2freg_opt(rreg = Z_fscratch_1, raddr, true); 1559 } 1560 } 1561 1562 if (rreg != fnoreg) { 1563 switch (code) { 1564 case lir_add: __ z_adbr(lreg, rreg); break; 1565 case lir_sub: __ z_sdbr(lreg, rreg); break; 1566 case lir_mul_strictfp: // fall through 1567 case lir_mul: __ z_mdbr(lreg, rreg); break; 1568 case lir_div_strictfp: // fall through 1569 case lir_div: __ z_ddbr(lreg, rreg); break; 1570 default: ShouldNotReachHere(); 1571 } 1572 } else { 1573 switch (code) { 1574 case lir_add: __ z_adb(lreg, raddr); break; 1575 case lir_sub: __ z_sdb(lreg, raddr); break; 1576 case lir_mul_strictfp: // fall through 1577 case lir_mul: __ z_mdb(lreg, raddr); break; 1578 case lir_div_strictfp: // fall through 1579 case lir_div: __ z_ddb(lreg, raddr); break; 1580 default: ShouldNotReachHere(); 1581 } 1582 } 1583 } else if (left->is_address()) { 1584 assert(left == dest, "left and dest must be equal"); 1585 assert(code == lir_add, "unsupported operation"); 1586 assert(right->is_constant(), "unsupported operand"); 1587 jint c = right->as_constant_ptr()->as_jint(); 1588 LIR_Address* lir_addr = left->as_address_ptr(); 1589 Address addr = as_Address(lir_addr); 1590 switch (lir_addr->type()) { 1591 case T_INT: 1592 __ add2mem_32(addr, c, Z_R1_scratch); 1593 break; 1594 case T_LONG: 1595 __ add2mem_64(addr, c, Z_R1_scratch); 1596 break; 1597 default: 1598 ShouldNotReachHere(); 1599 } 1600 } else { 1601 ShouldNotReachHere(); 1602 } 1603 } 1604 1605 void LIR_Assembler::fpop() { 1606 // do nothing 1607 } 1608 1609 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { 1610 switch (code) { 1611 case lir_sqrt: { 1612 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt"); 1613 FloatRegister src_reg = value->as_double_reg(); 1614 FloatRegister dst_reg = dest->as_double_reg(); 1615 __ z_sqdbr(dst_reg, src_reg); 1616 break; 1617 } 1618 case lir_abs: { 1619 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs"); 1620 FloatRegister src_reg = value->as_double_reg(); 1621 FloatRegister dst_reg = dest->as_double_reg(); 1622 __ z_lpdbr(dst_reg, src_reg); 1623 break; 1624 } 1625 default: { 1626 ShouldNotReachHere(); 1627 break; 1628 } 1629 } 1630 } 1631 1632 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 1633 if (left->is_single_cpu()) { 1634 Register reg = left->as_register(); 1635 if (right->is_constant()) { 1636 int val = right->as_constant_ptr()->as_jint(); 1637 switch (code) { 1638 case lir_logic_and: __ z_nilf(reg, val); break; 1639 case lir_logic_or: __ z_oilf(reg, val); break; 1640 case lir_logic_xor: __ z_xilf(reg, val); break; 1641 default: ShouldNotReachHere(); 1642 } 1643 } else if (right->is_stack()) { 1644 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 1645 switch (code) { 1646 case lir_logic_and: __ z_ny(reg, raddr); break; 1647 case lir_logic_or: __ z_oy(reg, raddr); break; 1648 case lir_logic_xor: __ z_xy(reg, raddr); break; 1649 default: ShouldNotReachHere(); 1650 } 1651 } else { 1652 Register rright = right->as_register(); 1653 switch (code) { 1654 case lir_logic_and: __ z_nr(reg, rright); break; 1655 case lir_logic_or : __ z_or(reg, rright); break; 1656 case lir_logic_xor: __ z_xr(reg, rright); break; 1657 default: ShouldNotReachHere(); 1658 } 1659 } 1660 move_regs(reg, dst->as_register()); 1661 } else { 1662 Register l_lo = left->as_register_lo(); 1663 if (right->is_constant()) { 1664 __ load_const_optimized(Z_R1_scratch, right->as_constant_ptr()->as_jlong()); 1665 switch (code) { 1666 case lir_logic_and: 1667 __ z_ngr(l_lo, Z_R1_scratch); 1668 break; 1669 case lir_logic_or: 1670 __ z_ogr(l_lo, Z_R1_scratch); 1671 break; 1672 case lir_logic_xor: 1673 __ z_xgr(l_lo, Z_R1_scratch); 1674 break; 1675 default: ShouldNotReachHere(); 1676 } 1677 } else { 1678 Register r_lo; 1679 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { 1680 r_lo = right->as_register(); 1681 } else { 1682 r_lo = right->as_register_lo(); 1683 } 1684 switch (code) { 1685 case lir_logic_and: 1686 __ z_ngr(l_lo, r_lo); 1687 break; 1688 case lir_logic_or: 1689 __ z_ogr(l_lo, r_lo); 1690 break; 1691 case lir_logic_xor: 1692 __ z_xgr(l_lo, r_lo); 1693 break; 1694 default: ShouldNotReachHere(); 1695 } 1696 } 1697 1698 Register dst_lo = dst->as_register_lo(); 1699 1700 move_regs(l_lo, dst_lo); 1701 } 1702 } 1703 1704 // See operand selection in LIRGenerator::do_ArithmeticOp_Int(). 1705 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 1706 if (left->is_double_cpu()) { 1707 // 64 bit integer case 1708 assert(left->is_double_cpu(), "left must be register"); 1709 assert(right->is_double_cpu() || is_power_of_2_long(right->as_jlong()), 1710 "right must be register or power of 2 constant"); 1711 assert(result->is_double_cpu(), "result must be register"); 1712 1713 Register lreg = left->as_register_lo(); 1714 Register dreg = result->as_register_lo(); 1715 1716 if (right->is_constant()) { 1717 // Convert division by a power of two into some shifts and logical operations. 1718 Register treg1 = Z_R0_scratch; 1719 Register treg2 = Z_R1_scratch; 1720 jlong divisor = right->as_jlong(); 1721 jlong log_divisor = log2_long(right->as_jlong()); 1722 1723 if (divisor == min_jlong) { 1724 // Min_jlong is special. Result is '0' except for min_jlong/min_jlong = 1. 1725 if (dreg == lreg) { 1726 NearLabel done; 1727 __ load_const_optimized(treg2, min_jlong); 1728 __ z_cgr(lreg, treg2); 1729 __ z_lghi(dreg, 0); // Preserves condition code. 1730 __ z_brne(done); 1731 __ z_lghi(dreg, 1); // min_jlong / min_jlong = 1 1732 __ bind(done); 1733 } else { 1734 assert_different_registers(dreg, lreg); 1735 NearLabel done; 1736 __ z_lghi(dreg, 0); 1737 __ compare64_and_branch(lreg, min_jlong, Assembler::bcondNotEqual, done); 1738 __ z_lghi(dreg, 1); 1739 __ bind(done); 1740 } 1741 return; 1742 } 1743 __ move_reg_if_needed(dreg, T_LONG, lreg, T_LONG); 1744 if (divisor == 2) { 1745 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0 1746 } else { 1747 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0 1748 __ and_imm(treg2, divisor - 1, treg1, true); 1749 } 1750 if (code == lir_idiv) { 1751 __ z_agr(dreg, treg2); 1752 __ z_srag(dreg, dreg, log_divisor); 1753 } else { 1754 assert(code == lir_irem, "check"); 1755 __ z_agr(treg2, dreg); 1756 __ and_imm(treg2, ~(divisor - 1), treg1, true); 1757 __ z_sgr(dreg, treg2); 1758 } 1759 return; 1760 } 1761 1762 // Divisor is not a power of 2 constant. 1763 Register rreg = right->as_register_lo(); 1764 Register treg = temp->as_register_lo(); 1765 assert(right->is_double_cpu(), "right must be register"); 1766 assert(lreg == Z_R11, "see ldivInOpr()"); 1767 assert(rreg != lreg, "right register must not be same as left register"); 1768 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10) || 1769 (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see ldivInOpr(), ldivOutOpr(), lremOutOpr()"); 1770 1771 Register R1 = lreg->predecessor(); 1772 Register R2 = rreg; 1773 assert(code != lir_idiv || lreg==dreg, "see code below"); 1774 if (code == lir_idiv) { 1775 __ z_lcgr(lreg, lreg); 1776 } else { 1777 __ clear_reg(dreg, true, false); 1778 } 1779 NearLabel done; 1780 __ compare64_and_branch(R2, -1, Assembler::bcondEqual, done); 1781 if (code == lir_idiv) { 1782 __ z_lcgr(lreg, lreg); // Revert lcgr above. 1783 } 1784 if (ImplicitDiv0Checks) { 1785 // No debug info because the idiv won't trap. 1786 // Add_debug_info_for_div0 would instantiate another DivByZeroStub, 1787 // which is unnecessary, too. 1788 add_debug_info_for_div0(__ offset(), info); 1789 } 1790 __ z_dsgr(R1, R2); 1791 __ bind(done); 1792 return; 1793 } 1794 1795 // 32 bit integer case 1796 1797 assert(left->is_single_cpu(), "left must be register"); 1798 assert(right->is_single_cpu() || is_power_of_2(right->as_jint()), "right must be register or power of 2 constant"); 1799 assert(result->is_single_cpu(), "result must be register"); 1800 1801 Register lreg = left->as_register(); 1802 Register dreg = result->as_register(); 1803 1804 if (right->is_constant()) { 1805 // Convert division by a power of two into some shifts and logical operations. 1806 Register treg1 = Z_R0_scratch; 1807 Register treg2 = Z_R1_scratch; 1808 jlong divisor = right->as_jint(); 1809 jlong log_divisor = log2_long(right->as_jint()); 1810 __ move_reg_if_needed(dreg, T_LONG, lreg, T_INT); // sign extend 1811 if (divisor == 2) { 1812 __ z_srlg(treg2, dreg, 63); // dividend < 0 ? 1 : 0 1813 } else { 1814 __ z_srag(treg2, dreg, 63); // dividend < 0 ? -1 : 0 1815 __ and_imm(treg2, divisor - 1, treg1, true); 1816 } 1817 if (code == lir_idiv) { 1818 __ z_agr(dreg, treg2); 1819 __ z_srag(dreg, dreg, log_divisor); 1820 } else { 1821 assert(code == lir_irem, "check"); 1822 __ z_agr(treg2, dreg); 1823 __ and_imm(treg2, ~(divisor - 1), treg1, true); 1824 __ z_sgr(dreg, treg2); 1825 } 1826 return; 1827 } 1828 1829 // Divisor is not a power of 2 constant. 1830 Register rreg = right->as_register(); 1831 Register treg = temp->as_register(); 1832 assert(right->is_single_cpu(), "right must be register"); 1833 assert(lreg == Z_R11, "left register must be rax,"); 1834 assert(rreg != lreg, "right register must not be same as left register"); 1835 assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10) 1836 || (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see divInOpr(), divOutOpr(), remOutOpr()"); 1837 1838 Register R1 = lreg->predecessor(); 1839 Register R2 = rreg; 1840 __ move_reg_if_needed(lreg, T_LONG, lreg, T_INT); // sign extend 1841 if (ImplicitDiv0Checks) { 1842 // No debug info because the idiv won't trap. 1843 // Add_debug_info_for_div0 would instantiate another DivByZeroStub, 1844 // which is unnecessary, too. 1845 add_debug_info_for_div0(__ offset(), info); 1846 } 1847 __ z_dsgfr(R1, R2); 1848 } 1849 1850 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 1851 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match"); 1852 assert(exceptionPC->as_register() == Z_EXC_PC, "should match"); 1853 1854 // Exception object is not added to oop map by LinearScan 1855 // (LinearScan assumes that no oops are in fixed registers). 1856 info->add_register_oop(exceptionOop); 1857 1858 // Reuse the debug info from the safepoint poll for the throw op itself. 1859 __ get_PC(Z_EXC_PC); 1860 add_call_info(__ offset(), info); // for exception handler 1861 address stub = Runtime1::entry_for (compilation()->has_fpu_code() ? Runtime1::handle_exception_id 1862 : Runtime1::handle_exception_nofpu_id); 1863 emit_call_c(stub); 1864 } 1865 1866 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 1867 assert(exceptionOop->as_register() == Z_EXC_OOP, "should match"); 1868 1869 __ branch_optimized(Assembler::bcondAlways, _unwind_handler_entry); 1870 } 1871 1872 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 1873 ciArrayKlass* default_type = op->expected_type(); 1874 Register src = op->src()->as_register(); 1875 Register dst = op->dst()->as_register(); 1876 Register src_pos = op->src_pos()->as_register(); 1877 Register dst_pos = op->dst_pos()->as_register(); 1878 Register length = op->length()->as_register(); 1879 Register tmp = op->tmp()->as_register(); 1880 1881 CodeStub* stub = op->stub(); 1882 int flags = op->flags(); 1883 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 1884 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 1885 1886 // If we don't know anything, just go through the generic arraycopy. 1887 if (default_type == NULL) { 1888 Label done; 1889 // Save outgoing arguments in callee saved registers (C convention) in case 1890 // a call to System.arraycopy is needed. 1891 Register callee_saved_src = Z_R10; 1892 Register callee_saved_src_pos = Z_R11; 1893 Register callee_saved_dst = Z_R12; 1894 Register callee_saved_dst_pos = Z_R13; 1895 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved. 1896 1897 __ lgr_if_needed(callee_saved_src, src); 1898 __ lgr_if_needed(callee_saved_src_pos, src_pos); 1899 __ lgr_if_needed(callee_saved_dst, dst); 1900 __ lgr_if_needed(callee_saved_dst_pos, dst_pos); 1901 __ lgr_if_needed(callee_saved_length, length); 1902 1903 // C function requires 64 bit values. 1904 __ z_lgfr(src_pos, src_pos); 1905 __ z_lgfr(dst_pos, dst_pos); 1906 __ z_lgfr(length, length); 1907 1908 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); 1909 1910 address copyfunc_addr = StubRoutines::generic_arraycopy(); 1911 1912 // Pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint. 1913 1914 // The arguments are in the corresponding registers. 1915 assert(Z_ARG1 == src, "assumption"); 1916 assert(Z_ARG2 == src_pos, "assumption"); 1917 assert(Z_ARG3 == dst, "assumption"); 1918 assert(Z_ARG4 == dst_pos, "assumption"); 1919 assert(Z_ARG5 == length, "assumption"); 1920 if (copyfunc_addr == NULL) { // Use C version if stub was not generated. 1921 emit_call_c(C_entry); 1922 } else { 1923 #ifndef PRODUCT 1924 if (PrintC1Statistics) { 1925 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_generic_arraycopystub_cnt); 1926 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch); 1927 } 1928 #endif 1929 emit_call_c(copyfunc_addr); 1930 } 1931 CHECK_BAILOUT(); 1932 1933 __ compare32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation()); 1934 1935 if (copyfunc_addr != NULL) { 1936 __ z_lgr(tmp, Z_RET); 1937 __ z_xilf(tmp, -1); 1938 } 1939 1940 // Restore values from callee saved registers so they are where the stub 1941 // expects them. 1942 __ lgr_if_needed(src, callee_saved_src); 1943 __ lgr_if_needed(src_pos, callee_saved_src_pos); 1944 __ lgr_if_needed(dst, callee_saved_dst); 1945 __ lgr_if_needed(dst_pos, callee_saved_dst_pos); 1946 __ lgr_if_needed(length, callee_saved_length); 1947 1948 if (copyfunc_addr != NULL) { 1949 __ z_sr(length, tmp); 1950 __ z_ar(src_pos, tmp); 1951 __ z_ar(dst_pos, tmp); 1952 } 1953 __ branch_optimized(Assembler::bcondAlways, *stub->entry()); 1954 1955 __ bind(*stub->continuation()); 1956 return; 1957 } 1958 1959 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 1960 1961 int elem_size = type2aelembytes(basic_type); 1962 int shift_amount; 1963 1964 switch (elem_size) { 1965 case 1 : 1966 shift_amount = 0; 1967 break; 1968 case 2 : 1969 shift_amount = 1; 1970 break; 1971 case 4 : 1972 shift_amount = 2; 1973 break; 1974 case 8 : 1975 shift_amount = 3; 1976 break; 1977 default: 1978 shift_amount = -1; 1979 ShouldNotReachHere(); 1980 } 1981 1982 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 1983 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 1984 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 1985 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 1986 1987 // Length and pos's are all sign extended at this point on 64bit. 1988 1989 // test for NULL 1990 if (flags & LIR_OpArrayCopy::src_null_check) { 1991 __ compareU64_and_branch(src, (intptr_t)0, Assembler::bcondZero, *stub->entry()); 1992 } 1993 if (flags & LIR_OpArrayCopy::dst_null_check) { 1994 __ compareU64_and_branch(dst, (intptr_t)0, Assembler::bcondZero, *stub->entry()); 1995 } 1996 1997 // Check if negative. 1998 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 1999 __ compare32_and_branch(src_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry()); 2000 } 2001 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 2002 __ compare32_and_branch(dst_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry()); 2003 } 2004 2005 // If the compiler was not able to prove that exact type of the source or the destination 2006 // of the arraycopy is an array type, check at runtime if the source or the destination is 2007 // an instance type. 2008 if (flags & LIR_OpArrayCopy::type_check) { 2009 assert(Klass::_lh_neutral_value == 0, "or replace z_lt instructions"); 2010 2011 if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 2012 __ load_klass(tmp, dst); 2013 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset()))); 2014 __ branch_optimized(Assembler::bcondNotLow, *stub->entry()); 2015 } 2016 2017 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 2018 __ load_klass(tmp, src); 2019 __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset()))); 2020 __ branch_optimized(Assembler::bcondNotLow, *stub->entry()); 2021 } 2022 } 2023 2024 if (flags & LIR_OpArrayCopy::src_range_check) { 2025 __ z_la(tmp, Address(src_pos, length)); 2026 __ z_cl(tmp, src_length_addr); 2027 __ branch_optimized(Assembler::bcondHigh, *stub->entry()); 2028 } 2029 if (flags & LIR_OpArrayCopy::dst_range_check) { 2030 __ z_la(tmp, Address(dst_pos, length)); 2031 __ z_cl(tmp, dst_length_addr); 2032 __ branch_optimized(Assembler::bcondHigh, *stub->entry()); 2033 } 2034 2035 if (flags & LIR_OpArrayCopy::length_positive_check) { 2036 __ z_ltr(length, length); 2037 __ branch_optimized(Assembler::bcondNegative, *stub->entry()); 2038 } 2039 2040 // Stubs require 64 bit values. 2041 __ z_lgfr(src_pos, src_pos); // int -> long 2042 __ z_lgfr(dst_pos, dst_pos); // int -> long 2043 __ z_lgfr(length, length); // int -> long 2044 2045 if (flags & LIR_OpArrayCopy::type_check) { 2046 // We don't know the array types are compatible. 2047 if (basic_type != T_OBJECT) { 2048 // Simple test for basic type arrays. 2049 if (UseCompressedClassPointers) { 2050 __ z_l(tmp, src_klass_addr); 2051 __ z_c(tmp, dst_klass_addr); 2052 } else { 2053 __ z_lg(tmp, src_klass_addr); 2054 __ z_cg(tmp, dst_klass_addr); 2055 } 2056 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry()); 2057 } else { 2058 // For object arrays, if src is a sub class of dst then we can 2059 // safely do the copy. 2060 NearLabel cont, slow; 2061 Register src_klass = Z_R1_scratch; 2062 Register dst_klass = Z_R10; 2063 2064 __ load_klass(src_klass, src); 2065 __ load_klass(dst_klass, dst); 2066 2067 __ check_klass_subtype_fast_path(src_klass, dst_klass, tmp, &cont, &slow, NULL); 2068 2069 store_parameter(src_klass, 0); // sub 2070 store_parameter(dst_klass, 1); // super 2071 emit_call_c(Runtime1::entry_for (Runtime1::slow_subtype_check_id)); 2072 CHECK_BAILOUT(); 2073 // Sets condition code 0 for match (2 otherwise). 2074 __ branch_optimized(Assembler::bcondEqual, cont); 2075 2076 __ bind(slow); 2077 2078 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 2079 if (copyfunc_addr != NULL) { // use stub if available 2080 // Src is not a sub class of dst so we have to do a 2081 // per-element check. 2082 2083 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 2084 if ((flags & mask) != mask) { 2085 // Check that at least both of them object arrays. 2086 assert(flags & mask, "one of the two should be known to be an object array"); 2087 2088 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 2089 __ load_klass(tmp, src); 2090 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 2091 __ load_klass(tmp, dst); 2092 } 2093 Address klass_lh_addr(tmp, Klass::layout_helper_offset()); 2094 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 2095 __ load_const_optimized(Z_R1_scratch, objArray_lh); 2096 __ z_c(Z_R1_scratch, klass_lh_addr); 2097 __ branch_optimized(Assembler::bcondNotEqual, *stub->entry()); 2098 } 2099 2100 // Save outgoing arguments in callee saved registers (C convention) in case 2101 // a call to System.arraycopy is needed. 2102 Register callee_saved_src = Z_R10; 2103 Register callee_saved_src_pos = Z_R11; 2104 Register callee_saved_dst = Z_R12; 2105 Register callee_saved_dst_pos = Z_R13; 2106 Register callee_saved_length = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved. 2107 2108 __ lgr_if_needed(callee_saved_src, src); 2109 __ lgr_if_needed(callee_saved_src_pos, src_pos); 2110 __ lgr_if_needed(callee_saved_dst, dst); 2111 __ lgr_if_needed(callee_saved_dst_pos, dst_pos); 2112 __ lgr_if_needed(callee_saved_length, length); 2113 2114 __ z_llgfr(length, length); // Higher 32bits must be null. 2115 2116 __ z_sllg(Z_ARG1, src_pos, shift_amount); // index -> byte offset 2117 __ z_sllg(Z_ARG2, dst_pos, shift_amount); // index -> byte offset 2118 2119 __ z_la(Z_ARG1, Address(src, Z_ARG1, arrayOopDesc::base_offset_in_bytes(basic_type))); 2120 assert_different_registers(Z_ARG1, dst, dst_pos, length); 2121 __ z_la(Z_ARG2, Address(dst, Z_ARG2, arrayOopDesc::base_offset_in_bytes(basic_type))); 2122 assert_different_registers(Z_ARG2, dst, length); 2123 2124 __ z_lgr(Z_ARG3, length); 2125 assert_different_registers(Z_ARG3, dst); 2126 2127 __ load_klass(Z_ARG5, dst); 2128 __ z_lg(Z_ARG5, Address(Z_ARG5, ObjArrayKlass::element_klass_offset())); 2129 __ z_lg(Z_ARG4, Address(Z_ARG5, Klass::super_check_offset_offset())); 2130 emit_call_c(copyfunc_addr); 2131 CHECK_BAILOUT(); 2132 2133 #ifndef PRODUCT 2134 if (PrintC1Statistics) { 2135 NearLabel failed; 2136 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondNotEqual, failed); 2137 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_cnt); 2138 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch); 2139 __ bind(failed); 2140 } 2141 #endif 2142 2143 __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation()); 2144 2145 #ifndef PRODUCT 2146 if (PrintC1Statistics) { 2147 __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_attempt_cnt); 2148 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch); 2149 } 2150 #endif 2151 2152 __ z_lgr(tmp, Z_RET); 2153 __ z_xilf(tmp, -1); 2154 2155 // Restore previously spilled arguments 2156 __ lgr_if_needed(src, callee_saved_src); 2157 __ lgr_if_needed(src_pos, callee_saved_src_pos); 2158 __ lgr_if_needed(dst, callee_saved_dst); 2159 __ lgr_if_needed(dst_pos, callee_saved_dst_pos); 2160 __ lgr_if_needed(length, callee_saved_length); 2161 2162 __ z_sr(length, tmp); 2163 __ z_ar(src_pos, tmp); 2164 __ z_ar(dst_pos, tmp); 2165 } 2166 2167 __ branch_optimized(Assembler::bcondAlways, *stub->entry()); 2168 2169 __ bind(cont); 2170 } 2171 } 2172 2173 #ifdef ASSERT 2174 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 2175 // Sanity check the known type with the incoming class. For the 2176 // primitive case the types must match exactly with src.klass and 2177 // dst.klass each exactly matching the default type. For the 2178 // object array case, if no type check is needed then either the 2179 // dst type is exactly the expected type and the src type is a 2180 // subtype which we can't check or src is the same array as dst 2181 // but not necessarily exactly of type default_type. 2182 NearLabel known_ok, halt; 2183 metadata2reg(default_type->constant_encoding(), tmp); 2184 if (UseCompressedClassPointers) { 2185 __ encode_klass_not_null(tmp); 2186 } 2187 2188 if (basic_type != T_OBJECT) { 2189 if (UseCompressedClassPointers) { __ z_c (tmp, dst_klass_addr); } 2190 else { __ z_cg(tmp, dst_klass_addr); } 2191 __ branch_optimized(Assembler::bcondNotEqual, halt); 2192 if (UseCompressedClassPointers) { __ z_c (tmp, src_klass_addr); } 2193 else { __ z_cg(tmp, src_klass_addr); } 2194 __ branch_optimized(Assembler::bcondEqual, known_ok); 2195 } else { 2196 if (UseCompressedClassPointers) { __ z_c (tmp, dst_klass_addr); } 2197 else { __ z_cg(tmp, dst_klass_addr); } 2198 __ branch_optimized(Assembler::bcondEqual, known_ok); 2199 __ compareU64_and_branch(src, dst, Assembler::bcondEqual, known_ok); 2200 } 2201 __ bind(halt); 2202 __ stop("incorrect type information in arraycopy"); 2203 __ bind(known_ok); 2204 } 2205 #endif 2206 2207 #ifndef PRODUCT 2208 if (PrintC1Statistics) { 2209 __ load_const_optimized(Z_R1_scratch, Runtime1::arraycopy_count_address(basic_type)); 2210 __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch); 2211 } 2212 #endif 2213 2214 __ z_sllg(tmp, src_pos, shift_amount); // index -> byte offset 2215 __ z_sllg(Z_R1_scratch, dst_pos, shift_amount); // index -> byte offset 2216 2217 assert_different_registers(Z_ARG1, dst, dst_pos, length); 2218 __ z_la(Z_ARG1, Address(src, tmp, arrayOopDesc::base_offset_in_bytes(basic_type))); 2219 assert_different_registers(Z_ARG2, length); 2220 __ z_la(Z_ARG2, Address(dst, Z_R1_scratch, arrayOopDesc::base_offset_in_bytes(basic_type))); 2221 __ lgr_if_needed(Z_ARG3, length); 2222 2223 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 2224 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 2225 const char *name; 2226 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 2227 __ call_VM_leaf(entry); 2228 2229 __ bind(*stub->continuation()); 2230 } 2231 2232 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2233 if (dest->is_single_cpu()) { 2234 if (left->type() == T_OBJECT) { 2235 switch (code) { 2236 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, count->as_register()); break; 2237 case lir_shr: __ z_srag (dest->as_register(), left->as_register(), 0, count->as_register()); break; 2238 case lir_ushr: __ z_srlg (dest->as_register(), left->as_register(), 0, count->as_register()); break; 2239 default: ShouldNotReachHere(); 2240 } 2241 } else { 2242 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts"); 2243 Register masked_count = Z_R1_scratch; 2244 __ z_lr(masked_count, count->as_register()); 2245 __ z_nill(masked_count, 31); 2246 switch (code) { 2247 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), 0, masked_count); break; 2248 case lir_shr: __ z_sra (dest->as_register(), 0, masked_count); break; 2249 case lir_ushr: __ z_srl (dest->as_register(), 0, masked_count); break; 2250 default: ShouldNotReachHere(); 2251 } 2252 } 2253 } else { 2254 switch (code) { 2255 case lir_shl: __ z_sllg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break; 2256 case lir_shr: __ z_srag (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break; 2257 case lir_ushr: __ z_srlg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break; 2258 default: ShouldNotReachHere(); 2259 } 2260 } 2261 } 2262 2263 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2264 if (left->type() == T_OBJECT) { 2265 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t). 2266 Register l = left->as_register(); 2267 Register d = dest->as_register_lo(); 2268 switch (code) { 2269 case lir_shl: __ z_sllg (d, l, count); break; 2270 case lir_shr: __ z_srag (d, l, count); break; 2271 case lir_ushr: __ z_srlg (d, l, count); break; 2272 default: ShouldNotReachHere(); 2273 } 2274 return; 2275 } 2276 if (dest->is_single_cpu()) { 2277 assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts"); 2278 count = count & 0x1F; // Java spec 2279 switch (code) { 2280 case lir_shl: __ z_sllg (dest->as_register(), left->as_register(), count); break; 2281 case lir_shr: __ z_sra (dest->as_register(), count); break; 2282 case lir_ushr: __ z_srl (dest->as_register(), count); break; 2283 default: ShouldNotReachHere(); 2284 } 2285 } else if (dest->is_double_cpu()) { 2286 count = count & 63; // Java spec 2287 Register l = left->as_pointer_register(); 2288 Register d = dest->as_pointer_register(); 2289 switch (code) { 2290 case lir_shl: __ z_sllg (d, l, count); break; 2291 case lir_shr: __ z_srag (d, l, count); break; 2292 case lir_ushr: __ z_srlg (d, l, count); break; 2293 default: ShouldNotReachHere(); 2294 } 2295 } else { 2296 ShouldNotReachHere(); 2297 } 2298 } 2299 2300 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 2301 if (op->init_check()) { 2302 // Make sure klass is initialized & doesn't have finalizer. 2303 const int state_offset = in_bytes(InstanceKlass::init_state_offset()); 2304 Register iklass = op->klass()->as_register(); 2305 add_debug_info_for_null_check_here(op->stub()->info()); 2306 if (Immediate::is_uimm12(state_offset)) { 2307 __ z_cli(state_offset, iklass, InstanceKlass::fully_initialized); 2308 } else { 2309 __ z_cliy(state_offset, iklass, InstanceKlass::fully_initialized); 2310 } 2311 __ branch_optimized(Assembler::bcondNotEqual, *op->stub()->entry()); // Use long branch, because slow_case might be far. 2312 } 2313 __ allocate_object(op->obj()->as_register(), 2314 op->tmp1()->as_register(), 2315 op->tmp2()->as_register(), 2316 op->header_size(), 2317 op->object_size(), 2318 op->klass()->as_register(), 2319 *op->stub()->entry()); 2320 __ bind(*op->stub()->continuation()); 2321 __ verify_oop(op->obj()->as_register()); 2322 } 2323 2324 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 2325 Register len = op->len()->as_register(); 2326 __ move_reg_if_needed(len, T_LONG, len, T_INT); // sign extend 2327 2328 if (UseSlowPath || 2329 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 2330 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 2331 __ z_brul(*op->stub()->entry()); 2332 } else { 2333 __ allocate_array(op->obj()->as_register(), 2334 op->len()->as_register(), 2335 op->tmp1()->as_register(), 2336 op->tmp2()->as_register(), 2337 arrayOopDesc::header_size(op->type()), 2338 type2aelembytes(op->type()), 2339 op->klass()->as_register(), 2340 *op->stub()->entry()); 2341 } 2342 __ bind(*op->stub()->continuation()); 2343 } 2344 2345 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data, 2346 Register recv, Register tmp1, Label* update_done) { 2347 uint i; 2348 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2349 Label next_test; 2350 // See if the receiver is receiver[n]. 2351 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 2352 __ z_cg(recv, receiver_addr); 2353 __ z_brne(next_test); 2354 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 2355 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1); 2356 __ branch_optimized(Assembler::bcondAlways, *update_done); 2357 __ bind(next_test); 2358 } 2359 2360 // Didn't find receiver; find next empty slot and fill it in. 2361 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2362 Label next_test; 2363 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 2364 __ z_ltg(Z_R0_scratch, recv_addr); 2365 __ z_brne(next_test); 2366 __ z_stg(recv, recv_addr); 2367 __ load_const_optimized(tmp1, DataLayout::counter_increment); 2368 __ z_stg(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)), mdo); 2369 __ branch_optimized(Assembler::bcondAlways, *update_done); 2370 __ bind(next_test); 2371 } 2372 } 2373 2374 void LIR_Assembler::setup_md_access(ciMethod* method, int bci, 2375 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) { 2376 Unimplemented(); 2377 } 2378 2379 void LIR_Assembler::store_parameter(Register r, int param_num) { 2380 assert(param_num >= 0, "invalid num"); 2381 int offset_in_bytes = param_num * BytesPerWord + FrameMap::first_available_sp_in_frame; 2382 assert(offset_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2383 __ z_stg(r, offset_in_bytes, Z_SP); 2384 } 2385 2386 void LIR_Assembler::store_parameter(jint c, int param_num) { 2387 assert(param_num >= 0, "invalid num"); 2388 int offset_in_bytes = param_num * BytesPerWord + FrameMap::first_available_sp_in_frame; 2389 assert(offset_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2390 __ store_const(Address(Z_SP, offset_in_bytes), c, Z_R1_scratch, true); 2391 } 2392 2393 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 2394 // We always need a stub for the failure case. 2395 CodeStub* stub = op->stub(); 2396 Register obj = op->object()->as_register(); 2397 Register k_RInfo = op->tmp1()->as_register(); 2398 Register klass_RInfo = op->tmp2()->as_register(); 2399 Register dst = op->result_opr()->as_register(); 2400 Register Rtmp1 = Z_R1_scratch; 2401 ciKlass* k = op->klass(); 2402 2403 assert(!op->tmp3()->is_valid(), "tmp3's not needed"); 2404 2405 // Check if it needs to be profiled. 2406 ciMethodData* md = NULL; 2407 ciProfileData* data = NULL; 2408 2409 if (op->should_profile()) { 2410 ciMethod* method = op->profiled_method(); 2411 assert(method != NULL, "Should have method"); 2412 int bci = op->profiled_bci(); 2413 md = method->method_data_or_null(); 2414 assert(md != NULL, "Sanity"); 2415 data = md->bci_to_data(bci); 2416 assert(data != NULL, "need data for type check"); 2417 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 2418 } 2419 2420 // Temp operands do not overlap with inputs, if this is their last 2421 // use (end of range is exclusive), so a register conflict is possible. 2422 if (obj == k_RInfo) { 2423 k_RInfo = dst; 2424 } else if (obj == klass_RInfo) { 2425 klass_RInfo = dst; 2426 } 2427 assert_different_registers(obj, k_RInfo, klass_RInfo); 2428 2429 if (op->should_profile()) { 2430 NearLabel not_null; 2431 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondNotEqual, not_null); 2432 // Object is null; update MDO and exit. 2433 Register mdo = klass_RInfo; 2434 metadata2reg(md->constant_encoding(), mdo); 2435 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 2436 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 2437 __ or2mem_8(data_addr, header_bits); 2438 __ branch_optimized(Assembler::bcondAlways, *obj_is_null); 2439 __ bind(not_null); 2440 } else { 2441 __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondEqual, *obj_is_null); 2442 } 2443 2444 NearLabel profile_cast_failure, profile_cast_success; 2445 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 2446 Label *success_target = op->should_profile() ? &profile_cast_success : success; 2447 2448 // Patching may screw with our temporaries on sparc, 2449 // so let's do it before loading the class. 2450 if (k->is_loaded()) { 2451 metadata2reg(k->constant_encoding(), k_RInfo); 2452 } else { 2453 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 2454 } 2455 assert(obj != k_RInfo, "must be different"); 2456 2457 __ verify_oop(obj); 2458 2459 // Get object class. 2460 // Not a safepoint as obj null check happens earlier. 2461 if (op->fast_check()) { 2462 if (UseCompressedClassPointers) { 2463 __ load_klass(klass_RInfo, obj); 2464 __ compareU64_and_branch(k_RInfo, klass_RInfo, Assembler::bcondNotEqual, *failure_target); 2465 } else { 2466 __ z_cg(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 2467 __ branch_optimized(Assembler::bcondNotEqual, *failure_target); 2468 } 2469 // Successful cast, fall through to profile or jump. 2470 } else { 2471 bool need_slow_path = !k->is_loaded() || 2472 ((int) k->super_check_offset() == in_bytes(Klass::secondary_super_cache_offset())); 2473 intptr_t super_check_offset = k->is_loaded() ? k->super_check_offset() : -1L; 2474 __ load_klass(klass_RInfo, obj); 2475 // Perform the fast part of the checking logic. 2476 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, 2477 (need_slow_path ? success_target : NULL), 2478 failure_target, NULL, 2479 RegisterOrConstant(super_check_offset)); 2480 if (need_slow_path) { 2481 // Call out-of-line instance of __ check_klass_subtype_slow_path(...): 2482 address a = Runtime1::entry_for (Runtime1::slow_subtype_check_id); 2483 store_parameter(klass_RInfo, 0); // sub 2484 store_parameter(k_RInfo, 1); // super 2485 emit_call_c(a); // Sets condition code 0 for match (2 otherwise). 2486 CHECK_BAILOUT(); 2487 __ branch_optimized(Assembler::bcondNotEqual, *failure_target); 2488 // Fall through to success case. 2489 } 2490 } 2491 2492 if (op->should_profile()) { 2493 Register mdo = klass_RInfo, recv = k_RInfo; 2494 assert_different_registers(obj, mdo, recv); 2495 __ bind(profile_cast_success); 2496 metadata2reg(md->constant_encoding(), mdo); 2497 __ load_klass(recv, obj); 2498 type_profile_helper(mdo, md, data, recv, Rtmp1, success); 2499 __ branch_optimized(Assembler::bcondAlways, *success); 2500 2501 __ bind(profile_cast_failure); 2502 metadata2reg(md->constant_encoding(), mdo); 2503 __ add2mem_64(Address(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())), -(int)DataLayout::counter_increment, Rtmp1); 2504 __ branch_optimized(Assembler::bcondAlways, *failure); 2505 } else { 2506 __ branch_optimized(Assembler::bcondAlways, *success); 2507 } 2508 } 2509 2510 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 2511 LIR_Code code = op->code(); 2512 if (code == lir_store_check) { 2513 Register value = op->object()->as_register(); 2514 Register array = op->array()->as_register(); 2515 Register k_RInfo = op->tmp1()->as_register(); 2516 Register klass_RInfo = op->tmp2()->as_register(); 2517 Register Rtmp1 = Z_R1_scratch; 2518 2519 CodeStub* stub = op->stub(); 2520 2521 // Check if it needs to be profiled. 2522 ciMethodData* md = NULL; 2523 ciProfileData* data = NULL; 2524 2525 assert_different_registers(value, k_RInfo, klass_RInfo); 2526 2527 if (op->should_profile()) { 2528 ciMethod* method = op->profiled_method(); 2529 assert(method != NULL, "Should have method"); 2530 int bci = op->profiled_bci(); 2531 md = method->method_data_or_null(); 2532 assert(md != NULL, "Sanity"); 2533 data = md->bci_to_data(bci); 2534 assert(data != NULL, "need data for type check"); 2535 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 2536 } 2537 NearLabel profile_cast_success, profile_cast_failure, done; 2538 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 2539 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 2540 2541 if (op->should_profile()) { 2542 NearLabel not_null; 2543 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondNotEqual, not_null); 2544 // Object is null; update MDO and exit. 2545 Register mdo = klass_RInfo; 2546 metadata2reg(md->constant_encoding(), mdo); 2547 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 2548 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 2549 __ or2mem_8(data_addr, header_bits); 2550 __ branch_optimized(Assembler::bcondAlways, done); 2551 __ bind(not_null); 2552 } else { 2553 __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondEqual, done); 2554 } 2555 2556 add_debug_info_for_null_check_here(op->info_for_exception()); 2557 __ load_klass(k_RInfo, array); 2558 __ load_klass(klass_RInfo, value); 2559 2560 // Get instance klass (it's already uncompressed). 2561 __ z_lg(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); 2562 // Perform the fast part of the checking logic. 2563 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 2564 // Call out-of-line instance of __ check_klass_subtype_slow_path(...): 2565 address a = Runtime1::entry_for (Runtime1::slow_subtype_check_id); 2566 store_parameter(klass_RInfo, 0); // sub 2567 store_parameter(k_RInfo, 1); // super 2568 emit_call_c(a); // Sets condition code 0 for match (2 otherwise). 2569 CHECK_BAILOUT(); 2570 __ branch_optimized(Assembler::bcondNotEqual, *failure_target); 2571 // Fall through to success case. 2572 2573 if (op->should_profile()) { 2574 Register mdo = klass_RInfo, recv = k_RInfo; 2575 assert_different_registers(value, mdo, recv); 2576 __ bind(profile_cast_success); 2577 metadata2reg(md->constant_encoding(), mdo); 2578 __ load_klass(recv, value); 2579 type_profile_helper(mdo, md, data, recv, Rtmp1, &done); 2580 __ branch_optimized(Assembler::bcondAlways, done); 2581 2582 __ bind(profile_cast_failure); 2583 metadata2reg(md->constant_encoding(), mdo); 2584 __ add2mem_64(Address(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())), -(int)DataLayout::counter_increment, Rtmp1); 2585 __ branch_optimized(Assembler::bcondAlways, *stub->entry()); 2586 } 2587 2588 __ bind(done); 2589 } else { 2590 if (code == lir_checkcast) { 2591 Register obj = op->object()->as_register(); 2592 Register dst = op->result_opr()->as_register(); 2593 NearLabel success; 2594 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 2595 __ bind(success); 2596 __ lgr_if_needed(dst, obj); 2597 } else { 2598 if (code == lir_instanceof) { 2599 Register obj = op->object()->as_register(); 2600 Register dst = op->result_opr()->as_register(); 2601 NearLabel success, failure, done; 2602 emit_typecheck_helper(op, &success, &failure, &failure); 2603 __ bind(failure); 2604 __ clear_reg(dst); 2605 __ branch_optimized(Assembler::bcondAlways, done); 2606 __ bind(success); 2607 __ load_const_optimized(dst, 1); 2608 __ bind(done); 2609 } else { 2610 ShouldNotReachHere(); 2611 } 2612 } 2613 } 2614 } 2615 2616 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 2617 Register addr = op->addr()->as_pointer_register(); 2618 Register t1_cmp = Z_R1_scratch; 2619 if (op->code() == lir_cas_long) { 2620 assert(VM_Version::supports_cx8(), "wrong machine"); 2621 Register cmp_value_lo = op->cmp_value()->as_register_lo(); 2622 Register new_value_lo = op->new_value()->as_register_lo(); 2623 __ z_lgr(t1_cmp, cmp_value_lo); 2624 // Perform the compare and swap operation. 2625 __ z_csg(t1_cmp, new_value_lo, 0, addr); 2626 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { 2627 Register cmp_value = op->cmp_value()->as_register(); 2628 Register new_value = op->new_value()->as_register(); 2629 if (op->code() == lir_cas_obj) { 2630 if (UseCompressedOops) { 2631 t1_cmp = op->tmp1()->as_register(); 2632 Register t2_new = op->tmp2()->as_register(); 2633 assert_different_registers(cmp_value, new_value, addr, t1_cmp, t2_new); 2634 __ oop_encoder(t1_cmp, cmp_value, true /*maybe null*/); 2635 __ oop_encoder(t2_new, new_value, true /*maybe null*/); 2636 __ z_cs(t1_cmp, t2_new, 0, addr); 2637 } else { 2638 __ z_lgr(t1_cmp, cmp_value); 2639 __ z_csg(t1_cmp, new_value, 0, addr); 2640 } 2641 } else { 2642 __ z_lr(t1_cmp, cmp_value); 2643 __ z_cs(t1_cmp, new_value, 0, addr); 2644 } 2645 } else { 2646 ShouldNotReachHere(); // new lir_cas_?? 2647 } 2648 } 2649 2650 void LIR_Assembler::set_24bit_FPU() { 2651 ShouldNotCallThis(); // x86 only 2652 } 2653 2654 void LIR_Assembler::reset_FPU() { 2655 ShouldNotCallThis(); // x86 only 2656 } 2657 2658 void LIR_Assembler::breakpoint() { 2659 Unimplemented(); 2660 // __ breakpoint_trap(); 2661 } 2662 2663 void LIR_Assembler::push(LIR_Opr opr) { 2664 ShouldNotCallThis(); // unused 2665 } 2666 2667 void LIR_Assembler::pop(LIR_Opr opr) { 2668 ShouldNotCallThis(); // unused 2669 } 2670 2671 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { 2672 Address addr = frame_map()->address_for_monitor_lock(monitor_no); 2673 __ add2reg(dst_opr->as_register(), addr.disp(), addr.base()); 2674 } 2675 2676 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 2677 Register obj = op->obj_opr()->as_register(); // May not be an oop. 2678 Register hdr = op->hdr_opr()->as_register(); 2679 Register lock = op->lock_opr()->as_register(); 2680 if (!UseFastLocking) { 2681 __ branch_optimized(Assembler::bcondAlways, *op->stub()->entry()); 2682 } else if (op->code() == lir_lock) { 2683 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2684 // Add debug info for NullPointerException only if one is possible. 2685 if (op->info() != NULL) { 2686 add_debug_info_for_null_check_here(op->info()); 2687 } 2688 __ lock_object(hdr, obj, lock, *op->stub()->entry()); 2689 // done 2690 } else if (op->code() == lir_unlock) { 2691 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2692 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 2693 } else { 2694 ShouldNotReachHere(); 2695 } 2696 __ bind(*op->stub()->continuation()); 2697 } 2698 2699 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 2700 ciMethod* method = op->profiled_method(); 2701 int bci = op->profiled_bci(); 2702 ciMethod* callee = op->profiled_callee(); 2703 2704 // Update counter for all call types. 2705 ciMethodData* md = method->method_data_or_null(); 2706 assert(md != NULL, "Sanity"); 2707 ciProfileData* data = md->bci_to_data(bci); 2708 assert(data->is_CounterData(), "need CounterData for calls"); 2709 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 2710 Register mdo = op->mdo()->as_register(); 2711 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated"); 2712 Register tmp1 = op->tmp1()->as_register_lo(); 2713 metadata2reg(md->constant_encoding(), mdo); 2714 2715 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 2716 Bytecodes::Code bc = method->java_code_at_bci(bci); 2717 const bool callee_is_static = callee->is_loaded() && callee->is_static(); 2718 // Perform additional virtual call profiling for invokevirtual and 2719 // invokeinterface bytecodes. 2720 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && 2721 !callee_is_static && // Required for optimized MH invokes. 2722 C1ProfileVirtualCalls) { 2723 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 2724 Register recv = op->recv()->as_register(); 2725 assert_different_registers(mdo, tmp1, recv); 2726 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 2727 ciKlass* known_klass = op->known_holder(); 2728 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 2729 // We know the type that will be seen at this call site; we can 2730 // statically update the MethodData* rather than needing to do 2731 // dynamic tests on the receiver type. 2732 2733 // NOTE: we should probably put a lock around this search to 2734 // avoid collisions by concurrent compilations. 2735 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 2736 uint i; 2737 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2738 ciKlass* receiver = vc_data->receiver(i); 2739 if (known_klass->equals(receiver)) { 2740 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 2741 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1); 2742 return; 2743 } 2744 } 2745 2746 // Receiver type not found in profile data. Select an empty slot. 2747 2748 // Note that this is less efficient than it should be because it 2749 // always does a write to the receiver part of the 2750 // VirtualCallData rather than just the first time. 2751 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2752 ciKlass* receiver = vc_data->receiver(i); 2753 if (receiver == NULL) { 2754 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 2755 metadata2reg(known_klass->constant_encoding(), tmp1); 2756 __ z_stg(tmp1, recv_addr); 2757 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 2758 __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1); 2759 return; 2760 } 2761 } 2762 } else { 2763 __ load_klass(recv, recv); 2764 NearLabel update_done; 2765 type_profile_helper(mdo, md, data, recv, tmp1, &update_done); 2766 // Receiver did not match any saved receiver and there is no empty row for it. 2767 // Increment total counter to indicate polymorphic case. 2768 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1); 2769 __ bind(update_done); 2770 } 2771 } else { 2772 // static call 2773 __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1); 2774 } 2775 } 2776 2777 void LIR_Assembler::align_backward_branch_target() { 2778 __ align(OptoLoopAlignment); 2779 } 2780 2781 void LIR_Assembler::emit_delay(LIR_OpDelay* op) { 2782 ShouldNotCallThis(); // There are no delay slots on ZARCH_64. 2783 } 2784 2785 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 2786 assert(left->is_register(), "can only handle registers"); 2787 2788 if (left->is_single_cpu()) { 2789 __ z_lcr(dest->as_register(), left->as_register()); 2790 } else if (left->is_single_fpu()) { 2791 __ z_lcebr(dest->as_float_reg(), left->as_float_reg()); 2792 } else if (left->is_double_fpu()) { 2793 __ z_lcdbr(dest->as_double_reg(), left->as_double_reg()); 2794 } else { 2795 assert(left->is_double_cpu(), "Must be a long"); 2796 __ z_lcgr(dest->as_register_lo(), left->as_register_lo()); 2797 } 2798 } 2799 2800 void LIR_Assembler::fxch(int i) { 2801 ShouldNotCallThis(); // x86 only 2802 } 2803 2804 void LIR_Assembler::fld(int i) { 2805 ShouldNotCallThis(); // x86 only 2806 } 2807 2808 void LIR_Assembler::ffree(int i) { 2809 ShouldNotCallThis(); // x86 only 2810 } 2811 2812 void LIR_Assembler::rt_call(LIR_Opr result, address dest, 2813 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 2814 assert(!tmp->is_valid(), "don't need temporary"); 2815 emit_call_c(dest); 2816 CHECK_BAILOUT(); 2817 if (info != NULL) { 2818 add_call_info_here(info); 2819 } 2820 } 2821 2822 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 2823 ShouldNotCallThis(); // not needed on ZARCH_64 2824 } 2825 2826 void LIR_Assembler::membar() { 2827 __ z_fence(); 2828 } 2829 2830 void LIR_Assembler::membar_acquire() { 2831 __ z_acquire(); 2832 } 2833 2834 void LIR_Assembler::membar_release() { 2835 __ z_release(); 2836 } 2837 2838 void LIR_Assembler::membar_loadload() { 2839 __ z_acquire(); 2840 } 2841 2842 void LIR_Assembler::membar_storestore() { 2843 __ z_release(); 2844 } 2845 2846 void LIR_Assembler::membar_loadstore() { 2847 __ z_acquire(); 2848 } 2849 2850 void LIR_Assembler::membar_storeload() { 2851 __ z_fence(); 2852 } 2853 2854 void LIR_Assembler::on_spin_wait() { 2855 Unimplemented(); 2856 } 2857 2858 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) { 2859 LIR_Address* addr = addr_opr->as_address_ptr(); 2860 assert(addr->scale() == LIR_Address::times_1, "scaling unsupported"); 2861 __ load_address(dest->as_pointer_register(), as_Address(addr)); 2862 } 2863 2864 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 2865 ShouldNotCallThis(); // unused 2866 } 2867 2868 #ifdef ASSERT 2869 // Emit run-time assertion. 2870 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 2871 Unimplemented(); 2872 } 2873 #endif 2874 2875 void LIR_Assembler::peephole(LIR_List*) { 2876 // Do nothing for now. 2877 } 2878 2879 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 2880 assert(code == lir_xadd, "lir_xchg not supported"); 2881 Address src_addr = as_Address(src->as_address_ptr()); 2882 Register base = src_addr.base(); 2883 intptr_t disp = src_addr.disp(); 2884 if (src_addr.index()->is_valid()) { 2885 // LAA and LAAG do not support index register. 2886 __ load_address(Z_R1_scratch, src_addr); 2887 base = Z_R1_scratch; 2888 disp = 0; 2889 } 2890 if (data->type() == T_INT) { 2891 __ z_laa(dest->as_register(), data->as_register(), disp, base); 2892 } else if (data->type() == T_LONG) { 2893 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); 2894 __ z_laag(dest->as_register_lo(), data->as_register_lo(), disp, base); 2895 } else { 2896 ShouldNotReachHere(); 2897 } 2898 } 2899 2900 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 2901 Register obj = op->obj()->as_register(); 2902 Register tmp1 = op->tmp()->as_pointer_register(); 2903 Register tmp2 = Z_R1_scratch; 2904 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 2905 ciKlass* exact_klass = op->exact_klass(); 2906 intptr_t current_klass = op->current_klass(); 2907 bool not_null = op->not_null(); 2908 bool no_conflict = op->no_conflict(); 2909 2910 Label update, next, none, null_seen, init_klass; 2911 2912 bool do_null = !not_null; 2913 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 2914 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 2915 2916 assert(do_null || do_update, "why are we here?"); 2917 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 2918 2919 __ verify_oop(obj); 2920 2921 if (do_null || tmp1 != obj DEBUG_ONLY(|| true)) { 2922 __ z_ltgr(tmp1, obj); 2923 } 2924 if (do_null) { 2925 __ z_brnz(update); 2926 if (!TypeEntries::was_null_seen(current_klass)) { 2927 __ z_lg(tmp1, mdo_addr); 2928 __ z_oill(tmp1, TypeEntries::null_seen); 2929 __ z_stg(tmp1, mdo_addr); 2930 } 2931 if (do_update) { 2932 __ z_bru(next); 2933 } 2934 } else { 2935 __ asm_assert_ne("unexpect null obj", __LINE__); 2936 } 2937 2938 __ bind(update); 2939 2940 if (do_update) { 2941 #ifdef ASSERT 2942 if (exact_klass != NULL) { 2943 __ load_klass(tmp1, tmp1); 2944 metadata2reg(exact_klass->constant_encoding(), tmp2); 2945 __ z_cgr(tmp1, tmp2); 2946 __ asm_assert_eq("exact klass and actual klass differ", __LINE__); 2947 } 2948 #endif 2949 2950 Label do_update; 2951 __ z_lg(tmp2, mdo_addr); 2952 2953 if (!no_conflict) { 2954 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 2955 if (exact_klass != NULL) { 2956 metadata2reg(exact_klass->constant_encoding(), tmp1); 2957 } else { 2958 __ load_klass(tmp1, tmp1); 2959 } 2960 2961 // Klass seen before: nothing to do (regardless of unknown bit). 2962 __ z_lgr(Z_R0_scratch, tmp2); 2963 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction"); 2964 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF); 2965 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next); 2966 2967 // Already unknown: Nothing to do anymore. 2968 __ z_tmll(tmp2, TypeEntries::type_unknown); 2969 __ z_brc(Assembler::bcondAllOne, next); 2970 2971 if (TypeEntries::is_type_none(current_klass)) { 2972 __ z_lgr(Z_R0_scratch, tmp2); 2973 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction"); 2974 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF); 2975 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, init_klass); 2976 } 2977 } else { 2978 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 2979 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 2980 2981 // Already unknown: Nothing to do anymore. 2982 __ z_tmll(tmp2, TypeEntries::type_unknown); 2983 __ z_brc(Assembler::bcondAllOne, next); 2984 } 2985 2986 // Different than before. Cannot keep accurate profile. 2987 __ z_oill(tmp2, TypeEntries::type_unknown); 2988 __ z_bru(do_update); 2989 } else { 2990 // There's a single possible klass at this profile point. 2991 assert(exact_klass != NULL, "should be"); 2992 if (TypeEntries::is_type_none(current_klass)) { 2993 metadata2reg(exact_klass->constant_encoding(), tmp1); 2994 __ z_lgr(Z_R0_scratch, tmp2); 2995 assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction"); 2996 __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF); 2997 __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next); 2998 #ifdef ASSERT 2999 { 3000 Label ok; 3001 __ z_lgr(Z_R0_scratch, tmp2); 3002 assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction"); 3003 __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF); 3004 __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, ok); 3005 __ stop("unexpected profiling mismatch"); 3006 __ bind(ok); 3007 } 3008 #endif 3009 3010 } else { 3011 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 3012 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 3013 3014 // Already unknown: Nothing to do anymore. 3015 __ z_tmll(tmp2, TypeEntries::type_unknown); 3016 __ z_brc(Assembler::bcondAllOne, next); 3017 __ z_oill(tmp2, TypeEntries::type_unknown); 3018 __ z_bru(do_update); 3019 } 3020 } 3021 3022 __ bind(init_klass); 3023 // Combine klass and null_seen bit (only used if (tmp & type_mask)==0). 3024 __ z_ogr(tmp2, tmp1); 3025 3026 __ bind(do_update); 3027 __ z_stg(tmp2, mdo_addr); 3028 3029 __ bind(next); 3030 } 3031 } 3032 3033 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 3034 assert(op->crc()->is_single_cpu(), "crc must be register"); 3035 assert(op->val()->is_single_cpu(), "byte value must be register"); 3036 assert(op->result_opr()->is_single_cpu(), "result must be register"); 3037 Register crc = op->crc()->as_register(); 3038 Register val = op->val()->as_register(); 3039 Register res = op->result_opr()->as_register(); 3040 3041 assert_different_registers(val, crc, res); 3042 3043 __ load_const_optimized(res, StubRoutines::crc_table_addr()); 3044 __ kernel_crc32_singleByteReg(crc, val, res, true); 3045 __ z_lgfr(res, crc); 3046 } 3047 3048 #undef __