src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.aarch64.test/src/org/graalvm/compiler/asm/aarch64/test/TestProtectedAssembler.java
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src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.aarch64.test/src/org/graalvm/compiler/asm/aarch64/test/TestProtectedAssembler.java

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 209     protected void bfm(int size, Register dst, Register src, int r, int s) {
 210         super.bfm(size, dst, src, r, s);
 211     }
 212 
 213     @Override
 214     protected void ubfm(int size, Register dst, Register src, int r, int s) {
 215         super.ubfm(size, dst, src, r, s);
 216     }
 217 
 218     @Override
 219     protected void sbfm(int size, Register dst, Register src, int r, int s) {
 220         super.sbfm(size, dst, src, r, s);
 221     }
 222 
 223     @Override
 224     protected void extr(int size, Register dst, Register src1, Register src2, int lsb) {
 225         super.extr(size, dst, src1, src2, lsb);
 226     }
 227 
 228     @Override
 229     protected void adds(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) {
 230         super.adds(size, dst, src1, src2, shiftType, imm);
 231     }
 232 
 233     @Override
 234     protected void subs(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) {
 235         super.subs(size, dst, src1, src2, shiftType, imm);
 236     }
 237 
 238     @Override
 239     protected void add(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) {
 240         super.add(size, dst, src1, src2, shiftType, imm);
 241     }
 242 
 243     @Override
 244     protected void sub(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) {
 245         super.sub(size, dst, src1, src2, shiftType, imm);
 246     }
 247 
 248     @Override
 249     public void add(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) {
 250         super.add(size, dst, src1, src2, extendType, shiftAmt);
 251     }
 252 
 253     @Override
 254     protected void adds(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) {
 255         super.adds(size, dst, src1, src2, extendType, shiftAmt);
 256     }
 257 
 258     @Override
 259     protected void sub(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) {
 260         super.sub(size, dst, src1, src2, extendType, shiftAmt);
 261     }
 262 
 263     @Override
 264     protected void subs(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) {
 265         super.subs(size, dst, src1, src2, extendType, shiftAmt);
 266     }
 267 
 268     @Override
 269     protected void and(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) {
 270         super.and(size, dst, src1, src2, shiftType, shiftAmt);
 271     }
 272 
 273     @Override
 274     protected void ands(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) {
 275         super.ands(size, dst, src1, src2, shiftType, shiftAmt);
 276     }
 277 
 278     @Override
 279     protected void bic(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) {
 280         super.bic(size, dst, src1, src2, shiftType, shiftAmt);
 281     }
 282 
 283     @Override
 284     protected void bics(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) {


 319     protected void lsr(int size, Register dst, Register src1, Register src2) {
 320         super.lsr(size, dst, src1, src2);
 321     }
 322 
 323     @Override
 324     protected void ror(int size, Register dst, Register src1, Register src2) {
 325         super.ror(size, dst, src1, src2);
 326     }
 327 
 328     @Override
 329     protected void cls(int size, Register dst, Register src) {
 330         super.cls(size, dst, src);
 331     }
 332 
 333     @Override
 334     public void clz(int size, Register dst, Register src) {
 335         super.clz(size, dst, src);
 336     }
 337 
 338     @Override
 339     protected void rbit(int size, Register dst, Register src) {
 340         super.rbit(size, dst, src);
 341     }
 342 
 343     @Override
 344     public void rev(int size, Register dst, Register src) {
 345         super.rev(size, dst, src);
 346     }
 347 
 348     @Override
 349     protected void csel(int size, Register dst, Register src1, Register src2, ConditionFlag condition) {
 350         super.csel(size, dst, src1, src2, condition);
 351     }
 352 
 353     @Override
 354     protected void csneg(int size, Register dst, Register src1, Register src2, ConditionFlag condition) {
 355         super.csneg(size, dst, src1, src2, condition);
 356     }
 357 
 358     @Override
 359     protected void csinc(int size, Register dst, Register src1, Register src2, ConditionFlag condition) {




 209     protected void bfm(int size, Register dst, Register src, int r, int s) {
 210         super.bfm(size, dst, src, r, s);
 211     }
 212 
 213     @Override
 214     protected void ubfm(int size, Register dst, Register src, int r, int s) {
 215         super.ubfm(size, dst, src, r, s);
 216     }
 217 
 218     @Override
 219     protected void sbfm(int size, Register dst, Register src, int r, int s) {
 220         super.sbfm(size, dst, src, r, s);
 221     }
 222 
 223     @Override
 224     protected void extr(int size, Register dst, Register src1, Register src2, int lsb) {
 225         super.extr(size, dst, src1, src2, lsb);
 226     }
 227 
 228     @Override
 229     public void adds(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) {
 230         super.adds(size, dst, src1, src2, shiftType, imm);
 231     }
 232 
 233     @Override
 234     public void subs(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) {
 235         super.subs(size, dst, src1, src2, shiftType, imm);
 236     }
 237 
 238     @Override
 239     protected void add(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) {
 240         super.add(size, dst, src1, src2, shiftType, imm);
 241     }
 242 
 243     @Override
 244     protected void sub(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) {
 245         super.sub(size, dst, src1, src2, shiftType, imm);
 246     }
 247 
 248     @Override
 249     public void add(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) {
 250         super.add(size, dst, src1, src2, extendType, shiftAmt);
 251     }
 252 
 253     @Override
 254     protected void adds(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) {
 255         super.adds(size, dst, src1, src2, extendType, shiftAmt);
 256     }
 257 
 258     @Override
 259     protected void sub(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) {
 260         super.sub(size, dst, src1, src2, extendType, shiftAmt);
 261     }
 262 
 263     @Override
 264     public void subs(int size, Register dst, Register src1, Register src2, ExtendType extendType, int shiftAmt) {
 265         super.subs(size, dst, src1, src2, extendType, shiftAmt);
 266     }
 267 
 268     @Override
 269     protected void and(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) {
 270         super.and(size, dst, src1, src2, shiftType, shiftAmt);
 271     }
 272 
 273     @Override
 274     protected void ands(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) {
 275         super.ands(size, dst, src1, src2, shiftType, shiftAmt);
 276     }
 277 
 278     @Override
 279     protected void bic(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) {
 280         super.bic(size, dst, src1, src2, shiftType, shiftAmt);
 281     }
 282 
 283     @Override
 284     protected void bics(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int shiftAmt) {


 319     protected void lsr(int size, Register dst, Register src1, Register src2) {
 320         super.lsr(size, dst, src1, src2);
 321     }
 322 
 323     @Override
 324     protected void ror(int size, Register dst, Register src1, Register src2) {
 325         super.ror(size, dst, src1, src2);
 326     }
 327 
 328     @Override
 329     protected void cls(int size, Register dst, Register src) {
 330         super.cls(size, dst, src);
 331     }
 332 
 333     @Override
 334     public void clz(int size, Register dst, Register src) {
 335         super.clz(size, dst, src);
 336     }
 337 
 338     @Override
 339     public void rbit(int size, Register dst, Register src) {
 340         super.rbit(size, dst, src);
 341     }
 342 
 343     @Override
 344     public void rev(int size, Register dst, Register src) {
 345         super.rev(size, dst, src);
 346     }
 347 
 348     @Override
 349     protected void csel(int size, Register dst, Register src1, Register src2, ConditionFlag condition) {
 350         super.csel(size, dst, src1, src2, condition);
 351     }
 352 
 353     @Override
 354     protected void csneg(int size, Register dst, Register src1, Register src2, ConditionFlag condition) {
 355         super.csneg(size, dst, src1, src2, condition);
 356     }
 357 
 358     @Override
 359     protected void csinc(int size, Register dst, Register src1, Register src2, ConditionFlag condition) {


src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.aarch64.test/src/org/graalvm/compiler/asm/aarch64/test/TestProtectedAssembler.java
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