483 int encode = prefixAndEncode(dst.encoding, src.encoding);
484 emitByte(0x23);
485 emitByte(0xC0 | encode);
486 }
487
488 public final void bsfq(Register dst, Register src) {
489 int encode = prefixqAndEncode(dst.encoding, src.encoding);
490 emitByte(0x0F);
491 emitByte(0xBC);
492 emitByte(0xC0 | encode);
493 }
494
495 public final void bsfq(Register dst, AMD64Address src) {
496 prefixq(src, dst);
497 emitByte(0x0F);
498 emitByte(0xBC);
499 emitOperandHelper(dst, src);
500 }
501
502 public final void bsrq(Register dst, Register src) {
503 assert !supports(CPUFeature.LZCNT);
504 int encode = prefixqAndEncode(dst.encoding, src.encoding);
505 emitByte(0x0F);
506 emitByte(0xBD);
507 emitByte(0xC0 | encode);
508 }
509
510 public final void bsrq(Register dst, AMD64Address src) {
511 assert !supports(CPUFeature.LZCNT);
512 prefixq(src, dst);
513 emitByte(0x0F);
514 emitByte(0xBD);
515 emitOperandHelper(dst, src);
516 }
517
518 public final void bsrl(Register dst, Register src) {
519 assert !supports(CPUFeature.LZCNT);
520 int encode = prefixAndEncode(dst.encoding, src.encoding);
521 emitByte(0x0F);
522 emitByte(0xBD);
523 emitByte(0xC0 | encode);
524 }
525
526 public final void bsrl(Register dst, AMD64Address src) {
527 assert !supports(CPUFeature.LZCNT);
528 prefix(src, dst);
529 emitByte(0x0F);
530 emitByte(0xBD);
531 emitOperandHelper(dst, src);
532 }
533
534 public final void bswapl(Register reg) {
535 int encode = prefixAndEncode(reg.encoding);
536 emitByte(0x0F);
537 emitByte(0xC8 | encode);
538 }
539
540 public final void cdql() {
541 emitByte(0x99);
542 }
543
544 public final void cmovl(ConditionFlag cc, Register dst, Register src) {
545 int encode = prefixAndEncode(dst.encoding, src.encoding);
546 emitByte(0x0F);
547 emitByte(0x40 | cc.getValue());
1310 emitByte(0xC0 | encode);
1311 }
1312
1313 public final void negl(Register dst) {
1314 int encode = prefixAndEncode(dst.encoding);
1315 emitByte(0xF7);
1316 emitByte(0xD8 | encode);
1317 }
1318
1319 public final void notl(Register dst) {
1320 int encode = prefixAndEncode(dst.encoding);
1321 emitByte(0xF7);
1322 emitByte(0xD0 | encode);
1323 }
1324
1325 @Override
1326 public final void ensureUniquePC() {
1327 nop();
1328 }
1329
1330 public final void nop() {
1331 nop(1);
1332 }
1333
1334 public void nop(int count) {
1335 int i = count;
1336 if (UseNormalNop) {
1337 assert i > 0 : " ";
1338 // The fancy nops aren't currently recognized by debuggers making it a
1339 // pain to disassemble code while debugging. If assert are on clearly
1340 // speed is not an issue so simply use the single byte traditional nop
1341 // to do alignment.
1342
1343 for (; i > 0; i--) {
1344 emitByte(0x90);
1345 }
1346 return;
1347 }
1348
1349 if (UseAddressNop) {
1861
1862 public final void testl(AMD64Address dst, int imm32) {
1863 prefix(dst);
1864 emitByte(0xF7);
1865 emitOperandHelper(0, dst);
1866 emitInt(imm32);
1867 }
1868
1869 public final void testl(Register dst, Register src) {
1870 int encode = prefixAndEncode(dst.encoding, src.encoding);
1871 emitByte(0x85);
1872 emitByte(0xC0 | encode);
1873 }
1874
1875 public final void testl(Register dst, AMD64Address src) {
1876 prefix(src, dst);
1877 emitByte(0x85);
1878 emitOperandHelper(dst, src);
1879 }
1880
1881 public final void ucomisd(Register dst, AMD64Address src) {
1882 assert dst.getRegisterCategory().equals(AMD64.XMM);
1883 emitByte(0x66);
1884 ucomiss(dst, src);
1885 }
1886
1887 public final void ucomisd(Register dst, Register src) {
1888 assert dst.getRegisterCategory().equals(AMD64.XMM);
1889 assert src.getRegisterCategory().equals(AMD64.XMM);
1890 emitByte(0x66);
1891 ucomiss(dst, src);
1892 }
1893
1894 public final void ucomiss(Register dst, AMD64Address src) {
1895 assert dst.getRegisterCategory().equals(AMD64.XMM);
1896
1897 prefix(src, dst);
1898 emitByte(0x0F);
1899 emitByte(0x2E);
1900 emitOperandHelper(dst, src);
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483 int encode = prefixAndEncode(dst.encoding, src.encoding);
484 emitByte(0x23);
485 emitByte(0xC0 | encode);
486 }
487
488 public final void bsfq(Register dst, Register src) {
489 int encode = prefixqAndEncode(dst.encoding, src.encoding);
490 emitByte(0x0F);
491 emitByte(0xBC);
492 emitByte(0xC0 | encode);
493 }
494
495 public final void bsfq(Register dst, AMD64Address src) {
496 prefixq(src, dst);
497 emitByte(0x0F);
498 emitByte(0xBC);
499 emitOperandHelper(dst, src);
500 }
501
502 public final void bsrq(Register dst, Register src) {
503 int encode = prefixqAndEncode(dst.encoding, src.encoding);
504 emitByte(0x0F);
505 emitByte(0xBD);
506 emitByte(0xC0 | encode);
507 }
508
509 public final void bsrq(Register dst, AMD64Address src) {
510 prefixq(src, dst);
511 emitByte(0x0F);
512 emitByte(0xBD);
513 emitOperandHelper(dst, src);
514 }
515
516 public final void bsrl(Register dst, Register src) {
517 int encode = prefixAndEncode(dst.encoding, src.encoding);
518 emitByte(0x0F);
519 emitByte(0xBD);
520 emitByte(0xC0 | encode);
521 }
522
523 public final void bsrl(Register dst, AMD64Address src) {
524 prefix(src, dst);
525 emitByte(0x0F);
526 emitByte(0xBD);
527 emitOperandHelper(dst, src);
528 }
529
530 public final void bswapl(Register reg) {
531 int encode = prefixAndEncode(reg.encoding);
532 emitByte(0x0F);
533 emitByte(0xC8 | encode);
534 }
535
536 public final void cdql() {
537 emitByte(0x99);
538 }
539
540 public final void cmovl(ConditionFlag cc, Register dst, Register src) {
541 int encode = prefixAndEncode(dst.encoding, src.encoding);
542 emitByte(0x0F);
543 emitByte(0x40 | cc.getValue());
1306 emitByte(0xC0 | encode);
1307 }
1308
1309 public final void negl(Register dst) {
1310 int encode = prefixAndEncode(dst.encoding);
1311 emitByte(0xF7);
1312 emitByte(0xD8 | encode);
1313 }
1314
1315 public final void notl(Register dst) {
1316 int encode = prefixAndEncode(dst.encoding);
1317 emitByte(0xF7);
1318 emitByte(0xD0 | encode);
1319 }
1320
1321 @Override
1322 public final void ensureUniquePC() {
1323 nop();
1324 }
1325
1326 public final void lzcntl(Register dst, Register src) {
1327 assert supports(CPUFeature.LZCNT);
1328 emitByte(0xF3);
1329 int encode = prefixAndEncode(dst.encoding, src.encoding);
1330 emitByte(0x0F);
1331 emitByte(0xBD);
1332 emitByte(0xC0 | encode);
1333 }
1334
1335 public final void lzcntq(Register dst, Register src) {
1336 assert supports(CPUFeature.LZCNT);
1337 emitByte(0xF3);
1338 int encode = prefixqAndEncode(dst.encoding, src.encoding);
1339 emitByte(0x0F);
1340 emitByte(0xBD);
1341 emitByte(0xC0 | encode);
1342 }
1343
1344 public final void lzcntl(Register dst, AMD64Address src) {
1345 assert supports(CPUFeature.LZCNT);
1346 emitByte(0xF3);
1347 prefix(src, dst);
1348 emitByte(0x0F);
1349 emitByte(0xBD);
1350 emitOperandHelper(dst, src);
1351 }
1352
1353 public final void lzcntq(Register dst, AMD64Address src) {
1354 assert supports(CPUFeature.LZCNT);
1355 emitByte(0xF3);
1356 prefixq(src, dst);
1357 emitByte(0x0F);
1358 emitByte(0xBD);
1359 emitOperandHelper(dst, src);
1360 }
1361
1362 public final void nop() {
1363 nop(1);
1364 }
1365
1366 public void nop(int count) {
1367 int i = count;
1368 if (UseNormalNop) {
1369 assert i > 0 : " ";
1370 // The fancy nops aren't currently recognized by debuggers making it a
1371 // pain to disassemble code while debugging. If assert are on clearly
1372 // speed is not an issue so simply use the single byte traditional nop
1373 // to do alignment.
1374
1375 for (; i > 0; i--) {
1376 emitByte(0x90);
1377 }
1378 return;
1379 }
1380
1381 if (UseAddressNop) {
1893
1894 public final void testl(AMD64Address dst, int imm32) {
1895 prefix(dst);
1896 emitByte(0xF7);
1897 emitOperandHelper(0, dst);
1898 emitInt(imm32);
1899 }
1900
1901 public final void testl(Register dst, Register src) {
1902 int encode = prefixAndEncode(dst.encoding, src.encoding);
1903 emitByte(0x85);
1904 emitByte(0xC0 | encode);
1905 }
1906
1907 public final void testl(Register dst, AMD64Address src) {
1908 prefix(src, dst);
1909 emitByte(0x85);
1910 emitOperandHelper(dst, src);
1911 }
1912
1913 public final void tzcntl(Register dst, Register src) {
1914 assert supports(CPUFeature.BMI1);
1915 emitByte(0xF3);
1916 int encode = prefixAndEncode(dst.encoding, src.encoding);
1917 emitByte(0x0F);
1918 emitByte(0xBC);
1919 emitByte(0xC0 | encode);
1920 }
1921
1922 public final void tzcntq(Register dst, Register src) {
1923 assert supports(CPUFeature.BMI1);
1924 emitByte(0xF3);
1925 int encode = prefixqAndEncode(dst.encoding, src.encoding);
1926 emitByte(0x0F);
1927 emitByte(0xBC);
1928 emitByte(0xC0 | encode);
1929 }
1930
1931 public final void tzcntl(Register dst, AMD64Address src) {
1932 assert supports(CPUFeature.BMI1);
1933 emitByte(0xF3);
1934 prefix(src, dst);
1935 emitByte(0x0F);
1936 emitByte(0xBC);
1937 emitOperandHelper(dst, src);
1938 }
1939
1940 public final void tzcntq(Register dst, AMD64Address src) {
1941 assert supports(CPUFeature.BMI1);
1942 emitByte(0xF3);
1943 prefixq(src, dst);
1944 emitByte(0x0F);
1945 emitByte(0xBC);
1946 emitOperandHelper(dst, src);
1947 }
1948
1949 public final void ucomisd(Register dst, AMD64Address src) {
1950 assert dst.getRegisterCategory().equals(AMD64.XMM);
1951 emitByte(0x66);
1952 ucomiss(dst, src);
1953 }
1954
1955 public final void ucomisd(Register dst, Register src) {
1956 assert dst.getRegisterCategory().equals(AMD64.XMM);
1957 assert src.getRegisterCategory().equals(AMD64.XMM);
1958 emitByte(0x66);
1959 ucomiss(dst, src);
1960 }
1961
1962 public final void ucomiss(Register dst, AMD64Address src) {
1963 assert dst.getRegisterCategory().equals(AMD64.XMM);
1964
1965 prefix(src, dst);
1966 emitByte(0x0F);
1967 emitByte(0x2E);
1968 emitOperandHelper(dst, src);
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