graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64BitManipulationOp.java
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basic-graal Cdiff graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64BitManipulationOp.java
graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64BitManipulationOp.java
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*** 33,43 ****
public enum IntrinsicOpcode {
IPOPCNT,
LPOPCNT,
IBSR,
LBSR,
! BSF;
}
@Opcode private final IntrinsicOpcode opcode;
@Def protected AllocatableValue result;
@Use({OperandFlag.REG, OperandFlag.STACK}) protected AllocatableValue input;
--- 33,47 ----
public enum IntrinsicOpcode {
IPOPCNT,
LPOPCNT,
IBSR,
LBSR,
! BSF,
! ILZCNT,
! LLZCNT,
! ITZCNT,
! LTZCNT
}
@Opcode private final IntrinsicOpcode opcode;
@Def protected AllocatableValue result;
@Use({OperandFlag.REG, OperandFlag.STACK}) protected AllocatableValue input;
*** 67,76 ****
--- 71,92 ----
masm.bsrl(dst, src);
break;
case LBSR:
masm.bsrq(dst, src);
break;
+ case ILZCNT:
+ masm.lzcntl(dst, src);
+ break;
+ case LLZCNT:
+ masm.lzcntq(dst, src);
+ break;
+ case ITZCNT:
+ masm.tzcntl(dst, src);
+ break;
+ case LTZCNT:
+ masm.tzcntq(dst, src);
+ break;
}
} else {
AMD64Address src = (AMD64Address) crb.asAddress(input);
switch (opcode) {
case IPOPCNT:
*** 86,95 ****
--- 102,123 ----
masm.bsrl(dst, src);
break;
case LBSR:
masm.bsrq(dst, src);
break;
+ case ILZCNT:
+ masm.lzcntl(dst, src);
+ break;
+ case LLZCNT:
+ masm.lzcntq(dst, src);
+ break;
+ case ITZCNT:
+ masm.tzcntl(dst, src);
+ break;
+ case LTZCNT:
+ masm.tzcntq(dst, src);
+ break;
}
}
}
}
graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64BitManipulationOp.java
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