18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  */
  23 package com.oracle.graal.lir.amd64;
  24 
  25 import com.oracle.graal.api.code.*;
  26 import com.oracle.graal.api.meta.*;
  27 import com.oracle.graal.asm.amd64.*;
  28 import com.oracle.graal.lir.*;
  29 import com.oracle.graal.lir.asm.*;
  30 
  31 public class AMD64BitManipulationOp extends AMD64LIRInstruction {
  32 
  33     public enum IntrinsicOpcode {
  34         IPOPCNT,
  35         LPOPCNT,
  36         IBSR,
  37         LBSR,
  38         BSF;




  39     }
  40 
  41     @Opcode private final IntrinsicOpcode opcode;
  42     @Def protected AllocatableValue result;
  43     @Use({OperandFlag.REG, OperandFlag.STACK}) protected AllocatableValue input;
  44 
  45     public AMD64BitManipulationOp(IntrinsicOpcode opcode, AllocatableValue result, AllocatableValue input) {
  46         this.opcode = opcode;
  47         this.result = result;
  48         this.input = input;
  49     }
  50 
  51     @Override
  52     public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
  53         Register dst = ValueUtil.asIntReg(result);
  54         if (ValueUtil.isRegister(input)) {
  55             Register src = ValueUtil.asRegister(input);
  56             switch (opcode) {
  57                 case IPOPCNT:
  58                     masm.popcntl(dst, src);
  59                     break;
  60                 case LPOPCNT:
  61                     masm.popcntq(dst, src);
  62                     break;
  63                 case BSF:
  64                     masm.bsfq(dst, src);
  65                     break;
  66                 case IBSR:
  67                     masm.bsrl(dst, src);
  68                     break;
  69                 case LBSR:
  70                     masm.bsrq(dst, src);
  71                     break;












  72             }
  73         } else {
  74             AMD64Address src = (AMD64Address) crb.asAddress(input);
  75             switch (opcode) {
  76                 case IPOPCNT:
  77                     masm.popcntl(dst, src);
  78                     break;
  79                 case LPOPCNT:
  80                     masm.popcntq(dst, src);
  81                     break;
  82                 case BSF:
  83                     masm.bsfq(dst, src);
  84                     break;
  85                 case IBSR:
  86                     masm.bsrl(dst, src);
  87                     break;
  88                 case LBSR:
  89                     masm.bsrq(dst, src);
  90                     break;












  91             }
  92         }
  93     }
  94 
  95 }

  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  */
  23 package com.oracle.graal.lir.amd64;
  24 
  25 import com.oracle.graal.api.code.*;
  26 import com.oracle.graal.api.meta.*;
  27 import com.oracle.graal.asm.amd64.*;
  28 import com.oracle.graal.lir.*;
  29 import com.oracle.graal.lir.asm.*;
  30 
  31 public class AMD64BitManipulationOp extends AMD64LIRInstruction {
  32 
  33     public enum IntrinsicOpcode {
  34         IPOPCNT,
  35         LPOPCNT,
  36         IBSR,
  37         LBSR,
  38         BSF,
  39         ILZCNT,
  40         LLZCNT,
  41         ITZCNT,
  42         LTZCNT
  43     }
  44 
  45     @Opcode private final IntrinsicOpcode opcode;
  46     @Def protected AllocatableValue result;
  47     @Use({OperandFlag.REG, OperandFlag.STACK}) protected AllocatableValue input;
  48 
  49     public AMD64BitManipulationOp(IntrinsicOpcode opcode, AllocatableValue result, AllocatableValue input) {
  50         this.opcode = opcode;
  51         this.result = result;
  52         this.input = input;
  53     }
  54 
  55     @Override
  56     public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
  57         Register dst = ValueUtil.asIntReg(result);
  58         if (ValueUtil.isRegister(input)) {
  59             Register src = ValueUtil.asRegister(input);
  60             switch (opcode) {
  61                 case IPOPCNT:
  62                     masm.popcntl(dst, src);
  63                     break;
  64                 case LPOPCNT:
  65                     masm.popcntq(dst, src);
  66                     break;
  67                 case BSF:
  68                     masm.bsfq(dst, src);
  69                     break;
  70                 case IBSR:
  71                     masm.bsrl(dst, src);
  72                     break;
  73                 case LBSR:
  74                     masm.bsrq(dst, src);
  75                     break;
  76                 case ILZCNT:
  77                     masm.lzcntl(dst, src);
  78                     break;
  79                 case LLZCNT:
  80                     masm.lzcntq(dst, src);
  81                     break;
  82                 case ITZCNT:
  83                     masm.tzcntl(dst, src);
  84                     break;
  85                 case LTZCNT:
  86                     masm.tzcntq(dst, src);
  87                     break;
  88             }
  89         } else {
  90             AMD64Address src = (AMD64Address) crb.asAddress(input);
  91             switch (opcode) {
  92                 case IPOPCNT:
  93                     masm.popcntl(dst, src);
  94                     break;
  95                 case LPOPCNT:
  96                     masm.popcntq(dst, src);
  97                     break;
  98                 case BSF:
  99                     masm.bsfq(dst, src);
 100                     break;
 101                 case IBSR:
 102                     masm.bsrl(dst, src);
 103                     break;
 104                 case LBSR:
 105                     masm.bsrq(dst, src);
 106                     break;
 107                 case ILZCNT:
 108                     masm.lzcntl(dst, src);
 109                     break;
 110                 case LLZCNT:
 111                     masm.lzcntq(dst, src);
 112                     break;
 113                 case ITZCNT:
 114                     masm.tzcntl(dst, src);
 115                     break;
 116                 case LTZCNT:
 117                     masm.tzcntq(dst, src);
 118                     break;
 119             }
 120         }
 121     }
 122 
 123 }