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src/cpu/x86/vm/assembler_x86.cpp

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rev 8713 : SIMD: CMoveVD - .ad is "almost" good. need to make CC in codegen taken rightly from IdealGraph.
Also added (Windows only) an option to stop in debugger after compiled file has been printed.
See compile.cpp: WINDOWS_ONLY(if(method()->has_option("BreakAfterCompilation")) DebugBreak();)
rev 8733 : SIMD: cleanup. src/cpu/x86/vm/x86.ad needs more.
Some !FIXME! are remaining, mostly for second thought
rev 8926 : Merge
rev 9039 : Merge
rev 9047 : SIMD: mberg review fixes
rev 9101 : Merge
rev 9147 : Merge


6295   emit_operand(dst, src);
6296 }
6297 
6298 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
6299                                VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
6300   int encode = vex_prefix_and_encode(dst, nds, src, pre, vector_len, VEX_OPCODE_0F, legacy_mode, no_mask_reg);
6301   emit_int8(opcode);
6302   emit_int8((unsigned char)(0xC0 | encode));
6303 }
6304 
6305 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
6306                                  VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
6307   int src_enc = src->encoding();
6308   int dst_enc = dst->encoding();
6309   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6310   int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
6311   emit_int8(opcode);
6312   emit_int8((unsigned char)(0xC0 | encode));
6313 }
6314 




















6315 #ifndef _LP64
6316 
6317 void Assembler::incl(Register dst) {
6318   // Don't use it directly. Use MacroAssembler::incrementl() instead.
6319   emit_int8(0x40 | dst->encoding());
6320 }
6321 
6322 void Assembler::lea(Register dst, Address src) {
6323   leal(dst, src);
6324 }
6325 
6326 void Assembler::mov_literal32(Address dst, int32_t imm32,  RelocationHolder const& rspec) {
6327   InstructionMark im(this);
6328   emit_int8((unsigned char)0xC7);
6329   emit_operand(rax, dst);
6330   emit_data((int)imm32, rspec, 0);
6331 }
6332 
6333 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6334   InstructionMark im(this);




6295   emit_operand(dst, src);
6296 }
6297 
6298 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
6299                                VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
6300   int encode = vex_prefix_and_encode(dst, nds, src, pre, vector_len, VEX_OPCODE_0F, legacy_mode, no_mask_reg);
6301   emit_int8(opcode);
6302   emit_int8((unsigned char)(0xC0 | encode));
6303 }
6304 
6305 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
6306                                  VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
6307   int src_enc = src->encoding();
6308   int dst_enc = dst->encoding();
6309   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6310   int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
6311   emit_int8(opcode);
6312   emit_int8((unsigned char)(0xC0 | encode));
6313 }
6314 
6315 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
6316   assert(VM_Version::supports_avx(), "");
6317   assert(!VM_Version::supports_evex(), "");
6318   int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F, /* no_mask_reg */ false);
6319   emit_int8((unsigned char)0xC2);
6320   emit_int8((unsigned char)(0xC0 | encode));
6321   emit_int8((unsigned char)(0xF & cop));
6322 }
6323 
6324 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
6325   assert(VM_Version::supports_avx(), "");
6326   assert(!VM_Version::supports_evex(), "");
6327   int encode = vex_prefix_and_encode(dst, nds, src1, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A, /* no_mask_reg */ false);
6328   emit_int8((unsigned char)0x4B);
6329   emit_int8((unsigned char)(0xC0 | encode));
6330   int src2_enc = src2->encoding();
6331   emit_int8((unsigned char)(0xF0 & src2_enc<<4));
6332 }
6333 
6334 
6335 #ifndef _LP64
6336 
6337 void Assembler::incl(Register dst) {
6338   // Don't use it directly. Use MacroAssembler::incrementl() instead.
6339   emit_int8(0x40 | dst->encoding());
6340 }
6341 
6342 void Assembler::lea(Register dst, Address src) {
6343   leal(dst, src);
6344 }
6345 
6346 void Assembler::mov_literal32(Address dst, int32_t imm32,  RelocationHolder const& rspec) {
6347   InstructionMark im(this);
6348   emit_int8((unsigned char)0xC7);
6349   emit_operand(rax, dst);
6350   emit_data((int)imm32, rspec, 0);
6351 }
6352 
6353 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6354   InstructionMark im(this);
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