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src/cpu/x86/vm/assembler_x86.cpp

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6309   emit_operand(dst, src);
6310 }
6311 
6312 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
6313                                VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
6314   int encode = vex_prefix_and_encode(dst, nds, src, pre, vector_len, VEX_OPCODE_0F, legacy_mode, no_mask_reg);
6315   emit_int8(opcode);
6316   emit_int8((unsigned char)(0xC0 | encode));
6317 }
6318 
6319 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
6320                                  VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
6321   int src_enc = src->encoding();
6322   int dst_enc = dst->encoding();
6323   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6324   int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
6325   emit_int8(opcode);
6326   emit_int8((unsigned char)(0xC0 | encode));
6327 }
6328 




















6329 #ifndef _LP64
6330 
6331 void Assembler::incl(Register dst) {
6332   // Don't use it directly. Use MacroAssembler::incrementl() instead.
6333   emit_int8(0x40 | dst->encoding());
6334 }
6335 
6336 void Assembler::lea(Register dst, Address src) {
6337   leal(dst, src);
6338 }
6339 
6340 void Assembler::mov_literal32(Address dst, int32_t imm32,  RelocationHolder const& rspec) {
6341   InstructionMark im(this);
6342   emit_int8((unsigned char)0xC7);
6343   emit_operand(rax, dst);
6344   emit_data((int)imm32, rspec, 0);
6345 }
6346 
6347 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6348   InstructionMark im(this);




6309   emit_operand(dst, src);
6310 }
6311 
6312 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
6313                                VexSimdPrefix pre, int vector_len, bool no_mask_reg, bool legacy_mode) {
6314   int encode = vex_prefix_and_encode(dst, nds, src, pre, vector_len, VEX_OPCODE_0F, legacy_mode, no_mask_reg);
6315   emit_int8(opcode);
6316   emit_int8((unsigned char)(0xC0 | encode));
6317 }
6318 
6319 void Assembler::emit_vex_arith_q(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src,
6320                                  VexSimdPrefix pre, int vector_len, bool no_mask_reg) {
6321   int src_enc = src->encoding();
6322   int dst_enc = dst->encoding();
6323   int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6324   int encode = vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, VEX_OPCODE_0F, true, vector_len, false, no_mask_reg);
6325   emit_int8(opcode);
6326   emit_int8((unsigned char)(0xC0 | encode));
6327 }
6328 
6329 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
6330   assert(VM_Version::supports_avx(), "");
6331   assert(!VM_Version::supports_evex(), "");
6332   int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector_len, VEX_OPCODE_0F, /* no_mask_reg */ false);
6333   emit_int8((unsigned char)0xC2);
6334   emit_int8((unsigned char)(0xC0 | encode));
6335   emit_int8((unsigned char)(0xF & cop));
6336 }
6337 
6338 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
6339   assert(VM_Version::supports_avx(), "");
6340   assert(!VM_Version::supports_evex(), "");
6341   int encode = vex_prefix_and_encode(dst, nds, src1, VEX_SIMD_66, vector_len, VEX_OPCODE_0F_3A, /* no_mask_reg */ false);
6342   emit_int8((unsigned char)0x4B);
6343   emit_int8((unsigned char)(0xC0 | encode));
6344   int src2_enc = src2->encoding();
6345   emit_int8((unsigned char)(0xF0 & src2_enc<<4));
6346 }
6347 
6348 
6349 #ifndef _LP64
6350 
6351 void Assembler::incl(Register dst) {
6352   // Don't use it directly. Use MacroAssembler::incrementl() instead.
6353   emit_int8(0x40 | dst->encoding());
6354 }
6355 
6356 void Assembler::lea(Register dst, Address src) {
6357   leal(dst, src);
6358 }
6359 
6360 void Assembler::mov_literal32(Address dst, int32_t imm32,  RelocationHolder const& rspec) {
6361   InstructionMark im(this);
6362   emit_int8((unsigned char)0xC7);
6363   emit_operand(rax, dst);
6364   emit_data((int)imm32, rspec, 0);
6365 }
6366 
6367 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6368   InstructionMark im(this);


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