1 /*
   2  * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "logging/log.hpp"
  29 #include "logging/logStream.hpp"
  30 #include "memory/resourceArea.hpp"
  31 #include "prims/jvm.h"
  32 #include "runtime/java.hpp"
  33 #include "runtime/os.hpp"
  34 #include "runtime/stubCodeGenerator.hpp"
  35 #include "vm_version_x86.hpp"
  36 
  37 
  38 int VM_Version::_cpu;
  39 int VM_Version::_model;
  40 int VM_Version::_stepping;
  41 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
  42 
  43 // Address of instruction which causes SEGV
  44 address VM_Version::_cpuinfo_segv_addr = 0;
  45 // Address of instruction after the one which causes SEGV
  46 address VM_Version::_cpuinfo_cont_addr = 0;
  47 
  48 static BufferBlob* stub_blob;
  49 static const int stub_size = 1100;
  50 
  51 extern "C" {
  52   typedef void (*get_cpu_info_stub_t)(void*);
  53 }
  54 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
  55 
  56 
  57 class VM_Version_StubGenerator: public StubCodeGenerator {
  58  public:
  59 
  60   VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
  61 
  62   address generate_get_cpu_info() {
  63     // Flags to test CPU type.
  64     const uint32_t HS_EFL_AC = 0x40000;
  65     const uint32_t HS_EFL_ID = 0x200000;
  66     // Values for when we don't have a CPUID instruction.
  67     const int      CPU_FAMILY_SHIFT = 8;
  68     const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
  69     const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
  70     bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2);
  71 
  72     Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
  73     Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, ext_cpuid8, done, wrapup;
  74     Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
  75 
  76     StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
  77 #   define __ _masm->
  78 
  79     address start = __ pc();
  80 
  81     //
  82     // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
  83     //
  84     // LP64: rcx and rdx are first and second argument registers on windows
  85 
  86     __ push(rbp);
  87 #ifdef _LP64
  88     __ mov(rbp, c_rarg0); // cpuid_info address
  89 #else
  90     __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
  91 #endif
  92     __ push(rbx);
  93     __ push(rsi);
  94     __ pushf();          // preserve rbx, and flags
  95     __ pop(rax);
  96     __ push(rax);
  97     __ mov(rcx, rax);
  98     //
  99     // if we are unable to change the AC flag, we have a 386
 100     //
 101     __ xorl(rax, HS_EFL_AC);
 102     __ push(rax);
 103     __ popf();
 104     __ pushf();
 105     __ pop(rax);
 106     __ cmpptr(rax, rcx);
 107     __ jccb(Assembler::notEqual, detect_486);
 108 
 109     __ movl(rax, CPU_FAMILY_386);
 110     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 111     __ jmp(done);
 112 
 113     //
 114     // If we are unable to change the ID flag, we have a 486 which does
 115     // not support the "cpuid" instruction.
 116     //
 117     __ bind(detect_486);
 118     __ mov(rax, rcx);
 119     __ xorl(rax, HS_EFL_ID);
 120     __ push(rax);
 121     __ popf();
 122     __ pushf();
 123     __ pop(rax);
 124     __ cmpptr(rcx, rax);
 125     __ jccb(Assembler::notEqual, detect_586);
 126 
 127     __ bind(cpu486);
 128     __ movl(rax, CPU_FAMILY_486);
 129     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 130     __ jmp(done);
 131 
 132     //
 133     // At this point, we have a chip which supports the "cpuid" instruction
 134     //
 135     __ bind(detect_586);
 136     __ xorl(rax, rax);
 137     __ cpuid();
 138     __ orl(rax, rax);
 139     __ jcc(Assembler::equal, cpu486);   // if cpuid doesn't support an input
 140                                         // value of at least 1, we give up and
 141                                         // assume a 486
 142     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
 143     __ movl(Address(rsi, 0), rax);
 144     __ movl(Address(rsi, 4), rbx);
 145     __ movl(Address(rsi, 8), rcx);
 146     __ movl(Address(rsi,12), rdx);
 147 
 148     __ cmpl(rax, 0xa);                  // Is cpuid(0xB) supported?
 149     __ jccb(Assembler::belowEqual, std_cpuid4);
 150 
 151     //
 152     // cpuid(0xB) Processor Topology
 153     //
 154     __ movl(rax, 0xb);
 155     __ xorl(rcx, rcx);   // Threads level
 156     __ cpuid();
 157 
 158     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
 159     __ movl(Address(rsi, 0), rax);
 160     __ movl(Address(rsi, 4), rbx);
 161     __ movl(Address(rsi, 8), rcx);
 162     __ movl(Address(rsi,12), rdx);
 163 
 164     __ movl(rax, 0xb);
 165     __ movl(rcx, 1);     // Cores level
 166     __ cpuid();
 167     __ push(rax);
 168     __ andl(rax, 0x1f);  // Determine if valid topology level
 169     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 170     __ andl(rax, 0xffff);
 171     __ pop(rax);
 172     __ jccb(Assembler::equal, std_cpuid4);
 173 
 174     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
 175     __ movl(Address(rsi, 0), rax);
 176     __ movl(Address(rsi, 4), rbx);
 177     __ movl(Address(rsi, 8), rcx);
 178     __ movl(Address(rsi,12), rdx);
 179 
 180     __ movl(rax, 0xb);
 181     __ movl(rcx, 2);     // Packages level
 182     __ cpuid();
 183     __ push(rax);
 184     __ andl(rax, 0x1f);  // Determine if valid topology level
 185     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 186     __ andl(rax, 0xffff);
 187     __ pop(rax);
 188     __ jccb(Assembler::equal, std_cpuid4);
 189 
 190     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
 191     __ movl(Address(rsi, 0), rax);
 192     __ movl(Address(rsi, 4), rbx);
 193     __ movl(Address(rsi, 8), rcx);
 194     __ movl(Address(rsi,12), rdx);
 195 
 196     //
 197     // cpuid(0x4) Deterministic cache params
 198     //
 199     __ bind(std_cpuid4);
 200     __ movl(rax, 4);
 201     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
 202     __ jccb(Assembler::greater, std_cpuid1);
 203 
 204     __ xorl(rcx, rcx);   // L1 cache
 205     __ cpuid();
 206     __ push(rax);
 207     __ andl(rax, 0x1f);  // Determine if valid cache parameters used
 208     __ orl(rax, rax);    // eax[4:0] == 0 indicates invalid cache
 209     __ pop(rax);
 210     __ jccb(Assembler::equal, std_cpuid1);
 211 
 212     __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
 213     __ movl(Address(rsi, 0), rax);
 214     __ movl(Address(rsi, 4), rbx);
 215     __ movl(Address(rsi, 8), rcx);
 216     __ movl(Address(rsi,12), rdx);
 217 
 218     //
 219     // Standard cpuid(0x1)
 220     //
 221     __ bind(std_cpuid1);
 222     __ movl(rax, 1);
 223     __ cpuid();
 224     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 225     __ movl(Address(rsi, 0), rax);
 226     __ movl(Address(rsi, 4), rbx);
 227     __ movl(Address(rsi, 8), rcx);
 228     __ movl(Address(rsi,12), rdx);
 229 
 230     //
 231     // Check if OS has enabled XGETBV instruction to access XCR0
 232     // (OSXSAVE feature flag) and CPU supports AVX
 233     //
 234     __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
 235     __ cmpl(rcx, 0x18000000);
 236     __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
 237 
 238     //
 239     // XCR0, XFEATURE_ENABLED_MASK register
 240     //
 241     __ xorl(rcx, rcx);   // zero for XCR0 register
 242     __ xgetbv();
 243     __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
 244     __ movl(Address(rsi, 0), rax);
 245     __ movl(Address(rsi, 4), rdx);
 246 
 247     //
 248     // cpuid(0x7) Structured Extended Features
 249     //
 250     __ bind(sef_cpuid);
 251     __ movl(rax, 7);
 252     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
 253     __ jccb(Assembler::greater, ext_cpuid);
 254 
 255     __ xorl(rcx, rcx);
 256     __ cpuid();
 257     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 258     __ movl(Address(rsi, 0), rax);
 259     __ movl(Address(rsi, 4), rbx);
 260 
 261     //
 262     // Extended cpuid(0x80000000)
 263     //
 264     __ bind(ext_cpuid);
 265     __ movl(rax, 0x80000000);
 266     __ cpuid();
 267     __ cmpl(rax, 0x80000000);     // Is cpuid(0x80000001) supported?
 268     __ jcc(Assembler::belowEqual, done);
 269     __ cmpl(rax, 0x80000004);     // Is cpuid(0x80000005) supported?
 270     __ jcc(Assembler::belowEqual, ext_cpuid1);
 271     __ cmpl(rax, 0x80000006);     // Is cpuid(0x80000007) supported?
 272     __ jccb(Assembler::belowEqual, ext_cpuid5);
 273     __ cmpl(rax, 0x80000007);     // Is cpuid(0x80000008) supported?
 274     __ jccb(Assembler::belowEqual, ext_cpuid7);
 275     __ cmpl(rax, 0x80000008);     // Is cpuid(0x80000009 and above) supported?
 276     __ jccb(Assembler::belowEqual, ext_cpuid8);
 277     __ cmpl(rax, 0x8000001E);     // Is cpuid(0x8000001E) supported?
 278     __ jccb(Assembler::below, ext_cpuid8);
 279     //
 280     // Extended cpuid(0x8000001E)
 281     //
 282     __ movl(rax, 0x8000001E);
 283     __ cpuid();
 284     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1E_offset())));
 285     __ movl(Address(rsi, 0), rax);
 286     __ movl(Address(rsi, 4), rbx);
 287     __ movl(Address(rsi, 8), rcx);
 288     __ movl(Address(rsi,12), rdx);
 289 
 290     //
 291     // Extended cpuid(0x80000008)
 292     //
 293     __ bind(ext_cpuid8);
 294     __ movl(rax, 0x80000008);
 295     __ cpuid();
 296     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
 297     __ movl(Address(rsi, 0), rax);
 298     __ movl(Address(rsi, 4), rbx);
 299     __ movl(Address(rsi, 8), rcx);
 300     __ movl(Address(rsi,12), rdx);
 301 
 302     //
 303     // Extended cpuid(0x80000007)
 304     //
 305     __ bind(ext_cpuid7);
 306     __ movl(rax, 0x80000007);
 307     __ cpuid();
 308     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
 309     __ movl(Address(rsi, 0), rax);
 310     __ movl(Address(rsi, 4), rbx);
 311     __ movl(Address(rsi, 8), rcx);
 312     __ movl(Address(rsi,12), rdx);
 313 
 314     //
 315     // Extended cpuid(0x80000005)
 316     //
 317     __ bind(ext_cpuid5);
 318     __ movl(rax, 0x80000005);
 319     __ cpuid();
 320     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
 321     __ movl(Address(rsi, 0), rax);
 322     __ movl(Address(rsi, 4), rbx);
 323     __ movl(Address(rsi, 8), rcx);
 324     __ movl(Address(rsi,12), rdx);
 325 
 326     //
 327     // Extended cpuid(0x80000001)
 328     //
 329     __ bind(ext_cpuid1);
 330     __ movl(rax, 0x80000001);
 331     __ cpuid();
 332     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
 333     __ movl(Address(rsi, 0), rax);
 334     __ movl(Address(rsi, 4), rbx);
 335     __ movl(Address(rsi, 8), rcx);
 336     __ movl(Address(rsi,12), rdx);
 337 
 338     //
 339     // Check if OS has enabled XGETBV instruction to access XCR0
 340     // (OSXSAVE feature flag) and CPU supports AVX
 341     //
 342     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 343     __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
 344     __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
 345     __ cmpl(rcx, 0x18000000);
 346     __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
 347 
 348     __ movl(rax, 0x6);
 349     __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 350     __ cmpl(rax, 0x6);
 351     __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
 352 
 353     // we need to bridge farther than imm8, so we use this island as a thunk
 354     __ bind(done);
 355     __ jmp(wrapup);
 356 
 357     __ bind(start_simd_check);
 358     //
 359     // Some OSs have a bug when upper 128/256bits of YMM/ZMM
 360     // registers are not restored after a signal processing.
 361     // Generate SEGV here (reference through NULL)
 362     // and check upper YMM/ZMM bits after it.
 363     //
 364     intx saved_useavx = UseAVX;
 365     intx saved_usesse = UseSSE;
 366     // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
 367     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 368     __ movl(rax, 0x10000);
 369     __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
 370     __ cmpl(rax, 0x10000);
 371     __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
 372     // check _cpuid_info.xem_xcr0_eax.bits.opmask
 373     // check _cpuid_info.xem_xcr0_eax.bits.zmm512
 374     // check _cpuid_info.xem_xcr0_eax.bits.zmm32
 375     __ movl(rax, 0xE0);
 376     __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 377     __ cmpl(rax, 0xE0);
 378     __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
 379 
 380     // If UseAVX is unitialized or is set by the user to include EVEX
 381     if (use_evex) {
 382       // EVEX setup: run in lowest evex mode
 383       VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
 384       UseAVX = 3;
 385       UseSSE = 2;
 386 #ifdef _WINDOWS
 387       // xmm5-xmm15 are not preserved by caller on windows
 388       // https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx
 389       __ subptr(rsp, 64);
 390       __ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit);
 391 #ifdef _LP64
 392       __ subptr(rsp, 64);
 393       __ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit);
 394       __ subptr(rsp, 64);
 395       __ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit);
 396 #endif // _LP64
 397 #endif // _WINDOWS
 398 
 399       // load value into all 64 bytes of zmm7 register
 400       __ movl(rcx, VM_Version::ymm_test_value());
 401       __ movdl(xmm0, rcx);
 402       __ movl(rcx, 0xffff);
 403       __ kmovwl(k1, rcx);
 404       __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
 405       __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
 406 #ifdef _LP64
 407       __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
 408       __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
 409 #endif
 410       VM_Version::clean_cpuFeatures();
 411       __ jmp(save_restore_except);
 412     }
 413 
 414     __ bind(legacy_setup);
 415     // AVX setup
 416     VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
 417     UseAVX = 1;
 418     UseSSE = 2;
 419 #ifdef _WINDOWS
 420     __ subptr(rsp, 32);
 421     __ vmovdqu(Address(rsp, 0), xmm7);
 422 #ifdef _LP64
 423     __ subptr(rsp, 32);
 424     __ vmovdqu(Address(rsp, 0), xmm8);
 425     __ subptr(rsp, 32);
 426     __ vmovdqu(Address(rsp, 0), xmm15);
 427 #endif // _LP64
 428 #endif // _WINDOWS
 429 
 430     // load value into all 32 bytes of ymm7 register
 431     __ movl(rcx, VM_Version::ymm_test_value());
 432 
 433     __ movdl(xmm0, rcx);
 434     __ pshufd(xmm0, xmm0, 0x00);
 435     __ vinsertf128_high(xmm0, xmm0);
 436     __ vmovdqu(xmm7, xmm0);
 437 #ifdef _LP64
 438     __ vmovdqu(xmm8, xmm0);
 439     __ vmovdqu(xmm15, xmm0);
 440 #endif
 441     VM_Version::clean_cpuFeatures();
 442 
 443     __ bind(save_restore_except);
 444     __ xorl(rsi, rsi);
 445     VM_Version::set_cpuinfo_segv_addr(__ pc());
 446     // Generate SEGV
 447     __ movl(rax, Address(rsi, 0));
 448 
 449     VM_Version::set_cpuinfo_cont_addr(__ pc());
 450     // Returns here after signal. Save xmm0 to check it later.
 451 
 452     // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
 453     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 454     __ movl(rax, 0x10000);
 455     __ andl(rax, Address(rsi, 4));
 456     __ cmpl(rax, 0x10000);
 457     __ jcc(Assembler::notEqual, legacy_save_restore);
 458     // check _cpuid_info.xem_xcr0_eax.bits.opmask
 459     // check _cpuid_info.xem_xcr0_eax.bits.zmm512
 460     // check _cpuid_info.xem_xcr0_eax.bits.zmm32
 461     __ movl(rax, 0xE0);
 462     __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 463     __ cmpl(rax, 0xE0);
 464     __ jcc(Assembler::notEqual, legacy_save_restore);
 465 
 466     // If UseAVX is unitialized or is set by the user to include EVEX
 467     if (use_evex) {
 468       // EVEX check: run in lowest evex mode
 469       VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
 470       UseAVX = 3;
 471       UseSSE = 2;
 472       __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
 473       __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
 474       __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
 475 #ifdef _LP64
 476       __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
 477       __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
 478 #endif
 479 
 480 #ifdef _WINDOWS
 481 #ifdef _LP64
 482       __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
 483       __ addptr(rsp, 64);
 484       __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
 485       __ addptr(rsp, 64);
 486 #endif // _LP64
 487       __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
 488       __ addptr(rsp, 64);
 489 #endif // _WINDOWS
 490       generate_vzeroupper(wrapup);
 491       VM_Version::clean_cpuFeatures();
 492       UseAVX = saved_useavx;
 493       UseSSE = saved_usesse;
 494       __ jmp(wrapup);
 495    }
 496 
 497     __ bind(legacy_save_restore);
 498     // AVX check
 499     VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
 500     UseAVX = 1;
 501     UseSSE = 2;
 502     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
 503     __ vmovdqu(Address(rsi, 0), xmm0);
 504     __ vmovdqu(Address(rsi, 32), xmm7);
 505 #ifdef _LP64
 506     __ vmovdqu(Address(rsi, 64), xmm8);
 507     __ vmovdqu(Address(rsi, 96), xmm15);
 508 #endif
 509 
 510 #ifdef _WINDOWS
 511 #ifdef _LP64
 512     __ vmovdqu(xmm15, Address(rsp, 0));
 513     __ addptr(rsp, 32);
 514     __ vmovdqu(xmm8, Address(rsp, 0));
 515     __ addptr(rsp, 32);
 516 #endif // _LP64
 517     __ vmovdqu(xmm7, Address(rsp, 0));
 518     __ addptr(rsp, 32);
 519 #endif // _WINDOWS
 520     generate_vzeroupper(wrapup);
 521     VM_Version::clean_cpuFeatures();
 522     UseAVX = saved_useavx;
 523     UseSSE = saved_usesse;
 524 
 525     __ bind(wrapup);
 526     __ popf();
 527     __ pop(rsi);
 528     __ pop(rbx);
 529     __ pop(rbp);
 530     __ ret(0);
 531 
 532 #   undef __
 533 
 534     return start;
 535   };
 536   void generate_vzeroupper(Label& L_wrapup) {
 537 #   define __ _masm->
 538     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
 539     __ cmpl(Address(rsi, 4), 0x756e6547);  // 'uneG'
 540     __ jcc(Assembler::notEqual, L_wrapup);
 541     __ movl(rcx, 0x0FFF0FF0);
 542     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 543     __ andl(rcx, Address(rsi, 0));
 544     __ cmpl(rcx, 0x00050670);              // If it is Xeon Phi 3200/5200/7200
 545     __ jcc(Assembler::equal, L_wrapup);
 546     __ cmpl(rcx, 0x00080650);              // If it is Future Xeon Phi
 547     __ jcc(Assembler::equal, L_wrapup);
 548     __ vzeroupper();
 549 #   undef __
 550   }
 551 };
 552 
 553 void VM_Version::get_processor_features() {
 554 
 555   _cpu = 4; // 486 by default
 556   _model = 0;
 557   _stepping = 0;
 558   _features = 0;
 559   _logical_processors_per_package = 1;
 560   // i486 internal cache is both I&D and has a 16-byte line size
 561   _L1_data_cache_line_size = 16;
 562 
 563   // Get raw processor info
 564 
 565   get_cpu_info_stub(&_cpuid_info);
 566 
 567   assert_is_initialized();
 568   _cpu = extended_cpu_family();
 569   _model = extended_cpu_model();
 570   _stepping = cpu_stepping();
 571 
 572   if (cpu_family() > 4) { // it supports CPUID
 573     _features = feature_flags();
 574     // Logical processors are only available on P4s and above,
 575     // and only if hyperthreading is available.
 576     _logical_processors_per_package = logical_processor_count();
 577     _L1_data_cache_line_size = L1_line_size();
 578   }
 579 
 580   _supports_cx8 = supports_cmpxchg8();
 581   // xchg and xadd instructions
 582   _supports_atomic_getset4 = true;
 583   _supports_atomic_getadd4 = true;
 584   LP64_ONLY(_supports_atomic_getset8 = true);
 585   LP64_ONLY(_supports_atomic_getadd8 = true);
 586 
 587 #ifdef _LP64
 588   // OS should support SSE for x64 and hardware should support at least SSE2.
 589   if (!VM_Version::supports_sse2()) {
 590     vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
 591   }
 592   // in 64 bit the use of SSE2 is the minimum
 593   if (UseSSE < 2) UseSSE = 2;
 594 #endif
 595 
 596 #ifdef AMD64
 597   // flush_icache_stub have to be generated first.
 598   // That is why Icache line size is hard coded in ICache class,
 599   // see icache_x86.hpp. It is also the reason why we can't use
 600   // clflush instruction in 32-bit VM since it could be running
 601   // on CPU which does not support it.
 602   //
 603   // The only thing we can do is to verify that flushed
 604   // ICache::line_size has correct value.
 605   guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
 606   // clflush_size is size in quadwords (8 bytes).
 607   guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
 608 #endif
 609 
 610   // If the OS doesn't support SSE, we can't use this feature even if the HW does
 611   if (!os::supports_sse())
 612     _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
 613 
 614   if (UseSSE < 4) {
 615     _features &= ~CPU_SSE4_1;
 616     _features &= ~CPU_SSE4_2;
 617   }
 618 
 619   if (UseSSE < 3) {
 620     _features &= ~CPU_SSE3;
 621     _features &= ~CPU_SSSE3;
 622     _features &= ~CPU_SSE4A;
 623   }
 624 
 625   if (UseSSE < 2)
 626     _features &= ~CPU_SSE2;
 627 
 628   if (UseSSE < 1)
 629     _features &= ~CPU_SSE;
 630 
 631   // first try initial setting and detect what we can support
 632   if (UseAVX > 0) {
 633     if (UseAVX > 2 && supports_evex()) {
 634       UseAVX = 3;
 635     } else if (UseAVX > 1 && supports_avx2()) {
 636       UseAVX = 2;
 637     } else if (UseAVX > 0 && supports_avx()) {
 638       UseAVX = 1;
 639     } else {
 640       UseAVX = 0;
 641     }
 642   } else if (UseAVX < 0) {
 643     UseAVX = 0;
 644   }
 645 
 646   if (UseAVX < 3) {
 647     _features &= ~CPU_AVX512F;
 648     _features &= ~CPU_AVX512DQ;
 649     _features &= ~CPU_AVX512CD;
 650     _features &= ~CPU_AVX512BW;
 651     _features &= ~CPU_AVX512VL;
 652   }
 653 
 654   if (UseAVX < 2)
 655     _features &= ~CPU_AVX2;
 656 
 657   if (UseAVX < 1) {
 658     _features &= ~CPU_AVX;
 659     _features &= ~CPU_VZEROUPPER;
 660   }
 661 
 662   if (logical_processors_per_package() == 1) {
 663     // HT processor could be installed on a system which doesn't support HT.
 664     _features &= ~CPU_HT;
 665   }
 666 
 667   if( is_intel() ) { // Intel cpus specific settings
 668     if (is_knights_family()) {
 669       _features &= ~CPU_VZEROUPPER;
 670     }
 671   }
 672 
 673   char buf[256];
 674   jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 675                cores_per_cpu(), threads_per_core(),
 676                cpu_family(), _model, _stepping,
 677                (supports_cmov() ? ", cmov" : ""),
 678                (supports_cmpxchg8() ? ", cx8" : ""),
 679                (supports_fxsr() ? ", fxsr" : ""),
 680                (supports_mmx()  ? ", mmx"  : ""),
 681                (supports_sse()  ? ", sse"  : ""),
 682                (supports_sse2() ? ", sse2" : ""),
 683                (supports_sse3() ? ", sse3" : ""),
 684                (supports_ssse3()? ", ssse3": ""),
 685                (supports_sse4_1() ? ", sse4.1" : ""),
 686                (supports_sse4_2() ? ", sse4.2" : ""),
 687                (supports_popcnt() ? ", popcnt" : ""),
 688                (supports_avx()    ? ", avx" : ""),
 689                (supports_avx2()   ? ", avx2" : ""),
 690                (supports_aes()    ? ", aes" : ""),
 691                (supports_clmul()  ? ", clmul" : ""),
 692                (supports_erms()   ? ", erms" : ""),
 693                (supports_rtm()    ? ", rtm" : ""),
 694                (supports_mmx_ext() ? ", mmxext" : ""),
 695                (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
 696                (supports_lzcnt()   ? ", lzcnt": ""),
 697                (supports_sse4a()   ? ", sse4a": ""),
 698                (supports_ht() ? ", ht": ""),
 699                (supports_tsc() ? ", tsc": ""),
 700                (supports_tscinv_bit() ? ", tscinvbit": ""),
 701                (supports_tscinv() ? ", tscinv": ""),
 702                (supports_bmi1() ? ", bmi1" : ""),
 703                (supports_bmi2() ? ", bmi2" : ""),
 704                (supports_adx() ? ", adx" : ""),
 705                (supports_evex() ? ", evex" : ""),
 706                (supports_sha() ? ", sha" : ""),
 707                (supports_fma() ? ", fma" : ""));
 708   _features_string = os::strdup(buf);
 709 
 710   // UseSSE is set to the smaller of what hardware supports and what
 711   // the command line requires.  I.e., you cannot set UseSSE to 2 on
 712   // older Pentiums which do not support it.
 713   if (UseSSE > 4) UseSSE=4;
 714   if (UseSSE < 0) UseSSE=0;
 715   if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
 716     UseSSE = MIN2((intx)3,UseSSE);
 717   if (!supports_sse3()) // Drop to 2 if no SSE3 support
 718     UseSSE = MIN2((intx)2,UseSSE);
 719   if (!supports_sse2()) // Drop to 1 if no SSE2 support
 720     UseSSE = MIN2((intx)1,UseSSE);
 721   if (!supports_sse ()) // Drop to 0 if no SSE  support
 722     UseSSE = 0;
 723 
 724   // Use AES instructions if available.
 725   if (supports_aes()) {
 726     if (FLAG_IS_DEFAULT(UseAES)) {
 727       FLAG_SET_DEFAULT(UseAES, true);
 728     }
 729     if (!UseAES) {
 730       if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 731         warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
 732       }
 733       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 734     } else {
 735       if (UseSSE > 2) {
 736         if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 737           FLAG_SET_DEFAULT(UseAESIntrinsics, true);
 738         }
 739       } else {
 740         // The AES intrinsic stubs require AES instruction support (of course)
 741         // but also require sse3 mode or higher for instructions it use.
 742         if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 743           warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
 744         }
 745         FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 746       }
 747 
 748       // --AES-CTR begins--
 749       if (!UseAESIntrinsics) {
 750         if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 751           warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
 752           FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 753         }
 754       } else {
 755         if(supports_sse4_1()) {
 756           if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 757             FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
 758           }
 759         } else {
 760            // The AES-CTR intrinsic stubs require AES instruction support (of course)
 761            // but also require sse4.1 mode or higher for instructions it use.
 762           if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 763              warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
 764            }
 765            FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 766         }
 767       }
 768       // --AES-CTR ends--
 769     }
 770   } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
 771     if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
 772       warning("AES instructions are not available on this CPU");
 773       FLAG_SET_DEFAULT(UseAES, false);
 774     }
 775     if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 776       warning("AES intrinsics are not available on this CPU");
 777       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 778     }
 779     if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 780       warning("AES-CTR intrinsics are not available on this CPU");
 781       FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 782     }
 783   }
 784 
 785   // Use CLMUL instructions if available.
 786   if (supports_clmul()) {
 787     if (FLAG_IS_DEFAULT(UseCLMUL)) {
 788       UseCLMUL = true;
 789     }
 790   } else if (UseCLMUL) {
 791     if (!FLAG_IS_DEFAULT(UseCLMUL))
 792       warning("CLMUL instructions not available on this CPU (AVX may also be required)");
 793     FLAG_SET_DEFAULT(UseCLMUL, false);
 794   }
 795 
 796   if (UseCLMUL && (UseSSE > 2)) {
 797     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 798       UseCRC32Intrinsics = true;
 799     }
 800   } else if (UseCRC32Intrinsics) {
 801     if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
 802       warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
 803     FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
 804   }
 805 
 806   if (supports_sse4_2() && supports_clmul()) {
 807     if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 808       UseCRC32CIntrinsics = true;
 809     }
 810   } else if (UseCRC32CIntrinsics) {
 811     if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 812       warning("CRC32C intrinsics are not available on this CPU");
 813     }
 814     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 815   }
 816 
 817   // GHASH/GCM intrinsics
 818   if (UseCLMUL && (UseSSE > 2)) {
 819     if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
 820       UseGHASHIntrinsics = true;
 821     }
 822   } else if (UseGHASHIntrinsics) {
 823     if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
 824       warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
 825     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 826   }
 827 
 828   if (supports_fma() && UseSSE >= 2) { // Check UseSSE since FMA code uses SSE instructions
 829     if (FLAG_IS_DEFAULT(UseFMA)) {
 830       UseFMA = true;
 831     }
 832   } else if (UseFMA) {
 833     warning("FMA instructions are not available on this CPU");
 834     FLAG_SET_DEFAULT(UseFMA, false);
 835   }
 836 
 837   if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) {
 838     if (FLAG_IS_DEFAULT(UseSHA)) {
 839       UseSHA = true;
 840     }
 841   } else if (UseSHA) {
 842     warning("SHA instructions are not available on this CPU");
 843     FLAG_SET_DEFAULT(UseSHA, false);
 844   }
 845 
 846   if (supports_sha() && UseSHA) {
 847     if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
 848       FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
 849     }
 850   } else if (UseSHA1Intrinsics) {
 851     warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
 852     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 853   }
 854 
 855   if (UseSHA) {
 856     if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
 857       FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
 858     }
 859   } else if (UseSHA256Intrinsics) {
 860     warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
 861     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 862   }
 863 
 864   if (UseSHA) {
 865     if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
 866       FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
 867     }
 868   } else if (UseSHA512Intrinsics) {
 869     warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
 870     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 871   }
 872 
 873   if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
 874     FLAG_SET_DEFAULT(UseSHA, false);
 875   }
 876 
 877   if (UseAdler32Intrinsics) {
 878     warning("Adler32Intrinsics not available on this CPU.");
 879     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
 880   }
 881 
 882   if (!supports_rtm() && UseRTMLocking) {
 883     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 884     // setting during arguments processing. See use_biased_locking().
 885     // VM_Version_init() is executed after UseBiasedLocking is used
 886     // in Thread::allocate().
 887     vm_exit_during_initialization("RTM instructions are not available on this CPU");
 888   }
 889 
 890 #if INCLUDE_RTM_OPT
 891   if (UseRTMLocking) {
 892     if (is_client_compilation_mode_vm()) {
 893       // Only C2 does RTM locking optimization.
 894       // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 895       // setting during arguments processing. See use_biased_locking().
 896       vm_exit_during_initialization("RTM locking optimization is not supported in emulated client VM");
 897     }
 898     if (is_intel_family_core()) {
 899       if ((_model == CPU_MODEL_HASWELL_E3) ||
 900           (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
 901           (_model == CPU_MODEL_BROADWELL  && _stepping < 4)) {
 902         // currently a collision between SKL and HSW_E3
 903         if (!UnlockExperimentalVMOptions && UseAVX < 3) {
 904           vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this "
 905                                         "platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
 906         } else {
 907           warning("UseRTMLocking is only available as experimental option on this platform.");
 908         }
 909       }
 910     }
 911     if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
 912       // RTM locking should be used only for applications with
 913       // high lock contention. For now we do not use it by default.
 914       vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
 915     }
 916   } else { // !UseRTMLocking
 917     if (UseRTMForStackLocks) {
 918       if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
 919         warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
 920       }
 921       FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
 922     }
 923     if (UseRTMDeopt) {
 924       FLAG_SET_DEFAULT(UseRTMDeopt, false);
 925     }
 926     if (PrintPreciseRTMLockingStatistics) {
 927       FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
 928     }
 929   }
 930 #else
 931   if (UseRTMLocking) {
 932     // Only C2 does RTM locking optimization.
 933     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 934     // setting during arguments processing. See use_biased_locking().
 935     vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
 936   }
 937 #endif
 938 
 939 #ifdef COMPILER2
 940   if (UseFPUForSpilling) {
 941     if (UseSSE < 2) {
 942       // Only supported with SSE2+
 943       FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 944     }
 945   }
 946 #endif
 947 #if COMPILER2_OR_JVMCI
 948   if (MaxVectorSize > 0) {
 949     if (!is_power_of_2(MaxVectorSize)) {
 950       warning("MaxVectorSize must be a power of 2");
 951       FLAG_SET_DEFAULT(MaxVectorSize, 64);
 952     }
 953     if (UseSSE < 2) {
 954       // Vectors (in XMM) are only supported with SSE2+
 955       if (MaxVectorSize > 0) {
 956         if (!FLAG_IS_DEFAULT(MaxVectorSize))
 957           warning("MaxVectorSize must be 0");
 958         FLAG_SET_DEFAULT(MaxVectorSize, 0);
 959       }
 960     }
 961     else if (UseAVX == 0 || !os_supports_avx_vectors()) {
 962       // 32 bytes vectors (in YMM) are only supported with AVX+
 963       if (MaxVectorSize > 16) {
 964         if (!FLAG_IS_DEFAULT(MaxVectorSize))
 965           warning("MaxVectorSize must be <= 16");
 966         FLAG_SET_DEFAULT(MaxVectorSize, 16);
 967       }
 968     }
 969     else if (UseAVX == 1 || UseAVX == 2) {
 970       // 64 bytes vectors (in ZMM) are only supported with AVX 3
 971       if (MaxVectorSize > 32) {
 972         if (!FLAG_IS_DEFAULT(MaxVectorSize))
 973           warning("MaxVectorSize must be <= 32");
 974         FLAG_SET_DEFAULT(MaxVectorSize, 32);
 975       }
 976     }
 977     else if (UseAVX > 2 ) {
 978       if (MaxVectorSize > 64) {
 979         if (!FLAG_IS_DEFAULT(MaxVectorSize))
 980           warning("MaxVectorSize must be <= 64");
 981         FLAG_SET_DEFAULT(MaxVectorSize, 64);
 982       }
 983     }
 984 #if defined(COMPILER2) && defined(ASSERT)
 985     if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
 986       tty->print_cr("State of YMM registers after signal handle:");
 987       int nreg = 2 LP64_ONLY(+2);
 988       const char* ymm_name[4] = {"0", "7", "8", "15"};
 989       for (int i = 0; i < nreg; i++) {
 990         tty->print("YMM%s:", ymm_name[i]);
 991         for (int j = 7; j >=0; j--) {
 992           tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
 993         }
 994         tty->cr();
 995       }
 996     }
 997 #endif // COMPILER2 && ASSERT
 998   }
 999 #endif // COMPILER2_OR_JVMCI
1000 
1001 #ifdef COMPILER2
1002 #ifdef _LP64
1003   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1004     UseMultiplyToLenIntrinsic = true;
1005   }
1006   if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1007     UseSquareToLenIntrinsic = true;
1008   }
1009   if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1010     UseMulAddIntrinsic = true;
1011   }
1012   if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1013     UseMontgomeryMultiplyIntrinsic = true;
1014   }
1015   if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1016     UseMontgomerySquareIntrinsic = true;
1017   }
1018 #else
1019   if (UseMultiplyToLenIntrinsic) {
1020     if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1021       warning("multiplyToLen intrinsic is not available in 32-bit VM");
1022     }
1023     FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
1024   }
1025   if (UseMontgomeryMultiplyIntrinsic) {
1026     if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1027       warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
1028     }
1029     FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
1030   }
1031   if (UseMontgomerySquareIntrinsic) {
1032     if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1033       warning("montgomerySquare intrinsic is not available in 32-bit VM");
1034     }
1035     FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
1036   }
1037   if (UseSquareToLenIntrinsic) {
1038     if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1039       warning("squareToLen intrinsic is not available in 32-bit VM");
1040     }
1041     FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
1042   }
1043   if (UseMulAddIntrinsic) {
1044     if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1045       warning("mulAdd intrinsic is not available in 32-bit VM");
1046     }
1047     FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
1048   }
1049 #endif
1050 #endif // COMPILER2
1051 
1052   // On new cpus instructions which update whole XMM register should be used
1053   // to prevent partial register stall due to dependencies on high half.
1054   //
1055   // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
1056   // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1057   // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
1058   // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).
1059 
1060   if( is_amd() ) { // AMD cpus specific settings
1061     if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
1062       // Use it on new AMD cpus starting from Opteron.
1063       UseAddressNop = true;
1064     }
1065     if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
1066       // Use it on new AMD cpus starting from Opteron.
1067       UseNewLongLShift = true;
1068     }
1069     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1070       if (supports_sse4a()) {
1071         UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1072       } else {
1073         UseXmmLoadAndClearUpper = false;
1074       }
1075     }
1076     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1077       if( supports_sse4a() ) {
1078         UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1079       } else {
1080         UseXmmRegToRegMoveAll = false;
1081       }
1082     }
1083     if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
1084       if( supports_sse4a() ) {
1085         UseXmmI2F = true;
1086       } else {
1087         UseXmmI2F = false;
1088       }
1089     }
1090     if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
1091       if( supports_sse4a() ) {
1092         UseXmmI2D = true;
1093       } else {
1094         UseXmmI2D = false;
1095       }
1096     }
1097     if (supports_sse4_2()) {
1098       if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1099         FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1100       }
1101     } else {
1102       if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1103         warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1104       }
1105       FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1106     }
1107 
1108     // some defaults for AMD family 15h
1109     if ( cpu_family() == 0x15 ) {
1110       // On family 15h processors default is no sw prefetch
1111       if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1112         FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1113       }
1114       // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1115       if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1116         FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1117       }
1118       // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1119       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1120         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1121       }
1122       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1123         FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1124       }
1125     }
1126 
1127 #ifdef COMPILER2
1128     if (cpu_family() < 0x17 && MaxVectorSize > 16) {
1129       // Limit vectors size to 16 bytes on AMD cpus < 17h.
1130       FLAG_SET_DEFAULT(MaxVectorSize, 16);
1131     }
1132 #endif // COMPILER2
1133 
1134     // Some defaults for AMD family 17h
1135     if ( cpu_family() == 0x17 ) {
1136       // On family 17h processors use XMM and UnalignedLoadStores for Array Copy
1137       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1138         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1139       }
1140       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1141         FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1142       }
1143 #ifdef COMPILER2
1144       if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1145         FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1146       }
1147 #endif
1148     }
1149   }
1150 
1151   if( is_intel() ) { // Intel cpus specific settings
1152     if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
1153       UseStoreImmI16 = false; // don't use it on Intel cpus
1154     }
1155     if( cpu_family() == 6 || cpu_family() == 15 ) {
1156       if( FLAG_IS_DEFAULT(UseAddressNop) ) {
1157         // Use it on all Intel cpus starting from PentiumPro
1158         UseAddressNop = true;
1159       }
1160     }
1161     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1162       UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1163     }
1164     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1165       if( supports_sse3() ) {
1166         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1167       } else {
1168         UseXmmRegToRegMoveAll = false;
1169       }
1170     }
1171     if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
1172 #ifdef COMPILER2
1173       if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
1174         // For new Intel cpus do the next optimization:
1175         // don't align the beginning of a loop if there are enough instructions
1176         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1177         // in current fetch line (OptoLoopAlignment) or the padding
1178         // is big (> MaxLoopPad).
1179         // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1180         // generated NOP instructions. 11 is the largest size of one
1181         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1182         MaxLoopPad = 11;
1183       }
1184 #endif // COMPILER2
1185       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1186         UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1187       }
1188       if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
1189         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1190           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1191         }
1192       }
1193       if (supports_sse4_2()) {
1194         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1195           FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1196         }
1197       } else {
1198         if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1199           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1200         }
1201         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1202       }
1203     }
1204     if (is_atom_family() || is_knights_family()) {
1205 #ifdef COMPILER2
1206       if (FLAG_IS_DEFAULT(OptoScheduling)) {
1207         OptoScheduling = true;
1208       }
1209 #endif
1210       if (supports_sse4_2()) { // Silvermont
1211         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1212           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1213         }
1214       }
1215       if (FLAG_IS_DEFAULT(UseIncDec)) {
1216         FLAG_SET_DEFAULT(UseIncDec, false);
1217       }
1218     }
1219     if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1220       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1221     }
1222   }
1223 
1224 #ifdef _LP64
1225   if (UseSSE42Intrinsics) {
1226     if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1227       UseVectorizedMismatchIntrinsic = true;
1228     }
1229   } else if (UseVectorizedMismatchIntrinsic) {
1230     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1231       warning("vectorizedMismatch intrinsics are not available on this CPU");
1232     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1233   }
1234 #else
1235   if (UseVectorizedMismatchIntrinsic) {
1236     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1237       warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1238     }
1239     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1240   }
1241 #endif // _LP64
1242 
1243   // Use count leading zeros count instruction if available.
1244   if (supports_lzcnt()) {
1245     if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1246       UseCountLeadingZerosInstruction = true;
1247     }
1248    } else if (UseCountLeadingZerosInstruction) {
1249     warning("lzcnt instruction is not available on this CPU");
1250     FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1251   }
1252 
1253   // Use count trailing zeros instruction if available
1254   if (supports_bmi1()) {
1255     // tzcnt does not require VEX prefix
1256     if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1257       if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1258         // Don't use tzcnt if BMI1 is switched off on command line.
1259         UseCountTrailingZerosInstruction = false;
1260       } else {
1261         UseCountTrailingZerosInstruction = true;
1262       }
1263     }
1264   } else if (UseCountTrailingZerosInstruction) {
1265     warning("tzcnt instruction is not available on this CPU");
1266     FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1267   }
1268 
1269   // BMI instructions (except tzcnt) use an encoding with VEX prefix.
1270   // VEX prefix is generated only when AVX > 0.
1271   if (supports_bmi1() && supports_avx()) {
1272     if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1273       UseBMI1Instructions = true;
1274     }
1275   } else if (UseBMI1Instructions) {
1276     warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1277     FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1278   }
1279 
1280   if (supports_bmi2() && supports_avx()) {
1281     if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1282       UseBMI2Instructions = true;
1283     }
1284   } else if (UseBMI2Instructions) {
1285     warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1286     FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1287   }
1288 
1289   // Use population count instruction if available.
1290   if (supports_popcnt()) {
1291     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1292       UsePopCountInstruction = true;
1293     }
1294   } else if (UsePopCountInstruction) {
1295     warning("POPCNT instruction is not available on this CPU");
1296     FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1297   }
1298 
1299   // Use fast-string operations if available.
1300   if (supports_erms()) {
1301     if (FLAG_IS_DEFAULT(UseFastStosb)) {
1302       UseFastStosb = true;
1303     }
1304   } else if (UseFastStosb) {
1305     warning("fast-string operations are not available on this CPU");
1306     FLAG_SET_DEFAULT(UseFastStosb, false);
1307   }
1308 
1309 #ifdef COMPILER2
1310   if (FLAG_IS_DEFAULT(AlignVector)) {
1311     // Modern processors allow misaligned memory operations for vectors.
1312     AlignVector = !UseUnalignedLoadStores;
1313   }
1314 #endif // COMPILER2
1315 
1316   if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1317     if (AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch()) {
1318       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
1319     } else if (!supports_sse() && supports_3dnow_prefetch()) {
1320       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1321     }
1322   }
1323 
1324   // Allocation prefetch settings
1325   intx cache_line_size = prefetch_data_size();
1326   if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) &&
1327       (cache_line_size > AllocatePrefetchStepSize)) {
1328     FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size);
1329   }
1330 
1331   if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) {
1332     assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0");
1333     if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1334       warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag.");
1335     }
1336     FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1337   }
1338 
1339   if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
1340     bool use_watermark_prefetch = (AllocatePrefetchStyle == 2);
1341     FLAG_SET_DEFAULT(AllocatePrefetchDistance, allocate_prefetch_distance(use_watermark_prefetch));
1342   }
1343 
1344   if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1345     if (FLAG_IS_DEFAULT(AllocatePrefetchLines) &&
1346         supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1347       FLAG_SET_DEFAULT(AllocatePrefetchLines, 4);
1348     }
1349 #ifdef COMPILER2
1350     if (FLAG_IS_DEFAULT(UseFPUForSpilling) && supports_sse4_2()) {
1351       FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1352     }
1353 #endif
1354   }
1355 
1356 #ifdef _LP64
1357   // Prefetch settings
1358 
1359   // Prefetch interval for gc copy/scan == 9 dcache lines.  Derived from
1360   // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
1361   // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
1362   // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
1363 
1364   // gc copy/scan is disabled if prefetchw isn't supported, because
1365   // Prefetch::write emits an inlined prefetchw on Linux.
1366   // Do not use the 3dnow prefetchw instruction.  It isn't supported on em64t.
1367   // The used prefetcht0 instruction works for both amd64 and em64t.
1368 
1369   if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) {
1370     FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 576);
1371   }
1372   if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
1373     FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576);
1374   }
1375   if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
1376     FLAG_SET_DEFAULT(PrefetchFieldsAhead, 1);
1377   }
1378 #endif
1379 
1380   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1381      (cache_line_size > ContendedPaddingWidth))
1382      ContendedPaddingWidth = cache_line_size;
1383 
1384   // This machine allows unaligned memory accesses
1385   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1386     FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1387   }
1388 
1389 #ifndef PRODUCT
1390   if (log_is_enabled(Info, os, cpu)) {
1391     LogStream ls(Log(os, cpu)::info());
1392     outputStream* log = &ls;
1393     log->print_cr("Logical CPUs per core: %u",
1394                   logical_processors_per_package());
1395     log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1396     log->print("UseSSE=%d", (int) UseSSE);
1397     if (UseAVX > 0) {
1398       log->print("  UseAVX=%d", (int) UseAVX);
1399     }
1400     if (UseAES) {
1401       log->print("  UseAES=1");
1402     }
1403 #ifdef COMPILER2
1404     if (MaxVectorSize > 0) {
1405       log->print("  MaxVectorSize=%d", (int) MaxVectorSize);
1406     }
1407 #endif
1408     log->cr();
1409     log->print("Allocation");
1410     if (AllocatePrefetchStyle <= 0 || (UseSSE == 0 && !supports_3dnow_prefetch())) {
1411       log->print_cr(": no prefetching");
1412     } else {
1413       log->print(" prefetching: ");
1414       if (UseSSE == 0 && supports_3dnow_prefetch()) {
1415         log->print("PREFETCHW");
1416       } else if (UseSSE >= 1) {
1417         if (AllocatePrefetchInstr == 0) {
1418           log->print("PREFETCHNTA");
1419         } else if (AllocatePrefetchInstr == 1) {
1420           log->print("PREFETCHT0");
1421         } else if (AllocatePrefetchInstr == 2) {
1422           log->print("PREFETCHT2");
1423         } else if (AllocatePrefetchInstr == 3) {
1424           log->print("PREFETCHW");
1425         }
1426       }
1427       if (AllocatePrefetchLines > 1) {
1428         log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1429       } else {
1430         log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1431       }
1432     }
1433 
1434     if (PrefetchCopyIntervalInBytes > 0) {
1435       log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1436     }
1437     if (PrefetchScanIntervalInBytes > 0) {
1438       log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1439     }
1440     if (PrefetchFieldsAhead > 0) {
1441       log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1442     }
1443     if (ContendedPaddingWidth > 0) {
1444       log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1445     }
1446   }
1447 #endif // !PRODUCT
1448 }
1449 
1450 bool VM_Version::use_biased_locking() {
1451 #if INCLUDE_RTM_OPT
1452   // RTM locking is most useful when there is high lock contention and
1453   // low data contention.  With high lock contention the lock is usually
1454   // inflated and biased locking is not suitable for that case.
1455   // RTM locking code requires that biased locking is off.
1456   // Note: we can't switch off UseBiasedLocking in get_processor_features()
1457   // because it is used by Thread::allocate() which is called before
1458   // VM_Version::initialize().
1459   if (UseRTMLocking && UseBiasedLocking) {
1460     if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1461       FLAG_SET_DEFAULT(UseBiasedLocking, false);
1462     } else {
1463       warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1464       UseBiasedLocking = false;
1465     }
1466   }
1467 #endif
1468   return UseBiasedLocking;
1469 }
1470 
1471 void VM_Version::initialize() {
1472   ResourceMark rm;
1473   // Making this stub must be FIRST use of assembler
1474 
1475   stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1476   if (stub_blob == NULL) {
1477     vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1478   }
1479   CodeBuffer c(stub_blob);
1480   VM_Version_StubGenerator g(&c);
1481   get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1482                                      g.generate_get_cpu_info());
1483 
1484   get_processor_features();
1485 }