1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "jvm.h"
  27 #include "asm/macroAssembler.hpp"
  28 #include "asm/macroAssembler.inline.hpp"
  29 #include "logging/log.hpp"
  30 #include "logging/logStream.hpp"
  31 #include "memory/resourceArea.hpp"
  32 #include "runtime/java.hpp"
  33 #include "runtime/os.hpp"
  34 #include "runtime/stubCodeGenerator.hpp"
  35 #include "vm_version_x86.hpp"
  36 
  37 
  38 int VM_Version::_cpu;
  39 int VM_Version::_model;
  40 int VM_Version::_stepping;
  41 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
  42 
  43 // Address of instruction which causes SEGV
  44 address VM_Version::_cpuinfo_segv_addr = 0;
  45 // Address of instruction after the one which causes SEGV
  46 address VM_Version::_cpuinfo_cont_addr = 0;
  47 
  48 static BufferBlob* stub_blob;
  49 static const int stub_size = 1100;
  50 
  51 extern "C" {
  52   typedef void (*get_cpu_info_stub_t)(void*);
  53 }
  54 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
  55 
  56 
  57 class VM_Version_StubGenerator: public StubCodeGenerator {
  58  public:
  59 
  60   VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
  61 
  62   address generate_get_cpu_info() {
  63     // Flags to test CPU type.
  64     const uint32_t HS_EFL_AC = 0x40000;
  65     const uint32_t HS_EFL_ID = 0x200000;
  66     // Values for when we don't have a CPUID instruction.
  67     const int      CPU_FAMILY_SHIFT = 8;
  68     const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
  69     const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
  70     bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2);
  71 
  72     Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
  73     Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, ext_cpuid8, done, wrapup;
  74     Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
  75 
  76     StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
  77 #   define __ _masm->
  78 
  79     address start = __ pc();
  80 
  81     //
  82     // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
  83     //
  84     // LP64: rcx and rdx are first and second argument registers on windows
  85 
  86     __ push(rbp);
  87 #ifdef _LP64
  88     __ mov(rbp, c_rarg0); // cpuid_info address
  89 #else
  90     __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
  91 #endif
  92     __ push(rbx);
  93     __ push(rsi);
  94     __ pushf();          // preserve rbx, and flags
  95     __ pop(rax);
  96     __ push(rax);
  97     __ mov(rcx, rax);
  98     //
  99     // if we are unable to change the AC flag, we have a 386
 100     //
 101     __ xorl(rax, HS_EFL_AC);
 102     __ push(rax);
 103     __ popf();
 104     __ pushf();
 105     __ pop(rax);
 106     __ cmpptr(rax, rcx);
 107     __ jccb(Assembler::notEqual, detect_486);
 108 
 109     __ movl(rax, CPU_FAMILY_386);
 110     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 111     __ jmp(done);
 112 
 113     //
 114     // If we are unable to change the ID flag, we have a 486 which does
 115     // not support the "cpuid" instruction.
 116     //
 117     __ bind(detect_486);
 118     __ mov(rax, rcx);
 119     __ xorl(rax, HS_EFL_ID);
 120     __ push(rax);
 121     __ popf();
 122     __ pushf();
 123     __ pop(rax);
 124     __ cmpptr(rcx, rax);
 125     __ jccb(Assembler::notEqual, detect_586);
 126 
 127     __ bind(cpu486);
 128     __ movl(rax, CPU_FAMILY_486);
 129     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 130     __ jmp(done);
 131 
 132     //
 133     // At this point, we have a chip which supports the "cpuid" instruction
 134     //
 135     __ bind(detect_586);
 136     __ xorl(rax, rax);
 137     __ cpuid();
 138     __ orl(rax, rax);
 139     __ jcc(Assembler::equal, cpu486);   // if cpuid doesn't support an input
 140                                         // value of at least 1, we give up and
 141                                         // assume a 486
 142     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
 143     __ movl(Address(rsi, 0), rax);
 144     __ movl(Address(rsi, 4), rbx);
 145     __ movl(Address(rsi, 8), rcx);
 146     __ movl(Address(rsi,12), rdx);
 147 
 148     __ cmpl(rax, 0xa);                  // Is cpuid(0xB) supported?
 149     __ jccb(Assembler::belowEqual, std_cpuid4);
 150 
 151     //
 152     // cpuid(0xB) Processor Topology
 153     //
 154     __ movl(rax, 0xb);
 155     __ xorl(rcx, rcx);   // Threads level
 156     __ cpuid();
 157 
 158     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
 159     __ movl(Address(rsi, 0), rax);
 160     __ movl(Address(rsi, 4), rbx);
 161     __ movl(Address(rsi, 8), rcx);
 162     __ movl(Address(rsi,12), rdx);
 163 
 164     __ movl(rax, 0xb);
 165     __ movl(rcx, 1);     // Cores level
 166     __ cpuid();
 167     __ push(rax);
 168     __ andl(rax, 0x1f);  // Determine if valid topology level
 169     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 170     __ andl(rax, 0xffff);
 171     __ pop(rax);
 172     __ jccb(Assembler::equal, std_cpuid4);
 173 
 174     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
 175     __ movl(Address(rsi, 0), rax);
 176     __ movl(Address(rsi, 4), rbx);
 177     __ movl(Address(rsi, 8), rcx);
 178     __ movl(Address(rsi,12), rdx);
 179 
 180     __ movl(rax, 0xb);
 181     __ movl(rcx, 2);     // Packages level
 182     __ cpuid();
 183     __ push(rax);
 184     __ andl(rax, 0x1f);  // Determine if valid topology level
 185     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 186     __ andl(rax, 0xffff);
 187     __ pop(rax);
 188     __ jccb(Assembler::equal, std_cpuid4);
 189 
 190     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
 191     __ movl(Address(rsi, 0), rax);
 192     __ movl(Address(rsi, 4), rbx);
 193     __ movl(Address(rsi, 8), rcx);
 194     __ movl(Address(rsi,12), rdx);
 195 
 196     //
 197     // cpuid(0x4) Deterministic cache params
 198     //
 199     __ bind(std_cpuid4);
 200     __ movl(rax, 4);
 201     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
 202     __ jccb(Assembler::greater, std_cpuid1);
 203 
 204     __ xorl(rcx, rcx);   // L1 cache
 205     __ cpuid();
 206     __ push(rax);
 207     __ andl(rax, 0x1f);  // Determine if valid cache parameters used
 208     __ orl(rax, rax);    // eax[4:0] == 0 indicates invalid cache
 209     __ pop(rax);
 210     __ jccb(Assembler::equal, std_cpuid1);
 211 
 212     __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
 213     __ movl(Address(rsi, 0), rax);
 214     __ movl(Address(rsi, 4), rbx);
 215     __ movl(Address(rsi, 8), rcx);
 216     __ movl(Address(rsi,12), rdx);
 217 
 218     //
 219     // Standard cpuid(0x1)
 220     //
 221     __ bind(std_cpuid1);
 222     __ movl(rax, 1);
 223     __ cpuid();
 224     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 225     __ movl(Address(rsi, 0), rax);
 226     __ movl(Address(rsi, 4), rbx);
 227     __ movl(Address(rsi, 8), rcx);
 228     __ movl(Address(rsi,12), rdx);
 229 
 230     //
 231     // Check if OS has enabled XGETBV instruction to access XCR0
 232     // (OSXSAVE feature flag) and CPU supports AVX
 233     //
 234     __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
 235     __ cmpl(rcx, 0x18000000);
 236     __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
 237 
 238     //
 239     // XCR0, XFEATURE_ENABLED_MASK register
 240     //
 241     __ xorl(rcx, rcx);   // zero for XCR0 register
 242     __ xgetbv();
 243     __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
 244     __ movl(Address(rsi, 0), rax);
 245     __ movl(Address(rsi, 4), rdx);
 246 
 247     //
 248     // cpuid(0x7) Structured Extended Features
 249     //
 250     __ bind(sef_cpuid);
 251     __ movl(rax, 7);
 252     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
 253     __ jccb(Assembler::greater, ext_cpuid);
 254 
 255     __ xorl(rcx, rcx);
 256     __ cpuid();
 257     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 258     __ movl(Address(rsi, 0), rax);
 259     __ movl(Address(rsi, 4), rbx);
 260     __ movl(Address(rsi, 8), rcx);
 261     __ movl(Address(rsi, 12), rdx);
 262 
 263     //
 264     // Extended cpuid(0x80000000)
 265     //
 266     __ bind(ext_cpuid);
 267     __ movl(rax, 0x80000000);
 268     __ cpuid();
 269     __ cmpl(rax, 0x80000000);     // Is cpuid(0x80000001) supported?
 270     __ jcc(Assembler::belowEqual, done);
 271     __ cmpl(rax, 0x80000004);     // Is cpuid(0x80000005) supported?
 272     __ jcc(Assembler::belowEqual, ext_cpuid1);
 273     __ cmpl(rax, 0x80000006);     // Is cpuid(0x80000007) supported?
 274     __ jccb(Assembler::belowEqual, ext_cpuid5);
 275     __ cmpl(rax, 0x80000007);     // Is cpuid(0x80000008) supported?
 276     __ jccb(Assembler::belowEqual, ext_cpuid7);
 277     __ cmpl(rax, 0x80000008);     // Is cpuid(0x80000009 and above) supported?
 278     __ jccb(Assembler::belowEqual, ext_cpuid8);
 279     __ cmpl(rax, 0x8000001E);     // Is cpuid(0x8000001E) supported?
 280     __ jccb(Assembler::below, ext_cpuid8);
 281     //
 282     // Extended cpuid(0x8000001E)
 283     //
 284     __ movl(rax, 0x8000001E);
 285     __ cpuid();
 286     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1E_offset())));
 287     __ movl(Address(rsi, 0), rax);
 288     __ movl(Address(rsi, 4), rbx);
 289     __ movl(Address(rsi, 8), rcx);
 290     __ movl(Address(rsi,12), rdx);
 291 
 292     //
 293     // Extended cpuid(0x80000008)
 294     //
 295     __ bind(ext_cpuid8);
 296     __ movl(rax, 0x80000008);
 297     __ cpuid();
 298     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
 299     __ movl(Address(rsi, 0), rax);
 300     __ movl(Address(rsi, 4), rbx);
 301     __ movl(Address(rsi, 8), rcx);
 302     __ movl(Address(rsi,12), rdx);
 303 
 304     //
 305     // Extended cpuid(0x80000007)
 306     //
 307     __ bind(ext_cpuid7);
 308     __ movl(rax, 0x80000007);
 309     __ cpuid();
 310     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
 311     __ movl(Address(rsi, 0), rax);
 312     __ movl(Address(rsi, 4), rbx);
 313     __ movl(Address(rsi, 8), rcx);
 314     __ movl(Address(rsi,12), rdx);
 315 
 316     //
 317     // Extended cpuid(0x80000005)
 318     //
 319     __ bind(ext_cpuid5);
 320     __ movl(rax, 0x80000005);
 321     __ cpuid();
 322     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
 323     __ movl(Address(rsi, 0), rax);
 324     __ movl(Address(rsi, 4), rbx);
 325     __ movl(Address(rsi, 8), rcx);
 326     __ movl(Address(rsi,12), rdx);
 327 
 328     //
 329     // Extended cpuid(0x80000001)
 330     //
 331     __ bind(ext_cpuid1);
 332     __ movl(rax, 0x80000001);
 333     __ cpuid();
 334     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
 335     __ movl(Address(rsi, 0), rax);
 336     __ movl(Address(rsi, 4), rbx);
 337     __ movl(Address(rsi, 8), rcx);
 338     __ movl(Address(rsi,12), rdx);
 339 
 340     //
 341     // Check if OS has enabled XGETBV instruction to access XCR0
 342     // (OSXSAVE feature flag) and CPU supports AVX
 343     //
 344     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 345     __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
 346     __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
 347     __ cmpl(rcx, 0x18000000);
 348     __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
 349 
 350     __ movl(rax, 0x6);
 351     __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 352     __ cmpl(rax, 0x6);
 353     __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
 354 
 355     // we need to bridge farther than imm8, so we use this island as a thunk
 356     __ bind(done);
 357     __ jmp(wrapup);
 358 
 359     __ bind(start_simd_check);
 360     //
 361     // Some OSs have a bug when upper 128/256bits of YMM/ZMM
 362     // registers are not restored after a signal processing.
 363     // Generate SEGV here (reference through NULL)
 364     // and check upper YMM/ZMM bits after it.
 365     //
 366     intx saved_useavx = UseAVX;
 367     intx saved_usesse = UseSSE;
 368     // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
 369     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 370     __ movl(rax, 0x10000);
 371     __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
 372     __ cmpl(rax, 0x10000);
 373     __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
 374     // check _cpuid_info.xem_xcr0_eax.bits.opmask
 375     // check _cpuid_info.xem_xcr0_eax.bits.zmm512
 376     // check _cpuid_info.xem_xcr0_eax.bits.zmm32
 377     __ movl(rax, 0xE0);
 378     __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 379     __ cmpl(rax, 0xE0);
 380     __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
 381 
 382     // If UseAVX is unitialized or is set by the user to include EVEX
 383     if (use_evex) {
 384       // EVEX setup: run in lowest evex mode
 385       VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
 386       UseAVX = 3;
 387       UseSSE = 2;
 388 #ifdef _WINDOWS
 389       // xmm5-xmm15 are not preserved by caller on windows
 390       // https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx
 391       __ subptr(rsp, 64);
 392       __ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit);
 393 #ifdef _LP64
 394       __ subptr(rsp, 64);
 395       __ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit);
 396       __ subptr(rsp, 64);
 397       __ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit);
 398 #endif // _LP64
 399 #endif // _WINDOWS
 400 
 401       // load value into all 64 bytes of zmm7 register
 402       __ movl(rcx, VM_Version::ymm_test_value());
 403       __ movdl(xmm0, rcx);
 404       __ movl(rcx, 0xffff);
 405       __ kmovwl(k1, rcx);
 406       __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
 407       __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
 408 #ifdef _LP64
 409       __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
 410       __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
 411 #endif
 412       VM_Version::clean_cpuFeatures();
 413       __ jmp(save_restore_except);
 414     }
 415 
 416     __ bind(legacy_setup);
 417     // AVX setup
 418     VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
 419     UseAVX = 1;
 420     UseSSE = 2;
 421 #ifdef _WINDOWS
 422     __ subptr(rsp, 32);
 423     __ vmovdqu(Address(rsp, 0), xmm7);
 424 #ifdef _LP64
 425     __ subptr(rsp, 32);
 426     __ vmovdqu(Address(rsp, 0), xmm8);
 427     __ subptr(rsp, 32);
 428     __ vmovdqu(Address(rsp, 0), xmm15);
 429 #endif // _LP64
 430 #endif // _WINDOWS
 431 
 432     // load value into all 32 bytes of ymm7 register
 433     __ movl(rcx, VM_Version::ymm_test_value());
 434 
 435     __ movdl(xmm0, rcx);
 436     __ pshufd(xmm0, xmm0, 0x00);
 437     __ vinsertf128_high(xmm0, xmm0);
 438     __ vmovdqu(xmm7, xmm0);
 439 #ifdef _LP64
 440     __ vmovdqu(xmm8, xmm0);
 441     __ vmovdqu(xmm15, xmm0);
 442 #endif
 443     VM_Version::clean_cpuFeatures();
 444 
 445     __ bind(save_restore_except);
 446     __ xorl(rsi, rsi);
 447     VM_Version::set_cpuinfo_segv_addr(__ pc());
 448     // Generate SEGV
 449     __ movl(rax, Address(rsi, 0));
 450 
 451     VM_Version::set_cpuinfo_cont_addr(__ pc());
 452     // Returns here after signal. Save xmm0 to check it later.
 453 
 454     // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
 455     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 456     __ movl(rax, 0x10000);
 457     __ andl(rax, Address(rsi, 4));
 458     __ cmpl(rax, 0x10000);
 459     __ jcc(Assembler::notEqual, legacy_save_restore);
 460     // check _cpuid_info.xem_xcr0_eax.bits.opmask
 461     // check _cpuid_info.xem_xcr0_eax.bits.zmm512
 462     // check _cpuid_info.xem_xcr0_eax.bits.zmm32
 463     __ movl(rax, 0xE0);
 464     __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 465     __ cmpl(rax, 0xE0);
 466     __ jcc(Assembler::notEqual, legacy_save_restore);
 467 
 468     // If UseAVX is unitialized or is set by the user to include EVEX
 469     if (use_evex) {
 470       // EVEX check: run in lowest evex mode
 471       VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
 472       UseAVX = 3;
 473       UseSSE = 2;
 474       __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
 475       __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
 476       __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
 477 #ifdef _LP64
 478       __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
 479       __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
 480 #endif
 481 
 482 #ifdef _WINDOWS
 483 #ifdef _LP64
 484       __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
 485       __ addptr(rsp, 64);
 486       __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
 487       __ addptr(rsp, 64);
 488 #endif // _LP64
 489       __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
 490       __ addptr(rsp, 64);
 491 #endif // _WINDOWS
 492       generate_vzeroupper(wrapup);
 493       VM_Version::clean_cpuFeatures();
 494       UseAVX = saved_useavx;
 495       UseSSE = saved_usesse;
 496       __ jmp(wrapup);
 497    }
 498 
 499     __ bind(legacy_save_restore);
 500     // AVX check
 501     VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
 502     UseAVX = 1;
 503     UseSSE = 2;
 504     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
 505     __ vmovdqu(Address(rsi, 0), xmm0);
 506     __ vmovdqu(Address(rsi, 32), xmm7);
 507 #ifdef _LP64
 508     __ vmovdqu(Address(rsi, 64), xmm8);
 509     __ vmovdqu(Address(rsi, 96), xmm15);
 510 #endif
 511 
 512 #ifdef _WINDOWS
 513 #ifdef _LP64
 514     __ vmovdqu(xmm15, Address(rsp, 0));
 515     __ addptr(rsp, 32);
 516     __ vmovdqu(xmm8, Address(rsp, 0));
 517     __ addptr(rsp, 32);
 518 #endif // _LP64
 519     __ vmovdqu(xmm7, Address(rsp, 0));
 520     __ addptr(rsp, 32);
 521 #endif // _WINDOWS
 522     generate_vzeroupper(wrapup);
 523     VM_Version::clean_cpuFeatures();
 524     UseAVX = saved_useavx;
 525     UseSSE = saved_usesse;
 526 
 527     __ bind(wrapup);
 528     __ popf();
 529     __ pop(rsi);
 530     __ pop(rbx);
 531     __ pop(rbp);
 532     __ ret(0);
 533 
 534 #   undef __
 535 
 536     return start;
 537   };
 538   void generate_vzeroupper(Label& L_wrapup) {
 539 #   define __ _masm->
 540     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
 541     __ cmpl(Address(rsi, 4), 0x756e6547);  // 'uneG'
 542     __ jcc(Assembler::notEqual, L_wrapup);
 543     __ movl(rcx, 0x0FFF0FF0);
 544     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 545     __ andl(rcx, Address(rsi, 0));
 546     __ cmpl(rcx, 0x00050670);              // If it is Xeon Phi 3200/5200/7200
 547     __ jcc(Assembler::equal, L_wrapup);
 548     __ cmpl(rcx, 0x00080650);              // If it is Future Xeon Phi
 549     __ jcc(Assembler::equal, L_wrapup);
 550     __ vzeroupper();
 551 #   undef __
 552   }
 553 };
 554 
 555 void VM_Version::get_processor_features() {
 556 
 557   _cpu = 4; // 486 by default
 558   _model = 0;
 559   _stepping = 0;
 560   _features = 0;
 561   _logical_processors_per_package = 1;
 562   // i486 internal cache is both I&D and has a 16-byte line size
 563   _L1_data_cache_line_size = 16;
 564 
 565   // Get raw processor info
 566 
 567   get_cpu_info_stub(&_cpuid_info);
 568 
 569   assert_is_initialized();
 570   _cpu = extended_cpu_family();
 571   _model = extended_cpu_model();
 572   _stepping = cpu_stepping();
 573 
 574   if (cpu_family() > 4) { // it supports CPUID
 575     _features = feature_flags();
 576     // Logical processors are only available on P4s and above,
 577     // and only if hyperthreading is available.
 578     _logical_processors_per_package = logical_processor_count();
 579     _L1_data_cache_line_size = L1_line_size();
 580   }
 581 
 582   _supports_cx8 = supports_cmpxchg8();
 583   // xchg and xadd instructions
 584   _supports_atomic_getset4 = true;
 585   _supports_atomic_getadd4 = true;
 586   LP64_ONLY(_supports_atomic_getset8 = true);
 587   LP64_ONLY(_supports_atomic_getadd8 = true);
 588 
 589 #ifdef _LP64
 590   // OS should support SSE for x64 and hardware should support at least SSE2.
 591   if (!VM_Version::supports_sse2()) {
 592     vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
 593   }
 594   // in 64 bit the use of SSE2 is the minimum
 595   if (UseSSE < 2) UseSSE = 2;
 596 #endif
 597 
 598 #ifdef AMD64
 599   // flush_icache_stub have to be generated first.
 600   // That is why Icache line size is hard coded in ICache class,
 601   // see icache_x86.hpp. It is also the reason why we can't use
 602   // clflush instruction in 32-bit VM since it could be running
 603   // on CPU which does not support it.
 604   //
 605   // The only thing we can do is to verify that flushed
 606   // ICache::line_size has correct value.
 607   guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
 608   // clflush_size is size in quadwords (8 bytes).
 609   guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
 610 #endif
 611 
 612   // If the OS doesn't support SSE, we can't use this feature even if the HW does
 613   if (!os::supports_sse())
 614     _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
 615 
 616   if (UseSSE < 4) {
 617     _features &= ~CPU_SSE4_1;
 618     _features &= ~CPU_SSE4_2;
 619   }
 620 
 621   if (UseSSE < 3) {
 622     _features &= ~CPU_SSE3;
 623     _features &= ~CPU_SSSE3;
 624     _features &= ~CPU_SSE4A;
 625   }
 626 
 627   if (UseSSE < 2)
 628     _features &= ~CPU_SSE2;
 629 
 630   if (UseSSE < 1)
 631     _features &= ~CPU_SSE;
 632 
 633   //since AVX instructions is slower than SSE in some ZX cpus, force USEAVX=0.
 634   if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7))) {
 635     UseAVX = 0;
 636   }
 637 
 638   // first try initial setting and detect what we can support
 639   int use_avx_limit = 0;
 640   if (UseAVX > 0) {
 641     if (UseAVX > 2 && supports_evex()) {
 642       use_avx_limit = 3;
 643     } else if (UseAVX > 1 && supports_avx2()) {
 644       use_avx_limit = 2;
 645     } else if (UseAVX > 0 && supports_avx()) {
 646       use_avx_limit = 1;
 647     } else {
 648       use_avx_limit = 0;
 649     }
 650   }
 651   if (FLAG_IS_DEFAULT(UseAVX)) {
 652     FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
 653   } else if (UseAVX > use_avx_limit) {
 654     warning("UseAVX=%d is not supported on this CPU, setting it to UseAVX=%d", (int) UseAVX, use_avx_limit);
 655     FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
 656   } else if (UseAVX < 0) {
 657     warning("UseAVX=%d is not valid, setting it to UseAVX=0", (int) UseAVX);
 658     FLAG_SET_DEFAULT(UseAVX, 0);
 659   }
 660 
 661   if (UseAVX < 3) {
 662     _features &= ~CPU_AVX512F;
 663     _features &= ~CPU_AVX512DQ;
 664     _features &= ~CPU_AVX512CD;
 665     _features &= ~CPU_AVX512BW;
 666     _features &= ~CPU_AVX512VL;
 667     _features &= ~CPU_AVX512_VPOPCNTDQ;
 668     _features &= ~CPU_VPCLMULQDQ;
 669   }
 670 
 671   if (UseAVX < 2)
 672     _features &= ~CPU_AVX2;
 673 
 674   if (UseAVX < 1) {
 675     _features &= ~CPU_AVX;
 676     _features &= ~CPU_VZEROUPPER;
 677   }
 678 
 679   if (logical_processors_per_package() == 1) {
 680     // HT processor could be installed on a system which doesn't support HT.
 681     _features &= ~CPU_HT;
 682   }
 683 
 684   if( is_intel() ) { // Intel cpus specific settings
 685     if (is_knights_family()) {
 686       _features &= ~CPU_VZEROUPPER;
 687     }
 688   }
 689 
 690   char buf[256];
 691   jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 692                cores_per_cpu(), threads_per_core(),
 693                cpu_family(), _model, _stepping,
 694                (supports_cmov() ? ", cmov" : ""),
 695                (supports_cmpxchg8() ? ", cx8" : ""),
 696                (supports_fxsr() ? ", fxsr" : ""),
 697                (supports_mmx()  ? ", mmx"  : ""),
 698                (supports_sse()  ? ", sse"  : ""),
 699                (supports_sse2() ? ", sse2" : ""),
 700                (supports_sse3() ? ", sse3" : ""),
 701                (supports_ssse3()? ", ssse3": ""),
 702                (supports_sse4_1() ? ", sse4.1" : ""),
 703                (supports_sse4_2() ? ", sse4.2" : ""),
 704                (supports_popcnt() ? ", popcnt" : ""),
 705                (supports_avx()    ? ", avx" : ""),
 706                (supports_avx2()   ? ", avx2" : ""),
 707                (supports_aes()    ? ", aes" : ""),
 708                (supports_clmul()  ? ", clmul" : ""),
 709                (supports_erms()   ? ", erms" : ""),
 710                (supports_rtm()    ? ", rtm" : ""),
 711                (supports_mmx_ext() ? ", mmxext" : ""),
 712                (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
 713                (supports_lzcnt()   ? ", lzcnt": ""),
 714                (supports_sse4a()   ? ", sse4a": ""),
 715                (supports_ht() ? ", ht": ""),
 716                (supports_tsc() ? ", tsc": ""),
 717                (supports_tscinv_bit() ? ", tscinvbit": ""),
 718                (supports_tscinv() ? ", tscinv": ""),
 719                (supports_bmi1() ? ", bmi1" : ""),
 720                (supports_bmi2() ? ", bmi2" : ""),
 721                (supports_adx() ? ", adx" : ""),
 722                (supports_evex() ? ", evex" : ""),
 723                (supports_sha() ? ", sha" : ""),
 724                (supports_fma() ? ", fma" : ""));
 725   _features_string = os::strdup(buf);
 726 
 727   // UseSSE is set to the smaller of what hardware supports and what
 728   // the command line requires.  I.e., you cannot set UseSSE to 2 on
 729   // older Pentiums which do not support it.
 730   int use_sse_limit = 0;
 731   if (UseSSE > 0) {
 732     if (UseSSE > 3 && supports_sse4_1()) {
 733       use_sse_limit = 4;
 734     } else if (UseSSE > 2 && supports_sse3()) {
 735       use_sse_limit = 3;
 736     } else if (UseSSE > 1 && supports_sse2()) {
 737       use_sse_limit = 2;
 738     } else if (UseSSE > 0 && supports_sse()) {
 739       use_sse_limit = 1;
 740     } else {
 741       use_sse_limit = 0;
 742     }
 743   }
 744   if (FLAG_IS_DEFAULT(UseSSE)) {
 745     FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
 746   } else if (UseSSE > use_sse_limit) {
 747     warning("UseSSE=%d is not supported on this CPU, setting it to UseSSE=%d", (int) UseSSE, use_sse_limit);
 748     FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
 749   } else if (UseSSE < 0) {
 750     warning("UseSSE=%d is not valid, setting it to UseSSE=0", (int) UseSSE);
 751     FLAG_SET_DEFAULT(UseSSE, 0);
 752   }
 753 
 754   // Use AES instructions if available.
 755   if (supports_aes()) {
 756     if (FLAG_IS_DEFAULT(UseAES)) {
 757       FLAG_SET_DEFAULT(UseAES, true);
 758     }
 759     if (!UseAES) {
 760       if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 761         warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
 762       }
 763       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 764     } else {
 765       if (UseSSE > 2) {
 766         if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 767           FLAG_SET_DEFAULT(UseAESIntrinsics, true);
 768         }
 769       } else {
 770         // The AES intrinsic stubs require AES instruction support (of course)
 771         // but also require sse3 mode or higher for instructions it use.
 772         if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 773           warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
 774         }
 775         FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 776       }
 777 
 778       // --AES-CTR begins--
 779       if (!UseAESIntrinsics) {
 780         if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 781           warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
 782           FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 783         }
 784       } else {
 785         if(supports_sse4_1()) {
 786           if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 787             FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
 788           }
 789         } else {
 790            // The AES-CTR intrinsic stubs require AES instruction support (of course)
 791            // but also require sse4.1 mode or higher for instructions it use.
 792           if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 793              warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
 794            }
 795            FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 796         }
 797       }
 798       // --AES-CTR ends--
 799     }
 800   } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
 801     if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
 802       warning("AES instructions are not available on this CPU");
 803       FLAG_SET_DEFAULT(UseAES, false);
 804     }
 805     if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 806       warning("AES intrinsics are not available on this CPU");
 807       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 808     }
 809     if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
 810       warning("AES-CTR intrinsics are not available on this CPU");
 811       FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 812     }
 813   }
 814 
 815   // Use CLMUL instructions if available.
 816   if (supports_clmul()) {
 817     if (FLAG_IS_DEFAULT(UseCLMUL)) {
 818       UseCLMUL = true;
 819     }
 820   } else if (UseCLMUL) {
 821     if (!FLAG_IS_DEFAULT(UseCLMUL))
 822       warning("CLMUL instructions not available on this CPU (AVX may also be required)");
 823     FLAG_SET_DEFAULT(UseCLMUL, false);
 824   }
 825 
 826   if (UseCLMUL && (UseSSE > 2)) {
 827     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 828       UseCRC32Intrinsics = true;
 829     }
 830   } else if (UseCRC32Intrinsics) {
 831     if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
 832       warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
 833     FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
 834   }
 835 
 836   if (supports_sse4_2() && supports_clmul()) {
 837     if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 838       UseCRC32CIntrinsics = true;
 839     }
 840   } else if (UseCRC32CIntrinsics) {
 841     if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 842       warning("CRC32C intrinsics are not available on this CPU");
 843     }
 844     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 845   }
 846 
 847   // GHASH/GCM intrinsics
 848   if (UseCLMUL && (UseSSE > 2)) {
 849     if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
 850       UseGHASHIntrinsics = true;
 851     }
 852   } else if (UseGHASHIntrinsics) {
 853     if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
 854       warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
 855     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 856   }
 857 
 858   if (supports_fma() && UseSSE >= 2) { // Check UseSSE since FMA code uses SSE instructions
 859     if (FLAG_IS_DEFAULT(UseFMA)) {
 860       UseFMA = true;
 861     }
 862   } else if (UseFMA) {
 863     warning("FMA instructions are not available on this CPU");
 864     FLAG_SET_DEFAULT(UseFMA, false);
 865   }
 866 
 867   if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) {
 868     if (FLAG_IS_DEFAULT(UseSHA)) {
 869       UseSHA = true;
 870     }
 871   } else if (UseSHA) {
 872     warning("SHA instructions are not available on this CPU");
 873     FLAG_SET_DEFAULT(UseSHA, false);
 874   }
 875 
 876   if (supports_sha() && UseSHA) {
 877     if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
 878       FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
 879     }
 880   } else if (UseSHA1Intrinsics) {
 881     warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
 882     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 883   }
 884 
 885   if (UseSHA) {
 886     if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
 887       FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
 888     }
 889   } else if (UseSHA256Intrinsics) {
 890     warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
 891     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 892   }
 893 
 894   if (UseSHA && supports_avx2() && supports_bmi2()) {
 895     if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
 896       FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
 897     }
 898   } else if (UseSHA512Intrinsics) {
 899     warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
 900     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 901   }
 902 
 903   if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
 904     FLAG_SET_DEFAULT(UseSHA, false);
 905   }
 906 
 907   if (UseAdler32Intrinsics) {
 908     warning("Adler32Intrinsics not available on this CPU.");
 909     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
 910   }
 911 
 912   if (!supports_rtm() && UseRTMLocking) {
 913     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 914     // setting during arguments processing. See use_biased_locking().
 915     // VM_Version_init() is executed after UseBiasedLocking is used
 916     // in Thread::allocate().
 917     vm_exit_during_initialization("RTM instructions are not available on this CPU");
 918   }
 919 
 920 #if INCLUDE_RTM_OPT
 921   if (UseRTMLocking) {
 922     if (is_client_compilation_mode_vm()) {
 923       // Only C2 does RTM locking optimization.
 924       // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 925       // setting during arguments processing. See use_biased_locking().
 926       vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
 927     }
 928     if (is_intel_family_core()) {
 929       if ((_model == CPU_MODEL_HASWELL_E3) ||
 930           (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
 931           (_model == CPU_MODEL_BROADWELL  && _stepping < 4)) {
 932         // currently a collision between SKL and HSW_E3
 933         if (!UnlockExperimentalVMOptions && UseAVX < 3) {
 934           vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this "
 935                                         "platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
 936         } else {
 937           warning("UseRTMLocking is only available as experimental option on this platform.");
 938         }
 939       }
 940     }
 941     if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
 942       // RTM locking should be used only for applications with
 943       // high lock contention. For now we do not use it by default.
 944       vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
 945     }
 946   } else { // !UseRTMLocking
 947     if (UseRTMForStackLocks) {
 948       if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
 949         warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
 950       }
 951       FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
 952     }
 953     if (UseRTMDeopt) {
 954       FLAG_SET_DEFAULT(UseRTMDeopt, false);
 955     }
 956     if (PrintPreciseRTMLockingStatistics) {
 957       FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
 958     }
 959   }
 960 #else
 961   if (UseRTMLocking) {
 962     // Only C2 does RTM locking optimization.
 963     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 964     // setting during arguments processing. See use_biased_locking().
 965     vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
 966   }
 967 #endif
 968 
 969 #ifdef COMPILER2
 970   if (UseFPUForSpilling) {
 971     if (UseSSE < 2) {
 972       // Only supported with SSE2+
 973       FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 974     }
 975   }
 976 #endif
 977 #if COMPILER2_OR_JVMCI
 978   if (MaxVectorSize > 0) {
 979     if (!is_power_of_2(MaxVectorSize)) {
 980       warning("MaxVectorSize must be a power of 2");
 981       FLAG_SET_DEFAULT(MaxVectorSize, 64);
 982     }
 983     if (UseSSE < 2) {
 984       // Vectors (in XMM) are only supported with SSE2+
 985       if (MaxVectorSize > 0) {
 986         if (!FLAG_IS_DEFAULT(MaxVectorSize))
 987           warning("MaxVectorSize must be 0");
 988         FLAG_SET_DEFAULT(MaxVectorSize, 0);
 989       }
 990     }
 991     else if (UseAVX == 0 || !os_supports_avx_vectors()) {
 992       // 32 bytes vectors (in YMM) are only supported with AVX+
 993       if (MaxVectorSize > 16) {
 994         if (!FLAG_IS_DEFAULT(MaxVectorSize))
 995           warning("MaxVectorSize must be <= 16");
 996         FLAG_SET_DEFAULT(MaxVectorSize, 16);
 997       }
 998     }
 999     else if (UseAVX == 1 || UseAVX == 2) {
1000       // 64 bytes vectors (in ZMM) are only supported with AVX 3
1001       if (MaxVectorSize > 32) {
1002         if (!FLAG_IS_DEFAULT(MaxVectorSize))
1003           warning("MaxVectorSize must be <= 32");
1004         FLAG_SET_DEFAULT(MaxVectorSize, 32);
1005       }
1006     }
1007     else if (UseAVX > 2 ) {
1008       if (MaxVectorSize > 64) {
1009         if (!FLAG_IS_DEFAULT(MaxVectorSize))
1010           warning("MaxVectorSize must be <= 64");
1011         FLAG_SET_DEFAULT(MaxVectorSize, 64);
1012       }
1013     }
1014 #if defined(COMPILER2) && defined(ASSERT)
1015     if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
1016       tty->print_cr("State of YMM registers after signal handle:");
1017       int nreg = 2 LP64_ONLY(+2);
1018       const char* ymm_name[4] = {"0", "7", "8", "15"};
1019       for (int i = 0; i < nreg; i++) {
1020         tty->print("YMM%s:", ymm_name[i]);
1021         for (int j = 7; j >=0; j--) {
1022           tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
1023         }
1024         tty->cr();
1025       }
1026     }
1027 #endif // COMPILER2 && ASSERT
1028   }
1029 #endif // COMPILER2_OR_JVMCI
1030 
1031 #ifdef COMPILER2
1032 #ifdef _LP64
1033   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1034     UseMultiplyToLenIntrinsic = true;
1035   }
1036   if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1037     UseSquareToLenIntrinsic = true;
1038   }
1039   if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1040     UseMulAddIntrinsic = true;
1041   }
1042   if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1043     UseMontgomeryMultiplyIntrinsic = true;
1044   }
1045   if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1046     UseMontgomerySquareIntrinsic = true;
1047   }
1048 #else
1049   if (UseMultiplyToLenIntrinsic) {
1050     if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1051       warning("multiplyToLen intrinsic is not available in 32-bit VM");
1052     }
1053     FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
1054   }
1055   if (UseMontgomeryMultiplyIntrinsic) {
1056     if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1057       warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
1058     }
1059     FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
1060   }
1061   if (UseMontgomerySquareIntrinsic) {
1062     if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1063       warning("montgomerySquare intrinsic is not available in 32-bit VM");
1064     }
1065     FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
1066   }
1067   if (UseSquareToLenIntrinsic) {
1068     if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1069       warning("squareToLen intrinsic is not available in 32-bit VM");
1070     }
1071     FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
1072   }
1073   if (UseMulAddIntrinsic) {
1074     if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1075       warning("mulAdd intrinsic is not available in 32-bit VM");
1076     }
1077     FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
1078   }
1079 #endif
1080 #endif // COMPILER2
1081 
1082   // On new cpus instructions which update whole XMM register should be used
1083   // to prevent partial register stall due to dependencies on high half.
1084   //
1085   // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
1086   // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1087   // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
1088   // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).
1089 
1090 
1091   if (is_zx()) { // ZX cpus specific settings
1092     if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1093       UseStoreImmI16 = false; // don't use it on ZX cpus
1094     }
1095     if ((cpu_family() == 6) || (cpu_family() == 7)) {
1096       if (FLAG_IS_DEFAULT(UseAddressNop)) {
1097         // Use it on all ZX cpus
1098         UseAddressNop = true;
1099       }
1100     }
1101     if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1102       UseXmmLoadAndClearUpper = true; // use movsd on all ZX cpus
1103     }
1104     if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1105       if (supports_sse3()) {
1106         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new ZX cpus
1107       } else {
1108         UseXmmRegToRegMoveAll = false;
1109       }
1110     }
1111     if (((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse3()) { // new ZX cpus
1112 #ifdef COMPILER2
1113       if (FLAG_IS_DEFAULT(MaxLoopPad)) {
1114         // For new ZX cpus do the next optimization:
1115         // don't align the beginning of a loop if there are enough instructions
1116         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1117         // in current fetch line (OptoLoopAlignment) or the padding
1118         // is big (> MaxLoopPad).
1119         // Set MaxLoopPad to 11 for new ZX cpus to reduce number of
1120         // generated NOP instructions. 11 is the largest size of one
1121         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1122         MaxLoopPad = 11;
1123       }
1124 #endif // COMPILER2
1125       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1126         UseXMMForArrayCopy = true; // use SSE2 movq on new ZX cpus
1127       }
1128       if (supports_sse4_2()) { // new ZX cpus
1129         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1130           UseUnalignedLoadStores = true; // use movdqu on newest ZX cpus
1131         }
1132       }
1133       if (supports_sse4_2()) {
1134         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1135           FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1136         }
1137       } else {
1138         if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1139           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1140         }
1141         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1142       }
1143     }
1144 
1145     if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1146       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1147     }
1148   }
1149 
1150   if( is_amd() ) { // AMD cpus specific settings
1151     if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
1152       // Use it on new AMD cpus starting from Opteron.
1153       UseAddressNop = true;
1154     }
1155     if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
1156       // Use it on new AMD cpus starting from Opteron.
1157       UseNewLongLShift = true;
1158     }
1159     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1160       if (supports_sse4a()) {
1161         UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1162       } else {
1163         UseXmmLoadAndClearUpper = false;
1164       }
1165     }
1166     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1167       if( supports_sse4a() ) {
1168         UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1169       } else {
1170         UseXmmRegToRegMoveAll = false;
1171       }
1172     }
1173     if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
1174       if( supports_sse4a() ) {
1175         UseXmmI2F = true;
1176       } else {
1177         UseXmmI2F = false;
1178       }
1179     }
1180     if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
1181       if( supports_sse4a() ) {
1182         UseXmmI2D = true;
1183       } else {
1184         UseXmmI2D = false;
1185       }
1186     }
1187     if (supports_sse4_2()) {
1188       if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1189         FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1190       }
1191     } else {
1192       if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1193         warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1194       }
1195       FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1196     }
1197 
1198     // some defaults for AMD family 15h
1199     if ( cpu_family() == 0x15 ) {
1200       // On family 15h processors default is no sw prefetch
1201       if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1202         FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1203       }
1204       // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1205       if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1206         FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1207       }
1208       // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1209       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1210         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1211       }
1212       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1213         FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1214       }
1215     }
1216 
1217 #ifdef COMPILER2
1218     if (cpu_family() < 0x17 && MaxVectorSize > 16) {
1219       // Limit vectors size to 16 bytes on AMD cpus < 17h.
1220       FLAG_SET_DEFAULT(MaxVectorSize, 16);
1221     }
1222 #endif // COMPILER2
1223 
1224     // Some defaults for AMD family 17h
1225     if ( cpu_family() == 0x17 ) {
1226       // On family 17h processors use XMM and UnalignedLoadStores for Array Copy
1227       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1228         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1229       }
1230       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1231         FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1232       }
1233 #ifdef COMPILER2
1234       if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1235         FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1236       }
1237 #endif
1238     }
1239   }
1240 
1241   if( is_intel() ) { // Intel cpus specific settings
1242     if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
1243       UseStoreImmI16 = false; // don't use it on Intel cpus
1244     }
1245     if( cpu_family() == 6 || cpu_family() == 15 ) {
1246       if( FLAG_IS_DEFAULT(UseAddressNop) ) {
1247         // Use it on all Intel cpus starting from PentiumPro
1248         UseAddressNop = true;
1249       }
1250     }
1251     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1252       UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1253     }
1254     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1255       if( supports_sse3() ) {
1256         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1257       } else {
1258         UseXmmRegToRegMoveAll = false;
1259       }
1260     }
1261     if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
1262 #ifdef COMPILER2
1263       if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
1264         // For new Intel cpus do the next optimization:
1265         // don't align the beginning of a loop if there are enough instructions
1266         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1267         // in current fetch line (OptoLoopAlignment) or the padding
1268         // is big (> MaxLoopPad).
1269         // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1270         // generated NOP instructions. 11 is the largest size of one
1271         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1272         MaxLoopPad = 11;
1273       }
1274 #endif // COMPILER2
1275       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1276         UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1277       }
1278       if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
1279         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1280           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1281         }
1282       }
1283       if (supports_sse4_2()) {
1284         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1285           FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1286         }
1287       } else {
1288         if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1289           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1290         }
1291         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1292       }
1293     }
1294     if (is_atom_family() || is_knights_family()) {
1295 #ifdef COMPILER2
1296       if (FLAG_IS_DEFAULT(OptoScheduling)) {
1297         OptoScheduling = true;
1298       }
1299 #endif
1300       if (supports_sse4_2()) { // Silvermont
1301         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1302           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1303         }
1304       }
1305       if (FLAG_IS_DEFAULT(UseIncDec)) {
1306         FLAG_SET_DEFAULT(UseIncDec, false);
1307       }
1308     }
1309     if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1310       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1311     }
1312   }
1313 
1314 #ifdef _LP64
1315   if (UseSSE42Intrinsics) {
1316     if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1317       UseVectorizedMismatchIntrinsic = true;
1318     }
1319   } else if (UseVectorizedMismatchIntrinsic) {
1320     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1321       warning("vectorizedMismatch intrinsics are not available on this CPU");
1322     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1323   }
1324 #else
1325   if (UseVectorizedMismatchIntrinsic) {
1326     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1327       warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1328     }
1329     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1330   }
1331 #endif // _LP64
1332 
1333   // Use count leading zeros count instruction if available.
1334   if (supports_lzcnt()) {
1335     if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1336       UseCountLeadingZerosInstruction = true;
1337     }
1338    } else if (UseCountLeadingZerosInstruction) {
1339     warning("lzcnt instruction is not available on this CPU");
1340     FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1341   }
1342 
1343   // Use count trailing zeros instruction if available
1344   if (supports_bmi1()) {
1345     // tzcnt does not require VEX prefix
1346     if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1347       if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1348         // Don't use tzcnt if BMI1 is switched off on command line.
1349         UseCountTrailingZerosInstruction = false;
1350       } else {
1351         UseCountTrailingZerosInstruction = true;
1352       }
1353     }
1354   } else if (UseCountTrailingZerosInstruction) {
1355     warning("tzcnt instruction is not available on this CPU");
1356     FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1357   }
1358 
1359   // BMI instructions (except tzcnt) use an encoding with VEX prefix.
1360   // VEX prefix is generated only when AVX > 0.
1361   if (supports_bmi1() && supports_avx()) {
1362     if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1363       UseBMI1Instructions = true;
1364     }
1365   } else if (UseBMI1Instructions) {
1366     warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1367     FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1368   }
1369 
1370   if (supports_bmi2() && supports_avx()) {
1371     if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1372       UseBMI2Instructions = true;
1373     }
1374   } else if (UseBMI2Instructions) {
1375     warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1376     FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1377   }
1378 
1379   // Use population count instruction if available.
1380   if (supports_popcnt()) {
1381     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1382       UsePopCountInstruction = true;
1383     }
1384   } else if (UsePopCountInstruction) {
1385     warning("POPCNT instruction is not available on this CPU");
1386     FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1387   }
1388 
1389   // Use fast-string operations if available.
1390   if (supports_erms()) {
1391     if (FLAG_IS_DEFAULT(UseFastStosb)) {
1392       UseFastStosb = true;
1393     }
1394   } else if (UseFastStosb) {
1395     warning("fast-string operations are not available on this CPU");
1396     FLAG_SET_DEFAULT(UseFastStosb, false);
1397   }
1398 
1399 #ifdef COMPILER2
1400   if (FLAG_IS_DEFAULT(AlignVector)) {
1401     // Modern processors allow misaligned memory operations for vectors.
1402     AlignVector = !UseUnalignedLoadStores;
1403   }
1404 #endif // COMPILER2
1405 
1406   if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1407     if (AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch()) {
1408       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
1409     } else if (!supports_sse() && supports_3dnow_prefetch()) {
1410       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1411     }
1412   }
1413 
1414   // Allocation prefetch settings
1415   intx cache_line_size = prefetch_data_size();
1416   if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) &&
1417       (cache_line_size > AllocatePrefetchStepSize)) {
1418     FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size);
1419   }
1420 
1421   if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) {
1422     assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0");
1423     if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1424       warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag.");
1425     }
1426     FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1427   }
1428 
1429   if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
1430     bool use_watermark_prefetch = (AllocatePrefetchStyle == 2);
1431     FLAG_SET_DEFAULT(AllocatePrefetchDistance, allocate_prefetch_distance(use_watermark_prefetch));
1432   }
1433 
1434   if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1435     if (FLAG_IS_DEFAULT(AllocatePrefetchLines) &&
1436         supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1437       FLAG_SET_DEFAULT(AllocatePrefetchLines, 4);
1438     }
1439 #ifdef COMPILER2
1440     if (FLAG_IS_DEFAULT(UseFPUForSpilling) && supports_sse4_2()) {
1441       FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1442     }
1443 #endif
1444   }
1445 
1446   if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse4_2()) {
1447 #ifdef COMPILER2
1448     if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1449       FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1450     }
1451 #endif
1452   }
1453 
1454 #ifdef _LP64
1455   // Prefetch settings
1456 
1457   // Prefetch interval for gc copy/scan == 9 dcache lines.  Derived from
1458   // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
1459   // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
1460   // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
1461 
1462   // gc copy/scan is disabled if prefetchw isn't supported, because
1463   // Prefetch::write emits an inlined prefetchw on Linux.
1464   // Do not use the 3dnow prefetchw instruction.  It isn't supported on em64t.
1465   // The used prefetcht0 instruction works for both amd64 and em64t.
1466 
1467   if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) {
1468     FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 576);
1469   }
1470   if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
1471     FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576);
1472   }
1473   if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
1474     FLAG_SET_DEFAULT(PrefetchFieldsAhead, 1);
1475   }
1476 #endif
1477 
1478   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1479      (cache_line_size > ContendedPaddingWidth))
1480      ContendedPaddingWidth = cache_line_size;
1481 
1482   // This machine allows unaligned memory accesses
1483   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1484     FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1485   }
1486 
1487 #ifndef PRODUCT
1488   if (log_is_enabled(Info, os, cpu)) {
1489     LogStream ls(Log(os, cpu)::info());
1490     outputStream* log = &ls;
1491     log->print_cr("Logical CPUs per core: %u",
1492                   logical_processors_per_package());
1493     log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1494     log->print("UseSSE=%d", (int) UseSSE);
1495     if (UseAVX > 0) {
1496       log->print("  UseAVX=%d", (int) UseAVX);
1497     }
1498     if (UseAES) {
1499       log->print("  UseAES=1");
1500     }
1501 #ifdef COMPILER2
1502     if (MaxVectorSize > 0) {
1503       log->print("  MaxVectorSize=%d", (int) MaxVectorSize);
1504     }
1505 #endif
1506     log->cr();
1507     log->print("Allocation");
1508     if (AllocatePrefetchStyle <= 0 || (UseSSE == 0 && !supports_3dnow_prefetch())) {
1509       log->print_cr(": no prefetching");
1510     } else {
1511       log->print(" prefetching: ");
1512       if (UseSSE == 0 && supports_3dnow_prefetch()) {
1513         log->print("PREFETCHW");
1514       } else if (UseSSE >= 1) {
1515         if (AllocatePrefetchInstr == 0) {
1516           log->print("PREFETCHNTA");
1517         } else if (AllocatePrefetchInstr == 1) {
1518           log->print("PREFETCHT0");
1519         } else if (AllocatePrefetchInstr == 2) {
1520           log->print("PREFETCHT2");
1521         } else if (AllocatePrefetchInstr == 3) {
1522           log->print("PREFETCHW");
1523         }
1524       }
1525       if (AllocatePrefetchLines > 1) {
1526         log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1527       } else {
1528         log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1529       }
1530     }
1531 
1532     if (PrefetchCopyIntervalInBytes > 0) {
1533       log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1534     }
1535     if (PrefetchScanIntervalInBytes > 0) {
1536       log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1537     }
1538     if (PrefetchFieldsAhead > 0) {
1539       log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1540     }
1541     if (ContendedPaddingWidth > 0) {
1542       log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1543     }
1544   }
1545 #endif // !PRODUCT
1546 }
1547 
1548 bool VM_Version::use_biased_locking() {
1549 #if INCLUDE_RTM_OPT
1550   // RTM locking is most useful when there is high lock contention and
1551   // low data contention.  With high lock contention the lock is usually
1552   // inflated and biased locking is not suitable for that case.
1553   // RTM locking code requires that biased locking is off.
1554   // Note: we can't switch off UseBiasedLocking in get_processor_features()
1555   // because it is used by Thread::allocate() which is called before
1556   // VM_Version::initialize().
1557   if (UseRTMLocking && UseBiasedLocking) {
1558     if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1559       FLAG_SET_DEFAULT(UseBiasedLocking, false);
1560     } else {
1561       warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1562       UseBiasedLocking = false;
1563     }
1564   }
1565 #endif
1566   return UseBiasedLocking;
1567 }
1568 
1569 void VM_Version::initialize() {
1570   ResourceMark rm;
1571   // Making this stub must be FIRST use of assembler
1572 
1573   stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1574   if (stub_blob == NULL) {
1575     vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1576   }
1577   CodeBuffer c(stub_blob);
1578   VM_Version_StubGenerator g(&c);
1579   get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1580                                      g.generate_get_cpu_info());
1581 
1582   get_processor_features();
1583 }