1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.inline.hpp" 27 #include "memory/resourceArea.hpp" 28 #include "runtime/java.hpp" 29 #include "runtime/os.hpp" 30 #include "runtime/stubCodeGenerator.hpp" 31 #include "vm_version_sparc.hpp" 32 33 int VM_Version::_features = VM_Version::unknown_m; 34 const char* VM_Version::_features_str = ""; 35 unsigned int VM_Version::_L2_data_cache_line_size = 0; 36 37 void VM_Version::initialize() { 38 39 assert(_features != VM_Version::unknown_m, "System pre-initialization is not complete."); 40 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); 41 42 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); 43 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 44 PrefetchFieldsAhead = prefetch_fields_ahead(); 45 46 // Allocation prefetch settings 47 intx cache_line_size = prefetch_data_size(); 48 if( cache_line_size > AllocatePrefetchStepSize ) 49 AllocatePrefetchStepSize = cache_line_size; 50 51 assert(AllocatePrefetchLines > 0, "invalid value"); 52 if( AllocatePrefetchLines < 1 ) // set valid value in product VM 53 AllocatePrefetchLines = 3; 54 assert(AllocateInstancePrefetchLines > 0, "invalid value"); 55 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM 56 AllocateInstancePrefetchLines = 1; 57 58 AllocatePrefetchDistance = allocate_prefetch_distance(); 59 AllocatePrefetchStyle = allocate_prefetch_style(); 60 61 if (AllocatePrefetchStyle == 3 && !has_blk_init()) { 62 warning("BIS instructions are not available on this CPU"); 63 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); 64 } 65 66 UseSSE = 0; // Only on x86 and x64 67 68 _supports_cx8 = has_v9(); 69 _supports_atomic_getset4 = true; // swap instruction 70 71 if (is_niagara()) { 72 // Indirect branch is the same cost as direct 73 if (FLAG_IS_DEFAULT(UseInlineCaches)) { 74 FLAG_SET_DEFAULT(UseInlineCaches, false); 75 } 76 // Align loops on a single instruction boundary. 77 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { 78 FLAG_SET_DEFAULT(OptoLoopAlignment, 4); 79 } 80 #ifdef _LP64 81 // 32-bit oops don't make sense for the 64-bit VM on sparc 82 // since the 32-bit VM has the same registers and smaller objects. 83 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); 84 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes); 85 #endif // _LP64 86 #ifdef COMPILER2 87 // Indirect branch is the same cost as direct 88 if (FLAG_IS_DEFAULT(UseJumpTables)) { 89 FLAG_SET_DEFAULT(UseJumpTables, true); 90 } 91 // Single-issue, so entry and loop tops are 92 // aligned on a single instruction boundary 93 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { 94 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); 95 } 96 if (is_niagara_plus()) { 97 if (has_blk_init() && UseTLAB && 98 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { 99 // Use BIS instruction for TLAB allocation prefetch. 100 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); 101 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { 102 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); 103 } 104 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { 105 // Use smaller prefetch distance with BIS 106 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); 107 } 108 } 109 if (is_T4()) { 110 // Double number of prefetched cache lines on T4 111 // since L2 cache line size is smaller (32 bytes). 112 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { 113 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2); 114 } 115 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { 116 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2); 117 } 118 } 119 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { 120 // Use different prefetch distance without BIS 121 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); 122 } 123 if (AllocatePrefetchInstr == 1) { 124 // Need a space at the end of TLAB for BIS since it 125 // will fault when accessing memory outside of heap. 126 127 // +1 for rounding up to next cache line, +1 to be safe 128 int lines = AllocatePrefetchLines + 2; 129 int step_size = AllocatePrefetchStepSize; 130 int distance = AllocatePrefetchDistance; 131 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize; 132 } 133 } 134 #endif 135 } 136 137 // Use hardware population count instruction if available. 138 if (has_hardware_popc()) { 139 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { 140 FLAG_SET_DEFAULT(UsePopCountInstruction, true); 141 } 142 } else if (UsePopCountInstruction) { 143 warning("POPC instruction is not available on this CPU"); 144 FLAG_SET_DEFAULT(UsePopCountInstruction, false); 145 } 146 147 // T4 and newer Sparc cpus have new compare and branch instruction. 148 if (has_cbcond()) { 149 if (FLAG_IS_DEFAULT(UseCBCond)) { 150 FLAG_SET_DEFAULT(UseCBCond, true); 151 } 152 } else if (UseCBCond) { 153 warning("CBCOND instruction is not available on this CPU"); 154 FLAG_SET_DEFAULT(UseCBCond, false); 155 } 156 157 assert(BlockZeroingLowLimit > 0, "invalid value"); 158 if (has_block_zeroing() && cache_line_size > 0) { 159 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { 160 FLAG_SET_DEFAULT(UseBlockZeroing, true); 161 } 162 } else if (UseBlockZeroing) { 163 warning("BIS zeroing instructions are not available on this CPU"); 164 FLAG_SET_DEFAULT(UseBlockZeroing, false); 165 } 166 167 assert(BlockCopyLowLimit > 0, "invalid value"); 168 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache 169 if (FLAG_IS_DEFAULT(UseBlockCopy)) { 170 FLAG_SET_DEFAULT(UseBlockCopy, true); 171 } 172 } else if (UseBlockCopy) { 173 warning("BIS instructions are not available or expensive on this CPU"); 174 FLAG_SET_DEFAULT(UseBlockCopy, false); 175 } 176 177 #ifdef COMPILER2 178 // T4 and newer Sparc cpus have fast RDPC. 179 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { 180 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); 181 } 182 183 // Currently not supported anywhere. 184 FLAG_SET_DEFAULT(UseFPUForSpilling, false); 185 186 MaxVectorSize = 8; 187 188 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 189 #endif 190 191 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 192 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 193 194 char buf[512]; 195 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 196 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), 197 (has_hardware_popc() ? ", popc" : ""), 198 (has_vis1() ? ", vis1" : ""), 199 (has_vis2() ? ", vis2" : ""), 200 (has_vis3() ? ", vis3" : ""), 201 (has_blk_init() ? ", blk_init" : ""), 202 (has_cbcond() ? ", cbcond" : ""), 203 (has_aes() ? ", aes" : ""), 204 (has_sha1() ? ", sha1" : ""), 205 (has_sha256() ? ", sha256" : ""), 206 (has_sha512() ? ", sha512" : ""), 207 (has_crc32c() ? ", crc32c" : ""), 208 (is_ultra3() ? ", ultra3" : ""), 209 (is_sun4v() ? ", sun4v" : ""), 210 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), 211 (is_sparc64() ? ", sparc64" : ""), 212 (!has_hardware_mul32() ? ", no-mul32" : ""), 213 (!has_hardware_div32() ? ", no-div32" : ""), 214 (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); 215 216 // buf is started with ", " or is empty 217 _features_str = os::strdup(strlen(buf) > 2 ? buf + 2 : buf); 218 219 // UseVIS is set to the smallest of what hardware supports and what 220 // the command line requires. I.e., you cannot set UseVIS to 3 on 221 // older UltraSparc which do not support it. 222 if (UseVIS > 3) UseVIS=3; 223 if (UseVIS < 0) UseVIS=0; 224 if (!has_vis3()) // Drop to 2 if no VIS3 support 225 UseVIS = MIN2((intx)2,UseVIS); 226 if (!has_vis2()) // Drop to 1 if no VIS2 support 227 UseVIS = MIN2((intx)1,UseVIS); 228 if (!has_vis1()) // Drop to 0 if no VIS1 support 229 UseVIS = 0; 230 231 // SPARC T4 and above should have support for AES instructions 232 if (has_aes()) { 233 if (FLAG_IS_DEFAULT(UseAES)) { 234 FLAG_SET_DEFAULT(UseAES, true); 235 } 236 if (!UseAES) { 237 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 238 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled."); 239 } 240 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 241 } else { 242 // The AES intrinsic stubs require AES instruction support (of course) 243 // but also require VIS3 mode or higher for instructions it use. 244 if (UseVIS > 2) { 245 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { 246 FLAG_SET_DEFAULT(UseAESIntrinsics, true); 247 } 248 } else { 249 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 250 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled."); 251 } 252 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 253 } 254 } 255 } else if (UseAES || UseAESIntrinsics) { 256 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) { 257 warning("AES instructions are not available on this CPU"); 258 FLAG_SET_DEFAULT(UseAES, false); 259 } 260 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 261 warning("AES intrinsics are not available on this CPU"); 262 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 263 } 264 } 265 266 // GHASH/GCM intrinsics 267 if (has_vis3() && (UseVIS > 2)) { 268 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { 269 UseGHASHIntrinsics = true; 270 } 271 } else if (UseGHASHIntrinsics) { 272 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics)) 273 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled"); 274 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 275 } 276 277 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times 278 if (has_sha1() || has_sha256() || has_sha512()) { 279 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions 280 if (FLAG_IS_DEFAULT(UseSHA)) { 281 FLAG_SET_DEFAULT(UseSHA, true); 282 } 283 } else { 284 if (UseSHA) { 285 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled."); 286 FLAG_SET_DEFAULT(UseSHA, false); 287 } 288 } 289 } else if (UseSHA) { 290 warning("SHA instructions are not available on this CPU"); 291 FLAG_SET_DEFAULT(UseSHA, false); 292 } 293 294 if (UseSHA && has_sha1()) { 295 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { 296 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); 297 } 298 } else if (UseSHA1Intrinsics) { 299 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU."); 300 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 301 } 302 303 if (UseSHA && has_sha256()) { 304 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { 305 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); 306 } 307 } else if (UseSHA256Intrinsics) { 308 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU."); 309 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 310 } 311 312 if (UseSHA && has_sha512()) { 313 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { 314 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); 315 } 316 } else if (UseSHA512Intrinsics) { 317 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU."); 318 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 319 } 320 321 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { 322 FLAG_SET_DEFAULT(UseSHA, false); 323 } 324 325 // SPARC T4 and above should have support for CRC32C instruction 326 if (has_crc32c()) { 327 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions 328 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 329 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true); 330 } 331 } else { 332 if (UseCRC32CIntrinsics) { 333 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled."); 334 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 335 } 336 } 337 } else if (UseCRC32CIntrinsics) { 338 warning("CRC32C instruction is not available on this CPU"); 339 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 340 } 341 342 if (UseVIS > 2) { 343 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) { 344 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true); 345 } 346 } else if (UseAdler32Intrinsics) { 347 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled."); 348 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); 349 } 350 351 if (UseVIS > 2) { 352 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 353 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true); 354 } 355 } else if (UseCRC32Intrinsics) { 356 warning("SPARC CRC32 intrinsics require VIS3 insructions support. Intriniscs will be disabled"); 357 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); 358 } 359 360 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && 361 (cache_line_size > ContendedPaddingWidth)) 362 ContendedPaddingWidth = cache_line_size; 363 364 // This machine does not allow unaligned memory accesses 365 if (UseUnalignedAccesses) { 366 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses)) 367 warning("Unaligned memory access is not available on this CPU"); 368 FLAG_SET_DEFAULT(UseUnalignedAccesses, false); 369 } 370 371 if (PrintMiscellaneous && Verbose) { 372 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size()); 373 tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size()); 374 tty->print("Allocation"); 375 if (AllocatePrefetchStyle <= 0) { 376 tty->print_cr(": no prefetching"); 377 } else { 378 tty->print(" prefetching: "); 379 if (AllocatePrefetchInstr == 0) { 380 tty->print("PREFETCH"); 381 } else if (AllocatePrefetchInstr == 1) { 382 tty->print("BIS"); 383 } 384 if (AllocatePrefetchLines > 1) { 385 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); 386 } else { 387 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); 388 } 389 } 390 if (PrefetchCopyIntervalInBytes > 0) { 391 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); 392 } 393 if (PrefetchScanIntervalInBytes > 0) { 394 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); 395 } 396 if (PrefetchFieldsAhead > 0) { 397 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); 398 } 399 if (ContendedPaddingWidth > 0) { 400 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); 401 } 402 } 403 } 404 405 void VM_Version::print_features() { 406 tty->print_cr("Version:%s", cpu_features()); 407 } 408 409 int VM_Version::determine_features() { 410 if (UseV8InstrsOnly) { 411 if (PrintMiscellaneous && Verbose) { tty->print_cr("Version is Forced-V8"); } 412 return generic_v8_m; 413 } 414 415 int features = platform_features(unknown_m); // platform_features() is os_arch specific 416 417 if (features == unknown_m) { 418 features = generic_v9_m; 419 warning("Cannot recognize SPARC version. Default to V9"); 420 } 421 422 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); 423 if (UseNiagaraInstrs) { // Force code generation for Niagara 424 if (is_T_family(features)) { 425 // Happy to accomodate... 426 } else { 427 if (PrintMiscellaneous && Verbose) { tty->print_cr("Version is Forced-Niagara"); } 428 features |= T_family_m; 429 } 430 } else { 431 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { 432 if (PrintMiscellaneous && Verbose) { tty->print_cr("Version is Forced-Not-Niagara"); } 433 features &= ~(T_family_m | T1_model_m); 434 } else { 435 // Happy to accomodate... 436 } 437 } 438 439 return features; 440 } 441 442 static int saved_features = 0; 443 444 void VM_Version::allow_all() { 445 saved_features = _features; 446 _features = all_features_m; 447 } 448 449 void VM_Version::revert() { 450 _features = saved_features; 451 } 452 453 unsigned int VM_Version::calc_parallel_worker_threads() { 454 unsigned int result; 455 if (is_M_series()) { 456 // for now, use same gc thread calculation for M-series as for niagara-plus 457 // in future, we may want to tweak parameters for nof_parallel_worker_thread 458 result = nof_parallel_worker_threads(5, 16, 8); 459 } else if (is_niagara_plus()) { 460 result = nof_parallel_worker_threads(5, 16, 8); 461 } else { 462 result = nof_parallel_worker_threads(5, 8, 8); 463 } 464 return result; 465 }