1 /*
   2  * Copyright 1997-2009 Sun Microsystems, Inc.  All Rights Reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
  20  * CA 95054 USA or visit www.sun.com if you need additional information or
  21  * have any questions.
  22  *
  23  */
  24 
  25 class BiasedLockingCounters;
  26 
  27 // Contains all the definitions needed for x86 assembly code generation.
  28 
  29 // Calling convention
  30 class Argument VALUE_OBJ_CLASS_SPEC {
  31  public:
  32   enum {
  33 #ifdef _LP64
  34 #ifdef _WIN64
  35     n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
  36     n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
  37 #else
  38     n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
  39     n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
  40 #endif // _WIN64
  41     n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
  42     n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
  43 #else
  44     n_register_parameters = 0   // 0 registers used to pass arguments
  45 #endif // _LP64
  46   };
  47 };
  48 
  49 
  50 #ifdef _LP64
  51 // Symbolically name the register arguments used by the c calling convention.
  52 // Windows is different from linux/solaris. So much for standards...
  53 
  54 #ifdef _WIN64
  55 
  56 REGISTER_DECLARATION(Register, c_rarg0, rcx);
  57 REGISTER_DECLARATION(Register, c_rarg1, rdx);
  58 REGISTER_DECLARATION(Register, c_rarg2, r8);
  59 REGISTER_DECLARATION(Register, c_rarg3, r9);
  60 
  61 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  62 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  63 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  64 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  65 
  66 #else
  67 
  68 REGISTER_DECLARATION(Register, c_rarg0, rdi);
  69 REGISTER_DECLARATION(Register, c_rarg1, rsi);
  70 REGISTER_DECLARATION(Register, c_rarg2, rdx);
  71 REGISTER_DECLARATION(Register, c_rarg3, rcx);
  72 REGISTER_DECLARATION(Register, c_rarg4, r8);
  73 REGISTER_DECLARATION(Register, c_rarg5, r9);
  74 
  75 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
  76 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
  77 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
  78 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
  79 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
  80 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
  81 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
  82 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
  83 
  84 #endif // _WIN64
  85 
  86 // Symbolically name the register arguments used by the Java calling convention.
  87 // We have control over the convention for java so we can do what we please.
  88 // What pleases us is to offset the java calling convention so that when
  89 // we call a suitable jni method the arguments are lined up and we don't
  90 // have to do little shuffling. A suitable jni method is non-static and a
  91 // small number of arguments (two fewer args on windows)
  92 //
  93 //        |-------------------------------------------------------|
  94 //        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
  95 //        |-------------------------------------------------------|
  96 //        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
  97 //        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
  98 //        |-------------------------------------------------------|
  99 //        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
 100 //        |-------------------------------------------------------|
 101 
 102 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
 103 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
 104 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
 105 // Windows runs out of register args here
 106 #ifdef _WIN64
 107 REGISTER_DECLARATION(Register, j_rarg3, rdi);
 108 REGISTER_DECLARATION(Register, j_rarg4, rsi);
 109 #else
 110 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
 111 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
 112 #endif /* _WIN64 */
 113 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
 114 
 115 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
 116 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
 117 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
 118 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
 119 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
 120 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
 121 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
 122 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
 123 
 124 REGISTER_DECLARATION(Register, rscratch1, r10);  // volatile
 125 REGISTER_DECLARATION(Register, rscratch2, r11);  // volatile
 126 
 127 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
 128 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
 129 
 130 #else
 131 // rscratch1 will apear in 32bit code that is dead but of course must compile
 132 // Using noreg ensures if the dead code is incorrectly live and executed it
 133 // will cause an assertion failure
 134 #define rscratch1 noreg
 135 
 136 #endif // _LP64
 137 
 138 // Address is an abstraction used to represent a memory location
 139 // using any of the amd64 addressing modes with one object.
 140 //
 141 // Note: A register location is represented via a Register, not
 142 //       via an address for efficiency & simplicity reasons.
 143 
 144 class ArrayAddress;
 145 
 146 class Address VALUE_OBJ_CLASS_SPEC {
 147  public:
 148   enum ScaleFactor {
 149     no_scale = -1,
 150     times_1  =  0,
 151     times_2  =  1,
 152     times_4  =  2,
 153     times_8  =  3,
 154     times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
 155   };
 156   static ScaleFactor times(int size) {
 157     assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
 158     if (size == 8)  return times_8;
 159     if (size == 4)  return times_4;
 160     if (size == 2)  return times_2;
 161     return times_1;
 162   }
 163   static int scale_size(ScaleFactor scale) {
 164     assert(scale != no_scale, "");
 165     assert(((1 << (int)times_1) == 1 &&
 166             (1 << (int)times_2) == 2 &&
 167             (1 << (int)times_4) == 4 &&
 168             (1 << (int)times_8) == 8), "");
 169     return (1 << (int)scale);
 170   }
 171 
 172  private:
 173   Register         _base;
 174   Register         _index;
 175   ScaleFactor      _scale;
 176   int              _disp;
 177   RelocationHolder _rspec;
 178 
 179   // Easily misused constructors make them private
 180   // %%% can we make these go away?
 181   NOT_LP64(Address(address loc, RelocationHolder spec);)
 182   Address(int disp, address loc, relocInfo::relocType rtype);
 183   Address(int disp, address loc, RelocationHolder spec);
 184 
 185  public:
 186 
 187  int disp() { return _disp; }
 188   // creation
 189   Address()
 190     : _base(noreg),
 191       _index(noreg),
 192       _scale(no_scale),
 193       _disp(0) {
 194   }
 195 
 196   // No default displacement otherwise Register can be implicitly
 197   // converted to 0(Register) which is quite a different animal.
 198 
 199   Address(Register base, int disp)
 200     : _base(base),
 201       _index(noreg),
 202       _scale(no_scale),
 203       _disp(disp) {
 204   }
 205 
 206   Address(Register base, Register index, ScaleFactor scale, int disp = 0)
 207     : _base (base),
 208       _index(index),
 209       _scale(scale),
 210       _disp (disp) {
 211     assert(!index->is_valid() == (scale == Address::no_scale),
 212            "inconsistent address");
 213   }
 214 
 215   Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
 216     : _base (base),
 217       _index(index.register_or_noreg()),
 218       _scale(scale),
 219       _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
 220     if (!index.is_register())  scale = Address::no_scale;
 221     assert(!_index->is_valid() == (scale == Address::no_scale),
 222            "inconsistent address");
 223   }
 224 
 225   Address plus_disp(int disp) const {
 226     Address a = (*this);
 227     a._disp += disp;
 228     return a;
 229   }
 230 
 231   // The following two overloads are used in connection with the
 232   // ByteSize type (see sizes.hpp).  They simplify the use of
 233   // ByteSize'd arguments in assembly code. Note that their equivalent
 234   // for the optimized build are the member functions with int disp
 235   // argument since ByteSize is mapped to an int type in that case.
 236   //
 237   // Note: DO NOT introduce similar overloaded functions for WordSize
 238   // arguments as in the optimized mode, both ByteSize and WordSize
 239   // are mapped to the same type and thus the compiler cannot make a
 240   // distinction anymore (=> compiler errors).
 241 
 242 #ifdef ASSERT
 243   Address(Register base, ByteSize disp)
 244     : _base(base),
 245       _index(noreg),
 246       _scale(no_scale),
 247       _disp(in_bytes(disp)) {
 248   }
 249 
 250   Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
 251     : _base(base),
 252       _index(index),
 253       _scale(scale),
 254       _disp(in_bytes(disp)) {
 255     assert(!index->is_valid() == (scale == Address::no_scale),
 256            "inconsistent address");
 257   }
 258 
 259   Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
 260     : _base (base),
 261       _index(index.register_or_noreg()),
 262       _scale(scale),
 263       _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
 264     if (!index.is_register())  scale = Address::no_scale;
 265     assert(!_index->is_valid() == (scale == Address::no_scale),
 266            "inconsistent address");
 267   }
 268 
 269 #endif // ASSERT
 270 
 271   // accessors
 272   bool        uses(Register reg) const { return _base == reg || _index == reg; }
 273   Register    base()             const { return _base;  }
 274   Register    index()            const { return _index; }
 275   ScaleFactor scale()            const { return _scale; }
 276   int         disp()             const { return _disp;  }
 277 
 278   // Convert the raw encoding form into the form expected by the constructor for
 279   // Address.  An index of 4 (rsp) corresponds to having no index, so convert
 280   // that to noreg for the Address constructor.
 281   static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
 282 
 283   static Address make_array(ArrayAddress);
 284 
 285  private:
 286   bool base_needs_rex() const {
 287     return _base != noreg && _base->encoding() >= 8;
 288   }
 289 
 290   bool index_needs_rex() const {
 291     return _index != noreg &&_index->encoding() >= 8;
 292   }
 293 
 294   relocInfo::relocType reloc() const { return _rspec.type(); }
 295 
 296   friend class Assembler;
 297   friend class MacroAssembler;
 298   friend class LIR_Assembler; // base/index/scale/disp
 299 };
 300 
 301 //
 302 // AddressLiteral has been split out from Address because operands of this type
 303 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
 304 // the few instructions that need to deal with address literals are unique and the
 305 // MacroAssembler does not have to implement every instruction in the Assembler
 306 // in order to search for address literals that may need special handling depending
 307 // on the instruction and the platform. As small step on the way to merging i486/amd64
 308 // directories.
 309 //
 310 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
 311   friend class ArrayAddress;
 312   RelocationHolder _rspec;
 313   // Typically we use AddressLiterals we want to use their rval
 314   // However in some situations we want the lval (effect address) of the item.
 315   // We provide a special factory for making those lvals.
 316   bool _is_lval;
 317 
 318   // If the target is far we'll need to load the ea of this to
 319   // a register to reach it. Otherwise if near we can do rip
 320   // relative addressing.
 321 
 322   address          _target;
 323 
 324  protected:
 325   // creation
 326   AddressLiteral()
 327     : _is_lval(false),
 328       _target(NULL)
 329   {}
 330 
 331   public:
 332 
 333 
 334   AddressLiteral(address target, relocInfo::relocType rtype);
 335 
 336   AddressLiteral(address target, RelocationHolder const& rspec)
 337     : _rspec(rspec),
 338       _is_lval(false),
 339       _target(target)
 340   {}
 341 
 342   AddressLiteral addr() {
 343     AddressLiteral ret = *this;
 344     ret._is_lval = true;
 345     return ret;
 346   }
 347 
 348 
 349  private:
 350 
 351   address target() { return _target; }
 352   bool is_lval() { return _is_lval; }
 353 
 354   relocInfo::relocType reloc() const { return _rspec.type(); }
 355   const RelocationHolder& rspec() const { return _rspec; }
 356 
 357   friend class Assembler;
 358   friend class MacroAssembler;
 359   friend class Address;
 360   friend class LIR_Assembler;
 361 };
 362 
 363 // Convience classes
 364 class RuntimeAddress: public AddressLiteral {
 365 
 366   public:
 367 
 368   RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
 369 
 370 };
 371 
 372 class OopAddress: public AddressLiteral {
 373 
 374   public:
 375 
 376   OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
 377 
 378 };
 379 
 380 class ExternalAddress: public AddressLiteral {
 381 
 382   public:
 383 
 384   ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
 385 
 386 };
 387 
 388 class InternalAddress: public AddressLiteral {
 389 
 390   public:
 391 
 392   InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
 393 
 394 };
 395 
 396 // x86 can do array addressing as a single operation since disp can be an absolute
 397 // address amd64 can't. We create a class that expresses the concept but does extra
 398 // magic on amd64 to get the final result
 399 
 400 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
 401   private:
 402 
 403   AddressLiteral _base;
 404   Address        _index;
 405 
 406   public:
 407 
 408   ArrayAddress() {};
 409   ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
 410   AddressLiteral base() { return _base; }
 411   Address index() { return _index; }
 412 
 413 };
 414 
 415 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
 416 
 417 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
 418 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
 419 // is what you get. The Assembler is generating code into a CodeBuffer.
 420 
 421 class Assembler : public AbstractAssembler  {
 422   friend class AbstractAssembler; // for the non-virtual hack
 423   friend class LIR_Assembler; // as_Address()
 424   friend class StubGenerator;
 425 
 426  public:
 427   enum Condition {                     // The x86 condition codes used for conditional jumps/moves.
 428     zero          = 0x4,
 429     notZero       = 0x5,
 430     equal         = 0x4,
 431     notEqual      = 0x5,
 432     less          = 0xc,
 433     lessEqual     = 0xe,
 434     greater       = 0xf,
 435     greaterEqual  = 0xd,
 436     below         = 0x2,
 437     belowEqual    = 0x6,
 438     above         = 0x7,
 439     aboveEqual    = 0x3,
 440     overflow      = 0x0,
 441     noOverflow    = 0x1,
 442     carrySet      = 0x2,
 443     carryClear    = 0x3,
 444     negative      = 0x8,
 445     positive      = 0x9,
 446     parity        = 0xa,
 447     noParity      = 0xb
 448   };
 449 
 450   enum Prefix {
 451     // segment overrides
 452     CS_segment = 0x2e,
 453     SS_segment = 0x36,
 454     DS_segment = 0x3e,
 455     ES_segment = 0x26,
 456     FS_segment = 0x64,
 457     GS_segment = 0x65,
 458 
 459     REX        = 0x40,
 460 
 461     REX_B      = 0x41,
 462     REX_X      = 0x42,
 463     REX_XB     = 0x43,
 464     REX_R      = 0x44,
 465     REX_RB     = 0x45,
 466     REX_RX     = 0x46,
 467     REX_RXB    = 0x47,
 468 
 469     REX_W      = 0x48,
 470 
 471     REX_WB     = 0x49,
 472     REX_WX     = 0x4A,
 473     REX_WXB    = 0x4B,
 474     REX_WR     = 0x4C,
 475     REX_WRB    = 0x4D,
 476     REX_WRX    = 0x4E,
 477     REX_WRXB   = 0x4F
 478   };
 479 
 480   enum WhichOperand {
 481     // input to locate_operand, and format code for relocations
 482     imm_operand  = 0,            // embedded 32-bit|64-bit immediate operand
 483     disp32_operand = 1,          // embedded 32-bit displacement or address
 484     call32_operand = 2,          // embedded 32-bit self-relative displacement
 485 #ifndef _LP64
 486     _WhichOperand_limit = 3
 487 #else
 488      narrow_oop_operand = 3,     // embedded 32-bit immediate narrow oop
 489     _WhichOperand_limit = 4
 490 #endif
 491   };
 492 
 493 
 494 
 495   // NOTE: The general philopsophy of the declarations here is that 64bit versions
 496   // of instructions are freely declared without the need for wrapping them an ifdef.
 497   // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
 498   // In the .cpp file the implementations are wrapped so that they are dropped out
 499   // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
 500   // to the size it was prior to merging up the 32bit and 64bit assemblers.
 501   //
 502   // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
 503   // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
 504 
 505 private:
 506 
 507 
 508   // 64bit prefixes
 509   int prefix_and_encode(int reg_enc, bool byteinst = false);
 510   int prefixq_and_encode(int reg_enc);
 511 
 512   int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
 513   int prefixq_and_encode(int dst_enc, int src_enc);
 514 
 515   void prefix(Register reg);
 516   void prefix(Address adr);
 517   void prefixq(Address adr);
 518 
 519   void prefix(Address adr, Register reg,  bool byteinst = false);
 520   void prefixq(Address adr, Register reg);
 521 
 522   void prefix(Address adr, XMMRegister reg);
 523 
 524   void prefetch_prefix(Address src);
 525 
 526   // Helper functions for groups of instructions
 527   void emit_arith_b(int op1, int op2, Register dst, int imm8);
 528 
 529   void emit_arith(int op1, int op2, Register dst, int32_t imm32);
 530   // only 32bit??
 531   void emit_arith(int op1, int op2, Register dst, jobject obj);
 532   void emit_arith(int op1, int op2, Register dst, Register src);
 533 
 534   void emit_operand(Register reg,
 535                     Register base, Register index, Address::ScaleFactor scale,
 536                     int disp,
 537                     RelocationHolder const& rspec,
 538                     int rip_relative_correction = 0);
 539 
 540   void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
 541 
 542   // operands that only take the original 32bit registers
 543   void emit_operand32(Register reg, Address adr);
 544 
 545   void emit_operand(XMMRegister reg,
 546                     Register base, Register index, Address::ScaleFactor scale,
 547                     int disp,
 548                     RelocationHolder const& rspec);
 549 
 550   void emit_operand(XMMRegister reg, Address adr);
 551 
 552   void emit_operand(MMXRegister reg, Address adr);
 553 
 554   // workaround gcc (3.2.1-7) bug
 555   void emit_operand(Address adr, MMXRegister reg);
 556 
 557 
 558   // Immediate-to-memory forms
 559   void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
 560 
 561   void emit_farith(int b1, int b2, int i);
 562 
 563 
 564  protected:
 565   #ifdef ASSERT
 566   void check_relocation(RelocationHolder const& rspec, int format);
 567   #endif
 568 
 569   inline void emit_long64(jlong x);
 570 
 571   void emit_data(jint data, relocInfo::relocType    rtype, int format);
 572   void emit_data(jint data, RelocationHolder const& rspec, int format);
 573   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
 574   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
 575 
 576 
 577   bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
 578 
 579   // These are all easily abused and hence protected
 580 
 581   // 32BIT ONLY SECTION
 582 #ifndef _LP64
 583   // Make these disappear in 64bit mode since they would never be correct
 584   void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);   // 32BIT ONLY
 585   void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 586 
 587   void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 588   void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);     // 32BIT ONLY
 589 
 590   void push_literal32(int32_t imm32, RelocationHolder const& rspec);                 // 32BIT ONLY
 591 #else
 592   // 64BIT ONLY SECTION
 593   void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);   // 64BIT ONLY
 594 
 595   void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
 596   void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
 597 
 598   void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
 599   void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
 600 #endif // _LP64
 601 
 602   // These are unique in that we are ensured by the caller that the 32bit
 603   // relative in these instructions will always be able to reach the potentially
 604   // 64bit address described by entry. Since they can take a 64bit address they
 605   // don't have the 32 suffix like the other instructions in this class.
 606 
 607   void call_literal(address entry, RelocationHolder const& rspec);
 608   void jmp_literal(address entry, RelocationHolder const& rspec);
 609 
 610   // Avoid using directly section
 611   // Instructions in this section are actually usable by anyone without danger
 612   // of failure but have performance issues that are addressed my enhanced
 613   // instructions which will do the proper thing base on the particular cpu.
 614   // We protect them because we don't trust you...
 615 
 616   // Don't use next inc() and dec() methods directly. INC & DEC instructions
 617   // could cause a partial flag stall since they don't set CF flag.
 618   // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
 619   // which call inc() & dec() or add() & sub() in accordance with
 620   // the product flag UseIncDec value.
 621 
 622   void decl(Register dst);
 623   void decl(Address dst);
 624   void decq(Register dst);
 625   void decq(Address dst);
 626 
 627   void incl(Register dst);
 628   void incl(Address dst);
 629   void incq(Register dst);
 630   void incq(Address dst);
 631 
 632   // New cpus require use of movsd and movss to avoid partial register stall
 633   // when loading from memory. But for old Opteron use movlpd instead of movsd.
 634   // The selection is done in MacroAssembler::movdbl() and movflt().
 635 
 636   // Move Scalar Single-Precision Floating-Point Values
 637   void movss(XMMRegister dst, Address src);
 638   void movss(XMMRegister dst, XMMRegister src);
 639   void movss(Address dst, XMMRegister src);
 640 
 641   // Move Scalar Double-Precision Floating-Point Values
 642   void movsd(XMMRegister dst, Address src);
 643   void movsd(XMMRegister dst, XMMRegister src);
 644   void movsd(Address dst, XMMRegister src);
 645   void movlpd(XMMRegister dst, Address src);
 646 
 647   // New cpus require use of movaps and movapd to avoid partial register stall
 648   // when moving between registers.
 649   void movaps(XMMRegister dst, XMMRegister src);
 650   void movapd(XMMRegister dst, XMMRegister src);
 651 
 652   // End avoid using directly
 653 
 654 
 655   // Instruction prefixes
 656   void prefix(Prefix p);
 657 
 658   public:
 659 
 660   // Creation
 661   Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
 662 
 663   // Decoding
 664   static address locate_operand(address inst, WhichOperand which);
 665   static address locate_next_instruction(address inst);
 666 
 667   // Utilities
 668 
 669 #ifdef _LP64
 670  static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) )  <= x   &&   x  <  ( CONST64(1) << (nbits-1) ); }
 671  static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; }
 672 #else
 673  static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) )  <= x   &&   x  <  ( 1 << (nbits-1) ); }
 674  static bool is_simm32(int32_t x) { return true; }
 675 #endif // LP64
 676 
 677   // Generic instructions
 678   // Does 32bit or 64bit as needed for the platform. In some sense these
 679   // belong in macro assembler but there is no need for both varieties to exist
 680 
 681   void lea(Register dst, Address src);
 682 
 683   void mov(Register dst, Register src);
 684 
 685   void pusha();
 686   void popa();
 687 
 688   void pushf();
 689   void popf();
 690 
 691   void push(int32_t imm32);
 692 
 693   void push(Register src);
 694 
 695   void pop(Register dst);
 696 
 697   // These are dummies to prevent surprise implicit conversions to Register
 698   void push(void* v);
 699   void pop(void* v);
 700 
 701 
 702   // These do register sized moves/scans
 703   void rep_mov();
 704   void rep_set();
 705   void repne_scan();
 706 #ifdef _LP64
 707   void repne_scanl();
 708 #endif
 709 
 710   // Vanilla instructions in lexical order
 711 
 712   void adcl(Register dst, int32_t imm32);
 713   void adcl(Register dst, Address src);
 714   void adcl(Register dst, Register src);
 715 
 716   void adcq(Register dst, int32_t imm32);
 717   void adcq(Register dst, Address src);
 718   void adcq(Register dst, Register src);
 719 
 720 
 721   void addl(Address dst, int32_t imm32);
 722   void addl(Address dst, Register src);
 723   void addl(Register dst, int32_t imm32);
 724   void addl(Register dst, Address src);
 725   void addl(Register dst, Register src);
 726 
 727   void addq(Address dst, int32_t imm32);
 728   void addq(Address dst, Register src);
 729   void addq(Register dst, int32_t imm32);
 730   void addq(Register dst, Address src);
 731   void addq(Register dst, Register src);
 732 
 733 
 734   void addr_nop_4();
 735   void addr_nop_5();
 736   void addr_nop_7();
 737   void addr_nop_8();
 738 
 739   // Add Scalar Double-Precision Floating-Point Values
 740   void addsd(XMMRegister dst, Address src);
 741   void addsd(XMMRegister dst, XMMRegister src);
 742 
 743   // Add Scalar Single-Precision Floating-Point Values
 744   void addss(XMMRegister dst, Address src);
 745   void addss(XMMRegister dst, XMMRegister src);
 746 
 747   void andl(Register dst, int32_t imm32);
 748   void andl(Register dst, Address src);
 749   void andl(Register dst, Register src);
 750 
 751   void andq(Register dst, int32_t imm32);
 752   void andq(Register dst, Address src);
 753   void andq(Register dst, Register src);
 754 
 755 
 756   // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
 757   void andpd(XMMRegister dst, Address src);
 758   void andpd(XMMRegister dst, XMMRegister src);
 759 
 760   void bsfl(Register dst, Register src);
 761   void bsrl(Register dst, Register src);
 762 
 763 #ifdef _LP64
 764   void bsfq(Register dst, Register src);
 765   void bsrq(Register dst, Register src);
 766 #endif
 767 
 768   void bswapl(Register reg);
 769 
 770   void bswapq(Register reg);
 771 
 772   void call(Label& L, relocInfo::relocType rtype);
 773   void call(Register reg);  // push pc; pc <- reg
 774   void call(Address adr);   // push pc; pc <- adr
 775 
 776   void cdql();
 777 
 778   void cdqq();
 779 
 780   void cld() { emit_byte(0xfc); }
 781 
 782   void clflush(Address adr);
 783 
 784   void cmovl(Condition cc, Register dst, Register src);
 785   void cmovl(Condition cc, Register dst, Address src);
 786 
 787   void cmovq(Condition cc, Register dst, Register src);
 788   void cmovq(Condition cc, Register dst, Address src);
 789 
 790 
 791   void cmpb(Address dst, int imm8);
 792 
 793   void cmpl(Address dst, int32_t imm32);
 794 
 795   void cmpl(Register dst, int32_t imm32);
 796   void cmpl(Register dst, Register src);
 797   void cmpl(Register dst, Address src);
 798 
 799   void cmpq(Address dst, int32_t imm32);
 800   void cmpq(Address dst, Register src);
 801 
 802   void cmpq(Register dst, int32_t imm32);
 803   void cmpq(Register dst, Register src);
 804   void cmpq(Register dst, Address src);
 805 
 806   // these are dummies used to catch attempting to convert NULL to Register
 807   void cmpl(Register dst, void* junk); // dummy
 808   void cmpq(Register dst, void* junk); // dummy
 809 
 810   void cmpw(Address dst, int imm16);
 811 
 812   void cmpxchg8 (Address adr);
 813 
 814   void cmpxchgl(Register reg, Address adr);
 815 
 816   void cmpxchgq(Register reg, Address adr);
 817 
 818   // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
 819   void comisd(XMMRegister dst, Address src);
 820 
 821   // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
 822   void comiss(XMMRegister dst, Address src);
 823 
 824   // Identify processor type and features
 825   void cpuid() {
 826     emit_byte(0x0F);
 827     emit_byte(0xA2);
 828   }
 829 
 830   // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
 831   void cvtsd2ss(XMMRegister dst, XMMRegister src);
 832 
 833   // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
 834   void cvtsi2sdl(XMMRegister dst, Register src);
 835   void cvtsi2sdq(XMMRegister dst, Register src);
 836 
 837   // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
 838   void cvtsi2ssl(XMMRegister dst, Register src);
 839   void cvtsi2ssq(XMMRegister dst, Register src);
 840 
 841   // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
 842   void cvtdq2pd(XMMRegister dst, XMMRegister src);
 843 
 844   // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
 845   void cvtdq2ps(XMMRegister dst, XMMRegister src);
 846 
 847   // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
 848   void cvtss2sd(XMMRegister dst, XMMRegister src);
 849 
 850   // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
 851   void cvttsd2sil(Register dst, Address src);
 852   void cvttsd2sil(Register dst, XMMRegister src);
 853   void cvttsd2siq(Register dst, XMMRegister src);
 854 
 855   // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
 856   void cvttss2sil(Register dst, XMMRegister src);
 857   void cvttss2siq(Register dst, XMMRegister src);
 858 
 859   // Divide Scalar Double-Precision Floating-Point Values
 860   void divsd(XMMRegister dst, Address src);
 861   void divsd(XMMRegister dst, XMMRegister src);
 862 
 863   // Divide Scalar Single-Precision Floating-Point Values
 864   void divss(XMMRegister dst, Address src);
 865   void divss(XMMRegister dst, XMMRegister src);
 866 
 867   void emms();
 868 
 869   void fabs();
 870 
 871   void fadd(int i);
 872 
 873   void fadd_d(Address src);
 874   void fadd_s(Address src);
 875 
 876   // "Alternate" versions of x87 instructions place result down in FPU
 877   // stack instead of on TOS
 878 
 879   void fadda(int i); // "alternate" fadd
 880   void faddp(int i = 1);
 881 
 882   void fchs();
 883 
 884   void fcom(int i);
 885 
 886   void fcomp(int i = 1);
 887   void fcomp_d(Address src);
 888   void fcomp_s(Address src);
 889 
 890   void fcompp();
 891 
 892   void fcos();
 893 
 894   void fdecstp();
 895 
 896   void fdiv(int i);
 897   void fdiv_d(Address src);
 898   void fdivr_s(Address src);
 899   void fdiva(int i);  // "alternate" fdiv
 900   void fdivp(int i = 1);
 901 
 902   void fdivr(int i);
 903   void fdivr_d(Address src);
 904   void fdiv_s(Address src);
 905 
 906   void fdivra(int i); // "alternate" reversed fdiv
 907 
 908   void fdivrp(int i = 1);
 909 
 910   void ffree(int i = 0);
 911 
 912   void fild_d(Address adr);
 913   void fild_s(Address adr);
 914 
 915   void fincstp();
 916 
 917   void finit();
 918 
 919   void fist_s (Address adr);
 920   void fistp_d(Address adr);
 921   void fistp_s(Address adr);
 922 
 923   void fld1();
 924 
 925   void fld_d(Address adr);
 926   void fld_s(Address adr);
 927   void fld_s(int index);
 928   void fld_x(Address adr);  // extended-precision (80-bit) format
 929 
 930   void fldcw(Address src);
 931 
 932   void fldenv(Address src);
 933 
 934   void fldlg2();
 935 
 936   void fldln2();
 937 
 938   void fldz();
 939 
 940   void flog();
 941   void flog10();
 942 
 943   void fmul(int i);
 944 
 945   void fmul_d(Address src);
 946   void fmul_s(Address src);
 947 
 948   void fmula(int i);  // "alternate" fmul
 949 
 950   void fmulp(int i = 1);
 951 
 952   void fnsave(Address dst);
 953 
 954   void fnstcw(Address src);
 955 
 956   void fnstsw_ax();
 957 
 958   void fprem();
 959   void fprem1();
 960 
 961   void frstor(Address src);
 962 
 963   void fsin();
 964 
 965   void fsqrt();
 966 
 967   void fst_d(Address adr);
 968   void fst_s(Address adr);
 969 
 970   void fstp_d(Address adr);
 971   void fstp_d(int index);
 972   void fstp_s(Address adr);
 973   void fstp_x(Address adr); // extended-precision (80-bit) format
 974 
 975   void fsub(int i);
 976   void fsub_d(Address src);
 977   void fsub_s(Address src);
 978 
 979   void fsuba(int i);  // "alternate" fsub
 980 
 981   void fsubp(int i = 1);
 982 
 983   void fsubr(int i);
 984   void fsubr_d(Address src);
 985   void fsubr_s(Address src);
 986 
 987   void fsubra(int i); // "alternate" reversed fsub
 988 
 989   void fsubrp(int i = 1);
 990 
 991   void ftan();
 992 
 993   void ftst();
 994 
 995   void fucomi(int i = 1);
 996   void fucomip(int i = 1);
 997 
 998   void fwait();
 999 
1000   void fxch(int i = 1);
1001 
1002   void fxrstor(Address src);
1003 
1004   void fxsave(Address dst);
1005 
1006   void fyl2x();
1007 
1008   void hlt();
1009 
1010   void idivl(Register src);
1011 
1012   void idivq(Register src);
1013 
1014   void imull(Register dst, Register src);
1015   void imull(Register dst, Register src, int value);
1016 
1017   void imulq(Register dst, Register src);
1018   void imulq(Register dst, Register src, int value);
1019 
1020 
1021   // jcc is the generic conditional branch generator to run-
1022   // time routines, jcc is used for branches to labels. jcc
1023   // takes a branch opcode (cc) and a label (L) and generates
1024   // either a backward branch or a forward branch and links it
1025   // to the label fixup chain. Usage:
1026   //
1027   // Label L;      // unbound label
1028   // jcc(cc, L);   // forward branch to unbound label
1029   // bind(L);      // bind label to the current pc
1030   // jcc(cc, L);   // backward branch to bound label
1031   // bind(L);      // illegal: a label may be bound only once
1032   //
1033   // Note: The same Label can be used for forward and backward branches
1034   // but it may be bound only once.
1035 
1036   void jcc(Condition cc, Label& L,
1037            relocInfo::relocType rtype = relocInfo::none);
1038 
1039   // Conditional jump to a 8-bit offset to L.
1040   // WARNING: be very careful using this for forward jumps.  If the label is
1041   // not bound within an 8-bit offset of this instruction, a run-time error
1042   // will occur.
1043   void jccb(Condition cc, Label& L);
1044 
1045   void jmp(Address entry);    // pc <- entry
1046 
1047   // Label operations & relative jumps (PPUM Appendix D)
1048   void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none);   // unconditional jump to L
1049 
1050   void jmp(Register entry); // pc <- entry
1051 
1052   // Unconditional 8-bit offset jump to L.
1053   // WARNING: be very careful using this for forward jumps.  If the label is
1054   // not bound within an 8-bit offset of this instruction, a run-time error
1055   // will occur.
1056   void jmpb(Label& L);
1057 
1058   void ldmxcsr( Address src );
1059 
1060   void leal(Register dst, Address src);
1061 
1062   void leaq(Register dst, Address src);
1063 
1064   void lfence() {
1065     emit_byte(0x0F);
1066     emit_byte(0xAE);
1067     emit_byte(0xE8);
1068   }
1069 
1070   void lock();
1071 
1072   void lzcntl(Register dst, Register src);
1073 
1074 #ifdef _LP64
1075   void lzcntq(Register dst, Register src);
1076 #endif
1077 
1078   enum Membar_mask_bits {
1079     StoreStore = 1 << 3,
1080     LoadStore  = 1 << 2,
1081     StoreLoad  = 1 << 1,
1082     LoadLoad   = 1 << 0
1083   };
1084 
1085   // Serializes memory and blows flags
1086   void membar(Membar_mask_bits order_constraint) {
1087     if (os::is_MP()) {
1088       // We only have to handle StoreLoad
1089       if (order_constraint & StoreLoad) {
1090         // All usable chips support "locked" instructions which suffice
1091         // as barriers, and are much faster than the alternative of
1092         // using cpuid instruction. We use here a locked add [esp],0.
1093         // This is conveniently otherwise a no-op except for blowing
1094         // flags.
1095         // Any change to this code may need to revisit other places in
1096         // the code where this idiom is used, in particular the
1097         // orderAccess code.
1098         lock();
1099         addl(Address(rsp, 0), 0);// Assert the lock# signal here
1100       }
1101     }
1102   }
1103 
1104   void mfence();
1105 
1106   // Moves
1107 
1108   void mov64(Register dst, int64_t imm64);
1109 
1110   void movb(Address dst, Register src);
1111   void movb(Address dst, int imm8);
1112   void movb(Register dst, Address src);
1113 
1114   void movdl(XMMRegister dst, Register src);
1115   void movdl(Register dst, XMMRegister src);
1116 
1117   // Move Double Quadword
1118   void movdq(XMMRegister dst, Register src);
1119   void movdq(Register dst, XMMRegister src);
1120 
1121   // Move Aligned Double Quadword
1122   void movdqa(Address     dst, XMMRegister src);
1123   void movdqa(XMMRegister dst, Address src);
1124   void movdqa(XMMRegister dst, XMMRegister src);
1125 
1126   // Move Unaligned Double Quadword
1127   void movdqu(Address     dst, XMMRegister src);
1128   void movdqu(XMMRegister dst, Address src);
1129   void movdqu(XMMRegister dst, XMMRegister src);
1130 
1131   void movl(Register dst, int32_t imm32);
1132   void movl(Address dst, int32_t imm32);
1133   void movl(Register dst, Register src);
1134   void movl(Register dst, Address src);
1135   void movl(Address dst, Register src);
1136 
1137   // These dummies prevent using movl from converting a zero (like NULL) into Register
1138   // by giving the compiler two choices it can't resolve
1139 
1140   void movl(Address  dst, void* junk);
1141   void movl(Register dst, void* junk);
1142 
1143 #ifdef _LP64
1144   void movq(Register dst, Register src);
1145   void movq(Register dst, Address src);
1146   void movq(Address dst, Register src);
1147 #endif
1148 
1149   void movq(Address     dst, MMXRegister src );
1150   void movq(MMXRegister dst, Address src );
1151 
1152 #ifdef _LP64
1153   // These dummies prevent using movq from converting a zero (like NULL) into Register
1154   // by giving the compiler two choices it can't resolve
1155 
1156   void movq(Address  dst, void* dummy);
1157   void movq(Register dst, void* dummy);
1158 #endif
1159 
1160   // Move Quadword
1161   void movq(Address     dst, XMMRegister src);
1162   void movq(XMMRegister dst, Address src);
1163 
1164   void movsbl(Register dst, Address src);
1165   void movsbl(Register dst, Register src);
1166 
1167 #ifdef _LP64
1168   void movsbq(Register dst, Address src);
1169   void movsbq(Register dst, Register src);
1170 
1171   // Move signed 32bit immediate to 64bit extending sign
1172   void movslq(Address dst, int32_t imm64);
1173   void movslq(Register dst, int32_t imm64);
1174 
1175   void movslq(Register dst, Address src);
1176   void movslq(Register dst, Register src);
1177   void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1178 #endif
1179 
1180   void movswl(Register dst, Address src);
1181   void movswl(Register dst, Register src);
1182 
1183 #ifdef _LP64
1184   void movswq(Register dst, Address src);
1185   void movswq(Register dst, Register src);
1186 #endif
1187 
1188   void movw(Address dst, int imm16);
1189   void movw(Register dst, Address src);
1190   void movw(Address dst, Register src);
1191 
1192   void movzbl(Register dst, Address src);
1193   void movzbl(Register dst, Register src);
1194 
1195 #ifdef _LP64
1196   void movzbq(Register dst, Address src);
1197   void movzbq(Register dst, Register src);
1198 #endif
1199 
1200   void movzwl(Register dst, Address src);
1201   void movzwl(Register dst, Register src);
1202 
1203 #ifdef _LP64
1204   void movzwq(Register dst, Address src);
1205   void movzwq(Register dst, Register src);
1206 #endif
1207 
1208   void mull(Address src);
1209   void mull(Register src);
1210 
1211   // Multiply Scalar Double-Precision Floating-Point Values
1212   void mulsd(XMMRegister dst, Address src);
1213   void mulsd(XMMRegister dst, XMMRegister src);
1214 
1215   // Multiply Scalar Single-Precision Floating-Point Values
1216   void mulss(XMMRegister dst, Address src);
1217   void mulss(XMMRegister dst, XMMRegister src);
1218 
1219   void negl(Register dst);
1220 
1221 #ifdef _LP64
1222   void negq(Register dst);
1223 #endif
1224 
1225   void nop(int i = 1);
1226 
1227   void notl(Register dst);
1228 
1229 #ifdef _LP64
1230   void notq(Register dst);
1231 #endif
1232 
1233   void orl(Address dst, int32_t imm32);
1234   void orl(Register dst, int32_t imm32);
1235   void orl(Register dst, Address src);
1236   void orl(Register dst, Register src);
1237 
1238   void orq(Address dst, int32_t imm32);
1239   void orq(Register dst, int32_t imm32);
1240   void orq(Register dst, Address src);
1241   void orq(Register dst, Register src);
1242 
1243   // SSE4.2 string instructions
1244   void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1245   void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1246 
1247   void popl(Address dst);
1248 
1249 #ifdef _LP64
1250   void popq(Address dst);
1251 #endif
1252 
1253   void popcntl(Register dst, Address src);
1254   void popcntl(Register dst, Register src);
1255 
1256 #ifdef _LP64
1257   void popcntq(Register dst, Address src);
1258   void popcntq(Register dst, Register src);
1259 #endif
1260 
1261   // Prefetches (SSE, SSE2, 3DNOW only)
1262 
1263   void prefetchnta(Address src);
1264   void prefetchr(Address src);
1265   void prefetcht0(Address src);
1266   void prefetcht1(Address src);
1267   void prefetcht2(Address src);
1268   void prefetchw(Address src);
1269 
1270   // Shuffle Packed Doublewords
1271   void pshufd(XMMRegister dst, XMMRegister src, int mode);
1272   void pshufd(XMMRegister dst, Address src,     int mode);
1273 
1274   // Shuffle Packed Low Words
1275   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1276   void pshuflw(XMMRegister dst, Address src,     int mode);
1277 
1278   // Shift Right Logical Quadword Immediate
1279   void psrlq(XMMRegister dst, int shift);
1280 
1281   // Logical Compare Double Quadword
1282   void ptest(XMMRegister dst, XMMRegister src);
1283   void ptest(XMMRegister dst, Address src);
1284 
1285   // Interleave Low Bytes
1286   void punpcklbw(XMMRegister dst, XMMRegister src);
1287 
1288   void pushl(Address src);
1289 
1290   void pushq(Address src);
1291 
1292   // Xor Packed Byte Integer Values
1293   void pxor(XMMRegister dst, Address src);
1294   void pxor(XMMRegister dst, XMMRegister src);
1295 
1296   void rcll(Register dst, int imm8);
1297 
1298   void rclq(Register dst, int imm8);
1299 
1300   void ret(int imm16);
1301 
1302   void sahf();
1303 
1304   void sarl(Register dst, int imm8);
1305   void sarl(Register dst);
1306 
1307   void sarq(Register dst, int imm8);
1308   void sarq(Register dst);
1309 
1310   void sbbl(Address dst, int32_t imm32);
1311   void sbbl(Register dst, int32_t imm32);
1312   void sbbl(Register dst, Address src);
1313   void sbbl(Register dst, Register src);
1314 
1315   void sbbq(Address dst, int32_t imm32);
1316   void sbbq(Register dst, int32_t imm32);
1317   void sbbq(Register dst, Address src);
1318   void sbbq(Register dst, Register src);
1319 
1320   void setb(Condition cc, Register dst);
1321 
1322   void shldl(Register dst, Register src);
1323 
1324   void shll(Register dst, int imm8);
1325   void shll(Register dst);
1326 
1327   void shlq(Register dst, int imm8);
1328   void shlq(Register dst);
1329 
1330   void shrdl(Register dst, Register src);
1331 
1332   void shrl(Register dst, int imm8);
1333   void shrl(Register dst);
1334 
1335   void shrq(Register dst, int imm8);
1336   void shrq(Register dst);
1337 
1338   void smovl(); // QQQ generic?
1339 
1340   // Compute Square Root of Scalar Double-Precision Floating-Point Value
1341   void sqrtsd(XMMRegister dst, Address src);
1342   void sqrtsd(XMMRegister dst, XMMRegister src);
1343 
1344   void std() { emit_byte(0xfd); }
1345 
1346   void stmxcsr( Address dst );
1347 
1348   void subl(Address dst, int32_t imm32);
1349   void subl(Address dst, Register src);
1350   void subl(Register dst, int32_t imm32);
1351   void subl(Register dst, Address src);
1352   void subl(Register dst, Register src);
1353 
1354   void subq(Address dst, int32_t imm32);
1355   void subq(Address dst, Register src);
1356   void subq(Register dst, int32_t imm32);
1357   void subq(Register dst, Address src);
1358   void subq(Register dst, Register src);
1359 
1360 
1361   // Subtract Scalar Double-Precision Floating-Point Values
1362   void subsd(XMMRegister dst, Address src);
1363   void subsd(XMMRegister dst, XMMRegister src);
1364 
1365   // Subtract Scalar Single-Precision Floating-Point Values
1366   void subss(XMMRegister dst, Address src);
1367   void subss(XMMRegister dst, XMMRegister src);
1368 
1369   void testb(Register dst, int imm8);
1370 
1371   void testl(Register dst, int32_t imm32);
1372   void testl(Register dst, Register src);
1373   void testl(Register dst, Address src);
1374 
1375   void testq(Register dst, int32_t imm32);
1376   void testq(Register dst, Register src);
1377 
1378 
1379   // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1380   void ucomisd(XMMRegister dst, Address src);
1381   void ucomisd(XMMRegister dst, XMMRegister src);
1382 
1383   // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1384   void ucomiss(XMMRegister dst, Address src);
1385   void ucomiss(XMMRegister dst, XMMRegister src);
1386 
1387   void xaddl(Address dst, Register src);
1388 
1389   void xaddq(Address dst, Register src);
1390 
1391   void xchgl(Register reg, Address adr);
1392   void xchgl(Register dst, Register src);
1393 
1394   void xchgq(Register reg, Address adr);
1395   void xchgq(Register dst, Register src);
1396 
1397   void xorl(Register dst, int32_t imm32);
1398   void xorl(Register dst, Address src);
1399   void xorl(Register dst, Register src);
1400 
1401   void xorq(Register dst, Address src);
1402   void xorq(Register dst, Register src);
1403 
1404   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1405   void xorpd(XMMRegister dst, Address src);
1406   void xorpd(XMMRegister dst, XMMRegister src);
1407 
1408   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1409   void xorps(XMMRegister dst, Address src);
1410   void xorps(XMMRegister dst, XMMRegister src);
1411 
1412   void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1413 };
1414 
1415 
1416 // MacroAssembler extends Assembler by frequently used macros.
1417 //
1418 // Instructions for which a 'better' code sequence exists depending
1419 // on arguments should also go in here.
1420 
1421 class MacroAssembler: public Assembler {
1422   friend class LIR_Assembler;
1423   friend class Runtime1;      // as_Address()
1424  protected:
1425 
1426   Address as_Address(AddressLiteral adr);
1427   Address as_Address(ArrayAddress adr);
1428 
1429   // Support for VM calls
1430   //
1431   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1432   // may customize this version by overriding it for its purposes (e.g., to save/restore
1433   // additional registers when doing a VM call).
1434 #ifdef CC_INTERP
1435   // c++ interpreter never wants to use interp_masm version of call_VM
1436   #define VIRTUAL
1437 #else
1438   #define VIRTUAL virtual
1439 #endif
1440 
1441   VIRTUAL void call_VM_leaf_base(
1442     address entry_point,               // the entry point
1443     int     number_of_arguments        // the number of arguments to pop after the call
1444   );
1445 
1446   // This is the base routine called by the different versions of call_VM. The interpreter
1447   // may customize this version by overriding it for its purposes (e.g., to save/restore
1448   // additional registers when doing a VM call).
1449   //
1450   // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1451   // returns the register which contains the thread upon return. If a thread register has been
1452   // specified, the return value will correspond to that register. If no last_java_sp is specified
1453   // (noreg) than rsp will be used instead.
1454   VIRTUAL void call_VM_base(           // returns the register containing the thread upon return
1455     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
1456     Register java_thread,              // the thread if computed before     ; use noreg otherwise
1457     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
1458     address  entry_point,              // the entry point
1459     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
1460     bool     check_exceptions          // whether to check for pending exceptions after return
1461   );
1462 
1463   // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1464   // The implementation is only non-empty for the InterpreterMacroAssembler,
1465   // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1466   virtual void check_and_handle_popframe(Register java_thread);
1467   virtual void check_and_handle_earlyret(Register java_thread);
1468 
1469   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1470 
1471   // helpers for FPU flag access
1472   // tmp is a temporary register, if none is available use noreg
1473   void save_rax   (Register tmp);
1474   void restore_rax(Register tmp);
1475 
1476  public:
1477   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1478 
1479   // Support for NULL-checks
1480   //
1481   // Generates code that causes a NULL OS exception if the content of reg is NULL.
1482   // If the accessed location is M[reg + offset] and the offset is known, provide the
1483   // offset. No explicit code generation is needed if the offset is within a certain
1484   // range (0 <= offset <= page_size).
1485 
1486   void null_check(Register reg, int offset = -1);
1487   static bool needs_explicit_null_check(intptr_t offset);
1488 
1489   // Required platform-specific helpers for Label::patch_instructions.
1490   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1491   void pd_patch_instruction(address branch, address target);
1492 #ifndef PRODUCT
1493   static void pd_print_patched_instruction(address branch);
1494 #endif
1495 
1496   // The following 4 methods return the offset of the appropriate move instruction
1497 
1498   // Support for fast byte/short loading with zero extension (depending on particular CPU)
1499   int load_unsigned_byte(Register dst, Address src);
1500   int load_unsigned_short(Register dst, Address src);
1501 
1502   // Support for fast byte/short loading with sign extension (depending on particular CPU)
1503   int load_signed_byte(Register dst, Address src);
1504   int load_signed_short(Register dst, Address src);
1505 
1506   // Support for sign-extension (hi:lo = extend_sign(lo))
1507   void extend_sign(Register hi, Register lo);
1508 
1509   // Loading values by size and signed-ness
1510   void load_sized_value(Register dst, Address src, int size_in_bytes, bool is_signed);
1511 
1512   // Support for inc/dec with optimal instruction selection depending on value
1513 
1514   void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1515   void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1516 
1517   void decrementl(Address dst, int value = 1);
1518   void decrementl(Register reg, int value = 1);
1519 
1520   void decrementq(Register reg, int value = 1);
1521   void decrementq(Address dst, int value = 1);
1522 
1523   void incrementl(Address dst, int value = 1);
1524   void incrementl(Register reg, int value = 1);
1525 
1526   void incrementq(Register reg, int value = 1);
1527   void incrementq(Address dst, int value = 1);
1528 
1529 
1530   // Support optimal SSE move instructions.
1531   void movflt(XMMRegister dst, XMMRegister src) {
1532     if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1533     else                       { movss (dst, src); return; }
1534   }
1535   void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1536   void movflt(XMMRegister dst, AddressLiteral src);
1537   void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1538 
1539   void movdbl(XMMRegister dst, XMMRegister src) {
1540     if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1541     else                       { movsd (dst, src); return; }
1542   }
1543 
1544   void movdbl(XMMRegister dst, AddressLiteral src);
1545 
1546   void movdbl(XMMRegister dst, Address src) {
1547     if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1548     else                         { movlpd(dst, src); return; }
1549   }
1550   void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1551 
1552   void incrementl(AddressLiteral dst);
1553   void incrementl(ArrayAddress dst);
1554 
1555   // Alignment
1556   void align(int modulus);
1557 
1558   // Misc
1559   void fat_nop(); // 5 byte nop
1560 
1561   // Stack frame creation/removal
1562   void enter();
1563   void leave();
1564 
1565   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1566   // The pointer will be loaded into the thread register.
1567   void get_thread(Register thread);
1568 
1569 
1570   // Support for VM calls
1571   //
1572   // It is imperative that all calls into the VM are handled via the call_VM macros.
1573   // They make sure that the stack linkage is setup correctly. call_VM's correspond
1574   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1575 
1576 
1577   void call_VM(Register oop_result,
1578                address entry_point,
1579                bool check_exceptions = true);
1580   void call_VM(Register oop_result,
1581                address entry_point,
1582                Register arg_1,
1583                bool check_exceptions = true);
1584   void call_VM(Register oop_result,
1585                address entry_point,
1586                Register arg_1, Register arg_2,
1587                bool check_exceptions = true);
1588   void call_VM(Register oop_result,
1589                address entry_point,
1590                Register arg_1, Register arg_2, Register arg_3,
1591                bool check_exceptions = true);
1592 
1593   // Overloadings with last_Java_sp
1594   void call_VM(Register oop_result,
1595                Register last_java_sp,
1596                address entry_point,
1597                int number_of_arguments = 0,
1598                bool check_exceptions = true);
1599   void call_VM(Register oop_result,
1600                Register last_java_sp,
1601                address entry_point,
1602                Register arg_1, bool
1603                check_exceptions = true);
1604   void call_VM(Register oop_result,
1605                Register last_java_sp,
1606                address entry_point,
1607                Register arg_1, Register arg_2,
1608                bool check_exceptions = true);
1609   void call_VM(Register oop_result,
1610                Register last_java_sp,
1611                address entry_point,
1612                Register arg_1, Register arg_2, Register arg_3,
1613                bool check_exceptions = true);
1614 
1615   void call_VM_leaf(address entry_point,
1616                     int number_of_arguments = 0);
1617   void call_VM_leaf(address entry_point,
1618                     Register arg_1);
1619   void call_VM_leaf(address entry_point,
1620                     Register arg_1, Register arg_2);
1621   void call_VM_leaf(address entry_point,
1622                     Register arg_1, Register arg_2, Register arg_3);
1623 
1624   // last Java Frame (fills frame anchor)
1625   void set_last_Java_frame(Register thread,
1626                            Register last_java_sp,
1627                            Register last_java_fp,
1628                            address last_java_pc);
1629 
1630   // thread in the default location (r15_thread on 64bit)
1631   void set_last_Java_frame(Register last_java_sp,
1632                            Register last_java_fp,
1633                            address last_java_pc);
1634 
1635   void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1636 
1637   // thread in the default location (r15_thread on 64bit)
1638   void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1639 
1640   // Stores
1641   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
1642   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
1643 
1644   void g1_write_barrier_pre(Register obj,
1645 #ifndef _LP64
1646                             Register thread,
1647 #endif
1648                             Register tmp,
1649                             Register tmp2,
1650                             bool     tosca_live);
1651   void g1_write_barrier_post(Register store_addr,
1652                              Register new_val,
1653 #ifndef _LP64
1654                              Register thread,
1655 #endif
1656                              Register tmp,
1657                              Register tmp2);
1658 
1659 
1660   // split store_check(Register obj) to enhance instruction interleaving
1661   void store_check_part_1(Register obj);
1662   void store_check_part_2(Register obj);
1663 
1664   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1665   void c2bool(Register x);
1666 
1667   // C++ bool manipulation
1668 
1669   void movbool(Register dst, Address src);
1670   void movbool(Address dst, bool boolconst);
1671   void movbool(Address dst, Register src);
1672   void testbool(Register dst);
1673 
1674   // oop manipulations
1675   void load_klass(Register dst, Register src);
1676   void store_klass(Register dst, Register src);
1677 
1678   void load_prototype_header(Register dst, Register src);
1679 
1680 #ifdef _LP64
1681   void store_klass_gap(Register dst, Register src);
1682 
1683   void load_heap_oop(Register dst, Address src);
1684   void store_heap_oop(Address dst, Register src);
1685 
1686   // This dummy is to prevent a call to store_heap_oop from
1687   // converting a zero (like NULL) into a Register by giving
1688   // the compiler two choices it can't resolve
1689 
1690   void store_heap_oop(Address dst, void* dummy);
1691 
1692   // Used for storing NULL. All other oop constants should be
1693   // stored using routines that take a jobject.
1694   void store_heap_oop_null(Address dst);
1695 
1696   void encode_heap_oop(Register r);
1697   void decode_heap_oop(Register r);
1698   void encode_heap_oop_not_null(Register r);
1699   void decode_heap_oop_not_null(Register r);
1700   void encode_heap_oop_not_null(Register dst, Register src);
1701   void decode_heap_oop_not_null(Register dst, Register src);
1702 
1703   void set_narrow_oop(Register dst, jobject obj);
1704   void set_narrow_oop(Address dst, jobject obj);
1705   void cmp_narrow_oop(Register dst, jobject obj);
1706   void cmp_narrow_oop(Address dst, jobject obj);
1707 
1708   // if heap base register is used - reinit it with the correct value
1709   void reinit_heapbase();
1710 #endif // _LP64
1711 
1712   // Int division/remainder for Java
1713   // (as idivl, but checks for special case as described in JVM spec.)
1714   // returns idivl instruction offset for implicit exception handling
1715   int corrected_idivl(Register reg);
1716 
1717   // Long division/remainder for Java
1718   // (as idivq, but checks for special case as described in JVM spec.)
1719   // returns idivq instruction offset for implicit exception handling
1720   int corrected_idivq(Register reg);
1721 
1722   void int3();
1723 
1724   // Long operation macros for a 32bit cpu
1725   // Long negation for Java
1726   void lneg(Register hi, Register lo);
1727 
1728   // Long multiplication for Java
1729   // (destroys contents of eax, ebx, ecx and edx)
1730   void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
1731 
1732   // Long shifts for Java
1733   // (semantics as described in JVM spec.)
1734   void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
1735   void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
1736 
1737   // Long compare for Java
1738   // (semantics as described in JVM spec.)
1739   void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
1740 
1741 
1742   // misc
1743 
1744   // Sign extension
1745   void sign_extend_short(Register reg);
1746   void sign_extend_byte(Register reg);
1747 
1748   // Division by power of 2, rounding towards 0
1749   void division_with_shift(Register reg, int shift_value);
1750 
1751   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
1752   //
1753   // CF (corresponds to C0) if x < y
1754   // PF (corresponds to C2) if unordered
1755   // ZF (corresponds to C3) if x = y
1756   //
1757   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1758   // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
1759   void fcmp(Register tmp);
1760   // Variant of the above which allows y to be further down the stack
1761   // and which only pops x and y if specified. If pop_right is
1762   // specified then pop_left must also be specified.
1763   void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
1764 
1765   // Floating-point comparison for Java
1766   // Compares the top-most stack entries on the FPU stack and stores the result in dst.
1767   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1768   // (semantics as described in JVM spec.)
1769   void fcmp2int(Register dst, bool unordered_is_less);
1770   // Variant of the above which allows y to be further down the stack
1771   // and which only pops x and y if specified. If pop_right is
1772   // specified then pop_left must also be specified.
1773   void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
1774 
1775   // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
1776   // tmp is a temporary register, if none is available use noreg
1777   void fremr(Register tmp);
1778 
1779 
1780   // same as fcmp2int, but using SSE2
1781   void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1782   void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1783 
1784   // Inlined sin/cos generator for Java; must not use CPU instruction
1785   // directly on Intel as it does not have high enough precision
1786   // outside of the range [-pi/4, pi/4]. Extra argument indicate the
1787   // number of FPU stack slots in use; all but the topmost will
1788   // require saving if a slow case is necessary. Assumes argument is
1789   // on FP TOS; result is on FP TOS.  No cpu registers are changed by
1790   // this code.
1791   void trigfunc(char trig, int num_fpu_regs_in_use = 1);
1792 
1793   // branch to L if FPU flag C2 is set/not set
1794   // tmp is a temporary register, if none is available use noreg
1795   void jC2 (Register tmp, Label& L);
1796   void jnC2(Register tmp, Label& L);
1797 
1798   // Pop ST (ffree & fincstp combined)
1799   void fpop();
1800 
1801   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1802   void push_fTOS();
1803 
1804   // pops double TOS element from CPU stack and pushes on FPU stack
1805   void pop_fTOS();
1806 
1807   void empty_FPU_stack();
1808 
1809   void push_IU_state();
1810   void pop_IU_state();
1811 
1812   void push_FPU_state();
1813   void pop_FPU_state();
1814 
1815   void push_CPU_state();
1816   void pop_CPU_state();
1817 
1818   // Round up to a power of two
1819   void round_to(Register reg, int modulus);
1820 
1821   // Callee saved registers handling
1822   void push_callee_saved_registers();
1823   void pop_callee_saved_registers();
1824 
1825   // allocation
1826   void eden_allocate(
1827     Register obj,                      // result: pointer to object after successful allocation
1828     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
1829     int      con_size_in_bytes,        // object size in bytes if   known at compile time
1830     Register t1,                       // temp register
1831     Label&   slow_case                 // continuation point if fast allocation fails
1832   );
1833   void tlab_allocate(
1834     Register obj,                      // result: pointer to object after successful allocation
1835     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
1836     int      con_size_in_bytes,        // object size in bytes if   known at compile time
1837     Register t1,                       // temp register
1838     Register t2,                       // temp register
1839     Label&   slow_case                 // continuation point if fast allocation fails
1840   );
1841   void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
1842 
1843   // interface method calling
1844   void lookup_interface_method(Register recv_klass,
1845                                Register intf_klass,
1846                                RegisterOrConstant itable_index,
1847                                Register method_result,
1848                                Register scan_temp,
1849                                Label& no_such_interface);
1850 
1851   // Test sub_klass against super_klass, with fast and slow paths.
1852 
1853   // The fast path produces a tri-state answer: yes / no / maybe-slow.
1854   // One of the three labels can be NULL, meaning take the fall-through.
1855   // If super_check_offset is -1, the value is loaded up from super_klass.
1856   // No registers are killed, except temp_reg.
1857   void check_klass_subtype_fast_path(Register sub_klass,
1858                                      Register super_klass,
1859                                      Register temp_reg,
1860                                      Label* L_success,
1861                                      Label* L_failure,
1862                                      Label* L_slow_path,
1863                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
1864 
1865   // The rest of the type check; must be wired to a corresponding fast path.
1866   // It does not repeat the fast path logic, so don't use it standalone.
1867   // The temp_reg and temp2_reg can be noreg, if no temps are available.
1868   // Updates the sub's secondary super cache as necessary.
1869   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1870   void check_klass_subtype_slow_path(Register sub_klass,
1871                                      Register super_klass,
1872                                      Register temp_reg,
1873                                      Register temp2_reg,
1874                                      Label* L_success,
1875                                      Label* L_failure,
1876                                      bool set_cond_codes = false);
1877 
1878   // Simplified, combined version, good for typical uses.
1879   // Falls through on failure.
1880   void check_klass_subtype(Register sub_klass,
1881                            Register super_klass,
1882                            Register temp_reg,
1883                            Label& L_success);
1884 
1885   // method handles (JSR 292)
1886   void check_method_handle_type(Register mtype_reg, Register mh_reg,
1887                                 Register temp_reg,
1888                                 Label& wrong_method_type);
1889   void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
1890                                   Register temp_reg);
1891   void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
1892   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1893 
1894 
1895   //----
1896   void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
1897 
1898   // Debugging
1899 
1900   // only if +VerifyOops
1901   void verify_oop(Register reg, const char* s = "broken oop");
1902   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
1903 
1904   // only if +VerifyFPU
1905   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1906 
1907   // prints msg, dumps registers and stops execution
1908   void stop(const char* msg);
1909 
1910   // prints msg and continues
1911   void warn(const char* msg);
1912 
1913   static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
1914   static void debug64(char* msg, int64_t pc, int64_t regs[]);
1915 
1916   void os_breakpoint();
1917 
1918   void untested()                                { stop("untested"); }
1919 
1920   void unimplemented(const char* what = "")      { char* b = new char[1024];  jio_snprintf(b, sizeof(b), "unimplemented: %s", what);  stop(b); }
1921 
1922   void should_not_reach_here()                   { stop("should not reach here"); }
1923 
1924   void print_CPU_state();
1925 
1926   // Stack overflow checking
1927   void bang_stack_with_offset(int offset) {
1928     // stack grows down, caller passes positive offset
1929     assert(offset > 0, "must bang with negative offset");
1930     movl(Address(rsp, (-offset)), rax);
1931   }
1932 
1933   // Writes to stack successive pages until offset reached to check for
1934   // stack overflow + shadow pages.  Also, clobbers tmp
1935   void bang_stack_size(Register size, Register tmp);
1936 
1937   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
1938                                                 Register tmp,
1939                                                 int offset);
1940 
1941   // Support for serializing memory accesses between threads
1942   void serialize_memory(Register thread, Register tmp);
1943 
1944   void verify_tlab();
1945 
1946   // Biased locking support
1947   // lock_reg and obj_reg must be loaded up with the appropriate values.
1948   // swap_reg must be rax, and is killed.
1949   // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
1950   // be killed; if not supplied, push/pop will be used internally to
1951   // allocate a temporary (inefficient, avoid if possible).
1952   // Optional slow case is for implementations (interpreter and C1) which branch to
1953   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
1954   // Returns offset of first potentially-faulting instruction for null
1955   // check info (currently consumed only by C1). If
1956   // swap_reg_contains_mark is true then returns -1 as it is assumed
1957   // the calling code has already passed any potential faults.
1958   int biased_locking_enter(Register lock_reg, Register obj_reg,
1959                            Register swap_reg, Register tmp_reg,
1960                            bool swap_reg_contains_mark,
1961                            Label& done, Label* slow_case = NULL,
1962                            BiasedLockingCounters* counters = NULL);
1963   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
1964 
1965 
1966   Condition negate_condition(Condition cond);
1967 
1968   // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
1969   // operands. In general the names are modified to avoid hiding the instruction in Assembler
1970   // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
1971   // here in MacroAssembler. The major exception to this rule is call
1972 
1973   // Arithmetics
1974 
1975 
1976   void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
1977   void addptr(Address dst, Register src);
1978 
1979   void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
1980   void addptr(Register dst, int32_t src);
1981   void addptr(Register dst, Register src);
1982 
1983   void andptr(Register dst, int32_t src);
1984   void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
1985 
1986   void cmp8(AddressLiteral src1, int imm);
1987 
1988   // renamed to drag out the casting of address to int32_t/intptr_t
1989   void cmp32(Register src1, int32_t imm);
1990 
1991   void cmp32(AddressLiteral src1, int32_t imm);
1992   // compare reg - mem, or reg - &mem
1993   void cmp32(Register src1, AddressLiteral src2);
1994 
1995   void cmp32(Register src1, Address src2);
1996 
1997 #ifndef _LP64
1998   void cmpoop(Address dst, jobject obj);
1999   void cmpoop(Register dst, jobject obj);
2000 #endif // _LP64
2001 
2002   // NOTE src2 must be the lval. This is NOT an mem-mem compare
2003   void cmpptr(Address src1, AddressLiteral src2);
2004 
2005   void cmpptr(Register src1, AddressLiteral src2);
2006 
2007   void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2008   void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2009   // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2010 
2011   void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2012   void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2013 
2014   // cmp64 to avoild hiding cmpq
2015   void cmp64(Register src1, AddressLiteral src);
2016 
2017   void cmpxchgptr(Register reg, Address adr);
2018 
2019   void locked_cmpxchgptr(Register reg, AddressLiteral adr);
2020 
2021 
2022   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
2023 
2024 
2025   void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
2026 
2027   void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
2028 
2029   void shlptr(Register dst, int32_t shift);
2030   void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
2031 
2032   void shrptr(Register dst, int32_t shift);
2033   void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
2034 
2035   void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
2036   void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
2037 
2038   void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2039 
2040   void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2041   void subptr(Register dst, int32_t src);
2042   void subptr(Register dst, Register src);
2043 
2044 
2045   void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2046   void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2047 
2048   void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2049   void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2050 
2051   void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
2052 
2053 
2054 
2055   // Helper functions for statistics gathering.
2056   // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
2057   void cond_inc32(Condition cond, AddressLiteral counter_addr);
2058   // Unconditional atomic increment.
2059   void atomic_incl(AddressLiteral counter_addr);
2060 
2061   void lea(Register dst, AddressLiteral adr);
2062   void lea(Address dst, AddressLiteral adr);
2063   void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
2064 
2065   void leal32(Register dst, Address src) { leal(dst, src); }
2066 
2067   void test32(Register src1, AddressLiteral src2);
2068 
2069   void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2070   void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2071   void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2072 
2073   void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
2074   void testptr(Register src1, Register src2);
2075 
2076   void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2077   void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2078 
2079   // Calls
2080 
2081   void call(Label& L, relocInfo::relocType rtype);
2082   void call(Register entry);
2083 
2084   // NOTE: this call tranfers to the effective address of entry NOT
2085   // the address contained by entry. This is because this is more natural
2086   // for jumps/calls.
2087   void call(AddressLiteral entry);
2088 
2089   // Jumps
2090 
2091   // NOTE: these jumps tranfer to the effective address of dst NOT
2092   // the address contained by dst. This is because this is more natural
2093   // for jumps/calls.
2094   void jump(AddressLiteral dst);
2095   void jump_cc(Condition cc, AddressLiteral dst);
2096 
2097   // 32bit can do a case table jump in one instruction but we no longer allow the base
2098   // to be installed in the Address class. This jump will tranfers to the address
2099   // contained in the location described by entry (not the address of entry)
2100   void jump(ArrayAddress entry);
2101 
2102   // Floating
2103 
2104   void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
2105   void andpd(XMMRegister dst, AddressLiteral src);
2106 
2107   void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
2108   void comiss(XMMRegister dst, AddressLiteral src);
2109 
2110   void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
2111   void comisd(XMMRegister dst, AddressLiteral src);
2112 
2113   void fldcw(Address src) { Assembler::fldcw(src); }
2114   void fldcw(AddressLiteral src);
2115 
2116   void fld_s(int index)   { Assembler::fld_s(index); }
2117   void fld_s(Address src) { Assembler::fld_s(src); }
2118   void fld_s(AddressLiteral src);
2119 
2120   void fld_d(Address src) { Assembler::fld_d(src); }
2121   void fld_d(AddressLiteral src);
2122 
2123   void fld_x(Address src) { Assembler::fld_x(src); }
2124   void fld_x(AddressLiteral src);
2125 
2126   void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
2127   void ldmxcsr(AddressLiteral src);
2128 
2129 private:
2130   // these are private because users should be doing movflt/movdbl
2131 
2132   void movss(Address dst, XMMRegister src)     { Assembler::movss(dst, src); }
2133   void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
2134   void movss(XMMRegister dst, Address src)     { Assembler::movss(dst, src); }
2135   void movss(XMMRegister dst, AddressLiteral src);
2136 
2137   void movlpd(XMMRegister dst, Address src)      {Assembler::movlpd(dst, src); }
2138   void movlpd(XMMRegister dst, AddressLiteral src);
2139 
2140 public:
2141 
2142   void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
2143   void movsd(Address dst, XMMRegister src)     { Assembler::movsd(dst, src); }
2144   void movsd(XMMRegister dst, Address src)     { Assembler::movsd(dst, src); }
2145   void movsd(XMMRegister dst, AddressLiteral src);
2146 
2147   void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2148   void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
2149   void ucomiss(XMMRegister dst, AddressLiteral src);
2150 
2151   void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2152   void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
2153   void ucomisd(XMMRegister dst, AddressLiteral src);
2154 
2155   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2156   void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2157   void xorpd(XMMRegister dst, Address src)     { Assembler::xorpd(dst, src); }
2158   void xorpd(XMMRegister dst, AddressLiteral src);
2159 
2160   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2161   void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2162   void xorps(XMMRegister dst, Address src)     { Assembler::xorps(dst, src); }
2163   void xorps(XMMRegister dst, AddressLiteral src);
2164 
2165   // Data
2166 
2167   void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2168 
2169   void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2170   void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2171 
2172   void movoop(Register dst, jobject obj);
2173   void movoop(Address dst, jobject obj);
2174 
2175   void movptr(ArrayAddress dst, Register src);
2176   // can this do an lea?
2177   void movptr(Register dst, ArrayAddress src);
2178 
2179   void movptr(Register dst, Address src);
2180 
2181   void movptr(Register dst, AddressLiteral src);
2182 
2183   void movptr(Register dst, intptr_t src);
2184   void movptr(Register dst, Register src);
2185   void movptr(Address dst, intptr_t src);
2186 
2187   void movptr(Address dst, Register src);
2188 
2189 #ifdef _LP64
2190   // Generally the next two are only used for moving NULL
2191   // Although there are situations in initializing the mark word where
2192   // they could be used. They are dangerous.
2193 
2194   // They only exist on LP64 so that int32_t and intptr_t are not the same
2195   // and we have ambiguous declarations.
2196 
2197   void movptr(Address dst, int32_t imm32);
2198   void movptr(Register dst, int32_t imm32);
2199 #endif // _LP64
2200 
2201   // to avoid hiding movl
2202   void mov32(AddressLiteral dst, Register src);
2203   void mov32(Register dst, AddressLiteral src);
2204 
2205   // to avoid hiding movb
2206   void movbyte(ArrayAddress dst, int src);
2207 
2208   // Can push value or effective address
2209   void pushptr(AddressLiteral src);
2210 
2211   void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2212   void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2213 
2214   void pushoop(jobject obj);
2215 
2216   // sign extend as need a l to ptr sized element
2217   void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2218   void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2219 
2220   // IndexOf strings.
2221   void string_indexof(Register str1, Register str2,
2222                       Register cnt1, Register cnt2, Register result,
2223                       XMMRegister vec, Register tmp);
2224 
2225   // Compare strings.
2226   void string_compare(Register str1, Register str2,
2227                       Register cnt1, Register cnt2, Register result,
2228                       XMMRegister vec1, XMMRegister vec2);
2229 
2230   // Compare char[] arrays.
2231   void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
2232                           Register limit, Register result, Register chr,
2233                           XMMRegister vec1, XMMRegister vec2);
2234 
2235 #undef VIRTUAL
2236 
2237 };
2238 
2239 /**
2240  * class SkipIfEqual:
2241  *
2242  * Instantiating this class will result in assembly code being output that will
2243  * jump around any code emitted between the creation of the instance and it's
2244  * automatic destruction at the end of a scope block, depending on the value of
2245  * the flag passed to the constructor, which will be checked at run-time.
2246  */
2247 class SkipIfEqual {
2248  private:
2249   MacroAssembler* _masm;
2250   Label _label;
2251 
2252  public:
2253    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2254    ~SkipIfEqual();
2255 };
2256 
2257 #ifdef ASSERT
2258 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2259 #endif