1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP
27
28 class BiasedLockingCounters;
29
30 // Contains all the definitions needed for x86 assembly code generation.
31
32 // Calling convention
33 class Argument VALUE_OBJ_CLASS_SPEC {
34 public:
35 enum {
36 #ifdef _LP64
37 #ifdef _WIN64
38 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
40 #else
41 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
42 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
43 #endif // _WIN64
44 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
45 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
46 #else
47 n_register_parameters = 0 // 0 registers used to pass arguments
48 #endif // _LP64
49 };
50 };
51
52
53 #ifdef _LP64
54 // Symbolically name the register arguments used by the c calling convention.
55 // Windows is different from linux/solaris. So much for standards...
56
57 #ifdef _WIN64
58
59 REGISTER_DECLARATION(Register, c_rarg0, rcx);
60 REGISTER_DECLARATION(Register, c_rarg1, rdx);
61 REGISTER_DECLARATION(Register, c_rarg2, r8);
62 REGISTER_DECLARATION(Register, c_rarg3, r9);
63
64 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
65 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
66 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
67 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
68
69 #else
70
71 REGISTER_DECLARATION(Register, c_rarg0, rdi);
72 REGISTER_DECLARATION(Register, c_rarg1, rsi);
73 REGISTER_DECLARATION(Register, c_rarg2, rdx);
74 REGISTER_DECLARATION(Register, c_rarg3, rcx);
75 REGISTER_DECLARATION(Register, c_rarg4, r8);
76 REGISTER_DECLARATION(Register, c_rarg5, r9);
77
78 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
79 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
80 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
81 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
82 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
83 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
84 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
85 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
86
87 #endif // _WIN64
88
89 // Symbolically name the register arguments used by the Java calling convention.
90 // We have control over the convention for java so we can do what we please.
91 // What pleases us is to offset the java calling convention so that when
92 // we call a suitable jni method the arguments are lined up and we don't
93 // have to do little shuffling. A suitable jni method is non-static and a
94 // small number of arguments (two fewer args on windows)
95 //
96 // |-------------------------------------------------------|
97 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
98 // |-------------------------------------------------------|
99 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
100 // | rdi rsi rdx rcx r8 r9 | solaris/linux
101 // |-------------------------------------------------------|
102 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
103 // |-------------------------------------------------------|
104
105 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
106 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
107 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
108 // Windows runs out of register args here
109 #ifdef _WIN64
110 REGISTER_DECLARATION(Register, j_rarg3, rdi);
111 REGISTER_DECLARATION(Register, j_rarg4, rsi);
112 #else
113 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
114 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
115 #endif /* _WIN64 */
116 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
117
118 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
119 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
120 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
121 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
122 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
123 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
124 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
125 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
126
127 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
128 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
129
130 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
131 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
132
133 #else
134 // rscratch1 will apear in 32bit code that is dead but of course must compile
135 // Using noreg ensures if the dead code is incorrectly live and executed it
136 // will cause an assertion failure
137 #define rscratch1 noreg
138 #define rscratch2 noreg
139
140 #endif // _LP64
141
142 // JSR 292 fixed register usages:
143 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp);
144
145 // Address is an abstraction used to represent a memory location
146 // using any of the amd64 addressing modes with one object.
147 //
148 // Note: A register location is represented via a Register, not
149 // via an address for efficiency & simplicity reasons.
150
151 class ArrayAddress;
152
153 class Address VALUE_OBJ_CLASS_SPEC {
154 public:
155 enum ScaleFactor {
156 no_scale = -1,
157 times_1 = 0,
158 times_2 = 1,
159 times_4 = 2,
160 times_8 = 3,
161 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
162 };
163 static ScaleFactor times(int size) {
164 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
165 if (size == 8) return times_8;
166 if (size == 4) return times_4;
167 if (size == 2) return times_2;
168 return times_1;
169 }
170 static int scale_size(ScaleFactor scale) {
171 assert(scale != no_scale, "");
172 assert(((1 << (int)times_1) == 1 &&
173 (1 << (int)times_2) == 2 &&
174 (1 << (int)times_4) == 4 &&
175 (1 << (int)times_8) == 8), "");
176 return (1 << (int)scale);
177 }
178
179 private:
180 Register _base;
181 Register _index;
182 ScaleFactor _scale;
183 int _disp;
184 RelocationHolder _rspec;
185
186 // Easily misused constructors make them private
187 // %%% can we make these go away?
188 NOT_LP64(Address(address loc, RelocationHolder spec);)
189 Address(int disp, address loc, relocInfo::relocType rtype);
190 Address(int disp, address loc, RelocationHolder spec);
191
192 public:
193
194 int disp() { return _disp; }
195 // creation
196 Address()
197 : _base(noreg),
198 _index(noreg),
199 _scale(no_scale),
200 _disp(0) {
201 }
202
203 // No default displacement otherwise Register can be implicitly
204 // converted to 0(Register) which is quite a different animal.
205
206 Address(Register base, int disp)
207 : _base(base),
208 _index(noreg),
209 _scale(no_scale),
210 _disp(disp) {
211 }
212
213 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
214 : _base (base),
215 _index(index),
216 _scale(scale),
217 _disp (disp) {
218 assert(!index->is_valid() == (scale == Address::no_scale),
219 "inconsistent address");
220 }
221
222 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
223 : _base (base),
224 _index(index.register_or_noreg()),
225 _scale(scale),
226 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
227 if (!index.is_register()) scale = Address::no_scale;
228 assert(!_index->is_valid() == (scale == Address::no_scale),
229 "inconsistent address");
230 }
231
232 Address plus_disp(int disp) const {
233 Address a = (*this);
234 a._disp += disp;
235 return a;
236 }
237
238 // The following two overloads are used in connection with the
239 // ByteSize type (see sizes.hpp). They simplify the use of
240 // ByteSize'd arguments in assembly code. Note that their equivalent
241 // for the optimized build are the member functions with int disp
242 // argument since ByteSize is mapped to an int type in that case.
243 //
244 // Note: DO NOT introduce similar overloaded functions for WordSize
245 // arguments as in the optimized mode, both ByteSize and WordSize
246 // are mapped to the same type and thus the compiler cannot make a
247 // distinction anymore (=> compiler errors).
248
249 #ifdef ASSERT
250 Address(Register base, ByteSize disp)
251 : _base(base),
252 _index(noreg),
253 _scale(no_scale),
254 _disp(in_bytes(disp)) {
255 }
256
257 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
258 : _base(base),
259 _index(index),
260 _scale(scale),
261 _disp(in_bytes(disp)) {
262 assert(!index->is_valid() == (scale == Address::no_scale),
263 "inconsistent address");
264 }
265
266 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
267 : _base (base),
268 _index(index.register_or_noreg()),
269 _scale(scale),
270 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
271 if (!index.is_register()) scale = Address::no_scale;
272 assert(!_index->is_valid() == (scale == Address::no_scale),
273 "inconsistent address");
274 }
275
276 #endif // ASSERT
277
278 // accessors
279 bool uses(Register reg) const { return _base == reg || _index == reg; }
280 Register base() const { return _base; }
281 Register index() const { return _index; }
282 ScaleFactor scale() const { return _scale; }
283 int disp() const { return _disp; }
284
285 // Convert the raw encoding form into the form expected by the constructor for
286 // Address. An index of 4 (rsp) corresponds to having no index, so convert
287 // that to noreg for the Address constructor.
288 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop);
289
290 static Address make_array(ArrayAddress);
291
292 private:
293 bool base_needs_rex() const {
294 return _base != noreg && _base->encoding() >= 8;
295 }
296
297 bool index_needs_rex() const {
298 return _index != noreg &&_index->encoding() >= 8;
299 }
300
301 relocInfo::relocType reloc() const { return _rspec.type(); }
302
303 friend class Assembler;
304 friend class MacroAssembler;
305 friend class LIR_Assembler; // base/index/scale/disp
306 };
307
308 //
309 // AddressLiteral has been split out from Address because operands of this type
310 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
311 // the few instructions that need to deal with address literals are unique and the
312 // MacroAssembler does not have to implement every instruction in the Assembler
313 // in order to search for address literals that may need special handling depending
314 // on the instruction and the platform. As small step on the way to merging i486/amd64
315 // directories.
316 //
317 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
318 friend class ArrayAddress;
319 RelocationHolder _rspec;
320 // Typically we use AddressLiterals we want to use their rval
321 // However in some situations we want the lval (effect address) of the item.
322 // We provide a special factory for making those lvals.
323 bool _is_lval;
324
325 // If the target is far we'll need to load the ea of this to
326 // a register to reach it. Otherwise if near we can do rip
327 // relative addressing.
328
329 address _target;
330
331 protected:
332 // creation
333 AddressLiteral()
334 : _is_lval(false),
335 _target(NULL)
336 {}
337
338 public:
339
340
341 AddressLiteral(address target, relocInfo::relocType rtype);
342
343 AddressLiteral(address target, RelocationHolder const& rspec)
344 : _rspec(rspec),
345 _is_lval(false),
346 _target(target)
347 {}
348
349 AddressLiteral addr() {
350 AddressLiteral ret = *this;
351 ret._is_lval = true;
352 return ret;
353 }
354
355
356 private:
357
358 address target() { return _target; }
359 bool is_lval() { return _is_lval; }
360
361 relocInfo::relocType reloc() const { return _rspec.type(); }
362 const RelocationHolder& rspec() const { return _rspec; }
363
364 friend class Assembler;
365 friend class MacroAssembler;
366 friend class Address;
367 friend class LIR_Assembler;
368 };
369
370 // Convience classes
371 class RuntimeAddress: public AddressLiteral {
372
373 public:
374
375 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
376
377 };
378
379 class OopAddress: public AddressLiteral {
380
381 public:
382
383 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
384
385 };
386
387 class ExternalAddress: public AddressLiteral {
388
389 public:
390
391 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
392
393 };
394
395 class InternalAddress: public AddressLiteral {
396
397 public:
398
399 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
400
401 };
402
403 // x86 can do array addressing as a single operation since disp can be an absolute
404 // address amd64 can't. We create a class that expresses the concept but does extra
405 // magic on amd64 to get the final result
406
407 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
408 private:
409
410 AddressLiteral _base;
411 Address _index;
412
413 public:
414
415 ArrayAddress() {};
416 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
417 AddressLiteral base() { return _base; }
418 Address index() { return _index; }
419
420 };
421
422 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
423
424 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
425 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
426 // is what you get. The Assembler is generating code into a CodeBuffer.
427
428 class Assembler : public AbstractAssembler {
429 friend class AbstractAssembler; // for the non-virtual hack
430 friend class LIR_Assembler; // as_Address()
431 friend class StubGenerator;
432
433 public:
434 enum Condition { // The x86 condition codes used for conditional jumps/moves.
435 zero = 0x4,
436 notZero = 0x5,
437 equal = 0x4,
438 notEqual = 0x5,
439 less = 0xc,
440 lessEqual = 0xe,
441 greater = 0xf,
442 greaterEqual = 0xd,
443 below = 0x2,
444 belowEqual = 0x6,
445 above = 0x7,
446 aboveEqual = 0x3,
447 overflow = 0x0,
448 noOverflow = 0x1,
449 carrySet = 0x2,
450 carryClear = 0x3,
451 negative = 0x8,
452 positive = 0x9,
453 parity = 0xa,
454 noParity = 0xb
455 };
456
457 enum Prefix {
458 // segment overrides
459 CS_segment = 0x2e,
460 SS_segment = 0x36,
461 DS_segment = 0x3e,
462 ES_segment = 0x26,
463 FS_segment = 0x64,
464 GS_segment = 0x65,
465
466 REX = 0x40,
467
468 REX_B = 0x41,
469 REX_X = 0x42,
470 REX_XB = 0x43,
471 REX_R = 0x44,
472 REX_RB = 0x45,
473 REX_RX = 0x46,
474 REX_RXB = 0x47,
475
476 REX_W = 0x48,
477
478 REX_WB = 0x49,
479 REX_WX = 0x4A,
480 REX_WXB = 0x4B,
481 REX_WR = 0x4C,
482 REX_WRB = 0x4D,
483 REX_WRX = 0x4E,
484 REX_WRXB = 0x4F
485 };
486
487 enum WhichOperand {
488 // input to locate_operand, and format code for relocations
489 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
490 disp32_operand = 1, // embedded 32-bit displacement or address
491 call32_operand = 2, // embedded 32-bit self-relative displacement
492 #ifndef _LP64
493 _WhichOperand_limit = 3
494 #else
495 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
496 _WhichOperand_limit = 4
497 #endif
498 };
499
500
501
502 // NOTE: The general philopsophy of the declarations here is that 64bit versions
503 // of instructions are freely declared without the need for wrapping them an ifdef.
504 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
505 // In the .cpp file the implementations are wrapped so that they are dropped out
506 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
507 // to the size it was prior to merging up the 32bit and 64bit assemblers.
508 //
509 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
510 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
511
512 private:
513
514
515 // 64bit prefixes
516 int prefix_and_encode(int reg_enc, bool byteinst = false);
517 int prefixq_and_encode(int reg_enc);
518
519 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
520 int prefixq_and_encode(int dst_enc, int src_enc);
521
522 void prefix(Register reg);
523 void prefix(Address adr);
524 void prefixq(Address adr);
525
526 void prefix(Address adr, Register reg, bool byteinst = false);
527 void prefixq(Address adr, Register reg);
528
529 void prefix(Address adr, XMMRegister reg);
530
531 void prefetch_prefix(Address src);
532
533 // Helper functions for groups of instructions
534 void emit_arith_b(int op1, int op2, Register dst, int imm8);
535
536 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
537 // only 32bit??
538 void emit_arith(int op1, int op2, Register dst, jobject obj);
539 void emit_arith(int op1, int op2, Register dst, Register src);
540
541 void emit_operand(Register reg,
542 Register base, Register index, Address::ScaleFactor scale,
543 int disp,
544 RelocationHolder const& rspec,
545 int rip_relative_correction = 0);
546
547 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
548
549 // operands that only take the original 32bit registers
550 void emit_operand32(Register reg, Address adr);
551
552 void emit_operand(XMMRegister reg,
553 Register base, Register index, Address::ScaleFactor scale,
554 int disp,
555 RelocationHolder const& rspec);
556
557 void emit_operand(XMMRegister reg, Address adr);
558
559 void emit_operand(MMXRegister reg, Address adr);
560
561 // workaround gcc (3.2.1-7) bug
562 void emit_operand(Address adr, MMXRegister reg);
563
564
565 // Immediate-to-memory forms
566 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
567
568 void emit_farith(int b1, int b2, int i);
569
570
571 protected:
572 #ifdef ASSERT
573 void check_relocation(RelocationHolder const& rspec, int format);
574 #endif
575
576 inline void emit_long64(jlong x);
577
578 void emit_data(jint data, relocInfo::relocType rtype, int format);
579 void emit_data(jint data, RelocationHolder const& rspec, int format);
580 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
581 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
582
583
584 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
585
586 // These are all easily abused and hence protected
587
588 // 32BIT ONLY SECTION
589 #ifndef _LP64
590 // Make these disappear in 64bit mode since they would never be correct
591 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
592 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
593
594 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
595 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
596
597 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
598 #else
599 // 64BIT ONLY SECTION
600 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
601
602 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
603 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
604
605 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
606 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
607 #endif // _LP64
608
609 // These are unique in that we are ensured by the caller that the 32bit
610 // relative in these instructions will always be able to reach the potentially
611 // 64bit address described by entry. Since they can take a 64bit address they
612 // don't have the 32 suffix like the other instructions in this class.
613
614 void call_literal(address entry, RelocationHolder const& rspec);
615 void jmp_literal(address entry, RelocationHolder const& rspec);
616
617 // Avoid using directly section
618 // Instructions in this section are actually usable by anyone without danger
619 // of failure but have performance issues that are addressed my enhanced
620 // instructions which will do the proper thing base on the particular cpu.
621 // We protect them because we don't trust you...
622
623 // Don't use next inc() and dec() methods directly. INC & DEC instructions
624 // could cause a partial flag stall since they don't set CF flag.
625 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
626 // which call inc() & dec() or add() & sub() in accordance with
627 // the product flag UseIncDec value.
628
629 void decl(Register dst);
630 void decl(Address dst);
631 void decq(Register dst);
632 void decq(Address dst);
633
634 void incl(Register dst);
635 void incl(Address dst);
636 void incq(Register dst);
637 void incq(Address dst);
638
639 // New cpus require use of movsd and movss to avoid partial register stall
640 // when loading from memory. But for old Opteron use movlpd instead of movsd.
641 // The selection is done in MacroAssembler::movdbl() and movflt().
642
643 // Move Scalar Single-Precision Floating-Point Values
644 void movss(XMMRegister dst, Address src);
645 void movss(XMMRegister dst, XMMRegister src);
646 void movss(Address dst, XMMRegister src);
647
648 // Move Scalar Double-Precision Floating-Point Values
649 void movsd(XMMRegister dst, Address src);
650 void movsd(XMMRegister dst, XMMRegister src);
651 void movsd(Address dst, XMMRegister src);
652 void movlpd(XMMRegister dst, Address src);
653
654 // New cpus require use of movaps and movapd to avoid partial register stall
655 // when moving between registers.
656 void movaps(XMMRegister dst, XMMRegister src);
657 void movapd(XMMRegister dst, XMMRegister src);
658
659 // End avoid using directly
660
661
662 // Instruction prefixes
663 void prefix(Prefix p);
664
665 public:
666
667 // Creation
668 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
669
670 // Decoding
671 static address locate_operand(address inst, WhichOperand which);
672 static address locate_next_instruction(address inst);
673
674 // Utilities
675
676 #ifdef _LP64
677 static bool is_simm(int64_t x, int nbits) { return -(CONST64(1) << (nbits-1)) <= x &&
678 x < (CONST64(1) << (nbits-1)); }
679 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; }
680 #else
681 static bool is_simm(int32_t x, int nbits) { return -(1 << (nbits-1)) <= x &&
682 x < (1 << (nbits-1)); }
683 static bool is_simm32(int32_t x) { return true; }
684 #endif // _LP64
685
686 // Generic instructions
687 // Does 32bit or 64bit as needed for the platform. In some sense these
688 // belong in macro assembler but there is no need for both varieties to exist
689
690 void lea(Register dst, Address src);
691
692 void mov(Register dst, Register src);
693
694 void pusha();
695 void popa();
696
697 void pushf();
698 void popf();
699
700 void push(int32_t imm32);
701
702 void push(Register src);
703
704 void pop(Register dst);
705
706 // These are dummies to prevent surprise implicit conversions to Register
707 void push(void* v);
708 void pop(void* v);
709
710 // These do register sized moves/scans
711 void rep_mov();
712 void rep_set();
713 void repne_scan();
714 #ifdef _LP64
715 void repne_scanl();
716 #endif
717
718 // Vanilla instructions in lexical order
719
720 void adcl(Address dst, int32_t imm32);
721 void adcl(Address dst, Register src);
722 void adcl(Register dst, int32_t imm32);
723 void adcl(Register dst, Address src);
724 void adcl(Register dst, Register src);
725
726 void adcq(Register dst, int32_t imm32);
727 void adcq(Register dst, Address src);
728 void adcq(Register dst, Register src);
729
730 void addl(Address dst, int32_t imm32);
731 void addl(Address dst, Register src);
732 void addl(Register dst, int32_t imm32);
733 void addl(Register dst, Address src);
734 void addl(Register dst, Register src);
735
736 void addq(Address dst, int32_t imm32);
737 void addq(Address dst, Register src);
738 void addq(Register dst, int32_t imm32);
739 void addq(Register dst, Address src);
740 void addq(Register dst, Register src);
741
742 void addr_nop_4();
743 void addr_nop_5();
744 void addr_nop_7();
745 void addr_nop_8();
746
747 // Add Scalar Double-Precision Floating-Point Values
748 void addsd(XMMRegister dst, Address src);
749 void addsd(XMMRegister dst, XMMRegister src);
750
751 // Add Scalar Single-Precision Floating-Point Values
752 void addss(XMMRegister dst, Address src);
753 void addss(XMMRegister dst, XMMRegister src);
754
755 void andl(Register dst, int32_t imm32);
756 void andl(Register dst, Address src);
757 void andl(Register dst, Register src);
758
759 void andq(Register dst, int32_t imm32);
760 void andq(Register dst, Address src);
761 void andq(Register dst, Register src);
762
763 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
764 void andpd(XMMRegister dst, Address src);
765 void andpd(XMMRegister dst, XMMRegister src);
766
767 void bsfl(Register dst, Register src);
768 void bsrl(Register dst, Register src);
769
770 #ifdef _LP64
771 void bsfq(Register dst, Register src);
772 void bsrq(Register dst, Register src);
773 #endif
774
775 void bswapl(Register reg);
776
777 void bswapq(Register reg);
778
779 void call(Label& L, relocInfo::relocType rtype);
780 void call(Register reg); // push pc; pc <- reg
781 void call(Address adr); // push pc; pc <- adr
782
783 void cdql();
784
785 void cdqq();
786
787 void cld() { emit_byte(0xfc); }
788
789 void clflush(Address adr);
790
791 void cmovl(Condition cc, Register dst, Register src);
792 void cmovl(Condition cc, Register dst, Address src);
793
794 void cmovq(Condition cc, Register dst, Register src);
795 void cmovq(Condition cc, Register dst, Address src);
796
797
798 void cmpb(Address dst, int imm8);
799
800 void cmpl(Address dst, int32_t imm32);
801
802 void cmpl(Register dst, int32_t imm32);
803 void cmpl(Register dst, Register src);
804 void cmpl(Register dst, Address src);
805
806 void cmpq(Address dst, int32_t imm32);
807 void cmpq(Address dst, Register src);
808
809 void cmpq(Register dst, int32_t imm32);
810 void cmpq(Register dst, Register src);
811 void cmpq(Register dst, Address src);
812
813 // these are dummies used to catch attempting to convert NULL to Register
814 void cmpl(Register dst, void* junk); // dummy
815 void cmpq(Register dst, void* junk); // dummy
816
817 void cmpw(Address dst, int imm16);
818
819 void cmpxchg8 (Address adr);
820
821 void cmpxchgl(Register reg, Address adr);
822
823 void cmpxchgq(Register reg, Address adr);
824
825 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
826 void comisd(XMMRegister dst, Address src);
827
828 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
829 void comiss(XMMRegister dst, Address src);
830
831 // Identify processor type and features
832 void cpuid() {
833 emit_byte(0x0F);
834 emit_byte(0xA2);
835 }
836
837 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
838 void cvtsd2ss(XMMRegister dst, XMMRegister src);
839
840 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
841 void cvtsi2sdl(XMMRegister dst, Register src);
842 void cvtsi2sdq(XMMRegister dst, Register src);
843
844 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
845 void cvtsi2ssl(XMMRegister dst, Register src);
846 void cvtsi2ssq(XMMRegister dst, Register src);
847
848 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
849 void cvtdq2pd(XMMRegister dst, XMMRegister src);
850
851 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
852 void cvtdq2ps(XMMRegister dst, XMMRegister src);
853
854 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
855 void cvtss2sd(XMMRegister dst, XMMRegister src);
856
857 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
858 void cvttsd2sil(Register dst, Address src);
859 void cvttsd2sil(Register dst, XMMRegister src);
860 void cvttsd2siq(Register dst, XMMRegister src);
861
862 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
863 void cvttss2sil(Register dst, XMMRegister src);
864 void cvttss2siq(Register dst, XMMRegister src);
865
866 // Divide Scalar Double-Precision Floating-Point Values
867 void divsd(XMMRegister dst, Address src);
868 void divsd(XMMRegister dst, XMMRegister src);
869
870 // Divide Scalar Single-Precision Floating-Point Values
871 void divss(XMMRegister dst, Address src);
872 void divss(XMMRegister dst, XMMRegister src);
873
874 void emms();
875
876 void fabs();
877
878 void fadd(int i);
879
880 void fadd_d(Address src);
881 void fadd_s(Address src);
882
883 // "Alternate" versions of x87 instructions place result down in FPU
884 // stack instead of on TOS
885
886 void fadda(int i); // "alternate" fadd
887 void faddp(int i = 1);
888
889 void fchs();
890
891 void fcom(int i);
892
893 void fcomp(int i = 1);
894 void fcomp_d(Address src);
895 void fcomp_s(Address src);
896
897 void fcompp();
898
899 void fcos();
900
901 void fdecstp();
902
903 void fdiv(int i);
904 void fdiv_d(Address src);
905 void fdivr_s(Address src);
906 void fdiva(int i); // "alternate" fdiv
907 void fdivp(int i = 1);
908
909 void fdivr(int i);
910 void fdivr_d(Address src);
911 void fdiv_s(Address src);
912
913 void fdivra(int i); // "alternate" reversed fdiv
914
915 void fdivrp(int i = 1);
916
917 void ffree(int i = 0);
918
919 void fild_d(Address adr);
920 void fild_s(Address adr);
921
922 void fincstp();
923
924 void finit();
925
926 void fist_s (Address adr);
927 void fistp_d(Address adr);
928 void fistp_s(Address adr);
929
930 void fld1();
931
932 void fld_d(Address adr);
933 void fld_s(Address adr);
934 void fld_s(int index);
935 void fld_x(Address adr); // extended-precision (80-bit) format
936
937 void fldcw(Address src);
938
939 void fldenv(Address src);
940
941 void fldlg2();
942
943 void fldln2();
944
945 void fldz();
946
947 void flog();
948 void flog10();
949
950 void fmul(int i);
951
952 void fmul_d(Address src);
953 void fmul_s(Address src);
954
955 void fmula(int i); // "alternate" fmul
956
957 void fmulp(int i = 1);
958
959 void fnsave(Address dst);
960
961 void fnstcw(Address src);
962
963 void fnstsw_ax();
964
965 void fprem();
966 void fprem1();
967
968 void frstor(Address src);
969
970 void fsin();
971
972 void fsqrt();
973
974 void fst_d(Address adr);
975 void fst_s(Address adr);
976
977 void fstp_d(Address adr);
978 void fstp_d(int index);
979 void fstp_s(Address adr);
980 void fstp_x(Address adr); // extended-precision (80-bit) format
981
982 void fsub(int i);
983 void fsub_d(Address src);
984 void fsub_s(Address src);
985
986 void fsuba(int i); // "alternate" fsub
987
988 void fsubp(int i = 1);
989
990 void fsubr(int i);
991 void fsubr_d(Address src);
992 void fsubr_s(Address src);
993
994 void fsubra(int i); // "alternate" reversed fsub
995
996 void fsubrp(int i = 1);
997
998 void ftan();
999
1000 void ftst();
1001
1002 void fucomi(int i = 1);
1003 void fucomip(int i = 1);
1004
1005 void fwait();
1006
1007 void fxch(int i = 1);
1008
1009 void fxrstor(Address src);
1010
1011 void fxsave(Address dst);
1012
1013 void fyl2x();
1014
1015 void hlt();
1016
1017 void idivl(Register src);
1018 void divl(Register src); // Unsigned division
1019
1020 void idivq(Register src);
1021
1022 void imull(Register dst, Register src);
1023 void imull(Register dst, Register src, int value);
1024
1025 void imulq(Register dst, Register src);
1026 void imulq(Register dst, Register src, int value);
1027
1028
1029 // jcc is the generic conditional branch generator to run-
1030 // time routines, jcc is used for branches to labels. jcc
1031 // takes a branch opcode (cc) and a label (L) and generates
1032 // either a backward branch or a forward branch and links it
1033 // to the label fixup chain. Usage:
1034 //
1035 // Label L; // unbound label
1036 // jcc(cc, L); // forward branch to unbound label
1037 // bind(L); // bind label to the current pc
1038 // jcc(cc, L); // backward branch to bound label
1039 // bind(L); // illegal: a label may be bound only once
1040 //
1041 // Note: The same Label can be used for forward and backward branches
1042 // but it may be bound only once.
1043
1044 void jcc(Condition cc, Label& L,
1045 relocInfo::relocType rtype = relocInfo::none);
1046
1047 // Conditional jump to a 8-bit offset to L.
1048 // WARNING: be very careful using this for forward jumps. If the label is
1049 // not bound within an 8-bit offset of this instruction, a run-time error
1050 // will occur.
1051 void jccb(Condition cc, Label& L);
1052
1053 void jmp(Address entry); // pc <- entry
1054
1055 // Label operations & relative jumps (PPUM Appendix D)
1056 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L
1057
1058 void jmp(Register entry); // pc <- entry
1059
1060 // Unconditional 8-bit offset jump to L.
1061 // WARNING: be very careful using this for forward jumps. If the label is
1062 // not bound within an 8-bit offset of this instruction, a run-time error
1063 // will occur.
1064 void jmpb(Label& L);
1065
1066 void ldmxcsr( Address src );
1067
1068 void leal(Register dst, Address src);
1069
1070 void leaq(Register dst, Address src);
1071
1072 void lfence() {
1073 emit_byte(0x0F);
1074 emit_byte(0xAE);
1075 emit_byte(0xE8);
1076 }
1077
1078 void lock();
1079
1080 void lzcntl(Register dst, Register src);
1081
1082 #ifdef _LP64
1083 void lzcntq(Register dst, Register src);
1084 #endif
1085
1086 enum Membar_mask_bits {
1087 StoreStore = 1 << 3,
1088 LoadStore = 1 << 2,
1089 StoreLoad = 1 << 1,
1090 LoadLoad = 1 << 0
1091 };
1092
1093 // Serializes memory and blows flags
1094 void membar(Membar_mask_bits order_constraint) {
1095 if (os::is_MP()) {
1096 // We only have to handle StoreLoad
1097 if (order_constraint & StoreLoad) {
1098 // All usable chips support "locked" instructions which suffice
1099 // as barriers, and are much faster than the alternative of
1100 // using cpuid instruction. We use here a locked add [esp],0.
1101 // This is conveniently otherwise a no-op except for blowing
1102 // flags.
1103 // Any change to this code may need to revisit other places in
1104 // the code where this idiom is used, in particular the
1105 // orderAccess code.
1106 lock();
1107 addl(Address(rsp, 0), 0);// Assert the lock# signal here
1108 }
1109 }
1110 }
1111
1112 void mfence();
1113
1114 // Moves
1115
1116 void mov64(Register dst, int64_t imm64);
1117
1118 void movb(Address dst, Register src);
1119 void movb(Address dst, int imm8);
1120 void movb(Register dst, Address src);
1121
1122 void movdl(XMMRegister dst, Register src);
1123 void movdl(Register dst, XMMRegister src);
1124
1125 // Move Double Quadword
1126 void movdq(XMMRegister dst, Register src);
1127 void movdq(Register dst, XMMRegister src);
1128
1129 // Move Aligned Double Quadword
1130 void movdqa(Address dst, XMMRegister src);
1131 void movdqa(XMMRegister dst, Address src);
1132 void movdqa(XMMRegister dst, XMMRegister src);
1133
1134 // Move Unaligned Double Quadword
1135 void movdqu(Address dst, XMMRegister src);
1136 void movdqu(XMMRegister dst, Address src);
1137 void movdqu(XMMRegister dst, XMMRegister src);
1138
1139 void movl(Register dst, int32_t imm32);
1140 void movl(Address dst, int32_t imm32);
1141 void movl(Register dst, Register src);
1142 void movl(Register dst, Address src);
1143 void movl(Address dst, Register src);
1144
1145 // These dummies prevent using movl from converting a zero (like NULL) into Register
1146 // by giving the compiler two choices it can't resolve
1147
1148 void movl(Address dst, void* junk);
1149 void movl(Register dst, void* junk);
1150
1151 #ifdef _LP64
1152 void movq(Register dst, Register src);
1153 void movq(Register dst, Address src);
1154 void movq(Address dst, Register src);
1155 #endif
1156
1157 void movq(Address dst, MMXRegister src );
1158 void movq(MMXRegister dst, Address src );
1159
1160 #ifdef _LP64
1161 // These dummies prevent using movq from converting a zero (like NULL) into Register
1162 // by giving the compiler two choices it can't resolve
1163
1164 void movq(Address dst, void* dummy);
1165 void movq(Register dst, void* dummy);
1166 #endif
1167
1168 // Move Quadword
1169 void movq(Address dst, XMMRegister src);
1170 void movq(XMMRegister dst, Address src);
1171
1172 void movsbl(Register dst, Address src);
1173 void movsbl(Register dst, Register src);
1174
1175 #ifdef _LP64
1176 void movsbq(Register dst, Address src);
1177 void movsbq(Register dst, Register src);
1178
1179 // Move signed 32bit immediate to 64bit extending sign
1180 void movslq(Address dst, int32_t imm64);
1181 void movslq(Register dst, int32_t imm64);
1182
1183 void movslq(Register dst, Address src);
1184 void movslq(Register dst, Register src);
1185 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1186 #endif
1187
1188 void movswl(Register dst, Address src);
1189 void movswl(Register dst, Register src);
1190
1191 #ifdef _LP64
1192 void movswq(Register dst, Address src);
1193 void movswq(Register dst, Register src);
1194 #endif
1195
1196 void movw(Address dst, int imm16);
1197 void movw(Register dst, Address src);
1198 void movw(Address dst, Register src);
1199
1200 void movzbl(Register dst, Address src);
1201 void movzbl(Register dst, Register src);
1202
1203 #ifdef _LP64
1204 void movzbq(Register dst, Address src);
1205 void movzbq(Register dst, Register src);
1206 #endif
1207
1208 void movzwl(Register dst, Address src);
1209 void movzwl(Register dst, Register src);
1210
1211 #ifdef _LP64
1212 void movzwq(Register dst, Address src);
1213 void movzwq(Register dst, Register src);
1214 #endif
1215
1216 void mull(Address src);
1217 void mull(Register src);
1218
1219 // Multiply Scalar Double-Precision Floating-Point Values
1220 void mulsd(XMMRegister dst, Address src);
1221 void mulsd(XMMRegister dst, XMMRegister src);
1222
1223 // Multiply Scalar Single-Precision Floating-Point Values
1224 void mulss(XMMRegister dst, Address src);
1225 void mulss(XMMRegister dst, XMMRegister src);
1226
1227 void negl(Register dst);
1228
1229 #ifdef _LP64
1230 void negq(Register dst);
1231 #endif
1232
1233 void nop(int i = 1);
1234
1235 void notl(Register dst);
1236
1237 #ifdef _LP64
1238 void notq(Register dst);
1239 #endif
1240
1241 void orl(Address dst, int32_t imm32);
1242 void orl(Register dst, int32_t imm32);
1243 void orl(Register dst, Address src);
1244 void orl(Register dst, Register src);
1245
1246 void orq(Address dst, int32_t imm32);
1247 void orq(Register dst, int32_t imm32);
1248 void orq(Register dst, Address src);
1249 void orq(Register dst, Register src);
1250
1251 // SSE4.2 string instructions
1252 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1253 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1254
1255 #ifndef _LP64 // no 32bit push/pop on amd64
1256 void popl(Address dst);
1257 #endif
1258
1259 #ifdef _LP64
1260 void popq(Address dst);
1261 #endif
1262
1263 void popcntl(Register dst, Address src);
1264 void popcntl(Register dst, Register src);
1265
1266 #ifdef _LP64
1267 void popcntq(Register dst, Address src);
1268 void popcntq(Register dst, Register src);
1269 #endif
1270
1271 // Prefetches (SSE, SSE2, 3DNOW only)
1272
1273 void prefetchnta(Address src);
1274 void prefetchr(Address src);
1275 void prefetcht0(Address src);
1276 void prefetcht1(Address src);
1277 void prefetcht2(Address src);
1278 void prefetchw(Address src);
1279
1280 // POR - Bitwise logical OR
1281 void por(XMMRegister dst, XMMRegister src);
1282
1283 // Shuffle Packed Doublewords
1284 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1285 void pshufd(XMMRegister dst, Address src, int mode);
1286
1287 // Shuffle Packed Low Words
1288 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1289 void pshuflw(XMMRegister dst, Address src, int mode);
1290
1291 // Shift Right Logical Quadword Immediate
1292 void psrlq(XMMRegister dst, int shift);
1293
1294 // Logical Compare Double Quadword
1295 void ptest(XMMRegister dst, XMMRegister src);
1296 void ptest(XMMRegister dst, Address src);
1297
1298 // Interleave Low Bytes
1299 void punpcklbw(XMMRegister dst, XMMRegister src);
1300
1301 #ifndef _LP64 // no 32bit push/pop on amd64
1302 void pushl(Address src);
1303 #endif
1304
1305 void pushq(Address src);
1306
1307 // Xor Packed Byte Integer Values
1308 void pxor(XMMRegister dst, Address src);
1309 void pxor(XMMRegister dst, XMMRegister src);
1310
1311 void rcll(Register dst, int imm8);
1312
1313 void rclq(Register dst, int imm8);
1314
1315 void ret(int imm16);
1316
1317 void sahf();
1318
1319 void sarl(Register dst, int imm8);
1320 void sarl(Register dst);
1321
1322 void sarq(Register dst, int imm8);
1323 void sarq(Register dst);
1324
1325 void sbbl(Address dst, int32_t imm32);
1326 void sbbl(Register dst, int32_t imm32);
1327 void sbbl(Register dst, Address src);
1328 void sbbl(Register dst, Register src);
1329
1330 void sbbq(Address dst, int32_t imm32);
1331 void sbbq(Register dst, int32_t imm32);
1332 void sbbq(Register dst, Address src);
1333 void sbbq(Register dst, Register src);
1334
1335 void setb(Condition cc, Register dst);
1336
1337 void shldl(Register dst, Register src);
1338
1339 void shll(Register dst, int imm8);
1340 void shll(Register dst);
1341
1342 void shlq(Register dst, int imm8);
1343 void shlq(Register dst);
1344
1345 void shrdl(Register dst, Register src);
1346
1347 void shrl(Register dst, int imm8);
1348 void shrl(Register dst);
1349
1350 void shrq(Register dst, int imm8);
1351 void shrq(Register dst);
1352
1353 void smovl(); // QQQ generic?
1354
1355 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1356 void sqrtsd(XMMRegister dst, Address src);
1357 void sqrtsd(XMMRegister dst, XMMRegister src);
1358
1359 // Compute Square Root of Scalar Single-Precision Floating-Point Value
1360 void sqrtss(XMMRegister dst, Address src);
1361 void sqrtss(XMMRegister dst, XMMRegister src);
1362
1363 void std() { emit_byte(0xfd); }
1364
1365 void stmxcsr( Address dst );
1366
1367 void subl(Address dst, int32_t imm32);
1368 void subl(Address dst, Register src);
1369 void subl(Register dst, int32_t imm32);
1370 void subl(Register dst, Address src);
1371 void subl(Register dst, Register src);
1372
1373 void subq(Address dst, int32_t imm32);
1374 void subq(Address dst, Register src);
1375 void subq(Register dst, int32_t imm32);
1376 void subq(Register dst, Address src);
1377 void subq(Register dst, Register src);
1378
1379
1380 // Subtract Scalar Double-Precision Floating-Point Values
1381 void subsd(XMMRegister dst, Address src);
1382 void subsd(XMMRegister dst, XMMRegister src);
1383
1384 // Subtract Scalar Single-Precision Floating-Point Values
1385 void subss(XMMRegister dst, Address src);
1386 void subss(XMMRegister dst, XMMRegister src);
1387
1388 void testb(Register dst, int imm8);
1389
1390 void testl(Register dst, int32_t imm32);
1391 void testl(Register dst, Register src);
1392 void testl(Register dst, Address src);
1393
1394 void testq(Register dst, int32_t imm32);
1395 void testq(Register dst, Register src);
1396
1397
1398 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1399 void ucomisd(XMMRegister dst, Address src);
1400 void ucomisd(XMMRegister dst, XMMRegister src);
1401
1402 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1403 void ucomiss(XMMRegister dst, Address src);
1404 void ucomiss(XMMRegister dst, XMMRegister src);
1405
1406 void xaddl(Address dst, Register src);
1407
1408 void xaddq(Address dst, Register src);
1409
1410 void xchgl(Register reg, Address adr);
1411 void xchgl(Register dst, Register src);
1412
1413 void xchgq(Register reg, Address adr);
1414 void xchgq(Register dst, Register src);
1415
1416 void xorl(Register dst, int32_t imm32);
1417 void xorl(Register dst, Address src);
1418 void xorl(Register dst, Register src);
1419
1420 void xorq(Register dst, Address src);
1421 void xorq(Register dst, Register src);
1422
1423 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1424 void xorpd(XMMRegister dst, Address src);
1425 void xorpd(XMMRegister dst, XMMRegister src);
1426
1427 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1428 void xorps(XMMRegister dst, Address src);
1429 void xorps(XMMRegister dst, XMMRegister src);
1430
1431 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1432 };
1433
1434
1435 // MacroAssembler extends Assembler by frequently used macros.
1436 //
1437 // Instructions for which a 'better' code sequence exists depending
1438 // on arguments should also go in here.
1439
1440 class MacroAssembler: public Assembler {
1441 friend class LIR_Assembler;
1442 friend class Runtime1; // as_Address()
1443 protected:
1444
1445 Address as_Address(AddressLiteral adr);
1446 Address as_Address(ArrayAddress adr);
1447
1448 // Support for VM calls
1449 //
1450 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1451 // may customize this version by overriding it for its purposes (e.g., to save/restore
1452 // additional registers when doing a VM call).
1453 #ifdef CC_INTERP
1454 // c++ interpreter never wants to use interp_masm version of call_VM
1455 #define VIRTUAL
1456 #else
1457 #define VIRTUAL virtual
1458 #endif
1459
1460 VIRTUAL void call_VM_leaf_base(
1461 address entry_point, // the entry point
1462 int number_of_arguments // the number of arguments to pop after the call
1463 );
1464
1465 // This is the base routine called by the different versions of call_VM. The interpreter
1466 // may customize this version by overriding it for its purposes (e.g., to save/restore
1467 // additional registers when doing a VM call).
1468 //
1469 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1470 // returns the register which contains the thread upon return. If a thread register has been
1471 // specified, the return value will correspond to that register. If no last_java_sp is specified
1472 // (noreg) than rsp will be used instead.
1473 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1474 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1475 Register java_thread, // the thread if computed before ; use noreg otherwise
1476 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1477 address entry_point, // the entry point
1478 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1479 bool check_exceptions // whether to check for pending exceptions after return
1480 );
1481
1482 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1483 // The implementation is only non-empty for the InterpreterMacroAssembler,
1484 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1485 virtual void check_and_handle_popframe(Register java_thread);
1486 virtual void check_and_handle_earlyret(Register java_thread);
1487
1488 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1489
1490 // helpers for FPU flag access
1491 // tmp is a temporary register, if none is available use noreg
1492 void save_rax (Register tmp);
1493 void restore_rax(Register tmp);
1494
1495 public:
1496 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1497
1498 // Support for NULL-checks
1499 //
1500 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1501 // If the accessed location is M[reg + offset] and the offset is known, provide the
1502 // offset. No explicit code generation is needed if the offset is within a certain
1503 // range (0 <= offset <= page_size).
1504
1505 void null_check(Register reg, int offset = -1);
1506 static bool needs_explicit_null_check(intptr_t offset);
1507
1508 // Required platform-specific helpers for Label::patch_instructions.
1509 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1510 void pd_patch_instruction(address branch, address target);
1511 #ifndef PRODUCT
1512 static void pd_print_patched_instruction(address branch);
1513 #endif
1514
1515 // The following 4 methods return the offset of the appropriate move instruction
1516
1517 // Support for fast byte/short loading with zero extension (depending on particular CPU)
1518 int load_unsigned_byte(Register dst, Address src);
1519 int load_unsigned_short(Register dst, Address src);
1520
1521 // Support for fast byte/short loading with sign extension (depending on particular CPU)
1522 int load_signed_byte(Register dst, Address src);
1523 int load_signed_short(Register dst, Address src);
1524
1525 // Support for sign-extension (hi:lo = extend_sign(lo))
1526 void extend_sign(Register hi, Register lo);
1527
1528 // Load and store values by size and signed-ness
1529 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
1530 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
1531
1532 // Support for inc/dec with optimal instruction selection depending on value
1533
1534 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1535 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1536
1537 void decrementl(Address dst, int value = 1);
1538 void decrementl(Register reg, int value = 1);
1539
1540 void decrementq(Register reg, int value = 1);
1541 void decrementq(Address dst, int value = 1);
1542
1543 void incrementl(Address dst, int value = 1);
1544 void incrementl(Register reg, int value = 1);
1545
1546 void incrementq(Register reg, int value = 1);
1547 void incrementq(Address dst, int value = 1);
1548
1549
1550 // Support optimal SSE move instructions.
1551 void movflt(XMMRegister dst, XMMRegister src) {
1552 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1553 else { movss (dst, src); return; }
1554 }
1555 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1556 void movflt(XMMRegister dst, AddressLiteral src);
1557 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1558
1559 void movdbl(XMMRegister dst, XMMRegister src) {
1560 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1561 else { movsd (dst, src); return; }
1562 }
1563
1564 void movdbl(XMMRegister dst, AddressLiteral src);
1565
1566 void movdbl(XMMRegister dst, Address src) {
1567 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1568 else { movlpd(dst, src); return; }
1569 }
1570 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1571
1572 void incrementl(AddressLiteral dst);
1573 void incrementl(ArrayAddress dst);
1574
1575 // Alignment
1576 void align(int modulus);
1577
1578 // Misc
1579 void fat_nop(); // 5 byte nop
1580
1581 // Stack frame creation/removal
1582 void enter();
1583 void leave();
1584
1585 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1586 // The pointer will be loaded into the thread register.
1587 void get_thread(Register thread);
1588
1589
1590 // Support for VM calls
1591 //
1592 // It is imperative that all calls into the VM are handled via the call_VM macros.
1593 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1594 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1595
1596
1597 void call_VM(Register oop_result,
1598 address entry_point,
1599 bool check_exceptions = true);
1600 void call_VM(Register oop_result,
1601 address entry_point,
1602 Register arg_1,
1603 bool check_exceptions = true);
1604 void call_VM(Register oop_result,
1605 address entry_point,
1606 Register arg_1, Register arg_2,
1607 bool check_exceptions = true);
1608 void call_VM(Register oop_result,
1609 address entry_point,
1610 Register arg_1, Register arg_2, Register arg_3,
1611 bool check_exceptions = true);
1612
1613 // Overloadings with last_Java_sp
1614 void call_VM(Register oop_result,
1615 Register last_java_sp,
1616 address entry_point,
1617 int number_of_arguments = 0,
1618 bool check_exceptions = true);
1619 void call_VM(Register oop_result,
1620 Register last_java_sp,
1621 address entry_point,
1622 Register arg_1, bool
1623 check_exceptions = true);
1624 void call_VM(Register oop_result,
1625 Register last_java_sp,
1626 address entry_point,
1627 Register arg_1, Register arg_2,
1628 bool check_exceptions = true);
1629 void call_VM(Register oop_result,
1630 Register last_java_sp,
1631 address entry_point,
1632 Register arg_1, Register arg_2, Register arg_3,
1633 bool check_exceptions = true);
1634
1635 void call_VM_leaf(address entry_point,
1636 int number_of_arguments = 0);
1637 void call_VM_leaf(address entry_point,
1638 Register arg_1);
1639 void call_VM_leaf(address entry_point,
1640 Register arg_1, Register arg_2);
1641 void call_VM_leaf(address entry_point,
1642 Register arg_1, Register arg_2, Register arg_3);
1643
1644 // last Java Frame (fills frame anchor)
1645 void set_last_Java_frame(Register thread,
1646 Register last_java_sp,
1647 Register last_java_fp,
1648 address last_java_pc);
1649
1650 // thread in the default location (r15_thread on 64bit)
1651 void set_last_Java_frame(Register last_java_sp,
1652 Register last_java_fp,
1653 address last_java_pc);
1654
1655 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1656
1657 // thread in the default location (r15_thread on 64bit)
1658 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1659
1660 // Stores
1661 void store_check(Register obj); // store check for obj - register is destroyed afterwards
1662 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
1663
1664 void g1_write_barrier_pre(Register obj,
1665 #ifndef _LP64
1666 Register thread,
1667 #endif
1668 Register tmp,
1669 Register tmp2,
1670 bool tosca_live);
1671 void g1_write_barrier_post(Register store_addr,
1672 Register new_val,
1673 #ifndef _LP64
1674 Register thread,
1675 #endif
1676 Register tmp,
1677 Register tmp2);
1678
1679
1680 // split store_check(Register obj) to enhance instruction interleaving
1681 void store_check_part_1(Register obj);
1682 void store_check_part_2(Register obj);
1683
1684 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1685 void c2bool(Register x);
1686
1687 // C++ bool manipulation
1688
1689 void movbool(Register dst, Address src);
1690 void movbool(Address dst, bool boolconst);
1691 void movbool(Address dst, Register src);
1692 void testbool(Register dst);
1693
1694 // oop manipulations
1695 void load_klass(Register dst, Register src);
1696 void store_klass(Register dst, Register src);
1697
1698 void load_heap_oop(Register dst, Address src);
1699 void store_heap_oop(Address dst, Register src);
1700
1701 // Used for storing NULL. All other oop constants should be
1702 // stored using routines that take a jobject.
1703 void store_heap_oop_null(Address dst);
1704
1705 void load_prototype_header(Register dst, Register src);
1706
1707 #ifdef _LP64
1708 void store_klass_gap(Register dst, Register src);
1709
1710 // This dummy is to prevent a call to store_heap_oop from
1711 // converting a zero (like NULL) into a Register by giving
1712 // the compiler two choices it can't resolve
1713
1714 void store_heap_oop(Address dst, void* dummy);
1715
1716 void encode_heap_oop(Register r);
1717 void decode_heap_oop(Register r);
1718 void encode_heap_oop_not_null(Register r);
1719 void decode_heap_oop_not_null(Register r);
1720 void encode_heap_oop_not_null(Register dst, Register src);
1721 void decode_heap_oop_not_null(Register dst, Register src);
1722
1723 void set_narrow_oop(Register dst, jobject obj);
1724 void set_narrow_oop(Address dst, jobject obj);
1725 void cmp_narrow_oop(Register dst, jobject obj);
1726 void cmp_narrow_oop(Address dst, jobject obj);
1727
1728 // if heap base register is used - reinit it with the correct value
1729 void reinit_heapbase();
1730
1731 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1732
1733 #endif // _LP64
1734
1735 // Int division/remainder for Java
1736 // (as idivl, but checks for special case as described in JVM spec.)
1737 // returns idivl instruction offset for implicit exception handling
1738 int corrected_idivl(Register reg);
1739
1740 // Long division/remainder for Java
1741 // (as idivq, but checks for special case as described in JVM spec.)
1742 // returns idivq instruction offset for implicit exception handling
1743 int corrected_idivq(Register reg);
1744
1745 void int3();
1746
1747 // Long operation macros for a 32bit cpu
1748 // Long negation for Java
1749 void lneg(Register hi, Register lo);
1750
1751 // Long multiplication for Java
1752 // (destroys contents of eax, ebx, ecx and edx)
1753 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
1754
1755 // Long shifts for Java
1756 // (semantics as described in JVM spec.)
1757 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
1758 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
1759
1760 // Long compare for Java
1761 // (semantics as described in JVM spec.)
1762 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
1763
1764
1765 // misc
1766
1767 // Sign extension
1768 void sign_extend_short(Register reg);
1769 void sign_extend_byte(Register reg);
1770
1771 // Division by power of 2, rounding towards 0
1772 void division_with_shift(Register reg, int shift_value);
1773
1774 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
1775 //
1776 // CF (corresponds to C0) if x < y
1777 // PF (corresponds to C2) if unordered
1778 // ZF (corresponds to C3) if x = y
1779 //
1780 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1781 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
1782 void fcmp(Register tmp);
1783 // Variant of the above which allows y to be further down the stack
1784 // and which only pops x and y if specified. If pop_right is
1785 // specified then pop_left must also be specified.
1786 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
1787
1788 // Floating-point comparison for Java
1789 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
1790 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1791 // (semantics as described in JVM spec.)
1792 void fcmp2int(Register dst, bool unordered_is_less);
1793 // Variant of the above which allows y to be further down the stack
1794 // and which only pops x and y if specified. If pop_right is
1795 // specified then pop_left must also be specified.
1796 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
1797
1798 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
1799 // tmp is a temporary register, if none is available use noreg
1800 void fremr(Register tmp);
1801
1802
1803 // same as fcmp2int, but using SSE2
1804 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1805 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1806
1807 // Inlined sin/cos generator for Java; must not use CPU instruction
1808 // directly on Intel as it does not have high enough precision
1809 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
1810 // number of FPU stack slots in use; all but the topmost will
1811 // require saving if a slow case is necessary. Assumes argument is
1812 // on FP TOS; result is on FP TOS. No cpu registers are changed by
1813 // this code.
1814 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
1815
1816 // branch to L if FPU flag C2 is set/not set
1817 // tmp is a temporary register, if none is available use noreg
1818 void jC2 (Register tmp, Label& L);
1819 void jnC2(Register tmp, Label& L);
1820
1821 // Pop ST (ffree & fincstp combined)
1822 void fpop();
1823
1824 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1825 void push_fTOS();
1826
1827 // pops double TOS element from CPU stack and pushes on FPU stack
1828 void pop_fTOS();
1829
1830 void empty_FPU_stack();
1831
1832 void push_IU_state();
1833 void pop_IU_state();
1834
1835 void push_FPU_state();
1836 void pop_FPU_state();
1837
1838 void push_CPU_state();
1839 void pop_CPU_state();
1840
1841 // Round up to a power of two
1842 void round_to(Register reg, int modulus);
1843
1844 // Callee saved registers handling
1845 void push_callee_saved_registers();
1846 void pop_callee_saved_registers();
1847
1848 // allocation
1849 void eden_allocate(
1850 Register obj, // result: pointer to object after successful allocation
1851 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1852 int con_size_in_bytes, // object size in bytes if known at compile time
1853 Register t1, // temp register
1854 Label& slow_case // continuation point if fast allocation fails
1855 );
1856 void tlab_allocate(
1857 Register obj, // result: pointer to object after successful allocation
1858 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1859 int con_size_in_bytes, // object size in bytes if known at compile time
1860 Register t1, // temp register
1861 Register t2, // temp register
1862 Label& slow_case // continuation point if fast allocation fails
1863 );
1864 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
1865 void incr_allocated_bytes(Register thread,
1866 Register var_size_in_bytes, int con_size_in_bytes,
1867 Register t1 = noreg);
1868
1869 // interface method calling
1870 void lookup_interface_method(Register recv_klass,
1871 Register intf_klass,
1872 RegisterOrConstant itable_index,
1873 Register method_result,
1874 Register scan_temp,
1875 Label& no_such_interface);
1876
1877 // Test sub_klass against super_klass, with fast and slow paths.
1878
1879 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1880 // One of the three labels can be NULL, meaning take the fall-through.
1881 // If super_check_offset is -1, the value is loaded up from super_klass.
1882 // No registers are killed, except temp_reg.
1883 void check_klass_subtype_fast_path(Register sub_klass,
1884 Register super_klass,
1885 Register temp_reg,
1886 Label* L_success,
1887 Label* L_failure,
1888 Label* L_slow_path,
1889 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
1890
1891 // The rest of the type check; must be wired to a corresponding fast path.
1892 // It does not repeat the fast path logic, so don't use it standalone.
1893 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1894 // Updates the sub's secondary super cache as necessary.
1895 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1896 void check_klass_subtype_slow_path(Register sub_klass,
1897 Register super_klass,
1898 Register temp_reg,
1899 Register temp2_reg,
1900 Label* L_success,
1901 Label* L_failure,
1902 bool set_cond_codes = false);
1903
1904 // Simplified, combined version, good for typical uses.
1905 // Falls through on failure.
1906 void check_klass_subtype(Register sub_klass,
1907 Register super_klass,
1908 Register temp_reg,
1909 Label& L_success);
1910
1911 // method handles (JSR 292)
1912 void check_method_handle_type(Register mtype_reg, Register mh_reg,
1913 Register temp_reg,
1914 Label& wrong_method_type);
1915 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
1916 Register temp_reg);
1917 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
1918 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1919
1920
1921 //----
1922 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
1923
1924 // Debugging
1925
1926 // only if +VerifyOops
1927 void verify_oop(Register reg, const char* s = "broken oop");
1928 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
1929
1930 // only if +VerifyFPU
1931 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1932
1933 // prints msg, dumps registers and stops execution
1934 void stop(const char* msg);
1935
1936 // prints msg and continues
1937 void warn(const char* msg);
1938
1939 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
1940 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1941
1942 void os_breakpoint();
1943
1944 void untested() { stop("untested"); }
1945
1946 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
1947
1948 void should_not_reach_here() { stop("should not reach here"); }
1949
1950 void print_CPU_state();
1951
1952 // Stack overflow checking
1953 void bang_stack_with_offset(int offset) {
1954 // stack grows down, caller passes positive offset
1955 assert(offset > 0, "must bang with negative offset");
1956 movl(Address(rsp, (-offset)), rax);
1957 }
1958
1959 // Writes to stack successive pages until offset reached to check for
1960 // stack overflow + shadow pages. Also, clobbers tmp
1961 void bang_stack_size(Register size, Register tmp);
1962
1963 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
1964 Register tmp,
1965 int offset);
1966
1967 // Support for serializing memory accesses between threads
1968 void serialize_memory(Register thread, Register tmp);
1969
1970 void verify_tlab();
1971
1972 // Biased locking support
1973 // lock_reg and obj_reg must be loaded up with the appropriate values.
1974 // swap_reg must be rax, and is killed.
1975 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
1976 // be killed; if not supplied, push/pop will be used internally to
1977 // allocate a temporary (inefficient, avoid if possible).
1978 // Optional slow case is for implementations (interpreter and C1) which branch to
1979 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
1980 // Returns offset of first potentially-faulting instruction for null
1981 // check info (currently consumed only by C1). If
1982 // swap_reg_contains_mark is true then returns -1 as it is assumed
1983 // the calling code has already passed any potential faults.
1984 int biased_locking_enter(Register lock_reg, Register obj_reg,
1985 Register swap_reg, Register tmp_reg,
1986 bool swap_reg_contains_mark,
1987 Label& done, Label* slow_case = NULL,
1988 BiasedLockingCounters* counters = NULL);
1989 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
1990
1991
1992 Condition negate_condition(Condition cond);
1993
1994 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
1995 // operands. In general the names are modified to avoid hiding the instruction in Assembler
1996 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
1997 // here in MacroAssembler. The major exception to this rule is call
1998
1999 // Arithmetics
2000
2001
2002 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
2003 void addptr(Address dst, Register src);
2004
2005 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
2006 void addptr(Register dst, int32_t src);
2007 void addptr(Register dst, Register src);
2008
2009 void andptr(Register dst, int32_t src);
2010 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
2011
2012 void cmp8(AddressLiteral src1, int imm);
2013
2014 // renamed to drag out the casting of address to int32_t/intptr_t
2015 void cmp32(Register src1, int32_t imm);
2016
2017 void cmp32(AddressLiteral src1, int32_t imm);
2018 // compare reg - mem, or reg - &mem
2019 void cmp32(Register src1, AddressLiteral src2);
2020
2021 void cmp32(Register src1, Address src2);
2022
2023 #ifndef _LP64
2024 void cmpoop(Address dst, jobject obj);
2025 void cmpoop(Register dst, jobject obj);
2026 #endif // _LP64
2027
2028 // NOTE src2 must be the lval. This is NOT an mem-mem compare
2029 void cmpptr(Address src1, AddressLiteral src2);
2030
2031 void cmpptr(Register src1, AddressLiteral src2);
2032
2033 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2034 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2035 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2036
2037 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2038 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
2039
2040 // cmp64 to avoild hiding cmpq
2041 void cmp64(Register src1, AddressLiteral src);
2042
2043 void cmpxchgptr(Register reg, Address adr);
2044
2045 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
2046
2047
2048 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
2049
2050
2051 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
2052
2053 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
2054
2055 void shlptr(Register dst, int32_t shift);
2056 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
2057
2058 void shrptr(Register dst, int32_t shift);
2059 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
2060
2061 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
2062 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
2063
2064 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2065
2066 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
2067 void subptr(Register dst, int32_t src);
2068 void subptr(Register dst, Register src);
2069
2070
2071 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2072 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
2073
2074 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2075 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
2076
2077 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
2078
2079
2080
2081 // Helper functions for statistics gathering.
2082 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
2083 void cond_inc32(Condition cond, AddressLiteral counter_addr);
2084 // Unconditional atomic increment.
2085 void atomic_incl(AddressLiteral counter_addr);
2086
2087 void lea(Register dst, AddressLiteral adr);
2088 void lea(Address dst, AddressLiteral adr);
2089 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
2090
2091 void leal32(Register dst, Address src) { leal(dst, src); }
2092
2093 void test32(Register src1, AddressLiteral src2);
2094
2095 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2096 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2097 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
2098
2099 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
2100 void testptr(Register src1, Register src2);
2101
2102 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2103 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2104
2105 // Calls
2106
2107 void call(Label& L, relocInfo::relocType rtype);
2108 void call(Register entry);
2109
2110 // NOTE: this call tranfers to the effective address of entry NOT
2111 // the address contained by entry. This is because this is more natural
2112 // for jumps/calls.
2113 void call(AddressLiteral entry);
2114
2115 // Jumps
2116
2117 // NOTE: these jumps tranfer to the effective address of dst NOT
2118 // the address contained by dst. This is because this is more natural
2119 // for jumps/calls.
2120 void jump(AddressLiteral dst);
2121 void jump_cc(Condition cc, AddressLiteral dst);
2122
2123 // 32bit can do a case table jump in one instruction but we no longer allow the base
2124 // to be installed in the Address class. This jump will tranfers to the address
2125 // contained in the location described by entry (not the address of entry)
2126 void jump(ArrayAddress entry);
2127
2128 // Floating
2129
2130 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
2131 void andpd(XMMRegister dst, AddressLiteral src);
2132
2133 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
2134 void comiss(XMMRegister dst, AddressLiteral src);
2135
2136 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
2137 void comisd(XMMRegister dst, AddressLiteral src);
2138
2139 void fadd_s(Address src) { Assembler::fadd_s(src); }
2140 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
2141
2142 void fldcw(Address src) { Assembler::fldcw(src); }
2143 void fldcw(AddressLiteral src);
2144
2145 void fld_s(int index) { Assembler::fld_s(index); }
2146 void fld_s(Address src) { Assembler::fld_s(src); }
2147 void fld_s(AddressLiteral src);
2148
2149 void fld_d(Address src) { Assembler::fld_d(src); }
2150 void fld_d(AddressLiteral src);
2151
2152 void fld_x(Address src) { Assembler::fld_x(src); }
2153 void fld_x(AddressLiteral src);
2154
2155 void fmul_s(Address src) { Assembler::fmul_s(src); }
2156 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
2157
2158 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
2159 void ldmxcsr(AddressLiteral src);
2160
2161 private:
2162 // these are private because users should be doing movflt/movdbl
2163
2164 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
2165 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
2166 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
2167 void movss(XMMRegister dst, AddressLiteral src);
2168
2169 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
2170 void movlpd(XMMRegister dst, AddressLiteral src);
2171
2172 public:
2173
2174 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
2175 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
2176 void addsd(XMMRegister dst, AddressLiteral src) { Assembler::addsd(dst, as_Address(src)); }
2177
2178 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
2179 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
2180 void addss(XMMRegister dst, AddressLiteral src) { Assembler::addss(dst, as_Address(src)); }
2181
2182 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
2183 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
2184 void divsd(XMMRegister dst, AddressLiteral src) { Assembler::divsd(dst, as_Address(src)); }
2185
2186 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
2187 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
2188 void divss(XMMRegister dst, AddressLiteral src) { Assembler::divss(dst, as_Address(src)); }
2189
2190 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
2191 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
2192 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
2193 void movsd(XMMRegister dst, AddressLiteral src) { Assembler::movsd(dst, as_Address(src)); }
2194
2195 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
2196 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
2197 void mulsd(XMMRegister dst, AddressLiteral src) { Assembler::mulsd(dst, as_Address(src)); }
2198
2199 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
2200 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
2201 void mulss(XMMRegister dst, AddressLiteral src) { Assembler::mulss(dst, as_Address(src)); }
2202
2203 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
2204 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
2205 void sqrtsd(XMMRegister dst, AddressLiteral src) { Assembler::sqrtsd(dst, as_Address(src)); }
2206
2207 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
2208 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
2209 void sqrtss(XMMRegister dst, AddressLiteral src) { Assembler::sqrtss(dst, as_Address(src)); }
2210
2211 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
2212 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
2213 void subsd(XMMRegister dst, AddressLiteral src) { Assembler::subsd(dst, as_Address(src)); }
2214
2215 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
2216 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
2217 void subss(XMMRegister dst, AddressLiteral src) { Assembler::subss(dst, as_Address(src)); }
2218
2219 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2220 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
2221 void ucomiss(XMMRegister dst, AddressLiteral src);
2222
2223 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2224 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
2225 void ucomisd(XMMRegister dst, AddressLiteral src);
2226
2227 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2228 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2229 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
2230 void xorpd(XMMRegister dst, AddressLiteral src);
2231
2232 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2233 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2234 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
2235 void xorps(XMMRegister dst, AddressLiteral src);
2236
2237 // Data
2238
2239 void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2240
2241 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2242 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2243
2244 void movoop(Register dst, jobject obj);
2245 void movoop(Address dst, jobject obj);
2246
2247 void movptr(ArrayAddress dst, Register src);
2248 // can this do an lea?
2249 void movptr(Register dst, ArrayAddress src);
2250
2251 void movptr(Register dst, Address src);
2252
2253 void movptr(Register dst, AddressLiteral src);
2254
2255 void movptr(Register dst, intptr_t src);
2256 void movptr(Register dst, Register src);
2257 void movptr(Address dst, intptr_t src);
2258
2259 void movptr(Address dst, Register src);
2260
2261 #ifdef _LP64
2262 // Generally the next two are only used for moving NULL
2263 // Although there are situations in initializing the mark word where
2264 // they could be used. They are dangerous.
2265
2266 // They only exist on LP64 so that int32_t and intptr_t are not the same
2267 // and we have ambiguous declarations.
2268
2269 void movptr(Address dst, int32_t imm32);
2270 void movptr(Register dst, int32_t imm32);
2271 #endif // _LP64
2272
2273 // to avoid hiding movl
2274 void mov32(AddressLiteral dst, Register src);
2275 void mov32(Register dst, AddressLiteral src);
2276
2277 // to avoid hiding movb
2278 void movbyte(ArrayAddress dst, int src);
2279
2280 // Can push value or effective address
2281 void pushptr(AddressLiteral src);
2282
2283 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2284 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2285
2286 void pushoop(jobject obj);
2287
2288 // sign extend as need a l to ptr sized element
2289 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2290 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2291
2292 // IndexOf strings.
2293 void string_indexof(Register str1, Register str2,
2294 Register cnt1, Register cnt2, Register result,
2295 XMMRegister vec, Register tmp);
2296
2297 // Compare strings.
2298 void string_compare(Register str1, Register str2,
2299 Register cnt1, Register cnt2, Register result,
2300 XMMRegister vec1);
2301
2302 // Compare char[] arrays.
2303 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
2304 Register limit, Register result, Register chr,
2305 XMMRegister vec1, XMMRegister vec2);
2306
2307 // Fill primitive arrays
2308 void generate_fill(BasicType t, bool aligned,
2309 Register to, Register value, Register count,
2310 Register rtmp, XMMRegister xtmp);
2311
2312 #undef VIRTUAL
2313
2314 };
2315
2316 /**
2317 * class SkipIfEqual:
2318 *
2319 * Instantiating this class will result in assembly code being output that will
2320 * jump around any code emitted between the creation of the instance and it's
2321 * automatic destruction at the end of a scope block, depending on the value of
2322 * the flag passed to the constructor, which will be checked at run-time.
2323 */
2324 class SkipIfEqual {
2325 private:
2326 MacroAssembler* _masm;
2327 Label _label;
2328
2329 public:
2330 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2331 ~SkipIfEqual();
2332 };
2333
2334 #ifdef ASSERT
2335 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2336 #endif
2337
2338 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP