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--- old/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp
+++ new/src/cpu/x86/vm/c1_LIRGenerator_x86.cpp
1 1 /*
2 2 * Copyright (c) 2005, 2011, Oracle and/or its affiliates. All rights reserved.
3 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 4 *
5 5 * This code is free software; you can redistribute it and/or modify it
6 6 * under the terms of the GNU General Public License version 2 only, as
7 7 * published by the Free Software Foundation.
8 8 *
9 9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 12 * version 2 for more details (a copy is included in the LICENSE file that
13 13 * accompanied this code).
14 14 *
15 15 * You should have received a copy of the GNU General Public License version
16 16 * 2 along with this work; if not, write to the Free Software Foundation,
17 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 18 *
19 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 20 * or visit www.oracle.com if you need additional information or have any
21 21 * questions.
22 22 *
23 23 */
24 24
25 25 #include "precompiled.hpp"
26 26 #include "c1/c1_Compilation.hpp"
27 27 #include "c1/c1_FrameMap.hpp"
28 28 #include "c1/c1_Instruction.hpp"
29 29 #include "c1/c1_LIRAssembler.hpp"
30 30 #include "c1/c1_LIRGenerator.hpp"
31 31 #include "c1/c1_Runtime1.hpp"
32 32 #include "c1/c1_ValueStack.hpp"
33 33 #include "ci/ciArray.hpp"
34 34 #include "ci/ciObjArrayKlass.hpp"
35 35 #include "ci/ciTypeArrayKlass.hpp"
36 36 #include "runtime/sharedRuntime.hpp"
37 37 #include "runtime/stubRoutines.hpp"
38 38 #include "vmreg_x86.inline.hpp"
39 39
40 40 #ifdef ASSERT
41 41 #define __ gen()->lir(__FILE__, __LINE__)->
42 42 #else
43 43 #define __ gen()->lir()->
44 44 #endif
45 45
46 46 // Item will be loaded into a byte register; Intel only
47 47 void LIRItem::load_byte_item() {
48 48 load_item();
49 49 LIR_Opr res = result();
50 50
51 51 if (!res->is_virtual() || !_gen->is_vreg_flag_set(res, LIRGenerator::byte_reg)) {
52 52 // make sure that it is a byte register
53 53 assert(!value()->type()->is_float() && !value()->type()->is_double(),
54 54 "can't load floats in byte register");
55 55 LIR_Opr reg = _gen->rlock_byte(T_BYTE);
56 56 __ move(res, reg);
57 57
58 58 _result = reg;
59 59 }
60 60 }
61 61
62 62
63 63 void LIRItem::load_nonconstant() {
64 64 LIR_Opr r = value()->operand();
65 65 if (r->is_constant()) {
66 66 _result = r;
67 67 } else {
68 68 load_item();
69 69 }
70 70 }
71 71
72 72 //--------------------------------------------------------------
73 73 // LIRGenerator
74 74 //--------------------------------------------------------------
75 75
76 76
77 77 LIR_Opr LIRGenerator::exceptionOopOpr() { return FrameMap::rax_oop_opr; }
78 78 LIR_Opr LIRGenerator::exceptionPcOpr() { return FrameMap::rdx_opr; }
79 79 LIR_Opr LIRGenerator::divInOpr() { return FrameMap::rax_opr; }
80 80 LIR_Opr LIRGenerator::divOutOpr() { return FrameMap::rax_opr; }
81 81 LIR_Opr LIRGenerator::remOutOpr() { return FrameMap::rdx_opr; }
82 82 LIR_Opr LIRGenerator::shiftCountOpr() { return FrameMap::rcx_opr; }
83 83 LIR_Opr LIRGenerator::syncTempOpr() { return FrameMap::rax_opr; }
84 84 LIR_Opr LIRGenerator::getThreadTemp() { return LIR_OprFact::illegalOpr; }
85 85
86 86
87 87 LIR_Opr LIRGenerator::result_register_for(ValueType* type, bool callee) {
88 88 LIR_Opr opr;
89 89 switch (type->tag()) {
90 90 case intTag: opr = FrameMap::rax_opr; break;
91 91 case objectTag: opr = FrameMap::rax_oop_opr; break;
92 92 case longTag: opr = FrameMap::long0_opr; break;
93 93 case floatTag: opr = UseSSE >= 1 ? FrameMap::xmm0_float_opr : FrameMap::fpu0_float_opr; break;
94 94 case doubleTag: opr = UseSSE >= 2 ? FrameMap::xmm0_double_opr : FrameMap::fpu0_double_opr; break;
95 95
96 96 case addressTag:
97 97 default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr;
98 98 }
99 99
100 100 assert(opr->type_field() == as_OprType(as_BasicType(type)), "type mismatch");
101 101 return opr;
102 102 }
103 103
104 104
105 105 LIR_Opr LIRGenerator::rlock_byte(BasicType type) {
106 106 LIR_Opr reg = new_register(T_INT);
107 107 set_vreg_flag(reg, LIRGenerator::byte_reg);
108 108 return reg;
109 109 }
110 110
111 111
112 112 //--------- loading items into registers --------------------------------
113 113
114 114
115 115 // i486 instructions can inline constants
116 116 bool LIRGenerator::can_store_as_constant(Value v, BasicType type) const {
117 117 if (type == T_SHORT || type == T_CHAR) {
118 118 // there is no immediate move of word values in asembler_i486.?pp
119 119 return false;
120 120 }
121 121 Constant* c = v->as_Constant();
122 122 if (c && c->state_before() == NULL) {
123 123 // constants of any type can be stored directly, except for
124 124 // unloaded object constants.
125 125 return true;
126 126 }
127 127 return false;
128 128 }
129 129
130 130
131 131 bool LIRGenerator::can_inline_as_constant(Value v) const {
132 132 if (v->type()->tag() == longTag) return false;
133 133 return v->type()->tag() != objectTag ||
134 134 (v->type()->is_constant() && v->type()->as_ObjectType()->constant_value()->is_null_object());
135 135 }
136 136
137 137
138 138 bool LIRGenerator::can_inline_as_constant(LIR_Const* c) const {
139 139 if (c->type() == T_LONG) return false;
140 140 return c->type() != T_OBJECT || c->as_jobject() == NULL;
141 141 }
142 142
143 143
144 144 LIR_Opr LIRGenerator::safepoint_poll_register() {
145 145 return LIR_OprFact::illegalOpr;
146 146 }
147 147
148 148
149 149 LIR_Address* LIRGenerator::generate_address(LIR_Opr base, LIR_Opr index,
150 150 int shift, int disp, BasicType type) {
151 151 assert(base->is_register(), "must be");
152 152 if (index->is_constant()) {
153 153 return new LIR_Address(base,
154 154 (index->as_constant_ptr()->as_jint() << shift) + disp,
155 155 type);
156 156 } else {
157 157 return new LIR_Address(base, index, (LIR_Address::Scale)shift, disp, type);
158 158 }
159 159 }
160 160
161 161
162 162 LIR_Address* LIRGenerator::emit_array_address(LIR_Opr array_opr, LIR_Opr index_opr,
163 163 BasicType type, bool needs_card_mark) {
164 164 int offset_in_bytes = arrayOopDesc::base_offset_in_bytes(type);
165 165
166 166 LIR_Address* addr;
167 167 if (index_opr->is_constant()) {
168 168 int elem_size = type2aelembytes(type);
169 169 addr = new LIR_Address(array_opr,
170 170 offset_in_bytes + index_opr->as_jint() * elem_size, type);
171 171 } else {
172 172 #ifdef _LP64
173 173 if (index_opr->type() == T_INT) {
174 174 LIR_Opr tmp = new_register(T_LONG);
175 175 __ convert(Bytecodes::_i2l, index_opr, tmp);
176 176 index_opr = tmp;
177 177 }
178 178 #endif // _LP64
179 179 addr = new LIR_Address(array_opr,
180 180 index_opr,
181 181 LIR_Address::scale(type),
182 182 offset_in_bytes, type);
183 183 }
184 184 if (needs_card_mark) {
185 185 // This store will need a precise card mark, so go ahead and
186 186 // compute the full adddres instead of computing once for the
187 187 // store and again for the card mark.
188 188 LIR_Opr tmp = new_pointer_register();
189 189 __ leal(LIR_OprFact::address(addr), tmp);
190 190 return new LIR_Address(tmp, type);
191 191 } else {
192 192 return addr;
193 193 }
194 194 }
195 195
196 196
197 197 LIR_Opr LIRGenerator::load_immediate(int x, BasicType type) {
198 198 LIR_Opr r;
199 199 if (type == T_LONG) {
200 200 r = LIR_OprFact::longConst(x);
201 201 } else if (type == T_INT) {
202 202 r = LIR_OprFact::intConst(x);
203 203 } else {
204 204 ShouldNotReachHere();
205 205 }
206 206 return r;
207 207 }
208 208
209 209 void LIRGenerator::increment_counter(address counter, BasicType type, int step) {
210 210 LIR_Opr pointer = new_pointer_register();
211 211 __ move(LIR_OprFact::intptrConst(counter), pointer);
212 212 LIR_Address* addr = new LIR_Address(pointer, type);
213 213 increment_counter(addr, step);
214 214 }
215 215
216 216
217 217 void LIRGenerator::increment_counter(LIR_Address* addr, int step) {
218 218 __ add((LIR_Opr)addr, LIR_OprFact::intConst(step), (LIR_Opr)addr);
219 219 }
220 220
221 221 void LIRGenerator::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
222 222 __ cmp_mem_int(condition, base, disp, c, info);
223 223 }
224 224
225 225
226 226 void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, int disp, BasicType type, CodeEmitInfo* info) {
227 227 __ cmp_reg_mem(condition, reg, new LIR_Address(base, disp, type), info);
228 228 }
229 229
230 230
231 231 void LIRGenerator::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Opr base, LIR_Opr disp, BasicType type, CodeEmitInfo* info) {
232 232 __ cmp_reg_mem(condition, reg, new LIR_Address(base, disp, type), info);
233 233 }
234 234
235 235
236 236 bool LIRGenerator::strength_reduce_multiply(LIR_Opr left, int c, LIR_Opr result, LIR_Opr tmp) {
237 237 if (tmp->is_valid()) {
238 238 if (is_power_of_2(c + 1)) {
239 239 __ move(left, tmp);
240 240 __ shift_left(left, log2_intptr(c + 1), left);
241 241 __ sub(left, tmp, result);
242 242 return true;
243 243 } else if (is_power_of_2(c - 1)) {
244 244 __ move(left, tmp);
245 245 __ shift_left(left, log2_intptr(c - 1), left);
246 246 __ add(left, tmp, result);
247 247 return true;
248 248 }
249 249 }
250 250 return false;
251 251 }
252 252
253 253
254 254 void LIRGenerator::store_stack_parameter (LIR_Opr item, ByteSize offset_from_sp) {
255 255 BasicType type = item->type();
256 256 __ store(item, new LIR_Address(FrameMap::rsp_opr, in_bytes(offset_from_sp), type));
257 257 }
258 258
259 259 //----------------------------------------------------------------------
260 260 // visitor functions
261 261 //----------------------------------------------------------------------
262 262
263 263
264 264 void LIRGenerator::do_StoreIndexed(StoreIndexed* x) {
265 265 assert(x->is_pinned(),"");
266 266 bool needs_range_check = true;
267 267 bool use_length = x->length() != NULL;
268 268 bool obj_store = x->elt_type() == T_ARRAY || x->elt_type() == T_OBJECT;
269 269 bool needs_store_check = obj_store && (x->value()->as_Constant() == NULL ||
270 270 !get_jobject_constant(x->value())->is_null_object());
271 271
272 272 LIRItem array(x->array(), this);
273 273 LIRItem index(x->index(), this);
274 274 LIRItem value(x->value(), this);
275 275 LIRItem length(this);
276 276
277 277 array.load_item();
278 278 index.load_nonconstant();
279 279
280 280 if (use_length) {
281 281 needs_range_check = x->compute_needs_range_check();
282 282 if (needs_range_check) {
283 283 length.set_instruction(x->length());
284 284 length.load_item();
285 285 }
286 286 }
287 287 if (needs_store_check) {
288 288 value.load_item();
289 289 } else {
290 290 value.load_for_store(x->elt_type());
291 291 }
292 292
293 293 set_no_result(x);
294 294
295 295 // the CodeEmitInfo must be duplicated for each different
296 296 // LIR-instruction because spilling can occur anywhere between two
297 297 // instructions and so the debug information must be different
298 298 CodeEmitInfo* range_check_info = state_for(x);
299 299 CodeEmitInfo* null_check_info = NULL;
300 300 if (x->needs_null_check()) {
301 301 null_check_info = new CodeEmitInfo(range_check_info);
302 302 }
303 303
304 304 // emit array address setup early so it schedules better
305 305 LIR_Address* array_addr = emit_array_address(array.result(), index.result(), x->elt_type(), obj_store);
306 306
307 307 if (GenerateRangeChecks && needs_range_check) {
308 308 if (use_length) {
309 309 __ cmp(lir_cond_belowEqual, length.result(), index.result());
310 310 __ branch(lir_cond_belowEqual, T_INT, new RangeCheckStub(range_check_info, index.result()));
311 311 } else {
312 312 array_range_check(array.result(), index.result(), null_check_info, range_check_info);
313 313 // range_check also does the null check
314 314 null_check_info = NULL;
315 315 }
316 316 }
317 317
318 318 if (GenerateArrayStoreCheck && needs_store_check) {
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319 319 LIR_Opr tmp1 = new_register(objectType);
320 320 LIR_Opr tmp2 = new_register(objectType);
321 321 LIR_Opr tmp3 = new_register(objectType);
322 322
323 323 CodeEmitInfo* store_check_info = new CodeEmitInfo(range_check_info);
324 324 __ store_check(value.result(), array.result(), tmp1, tmp2, tmp3, store_check_info);
325 325 }
326 326
327 327 if (obj_store) {
328 328 // Needs GC write barriers.
329 - pre_barrier(LIR_OprFact::address(array_addr), false, NULL);
329 + pre_barrier(LIR_OprFact::address(array_addr), LIR_OprFact::illegalOpr /* pre_val */,
330 + true /* do_load */, false /* patch */, NULL);
330 331 __ move(value.result(), array_addr, null_check_info);
331 332 // Seems to be a precise
332 333 post_barrier(LIR_OprFact::address(array_addr), value.result());
333 334 } else {
334 335 __ move(value.result(), array_addr, null_check_info);
335 336 }
336 337 }
337 338
338 339
339 340 void LIRGenerator::do_MonitorEnter(MonitorEnter* x) {
340 341 assert(x->is_pinned(),"");
341 342 LIRItem obj(x->obj(), this);
342 343 obj.load_item();
343 344
344 345 set_no_result(x);
345 346
346 347 // "lock" stores the address of the monitor stack slot, so this is not an oop
347 348 LIR_Opr lock = new_register(T_INT);
348 349 // Need a scratch register for biased locking on x86
349 350 LIR_Opr scratch = LIR_OprFact::illegalOpr;
350 351 if (UseBiasedLocking) {
351 352 scratch = new_register(T_INT);
352 353 }
353 354
354 355 CodeEmitInfo* info_for_exception = NULL;
355 356 if (x->needs_null_check()) {
356 357 info_for_exception = state_for(x);
357 358 }
358 359 // this CodeEmitInfo must not have the xhandlers because here the
359 360 // object is already locked (xhandlers expect object to be unlocked)
360 361 CodeEmitInfo* info = state_for(x, x->state(), true);
361 362 monitor_enter(obj.result(), lock, syncTempOpr(), scratch,
362 363 x->monitor_no(), info_for_exception, info);
363 364 }
364 365
365 366
366 367 void LIRGenerator::do_MonitorExit(MonitorExit* x) {
367 368 assert(x->is_pinned(),"");
368 369
369 370 LIRItem obj(x->obj(), this);
370 371 obj.dont_load_item();
371 372
372 373 LIR_Opr lock = new_register(T_INT);
373 374 LIR_Opr obj_temp = new_register(T_INT);
374 375 set_no_result(x);
375 376 monitor_exit(obj_temp, lock, syncTempOpr(), LIR_OprFact::illegalOpr, x->monitor_no());
376 377 }
377 378
378 379
379 380 // _ineg, _lneg, _fneg, _dneg
380 381 void LIRGenerator::do_NegateOp(NegateOp* x) {
381 382 LIRItem value(x->x(), this);
382 383 value.set_destroys_register();
383 384 value.load_item();
384 385 LIR_Opr reg = rlock(x);
385 386 __ negate(value.result(), reg);
386 387
387 388 set_result(x, round_item(reg));
388 389 }
389 390
390 391
391 392 // for _fadd, _fmul, _fsub, _fdiv, _frem
392 393 // _dadd, _dmul, _dsub, _ddiv, _drem
393 394 void LIRGenerator::do_ArithmeticOp_FPU(ArithmeticOp* x) {
394 395 LIRItem left(x->x(), this);
395 396 LIRItem right(x->y(), this);
396 397 LIRItem* left_arg = &left;
397 398 LIRItem* right_arg = &right;
398 399 assert(!left.is_stack() || !right.is_stack(), "can't both be memory operands");
399 400 bool must_load_both = (x->op() == Bytecodes::_frem || x->op() == Bytecodes::_drem);
400 401 if (left.is_register() || x->x()->type()->is_constant() || must_load_both) {
401 402 left.load_item();
402 403 } else {
403 404 left.dont_load_item();
404 405 }
405 406
406 407 // do not load right operand if it is a constant. only 0 and 1 are
407 408 // loaded because there are special instructions for loading them
408 409 // without memory access (not needed for SSE2 instructions)
409 410 bool must_load_right = false;
410 411 if (right.is_constant()) {
411 412 LIR_Const* c = right.result()->as_constant_ptr();
412 413 assert(c != NULL, "invalid constant");
413 414 assert(c->type() == T_FLOAT || c->type() == T_DOUBLE, "invalid type");
414 415
415 416 if (c->type() == T_FLOAT) {
416 417 must_load_right = UseSSE < 1 && (c->is_one_float() || c->is_zero_float());
417 418 } else {
418 419 must_load_right = UseSSE < 2 && (c->is_one_double() || c->is_zero_double());
419 420 }
420 421 }
421 422
422 423 if (must_load_both) {
423 424 // frem and drem destroy also right operand, so move it to a new register
424 425 right.set_destroys_register();
425 426 right.load_item();
426 427 } else if (right.is_register() || must_load_right) {
427 428 right.load_item();
428 429 } else {
429 430 right.dont_load_item();
430 431 }
431 432 LIR_Opr reg = rlock(x);
432 433 LIR_Opr tmp = LIR_OprFact::illegalOpr;
433 434 if (x->is_strictfp() && (x->op() == Bytecodes::_dmul || x->op() == Bytecodes::_ddiv)) {
434 435 tmp = new_register(T_DOUBLE);
435 436 }
436 437
437 438 if ((UseSSE >= 1 && x->op() == Bytecodes::_frem) || (UseSSE >= 2 && x->op() == Bytecodes::_drem)) {
438 439 // special handling for frem and drem: no SSE instruction, so must use FPU with temporary fpu stack slots
439 440 LIR_Opr fpu0, fpu1;
440 441 if (x->op() == Bytecodes::_frem) {
441 442 fpu0 = LIR_OprFact::single_fpu(0);
442 443 fpu1 = LIR_OprFact::single_fpu(1);
443 444 } else {
444 445 fpu0 = LIR_OprFact::double_fpu(0);
445 446 fpu1 = LIR_OprFact::double_fpu(1);
446 447 }
447 448 __ move(right.result(), fpu1); // order of left and right operand is important!
448 449 __ move(left.result(), fpu0);
449 450 __ rem (fpu0, fpu1, fpu0);
450 451 __ move(fpu0, reg);
451 452
452 453 } else {
453 454 arithmetic_op_fpu(x->op(), reg, left.result(), right.result(), x->is_strictfp(), tmp);
454 455 }
455 456
456 457 set_result(x, round_item(reg));
457 458 }
458 459
459 460
460 461 // for _ladd, _lmul, _lsub, _ldiv, _lrem
461 462 void LIRGenerator::do_ArithmeticOp_Long(ArithmeticOp* x) {
462 463 if (x->op() == Bytecodes::_ldiv || x->op() == Bytecodes::_lrem ) {
463 464 // long division is implemented as a direct call into the runtime
464 465 LIRItem left(x->x(), this);
465 466 LIRItem right(x->y(), this);
466 467
467 468 // the check for division by zero destroys the right operand
468 469 right.set_destroys_register();
469 470
470 471 BasicTypeList signature(2);
471 472 signature.append(T_LONG);
472 473 signature.append(T_LONG);
473 474 CallingConvention* cc = frame_map()->c_calling_convention(&signature);
474 475
475 476 // check for division by zero (destroys registers of right operand!)
476 477 CodeEmitInfo* info = state_for(x);
477 478
478 479 const LIR_Opr result_reg = result_register_for(x->type());
479 480 left.load_item_force(cc->at(1));
480 481 right.load_item();
481 482
482 483 __ move(right.result(), cc->at(0));
483 484
484 485 __ cmp(lir_cond_equal, right.result(), LIR_OprFact::longConst(0));
485 486 __ branch(lir_cond_equal, T_LONG, new DivByZeroStub(info));
486 487
487 488 address entry;
488 489 switch (x->op()) {
489 490 case Bytecodes::_lrem:
490 491 entry = CAST_FROM_FN_PTR(address, SharedRuntime::lrem);
491 492 break; // check if dividend is 0 is done elsewhere
492 493 case Bytecodes::_ldiv:
493 494 entry = CAST_FROM_FN_PTR(address, SharedRuntime::ldiv);
494 495 break; // check if dividend is 0 is done elsewhere
495 496 case Bytecodes::_lmul:
496 497 entry = CAST_FROM_FN_PTR(address, SharedRuntime::lmul);
497 498 break;
498 499 default:
499 500 ShouldNotReachHere();
500 501 }
501 502
502 503 LIR_Opr result = rlock_result(x);
503 504 __ call_runtime_leaf(entry, getThreadTemp(), result_reg, cc->args());
504 505 __ move(result_reg, result);
505 506 } else if (x->op() == Bytecodes::_lmul) {
506 507 // missing test if instr is commutative and if we should swap
507 508 LIRItem left(x->x(), this);
508 509 LIRItem right(x->y(), this);
509 510
510 511 // right register is destroyed by the long mul, so it must be
511 512 // copied to a new register.
512 513 right.set_destroys_register();
513 514
514 515 left.load_item();
515 516 right.load_item();
516 517
517 518 LIR_Opr reg = FrameMap::long0_opr;
518 519 arithmetic_op_long(x->op(), reg, left.result(), right.result(), NULL);
519 520 LIR_Opr result = rlock_result(x);
520 521 __ move(reg, result);
521 522 } else {
522 523 // missing test if instr is commutative and if we should swap
523 524 LIRItem left(x->x(), this);
524 525 LIRItem right(x->y(), this);
525 526
526 527 left.load_item();
527 528 // don't load constants to save register
528 529 right.load_nonconstant();
529 530 rlock_result(x);
530 531 arithmetic_op_long(x->op(), x->operand(), left.result(), right.result(), NULL);
531 532 }
532 533 }
533 534
534 535
535 536
536 537 // for: _iadd, _imul, _isub, _idiv, _irem
537 538 void LIRGenerator::do_ArithmeticOp_Int(ArithmeticOp* x) {
538 539 if (x->op() == Bytecodes::_idiv || x->op() == Bytecodes::_irem) {
539 540 // The requirements for division and modulo
540 541 // input : rax,: dividend min_int
541 542 // reg: divisor (may not be rax,/rdx) -1
542 543 //
543 544 // output: rax,: quotient (= rax, idiv reg) min_int
544 545 // rdx: remainder (= rax, irem reg) 0
545 546
546 547 // rax, and rdx will be destroyed
547 548
548 549 // Note: does this invalidate the spec ???
549 550 LIRItem right(x->y(), this);
550 551 LIRItem left(x->x() , this); // visit left second, so that the is_register test is valid
551 552
552 553 // call state_for before load_item_force because state_for may
553 554 // force the evaluation of other instructions that are needed for
554 555 // correct debug info. Otherwise the live range of the fix
555 556 // register might be too long.
556 557 CodeEmitInfo* info = state_for(x);
557 558
558 559 left.load_item_force(divInOpr());
559 560
560 561 right.load_item();
561 562
562 563 LIR_Opr result = rlock_result(x);
563 564 LIR_Opr result_reg;
564 565 if (x->op() == Bytecodes::_idiv) {
565 566 result_reg = divOutOpr();
566 567 } else {
567 568 result_reg = remOutOpr();
568 569 }
569 570
570 571 if (!ImplicitDiv0Checks) {
571 572 __ cmp(lir_cond_equal, right.result(), LIR_OprFact::intConst(0));
572 573 __ branch(lir_cond_equal, T_INT, new DivByZeroStub(info));
573 574 }
574 575 LIR_Opr tmp = FrameMap::rdx_opr; // idiv and irem use rdx in their implementation
575 576 if (x->op() == Bytecodes::_irem) {
576 577 __ irem(left.result(), right.result(), result_reg, tmp, info);
577 578 } else if (x->op() == Bytecodes::_idiv) {
578 579 __ idiv(left.result(), right.result(), result_reg, tmp, info);
579 580 } else {
580 581 ShouldNotReachHere();
581 582 }
582 583
583 584 __ move(result_reg, result);
584 585 } else {
585 586 // missing test if instr is commutative and if we should swap
586 587 LIRItem left(x->x(), this);
587 588 LIRItem right(x->y(), this);
588 589 LIRItem* left_arg = &left;
589 590 LIRItem* right_arg = &right;
590 591 if (x->is_commutative() && left.is_stack() && right.is_register()) {
591 592 // swap them if left is real stack (or cached) and right is real register(not cached)
592 593 left_arg = &right;
593 594 right_arg = &left;
594 595 }
595 596
596 597 left_arg->load_item();
597 598
598 599 // do not need to load right, as we can handle stack and constants
599 600 if (x->op() == Bytecodes::_imul ) {
600 601 // check if we can use shift instead
601 602 bool use_constant = false;
602 603 bool use_tmp = false;
603 604 if (right_arg->is_constant()) {
604 605 int iconst = right_arg->get_jint_constant();
605 606 if (iconst > 0) {
606 607 if (is_power_of_2(iconst)) {
607 608 use_constant = true;
608 609 } else if (is_power_of_2(iconst - 1) || is_power_of_2(iconst + 1)) {
609 610 use_constant = true;
610 611 use_tmp = true;
611 612 }
612 613 }
613 614 }
614 615 if (use_constant) {
615 616 right_arg->dont_load_item();
616 617 } else {
617 618 right_arg->load_item();
618 619 }
619 620 LIR_Opr tmp = LIR_OprFact::illegalOpr;
620 621 if (use_tmp) {
621 622 tmp = new_register(T_INT);
622 623 }
623 624 rlock_result(x);
624 625
625 626 arithmetic_op_int(x->op(), x->operand(), left_arg->result(), right_arg->result(), tmp);
626 627 } else {
627 628 right_arg->dont_load_item();
628 629 rlock_result(x);
629 630 LIR_Opr tmp = LIR_OprFact::illegalOpr;
630 631 arithmetic_op_int(x->op(), x->operand(), left_arg->result(), right_arg->result(), tmp);
631 632 }
632 633 }
633 634 }
634 635
635 636
636 637 void LIRGenerator::do_ArithmeticOp(ArithmeticOp* x) {
637 638 // when an operand with use count 1 is the left operand, then it is
638 639 // likely that no move for 2-operand-LIR-form is necessary
639 640 if (x->is_commutative() && x->y()->as_Constant() == NULL && x->x()->use_count() > x->y()->use_count()) {
640 641 x->swap_operands();
641 642 }
642 643
643 644 ValueTag tag = x->type()->tag();
644 645 assert(x->x()->type()->tag() == tag && x->y()->type()->tag() == tag, "wrong parameters");
645 646 switch (tag) {
646 647 case floatTag:
647 648 case doubleTag: do_ArithmeticOp_FPU(x); return;
648 649 case longTag: do_ArithmeticOp_Long(x); return;
649 650 case intTag: do_ArithmeticOp_Int(x); return;
650 651 }
651 652 ShouldNotReachHere();
652 653 }
653 654
654 655
655 656 // _ishl, _lshl, _ishr, _lshr, _iushr, _lushr
656 657 void LIRGenerator::do_ShiftOp(ShiftOp* x) {
657 658 // count must always be in rcx
658 659 LIRItem value(x->x(), this);
659 660 LIRItem count(x->y(), this);
660 661
661 662 ValueTag elemType = x->type()->tag();
662 663 bool must_load_count = !count.is_constant() || elemType == longTag;
663 664 if (must_load_count) {
664 665 // count for long must be in register
665 666 count.load_item_force(shiftCountOpr());
666 667 } else {
667 668 count.dont_load_item();
668 669 }
669 670 value.load_item();
670 671 LIR_Opr reg = rlock_result(x);
671 672
672 673 shift_op(x->op(), reg, value.result(), count.result(), LIR_OprFact::illegalOpr);
673 674 }
674 675
675 676
676 677 // _iand, _land, _ior, _lor, _ixor, _lxor
677 678 void LIRGenerator::do_LogicOp(LogicOp* x) {
678 679 // when an operand with use count 1 is the left operand, then it is
679 680 // likely that no move for 2-operand-LIR-form is necessary
680 681 if (x->is_commutative() && x->y()->as_Constant() == NULL && x->x()->use_count() > x->y()->use_count()) {
681 682 x->swap_operands();
682 683 }
683 684
684 685 LIRItem left(x->x(), this);
685 686 LIRItem right(x->y(), this);
686 687
687 688 left.load_item();
688 689 right.load_nonconstant();
689 690 LIR_Opr reg = rlock_result(x);
690 691
691 692 logic_op(x->op(), reg, left.result(), right.result());
692 693 }
693 694
694 695
695 696
696 697 // _lcmp, _fcmpl, _fcmpg, _dcmpl, _dcmpg
697 698 void LIRGenerator::do_CompareOp(CompareOp* x) {
698 699 LIRItem left(x->x(), this);
699 700 LIRItem right(x->y(), this);
700 701 ValueTag tag = x->x()->type()->tag();
701 702 if (tag == longTag) {
702 703 left.set_destroys_register();
703 704 }
704 705 left.load_item();
705 706 right.load_item();
706 707 LIR_Opr reg = rlock_result(x);
707 708
708 709 if (x->x()->type()->is_float_kind()) {
709 710 Bytecodes::Code code = x->op();
710 711 __ fcmp2int(left.result(), right.result(), reg, (code == Bytecodes::_fcmpl || code == Bytecodes::_dcmpl));
711 712 } else if (x->x()->type()->tag() == longTag) {
712 713 __ lcmp2int(left.result(), right.result(), reg);
713 714 } else {
714 715 Unimplemented();
715 716 }
716 717 }
717 718
718 719
719 720 void LIRGenerator::do_AttemptUpdate(Intrinsic* x) {
720 721 assert(x->number_of_arguments() == 3, "wrong type");
721 722 LIRItem obj (x->argument_at(0), this); // AtomicLong object
722 723 LIRItem cmp_value (x->argument_at(1), this); // value to compare with field
723 724 LIRItem new_value (x->argument_at(2), this); // replace field with new_value if it matches cmp_value
724 725
725 726 // compare value must be in rdx,eax (hi,lo); may be destroyed by cmpxchg8 instruction
726 727 cmp_value.load_item_force(FrameMap::long0_opr);
727 728
728 729 // new value must be in rcx,ebx (hi,lo)
729 730 new_value.load_item_force(FrameMap::long1_opr);
730 731
731 732 // object pointer register is overwritten with field address
732 733 obj.load_item();
733 734
734 735 // generate compare-and-swap; produces zero condition if swap occurs
735 736 int value_offset = sun_misc_AtomicLongCSImpl::value_offset();
736 737 LIR_Opr addr = new_pointer_register();
737 738 __ leal(LIR_OprFact::address(new LIR_Address(obj.result(), value_offset, T_LONG)), addr);
738 739 LIR_Opr t1 = LIR_OprFact::illegalOpr; // no temp needed
739 740 LIR_Opr t2 = LIR_OprFact::illegalOpr; // no temp needed
740 741 __ cas_long(addr, cmp_value.result(), new_value.result(), t1, t2);
741 742
742 743 // generate conditional move of boolean result
743 744 LIR_Opr result = rlock_result(x);
744 745 __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0), result, T_LONG);
745 746 }
746 747
747 748
748 749 void LIRGenerator::do_CompareAndSwap(Intrinsic* x, ValueType* type) {
749 750 assert(x->number_of_arguments() == 4, "wrong type");
750 751 LIRItem obj (x->argument_at(0), this); // object
751 752 LIRItem offset(x->argument_at(1), this); // offset of field
752 753 LIRItem cmp (x->argument_at(2), this); // value to compare with field
753 754 LIRItem val (x->argument_at(3), this); // replace field with val if matches cmp
754 755
755 756 assert(obj.type()->tag() == objectTag, "invalid type");
756 757
757 758 // In 64bit the type can be long, sparc doesn't have this assert
758 759 // assert(offset.type()->tag() == intTag, "invalid type");
759 760
760 761 assert(cmp.type()->tag() == type->tag(), "invalid type");
761 762 assert(val.type()->tag() == type->tag(), "invalid type");
762 763
763 764 // get address of field
764 765 obj.load_item();
765 766 offset.load_nonconstant();
766 767
767 768 if (type == objectType) {
768 769 cmp.load_item_force(FrameMap::rax_oop_opr);
769 770 val.load_item();
770 771 } else if (type == intType) {
771 772 cmp.load_item_force(FrameMap::rax_opr);
772 773 val.load_item();
773 774 } else if (type == longType) {
774 775 cmp.load_item_force(FrameMap::long0_opr);
775 776 val.load_item_force(FrameMap::long1_opr);
776 777 } else {
777 778 ShouldNotReachHere();
778 779 }
779 780
780 781 LIR_Opr addr = new_pointer_register();
781 782 LIR_Address* a;
782 783 if(offset.result()->is_constant()) {
783 784 a = new LIR_Address(obj.result(),
784 785 NOT_LP64(offset.result()->as_constant_ptr()->as_jint()) LP64_ONLY((int)offset.result()->as_constant_ptr()->as_jlong()),
785 786 as_BasicType(type));
786 787 } else {
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787 788 a = new LIR_Address(obj.result(),
788 789 offset.result(),
789 790 LIR_Address::times_1,
790 791 0,
791 792 as_BasicType(type));
792 793 }
793 794 __ leal(LIR_OprFact::address(a), addr);
794 795
795 796 if (type == objectType) { // Write-barrier needed for Object fields.
796 797 // Do the pre-write barrier, if any.
797 - pre_barrier(addr, false, NULL);
798 + pre_barrier(addr, LIR_OprFact::illegalOpr /* pre_val */,
799 + true /* do_load */, false /* patch */, NULL);
798 800 }
799 801
800 802 LIR_Opr ill = LIR_OprFact::illegalOpr; // for convenience
801 803 if (type == objectType)
802 804 __ cas_obj(addr, cmp.result(), val.result(), ill, ill);
803 805 else if (type == intType)
804 806 __ cas_int(addr, cmp.result(), val.result(), ill, ill);
805 807 else if (type == longType)
806 808 __ cas_long(addr, cmp.result(), val.result(), ill, ill);
807 809 else {
808 810 ShouldNotReachHere();
809 811 }
810 812
811 813 // generate conditional move of boolean result
812 814 LIR_Opr result = rlock_result(x);
813 815 __ cmove(lir_cond_equal, LIR_OprFact::intConst(1), LIR_OprFact::intConst(0),
814 816 result, as_BasicType(type));
815 817 if (type == objectType) { // Write-barrier needed for Object fields.
816 818 // Seems to be precise
817 819 post_barrier(addr, val.result());
818 820 }
819 821 }
820 822
821 823
822 824 void LIRGenerator::do_MathIntrinsic(Intrinsic* x) {
823 825 assert(x->number_of_arguments() == 1, "wrong type");
824 826 LIRItem value(x->argument_at(0), this);
825 827
826 828 bool use_fpu = false;
827 829 if (UseSSE >= 2) {
828 830 switch(x->id()) {
829 831 case vmIntrinsics::_dsin:
830 832 case vmIntrinsics::_dcos:
831 833 case vmIntrinsics::_dtan:
832 834 case vmIntrinsics::_dlog:
833 835 case vmIntrinsics::_dlog10:
834 836 use_fpu = true;
835 837 }
836 838 } else {
837 839 value.set_destroys_register();
838 840 }
839 841
840 842 value.load_item();
841 843
842 844 LIR_Opr calc_input = value.result();
843 845 LIR_Opr calc_result = rlock_result(x);
844 846
845 847 // sin and cos need two free fpu stack slots, so register two temporary operands
846 848 LIR_Opr tmp1 = FrameMap::caller_save_fpu_reg_at(0);
847 849 LIR_Opr tmp2 = FrameMap::caller_save_fpu_reg_at(1);
848 850
849 851 if (use_fpu) {
850 852 LIR_Opr tmp = FrameMap::fpu0_double_opr;
851 853 __ move(calc_input, tmp);
852 854
853 855 calc_input = tmp;
854 856 calc_result = tmp;
855 857 tmp1 = FrameMap::caller_save_fpu_reg_at(1);
856 858 tmp2 = FrameMap::caller_save_fpu_reg_at(2);
857 859 }
858 860
859 861 switch(x->id()) {
860 862 case vmIntrinsics::_dabs: __ abs (calc_input, calc_result, LIR_OprFact::illegalOpr); break;
861 863 case vmIntrinsics::_dsqrt: __ sqrt (calc_input, calc_result, LIR_OprFact::illegalOpr); break;
862 864 case vmIntrinsics::_dsin: __ sin (calc_input, calc_result, tmp1, tmp2); break;
863 865 case vmIntrinsics::_dcos: __ cos (calc_input, calc_result, tmp1, tmp2); break;
864 866 case vmIntrinsics::_dtan: __ tan (calc_input, calc_result, tmp1, tmp2); break;
865 867 case vmIntrinsics::_dlog: __ log (calc_input, calc_result, tmp1); break;
866 868 case vmIntrinsics::_dlog10: __ log10(calc_input, calc_result, tmp1); break;
867 869 default: ShouldNotReachHere();
868 870 }
869 871
870 872 if (use_fpu) {
871 873 __ move(calc_result, x->operand());
872 874 }
873 875 }
874 876
875 877
876 878 void LIRGenerator::do_ArrayCopy(Intrinsic* x) {
877 879 assert(x->number_of_arguments() == 5, "wrong type");
878 880
879 881 // Make all state_for calls early since they can emit code
880 882 CodeEmitInfo* info = state_for(x, x->state());
881 883
882 884 LIRItem src(x->argument_at(0), this);
883 885 LIRItem src_pos(x->argument_at(1), this);
884 886 LIRItem dst(x->argument_at(2), this);
885 887 LIRItem dst_pos(x->argument_at(3), this);
886 888 LIRItem length(x->argument_at(4), this);
887 889
888 890 // operands for arraycopy must use fixed registers, otherwise
889 891 // LinearScan will fail allocation (because arraycopy always needs a
890 892 // call)
891 893
892 894 #ifndef _LP64
893 895 src.load_item_force (FrameMap::rcx_oop_opr);
894 896 src_pos.load_item_force (FrameMap::rdx_opr);
895 897 dst.load_item_force (FrameMap::rax_oop_opr);
896 898 dst_pos.load_item_force (FrameMap::rbx_opr);
897 899 length.load_item_force (FrameMap::rdi_opr);
898 900 LIR_Opr tmp = (FrameMap::rsi_opr);
899 901 #else
900 902
901 903 // The java calling convention will give us enough registers
902 904 // so that on the stub side the args will be perfect already.
903 905 // On the other slow/special case side we call C and the arg
904 906 // positions are not similar enough to pick one as the best.
905 907 // Also because the java calling convention is a "shifted" version
906 908 // of the C convention we can process the java args trivially into C
907 909 // args without worry of overwriting during the xfer
908 910
909 911 src.load_item_force (FrameMap::as_oop_opr(j_rarg0));
910 912 src_pos.load_item_force (FrameMap::as_opr(j_rarg1));
911 913 dst.load_item_force (FrameMap::as_oop_opr(j_rarg2));
912 914 dst_pos.load_item_force (FrameMap::as_opr(j_rarg3));
913 915 length.load_item_force (FrameMap::as_opr(j_rarg4));
914 916
915 917 LIR_Opr tmp = FrameMap::as_opr(j_rarg5);
916 918 #endif // LP64
917 919
918 920 set_no_result(x);
919 921
920 922 int flags;
921 923 ciArrayKlass* expected_type;
922 924 arraycopy_helper(x, &flags, &expected_type);
923 925
924 926 __ arraycopy(src.result(), src_pos.result(), dst.result(), dst_pos.result(), length.result(), tmp, expected_type, flags, info); // does add_safepoint
925 927 }
926 928
927 929
928 930 // _i2l, _i2f, _i2d, _l2i, _l2f, _l2d, _f2i, _f2l, _f2d, _d2i, _d2l, _d2f
929 931 // _i2b, _i2c, _i2s
930 932 LIR_Opr fixed_register_for(BasicType type) {
931 933 switch (type) {
932 934 case T_FLOAT: return FrameMap::fpu0_float_opr;
933 935 case T_DOUBLE: return FrameMap::fpu0_double_opr;
934 936 case T_INT: return FrameMap::rax_opr;
935 937 case T_LONG: return FrameMap::long0_opr;
936 938 default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr;
937 939 }
938 940 }
939 941
940 942 void LIRGenerator::do_Convert(Convert* x) {
941 943 // flags that vary for the different operations and different SSE-settings
942 944 bool fixed_input, fixed_result, round_result, needs_stub;
943 945
944 946 switch (x->op()) {
945 947 case Bytecodes::_i2l: // fall through
946 948 case Bytecodes::_l2i: // fall through
947 949 case Bytecodes::_i2b: // fall through
948 950 case Bytecodes::_i2c: // fall through
949 951 case Bytecodes::_i2s: fixed_input = false; fixed_result = false; round_result = false; needs_stub = false; break;
950 952
951 953 case Bytecodes::_f2d: fixed_input = UseSSE == 1; fixed_result = false; round_result = false; needs_stub = false; break;
952 954 case Bytecodes::_d2f: fixed_input = false; fixed_result = UseSSE == 1; round_result = UseSSE < 1; needs_stub = false; break;
953 955 case Bytecodes::_i2f: fixed_input = false; fixed_result = false; round_result = UseSSE < 1; needs_stub = false; break;
954 956 case Bytecodes::_i2d: fixed_input = false; fixed_result = false; round_result = false; needs_stub = false; break;
955 957 case Bytecodes::_f2i: fixed_input = false; fixed_result = false; round_result = false; needs_stub = true; break;
956 958 case Bytecodes::_d2i: fixed_input = false; fixed_result = false; round_result = false; needs_stub = true; break;
957 959 case Bytecodes::_l2f: fixed_input = false; fixed_result = UseSSE >= 1; round_result = UseSSE < 1; needs_stub = false; break;
958 960 case Bytecodes::_l2d: fixed_input = false; fixed_result = UseSSE >= 2; round_result = UseSSE < 2; needs_stub = false; break;
959 961 case Bytecodes::_f2l: fixed_input = true; fixed_result = true; round_result = false; needs_stub = false; break;
960 962 case Bytecodes::_d2l: fixed_input = true; fixed_result = true; round_result = false; needs_stub = false; break;
961 963 default: ShouldNotReachHere();
962 964 }
963 965
964 966 LIRItem value(x->value(), this);
965 967 value.load_item();
966 968 LIR_Opr input = value.result();
967 969 LIR_Opr result = rlock(x);
968 970
969 971 // arguments of lir_convert
970 972 LIR_Opr conv_input = input;
971 973 LIR_Opr conv_result = result;
972 974 ConversionStub* stub = NULL;
973 975
974 976 if (fixed_input) {
975 977 conv_input = fixed_register_for(input->type());
976 978 __ move(input, conv_input);
977 979 }
978 980
979 981 assert(fixed_result == false || round_result == false, "cannot set both");
980 982 if (fixed_result) {
981 983 conv_result = fixed_register_for(result->type());
982 984 } else if (round_result) {
983 985 result = new_register(result->type());
984 986 set_vreg_flag(result, must_start_in_memory);
985 987 }
986 988
987 989 if (needs_stub) {
988 990 stub = new ConversionStub(x->op(), conv_input, conv_result);
989 991 }
990 992
991 993 __ convert(x->op(), conv_input, conv_result, stub);
992 994
993 995 if (result != conv_result) {
994 996 __ move(conv_result, result);
995 997 }
996 998
997 999 assert(result->is_virtual(), "result must be virtual register");
998 1000 set_result(x, result);
999 1001 }
1000 1002
1001 1003
1002 1004 void LIRGenerator::do_NewInstance(NewInstance* x) {
1003 1005 #ifndef PRODUCT
1004 1006 if (PrintNotLoaded && !x->klass()->is_loaded()) {
1005 1007 tty->print_cr(" ###class not loaded at new bci %d", x->printable_bci());
1006 1008 }
1007 1009 #endif
1008 1010 CodeEmitInfo* info = state_for(x, x->state());
1009 1011 LIR_Opr reg = result_register_for(x->type());
1010 1012 LIR_Opr klass_reg = new_register(objectType);
1011 1013 new_instance(reg, x->klass(),
1012 1014 FrameMap::rcx_oop_opr,
1013 1015 FrameMap::rdi_oop_opr,
1014 1016 FrameMap::rsi_oop_opr,
1015 1017 LIR_OprFact::illegalOpr,
1016 1018 FrameMap::rdx_oop_opr, info);
1017 1019 LIR_Opr result = rlock_result(x);
1018 1020 __ move(reg, result);
1019 1021 }
1020 1022
1021 1023
1022 1024 void LIRGenerator::do_NewTypeArray(NewTypeArray* x) {
1023 1025 CodeEmitInfo* info = state_for(x, x->state());
1024 1026
1025 1027 LIRItem length(x->length(), this);
1026 1028 length.load_item_force(FrameMap::rbx_opr);
1027 1029
1028 1030 LIR_Opr reg = result_register_for(x->type());
1029 1031 LIR_Opr tmp1 = FrameMap::rcx_oop_opr;
1030 1032 LIR_Opr tmp2 = FrameMap::rsi_oop_opr;
1031 1033 LIR_Opr tmp3 = FrameMap::rdi_oop_opr;
1032 1034 LIR_Opr tmp4 = reg;
1033 1035 LIR_Opr klass_reg = FrameMap::rdx_oop_opr;
1034 1036 LIR_Opr len = length.result();
1035 1037 BasicType elem_type = x->elt_type();
1036 1038
1037 1039 __ oop2reg(ciTypeArrayKlass::make(elem_type)->constant_encoding(), klass_reg);
1038 1040
1039 1041 CodeStub* slow_path = new NewTypeArrayStub(klass_reg, len, reg, info);
1040 1042 __ allocate_array(reg, len, tmp1, tmp2, tmp3, tmp4, elem_type, klass_reg, slow_path);
1041 1043
1042 1044 LIR_Opr result = rlock_result(x);
1043 1045 __ move(reg, result);
1044 1046 }
1045 1047
1046 1048
1047 1049 void LIRGenerator::do_NewObjectArray(NewObjectArray* x) {
1048 1050 LIRItem length(x->length(), this);
1049 1051 // in case of patching (i.e., object class is not yet loaded), we need to reexecute the instruction
1050 1052 // and therefore provide the state before the parameters have been consumed
1051 1053 CodeEmitInfo* patching_info = NULL;
1052 1054 if (!x->klass()->is_loaded() || PatchALot) {
1053 1055 patching_info = state_for(x, x->state_before());
1054 1056 }
1055 1057
1056 1058 CodeEmitInfo* info = state_for(x, x->state());
1057 1059
1058 1060 const LIR_Opr reg = result_register_for(x->type());
1059 1061 LIR_Opr tmp1 = FrameMap::rcx_oop_opr;
1060 1062 LIR_Opr tmp2 = FrameMap::rsi_oop_opr;
1061 1063 LIR_Opr tmp3 = FrameMap::rdi_oop_opr;
1062 1064 LIR_Opr tmp4 = reg;
1063 1065 LIR_Opr klass_reg = FrameMap::rdx_oop_opr;
1064 1066
1065 1067 length.load_item_force(FrameMap::rbx_opr);
1066 1068 LIR_Opr len = length.result();
1067 1069
1068 1070 CodeStub* slow_path = new NewObjectArrayStub(klass_reg, len, reg, info);
1069 1071 ciObject* obj = (ciObject*) ciObjArrayKlass::make(x->klass());
1070 1072 if (obj == ciEnv::unloaded_ciobjarrayklass()) {
1071 1073 BAILOUT("encountered unloaded_ciobjarrayklass due to out of memory error");
1072 1074 }
1073 1075 jobject2reg_with_patching(klass_reg, obj, patching_info);
1074 1076 __ allocate_array(reg, len, tmp1, tmp2, tmp3, tmp4, T_OBJECT, klass_reg, slow_path);
1075 1077
1076 1078 LIR_Opr result = rlock_result(x);
1077 1079 __ move(reg, result);
1078 1080 }
1079 1081
1080 1082
1081 1083 void LIRGenerator::do_NewMultiArray(NewMultiArray* x) {
1082 1084 Values* dims = x->dims();
1083 1085 int i = dims->length();
1084 1086 LIRItemList* items = new LIRItemList(dims->length(), NULL);
1085 1087 while (i-- > 0) {
1086 1088 LIRItem* size = new LIRItem(dims->at(i), this);
1087 1089 items->at_put(i, size);
1088 1090 }
1089 1091
1090 1092 // Evaluate state_for early since it may emit code.
1091 1093 CodeEmitInfo* patching_info = NULL;
1092 1094 if (!x->klass()->is_loaded() || PatchALot) {
1093 1095 patching_info = state_for(x, x->state_before());
1094 1096
1095 1097 // cannot re-use same xhandlers for multiple CodeEmitInfos, so
1096 1098 // clone all handlers. This is handled transparently in other
1097 1099 // places by the CodeEmitInfo cloning logic but is handled
1098 1100 // specially here because a stub isn't being used.
1099 1101 x->set_exception_handlers(new XHandlers(x->exception_handlers()));
1100 1102 }
1101 1103 CodeEmitInfo* info = state_for(x, x->state());
1102 1104
1103 1105 i = dims->length();
1104 1106 while (i-- > 0) {
1105 1107 LIRItem* size = items->at(i);
1106 1108 size->load_nonconstant();
1107 1109
1108 1110 store_stack_parameter(size->result(), in_ByteSize(i*4));
1109 1111 }
1110 1112
1111 1113 LIR_Opr reg = result_register_for(x->type());
1112 1114 jobject2reg_with_patching(reg, x->klass(), patching_info);
1113 1115
1114 1116 LIR_Opr rank = FrameMap::rbx_opr;
1115 1117 __ move(LIR_OprFact::intConst(x->rank()), rank);
1116 1118 LIR_Opr varargs = FrameMap::rcx_opr;
1117 1119 __ move(FrameMap::rsp_opr, varargs);
1118 1120 LIR_OprList* args = new LIR_OprList(3);
1119 1121 args->append(reg);
1120 1122 args->append(rank);
1121 1123 args->append(varargs);
1122 1124 __ call_runtime(Runtime1::entry_for(Runtime1::new_multi_array_id),
1123 1125 LIR_OprFact::illegalOpr,
1124 1126 reg, args, info);
1125 1127
1126 1128 LIR_Opr result = rlock_result(x);
1127 1129 __ move(reg, result);
1128 1130 }
1129 1131
1130 1132
1131 1133 void LIRGenerator::do_BlockBegin(BlockBegin* x) {
1132 1134 // nothing to do for now
1133 1135 }
1134 1136
1135 1137
1136 1138 void LIRGenerator::do_CheckCast(CheckCast* x) {
1137 1139 LIRItem obj(x->obj(), this);
1138 1140
1139 1141 CodeEmitInfo* patching_info = NULL;
1140 1142 if (!x->klass()->is_loaded() || (PatchALot && !x->is_incompatible_class_change_check())) {
1141 1143 // must do this before locking the destination register as an oop register,
1142 1144 // and before the obj is loaded (the latter is for deoptimization)
1143 1145 patching_info = state_for(x, x->state_before());
1144 1146 }
1145 1147 obj.load_item();
1146 1148
1147 1149 // info for exceptions
1148 1150 CodeEmitInfo* info_for_exception = state_for(x);
1149 1151
1150 1152 CodeStub* stub;
1151 1153 if (x->is_incompatible_class_change_check()) {
1152 1154 assert(patching_info == NULL, "can't patch this");
1153 1155 stub = new SimpleExceptionStub(Runtime1::throw_incompatible_class_change_error_id, LIR_OprFact::illegalOpr, info_for_exception);
1154 1156 } else {
1155 1157 stub = new SimpleExceptionStub(Runtime1::throw_class_cast_exception_id, obj.result(), info_for_exception);
1156 1158 }
1157 1159 LIR_Opr reg = rlock_result(x);
1158 1160 LIR_Opr tmp3 = LIR_OprFact::illegalOpr;
1159 1161 if (!x->klass()->is_loaded() || UseCompressedOops) {
1160 1162 tmp3 = new_register(objectType);
1161 1163 }
1162 1164 __ checkcast(reg, obj.result(), x->klass(),
1163 1165 new_register(objectType), new_register(objectType), tmp3,
1164 1166 x->direct_compare(), info_for_exception, patching_info, stub,
1165 1167 x->profiled_method(), x->profiled_bci());
1166 1168 }
1167 1169
1168 1170
1169 1171 void LIRGenerator::do_InstanceOf(InstanceOf* x) {
1170 1172 LIRItem obj(x->obj(), this);
1171 1173
1172 1174 // result and test object may not be in same register
1173 1175 LIR_Opr reg = rlock_result(x);
1174 1176 CodeEmitInfo* patching_info = NULL;
1175 1177 if ((!x->klass()->is_loaded() || PatchALot)) {
1176 1178 // must do this before locking the destination register as an oop register
1177 1179 patching_info = state_for(x, x->state_before());
1178 1180 }
1179 1181 obj.load_item();
1180 1182 LIR_Opr tmp3 = LIR_OprFact::illegalOpr;
1181 1183 if (!x->klass()->is_loaded() || UseCompressedOops) {
1182 1184 tmp3 = new_register(objectType);
1183 1185 }
1184 1186 __ instanceof(reg, obj.result(), x->klass(),
1185 1187 new_register(objectType), new_register(objectType), tmp3,
1186 1188 x->direct_compare(), patching_info, x->profiled_method(), x->profiled_bci());
1187 1189 }
1188 1190
1189 1191
1190 1192 void LIRGenerator::do_If(If* x) {
1191 1193 assert(x->number_of_sux() == 2, "inconsistency");
1192 1194 ValueTag tag = x->x()->type()->tag();
1193 1195 bool is_safepoint = x->is_safepoint();
1194 1196
1195 1197 If::Condition cond = x->cond();
1196 1198
1197 1199 LIRItem xitem(x->x(), this);
1198 1200 LIRItem yitem(x->y(), this);
1199 1201 LIRItem* xin = &xitem;
1200 1202 LIRItem* yin = &yitem;
1201 1203
1202 1204 if (tag == longTag) {
1203 1205 // for longs, only conditions "eql", "neq", "lss", "geq" are valid;
1204 1206 // mirror for other conditions
1205 1207 if (cond == If::gtr || cond == If::leq) {
1206 1208 cond = Instruction::mirror(cond);
1207 1209 xin = &yitem;
1208 1210 yin = &xitem;
1209 1211 }
1210 1212 xin->set_destroys_register();
1211 1213 }
1212 1214 xin->load_item();
1213 1215 if (tag == longTag && yin->is_constant() && yin->get_jlong_constant() == 0 && (cond == If::eql || cond == If::neq)) {
1214 1216 // inline long zero
1215 1217 yin->dont_load_item();
1216 1218 } else if (tag == longTag || tag == floatTag || tag == doubleTag) {
1217 1219 // longs cannot handle constants at right side
1218 1220 yin->load_item();
1219 1221 } else {
1220 1222 yin->dont_load_item();
1221 1223 }
1222 1224
1223 1225 // add safepoint before generating condition code so it can be recomputed
1224 1226 if (x->is_safepoint()) {
1225 1227 // increment backedge counter if needed
1226 1228 increment_backedge_counter(state_for(x, x->state_before()), x->profiled_bci());
1227 1229 __ safepoint(LIR_OprFact::illegalOpr, state_for(x, x->state_before()));
1228 1230 }
1229 1231 set_no_result(x);
1230 1232
1231 1233 LIR_Opr left = xin->result();
1232 1234 LIR_Opr right = yin->result();
1233 1235 __ cmp(lir_cond(cond), left, right);
1234 1236 // Generate branch profiling. Profiling code doesn't kill flags.
1235 1237 profile_branch(x, cond);
1236 1238 move_to_phi(x->state());
1237 1239 if (x->x()->type()->is_float_kind()) {
1238 1240 __ branch(lir_cond(cond), right->type(), x->tsux(), x->usux());
1239 1241 } else {
1240 1242 __ branch(lir_cond(cond), right->type(), x->tsux());
1241 1243 }
1242 1244 assert(x->default_sux() == x->fsux(), "wrong destination above");
1243 1245 __ jump(x->default_sux());
1244 1246 }
1245 1247
1246 1248
1247 1249 LIR_Opr LIRGenerator::getThreadPointer() {
1248 1250 #ifdef _LP64
1249 1251 return FrameMap::as_pointer_opr(r15_thread);
1250 1252 #else
1251 1253 LIR_Opr result = new_register(T_INT);
1252 1254 __ get_thread(result);
1253 1255 return result;
1254 1256 #endif //
1255 1257 }
1256 1258
1257 1259 void LIRGenerator::trace_block_entry(BlockBegin* block) {
1258 1260 store_stack_parameter(LIR_OprFact::intConst(block->block_id()), in_ByteSize(0));
1259 1261 LIR_OprList* args = new LIR_OprList();
1260 1262 address func = CAST_FROM_FN_PTR(address, Runtime1::trace_block_entry);
1261 1263 __ call_runtime_leaf(func, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, args);
1262 1264 }
1263 1265
1264 1266
1265 1267 void LIRGenerator::volatile_field_store(LIR_Opr value, LIR_Address* address,
1266 1268 CodeEmitInfo* info) {
1267 1269 if (address->type() == T_LONG) {
1268 1270 address = new LIR_Address(address->base(),
1269 1271 address->index(), address->scale(),
1270 1272 address->disp(), T_DOUBLE);
1271 1273 // Transfer the value atomically by using FP moves. This means
1272 1274 // the value has to be moved between CPU and FPU registers. It
1273 1275 // always has to be moved through spill slot since there's no
1274 1276 // quick way to pack the value into an SSE register.
1275 1277 LIR_Opr temp_double = new_register(T_DOUBLE);
1276 1278 LIR_Opr spill = new_register(T_LONG);
1277 1279 set_vreg_flag(spill, must_start_in_memory);
1278 1280 __ move(value, spill);
1279 1281 __ volatile_move(spill, temp_double, T_LONG);
1280 1282 __ volatile_move(temp_double, LIR_OprFact::address(address), T_LONG, info);
1281 1283 } else {
1282 1284 __ store(value, address, info);
1283 1285 }
1284 1286 }
1285 1287
1286 1288
1287 1289
1288 1290 void LIRGenerator::volatile_field_load(LIR_Address* address, LIR_Opr result,
1289 1291 CodeEmitInfo* info) {
1290 1292 if (address->type() == T_LONG) {
1291 1293 address = new LIR_Address(address->base(),
1292 1294 address->index(), address->scale(),
1293 1295 address->disp(), T_DOUBLE);
1294 1296 // Transfer the value atomically by using FP moves. This means
1295 1297 // the value has to be moved between CPU and FPU registers. In
1296 1298 // SSE0 and SSE1 mode it has to be moved through spill slot but in
1297 1299 // SSE2+ mode it can be moved directly.
1298 1300 LIR_Opr temp_double = new_register(T_DOUBLE);
1299 1301 __ volatile_move(LIR_OprFact::address(address), temp_double, T_LONG, info);
1300 1302 __ volatile_move(temp_double, result, T_LONG);
1301 1303 if (UseSSE < 2) {
1302 1304 // no spill slot needed in SSE2 mode because xmm->cpu register move is possible
1303 1305 set_vreg_flag(result, must_start_in_memory);
1304 1306 }
1305 1307 } else {
1306 1308 __ load(address, result, info);
1307 1309 }
1308 1310 }
1309 1311
1310 1312 void LIRGenerator::get_Object_unsafe(LIR_Opr dst, LIR_Opr src, LIR_Opr offset,
1311 1313 BasicType type, bool is_volatile) {
1312 1314 if (is_volatile && type == T_LONG) {
1313 1315 LIR_Address* addr = new LIR_Address(src, offset, T_DOUBLE);
1314 1316 LIR_Opr tmp = new_register(T_DOUBLE);
1315 1317 __ load(addr, tmp);
1316 1318 LIR_Opr spill = new_register(T_LONG);
1317 1319 set_vreg_flag(spill, must_start_in_memory);
1318 1320 __ move(tmp, spill);
1319 1321 __ move(spill, dst);
1320 1322 } else {
1321 1323 LIR_Address* addr = new LIR_Address(src, offset, type);
1322 1324 __ load(addr, dst);
1323 1325 }
1324 1326 }
1325 1327
1326 1328
1327 1329 void LIRGenerator::put_Object_unsafe(LIR_Opr src, LIR_Opr offset, LIR_Opr data,
1328 1330 BasicType type, bool is_volatile) {
1329 1331 if (is_volatile && type == T_LONG) {
1330 1332 LIR_Address* addr = new LIR_Address(src, offset, T_DOUBLE);
1331 1333 LIR_Opr tmp = new_register(T_DOUBLE);
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1332 1334 LIR_Opr spill = new_register(T_DOUBLE);
1333 1335 set_vreg_flag(spill, must_start_in_memory);
1334 1336 __ move(data, spill);
1335 1337 __ move(spill, tmp);
1336 1338 __ move(tmp, addr);
1337 1339 } else {
1338 1340 LIR_Address* addr = new LIR_Address(src, offset, type);
1339 1341 bool is_obj = (type == T_ARRAY || type == T_OBJECT);
1340 1342 if (is_obj) {
1341 1343 // Do the pre-write barrier, if any.
1342 - pre_barrier(LIR_OprFact::address(addr), false, NULL);
1344 + pre_barrier(LIR_OprFact::address(addr), LIR_OprFact::illegalOpr /* pre_val */,
1345 + true /* do_load */, false /* patch */, NULL);
1343 1346 __ move(data, addr);
1344 1347 assert(src->is_register(), "must be register");
1345 1348 // Seems to be a precise address
1346 1349 post_barrier(LIR_OprFact::address(addr), data);
1347 1350 } else {
1348 1351 __ move(data, addr);
1349 1352 }
1350 1353 }
1351 1354 }
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