2193 // For V8
2194 void read_ccr_trap(Register ccr_save);
2195 void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2);
2196
2197 #ifdef ASSERT
2198 // For V8 debugging. Uses V8 instruction sequence and checks
2199 // result with V9 insturctions rdccr and wrccr.
2200 // Uses Gscatch and Gscatch2
2201 void read_ccr_v8_assert(Register ccr_save);
2202 void write_ccr_v8_assert(Register ccr_save);
2203 #endif // ASSERT
2204
2205 public:
2206
2207 // Write to card table for - register is destroyed afterwards.
2208 void card_table_write(jbyte* byte_map_base, Register tmp, Register obj);
2209
2210 void card_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2211
2212 #ifndef SERIALGC
2213 // Array store and offset
2214 void g1_write_barrier_pre(Register obj, Register index, int offset, Register tmp, bool preserve_o_regs);
2215
2216 void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2217
2218 // May do filtering, depending on the boolean arguments.
2219 void g1_card_table_write(jbyte* byte_map_base,
2220 Register tmp, Register obj, Register new_val,
2221 bool region_filter, bool null_filter);
2222 #endif // SERIALGC
2223
2224 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
2225 void push_fTOS();
2226
2227 // pops double TOS element from CPU stack and pushes on FPU stack
2228 void pop_fTOS();
2229
2230 void empty_FPU_stack();
2231
2232 void push_IU_state();
2233 void pop_IU_state();
2234
2235 void push_FPU_state();
2236 void pop_FPU_state();
2237
2238 void push_CPU_state();
2239 void pop_CPU_state();
2240
2241 // if heap base register is used - reinit it with the correct value
|
2193 // For V8
2194 void read_ccr_trap(Register ccr_save);
2195 void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2);
2196
2197 #ifdef ASSERT
2198 // For V8 debugging. Uses V8 instruction sequence and checks
2199 // result with V9 insturctions rdccr and wrccr.
2200 // Uses Gscatch and Gscatch2
2201 void read_ccr_v8_assert(Register ccr_save);
2202 void write_ccr_v8_assert(Register ccr_save);
2203 #endif // ASSERT
2204
2205 public:
2206
2207 // Write to card table for - register is destroyed afterwards.
2208 void card_table_write(jbyte* byte_map_base, Register tmp, Register obj);
2209
2210 void card_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2211
2212 #ifndef SERIALGC
2213 // General G1 pre-barrier generator.
2214 void g1_write_barrier_pre(Register obj, Register index, int offset, Register pre_val, Register tmp, bool preserve_o_regs);
2215
2216 // General G1 post-barrier generator
2217 void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2218 #endif // SERIALGC
2219
2220 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
2221 void push_fTOS();
2222
2223 // pops double TOS element from CPU stack and pushes on FPU stack
2224 void pop_fTOS();
2225
2226 void empty_FPU_stack();
2227
2228 void push_IU_state();
2229 void pop_IU_state();
2230
2231 void push_FPU_state();
2232 void pop_FPU_state();
2233
2234 void push_CPU_state();
2235 void pop_CPU_state();
2236
2237 // if heap base register is used - reinit it with the correct value
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