1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "opto/ad.hpp"
29 #include "opto/addnode.hpp"
30 #include "opto/callnode.hpp"
31 #include "opto/idealGraphPrinter.hpp"
32 #include "opto/matcher.hpp"
33 #include "opto/memnode.hpp"
34 #include "opto/movenode.hpp"
35 #include "opto/opcodes.hpp"
36 #include "opto/regmask.hpp"
37 #include "opto/rootnode.hpp"
38 #include "opto/runtime.hpp"
39 #include "opto/type.hpp"
40 #include "opto/vectornode.hpp"
41 #include "runtime/os.hpp"
42 #include "runtime/sharedRuntime.hpp"
43
44 OptoReg::Name OptoReg::c_frame_pointer;
45
46 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
47 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
48 RegMask Matcher::STACK_ONLY_mask;
49 RegMask Matcher::c_frame_ptr_mask;
50 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
51 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
52
53 //---------------------------Matcher-------------------------------------------
54 Matcher::Matcher()
55 : PhaseTransform( Phase::Ins_Select ),
56 #ifdef ASSERT
57 _old2new_map(C->comp_arena()),
58 _new2old_map(C->comp_arena()),
59 #endif
60 _shared_nodes(C->comp_arena()),
61 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
62 _swallowed(swallowed),
63 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
64 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
65 _must_clone(must_clone),
66 _register_save_policy(register_save_policy),
67 _c_reg_save_policy(c_reg_save_policy),
68 _register_save_type(register_save_type),
69 _ruleName(ruleName),
70 _allocation_started(false),
71 _states_arena(Chunk::medium_size),
72 _visited(&_states_arena),
73 _shared(&_states_arena),
74 _dontcare(&_states_arena) {
75 C->set_matcher(this);
76
77 idealreg2spillmask [Op_RegI] = NULL;
78 idealreg2spillmask [Op_RegN] = NULL;
79 idealreg2spillmask [Op_RegL] = NULL;
80 idealreg2spillmask [Op_RegF] = NULL;
81 idealreg2spillmask [Op_RegD] = NULL;
82 idealreg2spillmask [Op_RegP] = NULL;
83 idealreg2spillmask [Op_VecS] = NULL;
84 idealreg2spillmask [Op_VecD] = NULL;
85 idealreg2spillmask [Op_VecX] = NULL;
86 idealreg2spillmask [Op_VecY] = NULL;
87 idealreg2spillmask [Op_VecZ] = NULL;
88
89 idealreg2debugmask [Op_RegI] = NULL;
90 idealreg2debugmask [Op_RegN] = NULL;
91 idealreg2debugmask [Op_RegL] = NULL;
92 idealreg2debugmask [Op_RegF] = NULL;
93 idealreg2debugmask [Op_RegD] = NULL;
94 idealreg2debugmask [Op_RegP] = NULL;
95 idealreg2debugmask [Op_VecS] = NULL;
96 idealreg2debugmask [Op_VecD] = NULL;
97 idealreg2debugmask [Op_VecX] = NULL;
98 idealreg2debugmask [Op_VecY] = NULL;
99 idealreg2debugmask [Op_VecZ] = NULL;
100
101 idealreg2mhdebugmask[Op_RegI] = NULL;
102 idealreg2mhdebugmask[Op_RegN] = NULL;
103 idealreg2mhdebugmask[Op_RegL] = NULL;
104 idealreg2mhdebugmask[Op_RegF] = NULL;
105 idealreg2mhdebugmask[Op_RegD] = NULL;
106 idealreg2mhdebugmask[Op_RegP] = NULL;
107 idealreg2mhdebugmask[Op_VecS] = NULL;
108 idealreg2mhdebugmask[Op_VecD] = NULL;
109 idealreg2mhdebugmask[Op_VecX] = NULL;
110 idealreg2mhdebugmask[Op_VecY] = NULL;
111 idealreg2mhdebugmask[Op_VecZ] = NULL;
112
113 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
114 }
115
116 //------------------------------warp_incoming_stk_arg------------------------
117 // This warps a VMReg into an OptoReg::Name
118 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
119 OptoReg::Name warped;
120 if( reg->is_stack() ) { // Stack slot argument?
121 warped = OptoReg::add(_old_SP, reg->reg2stack() );
122 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
123 if( warped >= _in_arg_limit )
124 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
125 if (!RegMask::can_represent_arg(warped)) {
126 // the compiler cannot represent this method's calling sequence
127 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
128 return OptoReg::Bad;
129 }
130 return warped;
131 }
132 return OptoReg::as_OptoReg(reg);
133 }
134
135 //---------------------------compute_old_SP------------------------------------
136 OptoReg::Name Compile::compute_old_SP() {
137 int fixed = fixed_slots();
138 int preserve = in_preserve_stack_slots();
139 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
140 }
141
142
143
144 #ifdef ASSERT
145 void Matcher::verify_new_nodes_only(Node* xroot) {
146 // Make sure that the new graph only references new nodes
147 ResourceMark rm;
148 Unique_Node_List worklist;
149 VectorSet visited(Thread::current()->resource_area());
150 worklist.push(xroot);
151 while (worklist.size() > 0) {
152 Node* n = worklist.pop();
153 visited <<= n->_idx;
154 assert(C->node_arena()->contains(n), "dead node");
155 for (uint j = 0; j < n->req(); j++) {
156 Node* in = n->in(j);
157 if (in != NULL) {
158 assert(C->node_arena()->contains(in), "dead node");
159 if (!visited.test(in->_idx)) {
160 worklist.push(in);
161 }
162 }
163 }
164 }
165 }
166 #endif
167
168
169 //---------------------------match---------------------------------------------
170 void Matcher::match( ) {
171 if( MaxLabelRootDepth < 100 ) { // Too small?
172 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
173 MaxLabelRootDepth = 100;
174 }
175 // One-time initialization of some register masks.
176 init_spill_mask( C->root()->in(1) );
177 _return_addr_mask = return_addr();
178 #ifdef _LP64
179 // Pointers take 2 slots in 64-bit land
180 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
181 #endif
182
183 // Map a Java-signature return type into return register-value
184 // machine registers for 0, 1 and 2 returned values.
185 const TypeTuple *range = C->tf()->range();
186 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
187 // Get ideal-register return type
188 int ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
189 // Get machine return register
190 uint sop = C->start()->Opcode();
191 OptoRegPair regs = return_value(ireg, false);
192
193 // And mask for same
194 _return_value_mask = RegMask(regs.first());
195 if( OptoReg::is_valid(regs.second()) )
196 _return_value_mask.Insert(regs.second());
197 }
198
199 // ---------------
200 // Frame Layout
201
202 // Need the method signature to determine the incoming argument types,
203 // because the types determine which registers the incoming arguments are
204 // in, and this affects the matched code.
205 const TypeTuple *domain = C->tf()->domain();
206 uint argcnt = domain->cnt() - TypeFunc::Parms;
207 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
208 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
209 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
210 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
211 uint i;
212 for( i = 0; i<argcnt; i++ ) {
213 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
214 }
215
216 // Pass array of ideal registers and length to USER code (from the AD file)
217 // that will convert this to an array of register numbers.
218 const StartNode *start = C->start();
219 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
220 #ifdef ASSERT
221 // Sanity check users' calling convention. Real handy while trying to
222 // get the initial port correct.
223 { for (uint i = 0; i<argcnt; i++) {
224 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
225 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
226 _parm_regs[i].set_bad();
227 continue;
228 }
229 VMReg parm_reg = vm_parm_regs[i].first();
230 assert(parm_reg->is_valid(), "invalid arg?");
231 if (parm_reg->is_reg()) {
232 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
233 assert(can_be_java_arg(opto_parm_reg) ||
234 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
235 opto_parm_reg == inline_cache_reg(),
236 "parameters in register must be preserved by runtime stubs");
237 }
238 for (uint j = 0; j < i; j++) {
239 assert(parm_reg != vm_parm_regs[j].first(),
240 "calling conv. must produce distinct regs");
241 }
242 }
243 }
244 #endif
245
246 // Do some initial frame layout.
247
248 // Compute the old incoming SP (may be called FP) as
249 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
250 _old_SP = C->compute_old_SP();
251 assert( is_even(_old_SP), "must be even" );
252
253 // Compute highest incoming stack argument as
254 // _old_SP + out_preserve_stack_slots + incoming argument size.
255 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
256 assert( is_even(_in_arg_limit), "out_preserve must be even" );
257 for( i = 0; i < argcnt; i++ ) {
258 // Permit args to have no register
259 _calling_convention_mask[i].Clear();
260 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
261 continue;
262 }
263 // calling_convention returns stack arguments as a count of
264 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
265 // the allocators point of view, taking into account all the
266 // preserve area, locks & pad2.
267
268 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
269 if( OptoReg::is_valid(reg1))
270 _calling_convention_mask[i].Insert(reg1);
271
272 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
273 if( OptoReg::is_valid(reg2))
274 _calling_convention_mask[i].Insert(reg2);
275
276 // Saved biased stack-slot register number
277 _parm_regs[i].set_pair(reg2, reg1);
278 }
279
280 // Finally, make sure the incoming arguments take up an even number of
281 // words, in case the arguments or locals need to contain doubleword stack
282 // slots. The rest of the system assumes that stack slot pairs (in
283 // particular, in the spill area) which look aligned will in fact be
284 // aligned relative to the stack pointer in the target machine. Double
285 // stack slots will always be allocated aligned.
286 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
287
288 // Compute highest outgoing stack argument as
289 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
290 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
291 assert( is_even(_out_arg_limit), "out_preserve must be even" );
292
293 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
294 // the compiler cannot represent this method's calling sequence
295 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
296 }
297
298 if (C->failing()) return; // bailed out on incoming arg failure
299
300 // ---------------
301 // Collect roots of matcher trees. Every node for which
302 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
303 // can be a valid interior of some tree.
304 find_shared( C->root() );
305 find_shared( C->top() );
306
307 C->print_method(PHASE_BEFORE_MATCHING);
308
309 // Create new ideal node ConP #NULL even if it does exist in old space
310 // to avoid false sharing if the corresponding mach node is not used.
311 // The corresponding mach node is only used in rare cases for derived
312 // pointers.
313 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
314
315 // Swap out to old-space; emptying new-space
316 Arena *old = C->node_arena()->move_contents(C->old_arena());
317
318 // Save debug and profile information for nodes in old space:
319 _old_node_note_array = C->node_note_array();
320 if (_old_node_note_array != NULL) {
321 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
322 (C->comp_arena(), _old_node_note_array->length(),
323 0, NULL));
324 }
325
326 // Pre-size the new_node table to avoid the need for range checks.
327 grow_new_node_array(C->unique());
328
329 // Reset node counter so MachNodes start with _idx at 0
330 int live_nodes = C->live_nodes();
331 C->set_unique(0);
332 C->reset_dead_node_list();
333
334 // Recursively match trees from old space into new space.
335 // Correct leaves of new-space Nodes; they point to old-space.
336 _visited.Clear(); // Clear visit bits for xform call
337 C->set_cached_top_node(xform( C->top(), live_nodes ));
338 if (!C->failing()) {
339 Node* xroot = xform( C->root(), 1 );
340 if (xroot == NULL) {
341 Matcher::soft_match_failure(); // recursive matching process failed
342 C->record_method_not_compilable("instruction match failed");
343 } else {
344 // During matching shared constants were attached to C->root()
345 // because xroot wasn't available yet, so transfer the uses to
346 // the xroot.
347 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
348 Node* n = C->root()->fast_out(j);
349 if (C->node_arena()->contains(n)) {
350 assert(n->in(0) == C->root(), "should be control user");
351 n->set_req(0, xroot);
352 --j;
353 --jmax;
354 }
355 }
356
357 // Generate new mach node for ConP #NULL
358 assert(new_ideal_null != NULL, "sanity");
359 _mach_null = match_tree(new_ideal_null);
360 // Don't set control, it will confuse GCM since there are no uses.
361 // The control will be set when this node is used first time
362 // in find_base_for_derived().
363 assert(_mach_null != NULL, "");
364
365 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
366
367 #ifdef ASSERT
368 verify_new_nodes_only(xroot);
369 #endif
370 }
371 }
372 if (C->top() == NULL || C->root() == NULL) {
373 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
374 }
375 if (C->failing()) {
376 // delete old;
377 old->destruct_contents();
378 return;
379 }
380 assert( C->top(), "" );
381 assert( C->root(), "" );
382 validate_null_checks();
383
384 // Now smoke old-space
385 NOT_DEBUG( old->destruct_contents() );
386
387 // ------------------------
388 // Set up save-on-entry registers
389 Fixup_Save_On_Entry( );
390 }
391
392
393 //------------------------------Fixup_Save_On_Entry----------------------------
394 // The stated purpose of this routine is to take care of save-on-entry
395 // registers. However, the overall goal of the Match phase is to convert into
396 // machine-specific instructions which have RegMasks to guide allocation.
397 // So what this procedure really does is put a valid RegMask on each input
398 // to the machine-specific variations of all Return, TailCall and Halt
399 // instructions. It also adds edgs to define the save-on-entry values (and of
400 // course gives them a mask).
401
402 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
403 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
404 // Do all the pre-defined register masks
405 rms[TypeFunc::Control ] = RegMask::Empty;
406 rms[TypeFunc::I_O ] = RegMask::Empty;
407 rms[TypeFunc::Memory ] = RegMask::Empty;
408 rms[TypeFunc::ReturnAdr] = ret_adr;
409 rms[TypeFunc::FramePtr ] = fp;
410 return rms;
411 }
412
413 //---------------------------init_first_stack_mask-----------------------------
414 // Create the initial stack mask used by values spilling to the stack.
415 // Disallow any debug info in outgoing argument areas by setting the
416 // initial mask accordingly.
417 void Matcher::init_first_stack_mask() {
418
419 // Allocate storage for spill masks as masks for the appropriate load type.
420 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5));
421
422 idealreg2spillmask [Op_RegN] = &rms[0];
423 idealreg2spillmask [Op_RegI] = &rms[1];
424 idealreg2spillmask [Op_RegL] = &rms[2];
425 idealreg2spillmask [Op_RegF] = &rms[3];
426 idealreg2spillmask [Op_RegD] = &rms[4];
427 idealreg2spillmask [Op_RegP] = &rms[5];
428
429 idealreg2debugmask [Op_RegN] = &rms[6];
430 idealreg2debugmask [Op_RegI] = &rms[7];
431 idealreg2debugmask [Op_RegL] = &rms[8];
432 idealreg2debugmask [Op_RegF] = &rms[9];
433 idealreg2debugmask [Op_RegD] = &rms[10];
434 idealreg2debugmask [Op_RegP] = &rms[11];
435
436 idealreg2mhdebugmask[Op_RegN] = &rms[12];
437 idealreg2mhdebugmask[Op_RegI] = &rms[13];
438 idealreg2mhdebugmask[Op_RegL] = &rms[14];
439 idealreg2mhdebugmask[Op_RegF] = &rms[15];
440 idealreg2mhdebugmask[Op_RegD] = &rms[16];
441 idealreg2mhdebugmask[Op_RegP] = &rms[17];
442
443 idealreg2spillmask [Op_VecS] = &rms[18];
444 idealreg2spillmask [Op_VecD] = &rms[19];
445 idealreg2spillmask [Op_VecX] = &rms[20];
446 idealreg2spillmask [Op_VecY] = &rms[21];
447 idealreg2spillmask [Op_VecZ] = &rms[22];
448
449 OptoReg::Name i;
450
451 // At first, start with the empty mask
452 C->FIRST_STACK_mask().Clear();
453
454 // Add in the incoming argument area
455 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
456 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
457 C->FIRST_STACK_mask().Insert(i);
458 }
459 // Add in all bits past the outgoing argument area
460 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
461 "must be able to represent all call arguments in reg mask");
462 OptoReg::Name init = _out_arg_limit;
463 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
464 C->FIRST_STACK_mask().Insert(i);
465 }
466 // Finally, set the "infinite stack" bit.
467 C->FIRST_STACK_mask().set_AllStack();
468
469 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
470 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
471 // Keep spill masks aligned.
472 aligned_stack_mask.clear_to_pairs();
473 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
474
475 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
476 #ifdef _LP64
477 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
478 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
479 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
480 #else
481 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
482 #endif
483 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
484 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
485 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
486 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
487 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
488 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
489 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
490 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
491
492 if (Matcher::vector_size_supported(T_BYTE,4)) {
493 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
494 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
495 }
496 if (Matcher::vector_size_supported(T_FLOAT,2)) {
497 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
498 // RA guarantees such alignment since it is needed for Double and Long values.
499 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
500 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
501 }
502 if (Matcher::vector_size_supported(T_FLOAT,4)) {
503 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
504 //
505 // RA can use input arguments stack slots for spills but until RA
506 // we don't know frame size and offset of input arg stack slots.
507 //
508 // Exclude last input arg stack slots to avoid spilling vectors there
509 // otherwise vector spills could stomp over stack slots in caller frame.
510 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
511 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
512 aligned_stack_mask.Remove(in);
513 in = OptoReg::add(in, -1);
514 }
515 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
516 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
517 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
518 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
519 }
520 if (Matcher::vector_size_supported(T_FLOAT,8)) {
521 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
522 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
523 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
524 aligned_stack_mask.Remove(in);
525 in = OptoReg::add(in, -1);
526 }
527 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
528 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
529 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
530 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
531 }
532 if (Matcher::vector_size_supported(T_FLOAT,16)) {
533 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
534 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
535 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
536 aligned_stack_mask.Remove(in);
537 in = OptoReg::add(in, -1);
538 }
539 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
540 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
541 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
542 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
543 }
544 if (UseFPUForSpilling) {
545 // This mask logic assumes that the spill operations are
546 // symmetric and that the registers involved are the same size.
547 // On sparc for instance we may have to use 64 bit moves will
548 // kill 2 registers when used with F0-F31.
549 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
550 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
551 #ifdef _LP64
552 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
553 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
554 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
555 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
556 #else
557 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
558 #ifdef ARM
559 // ARM has support for moving 64bit values between a pair of
560 // integer registers and a double register
561 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
562 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
563 #endif
564 #endif
565 }
566
567 // Make up debug masks. Any spill slot plus callee-save registers.
568 // Caller-save registers are assumed to be trashable by the various
569 // inline-cache fixup routines.
570 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
571 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
572 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
573 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
574 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
575 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
576
577 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
578 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
579 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
580 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
581 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
582 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
583
584 // Prevent stub compilations from attempting to reference
585 // callee-saved registers from debug info
586 bool exclude_soe = !Compile::current()->is_method_compilation();
587
588 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
589 // registers the caller has to save do not work
590 if( _register_save_policy[i] == 'C' ||
591 _register_save_policy[i] == 'A' ||
592 (_register_save_policy[i] == 'E' && exclude_soe) ) {
593 idealreg2debugmask [Op_RegN]->Remove(i);
594 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
595 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
596 idealreg2debugmask [Op_RegF]->Remove(i); // masks
597 idealreg2debugmask [Op_RegD]->Remove(i);
598 idealreg2debugmask [Op_RegP]->Remove(i);
599
600 idealreg2mhdebugmask[Op_RegN]->Remove(i);
601 idealreg2mhdebugmask[Op_RegI]->Remove(i);
602 idealreg2mhdebugmask[Op_RegL]->Remove(i);
603 idealreg2mhdebugmask[Op_RegF]->Remove(i);
604 idealreg2mhdebugmask[Op_RegD]->Remove(i);
605 idealreg2mhdebugmask[Op_RegP]->Remove(i);
606 }
607 }
608
609 // Subtract the register we use to save the SP for MethodHandle
610 // invokes to from the debug mask.
611 const RegMask save_mask = method_handle_invoke_SP_save_mask();
612 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
613 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
614 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
615 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
616 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
617 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
618 }
619
620 //---------------------------is_save_on_entry----------------------------------
621 bool Matcher::is_save_on_entry( int reg ) {
622 return
623 _register_save_policy[reg] == 'E' ||
624 _register_save_policy[reg] == 'A' || // Save-on-entry register?
625 // Also save argument registers in the trampolining stubs
626 (C->save_argument_registers() && is_spillable_arg(reg));
627 }
628
629 //---------------------------Fixup_Save_On_Entry-------------------------------
630 void Matcher::Fixup_Save_On_Entry( ) {
631 init_first_stack_mask();
632
633 Node *root = C->root(); // Short name for root
634 // Count number of save-on-entry registers.
635 uint soe_cnt = number_of_saved_registers();
636 uint i;
637
638 // Find the procedure Start Node
639 StartNode *start = C->start();
640 assert( start, "Expect a start node" );
641
642 // Save argument registers in the trampolining stubs
643 if( C->save_argument_registers() )
644 for( i = 0; i < _last_Mach_Reg; i++ )
645 if( is_spillable_arg(i) )
646 soe_cnt++;
647
648 // Input RegMask array shared by all Returns.
649 // The type for doubles and longs has a count of 2, but
650 // there is only 1 returned value
651 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
652 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
653 // Returns have 0 or 1 returned values depending on call signature.
654 // Return register is specified by return_value in the AD file.
655 if (ret_edge_cnt > TypeFunc::Parms)
656 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
657
658 // Input RegMask array shared by all Rethrows.
659 uint reth_edge_cnt = TypeFunc::Parms+1;
660 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
661 // Rethrow takes exception oop only, but in the argument 0 slot.
662 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
663 #ifdef _LP64
664 // Need two slots for ptrs in 64-bit land
665 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
666 #endif
667
668 // Input RegMask array shared by all TailCalls
669 uint tail_call_edge_cnt = TypeFunc::Parms+2;
670 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
671
672 // Input RegMask array shared by all TailJumps
673 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
674 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
675
676 // TailCalls have 2 returned values (target & moop), whose masks come
677 // from the usual MachNode/MachOper mechanism. Find a sample
678 // TailCall to extract these masks and put the correct masks into
679 // the tail_call_rms array.
680 for( i=1; i < root->req(); i++ ) {
681 MachReturnNode *m = root->in(i)->as_MachReturn();
682 if( m->ideal_Opcode() == Op_TailCall ) {
683 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
684 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
685 break;
686 }
687 }
688
689 // TailJumps have 2 returned values (target & ex_oop), whose masks come
690 // from the usual MachNode/MachOper mechanism. Find a sample
691 // TailJump to extract these masks and put the correct masks into
692 // the tail_jump_rms array.
693 for( i=1; i < root->req(); i++ ) {
694 MachReturnNode *m = root->in(i)->as_MachReturn();
695 if( m->ideal_Opcode() == Op_TailJump ) {
696 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
697 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
698 break;
699 }
700 }
701
702 // Input RegMask array shared by all Halts
703 uint halt_edge_cnt = TypeFunc::Parms;
704 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
705
706 // Capture the return input masks into each exit flavor
707 for( i=1; i < root->req(); i++ ) {
708 MachReturnNode *exit = root->in(i)->as_MachReturn();
709 switch( exit->ideal_Opcode() ) {
710 case Op_Return : exit->_in_rms = ret_rms; break;
711 case Op_Rethrow : exit->_in_rms = reth_rms; break;
712 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
713 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
714 case Op_Halt : exit->_in_rms = halt_rms; break;
715 default : ShouldNotReachHere();
716 }
717 }
718
719 // Next unused projection number from Start.
720 int proj_cnt = C->tf()->domain()->cnt();
721
722 // Do all the save-on-entry registers. Make projections from Start for
723 // them, and give them a use at the exit points. To the allocator, they
724 // look like incoming register arguments.
725 for( i = 0; i < _last_Mach_Reg; i++ ) {
726 if( is_save_on_entry(i) ) {
727
728 // Add the save-on-entry to the mask array
729 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
730 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
731 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
732 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
733 // Halts need the SOE registers, but only in the stack as debug info.
734 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
735 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
736
737 Node *mproj;
738
739 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
740 // into a single RegD.
741 if( (i&1) == 0 &&
742 _register_save_type[i ] == Op_RegF &&
743 _register_save_type[i+1] == Op_RegF &&
744 is_save_on_entry(i+1) ) {
745 // Add other bit for double
746 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
747 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
748 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
749 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
750 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
751 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
752 proj_cnt += 2; // Skip 2 for doubles
753 }
754 else if( (i&1) == 1 && // Else check for high half of double
755 _register_save_type[i-1] == Op_RegF &&
756 _register_save_type[i ] == Op_RegF &&
757 is_save_on_entry(i-1) ) {
758 ret_rms [ ret_edge_cnt] = RegMask::Empty;
759 reth_rms [ reth_edge_cnt] = RegMask::Empty;
760 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
761 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
762 halt_rms [ halt_edge_cnt] = RegMask::Empty;
763 mproj = C->top();
764 }
765 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
766 // into a single RegL.
767 else if( (i&1) == 0 &&
768 _register_save_type[i ] == Op_RegI &&
769 _register_save_type[i+1] == Op_RegI &&
770 is_save_on_entry(i+1) ) {
771 // Add other bit for long
772 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
773 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
774 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
775 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
776 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
777 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
778 proj_cnt += 2; // Skip 2 for longs
779 }
780 else if( (i&1) == 1 && // Else check for high half of long
781 _register_save_type[i-1] == Op_RegI &&
782 _register_save_type[i ] == Op_RegI &&
783 is_save_on_entry(i-1) ) {
784 ret_rms [ ret_edge_cnt] = RegMask::Empty;
785 reth_rms [ reth_edge_cnt] = RegMask::Empty;
786 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
787 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
788 halt_rms [ halt_edge_cnt] = RegMask::Empty;
789 mproj = C->top();
790 } else {
791 // Make a projection for it off the Start
792 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
793 }
794
795 ret_edge_cnt ++;
796 reth_edge_cnt ++;
797 tail_call_edge_cnt ++;
798 tail_jump_edge_cnt ++;
799 halt_edge_cnt ++;
800
801 // Add a use of the SOE register to all exit paths
802 for( uint j=1; j < root->req(); j++ )
803 root->in(j)->add_req(mproj);
804 } // End of if a save-on-entry register
805 } // End of for all machine registers
806 }
807
808 //------------------------------init_spill_mask--------------------------------
809 void Matcher::init_spill_mask( Node *ret ) {
810 if( idealreg2regmask[Op_RegI] ) return; // One time only init
811
812 OptoReg::c_frame_pointer = c_frame_pointer();
813 c_frame_ptr_mask = c_frame_pointer();
814 #ifdef _LP64
815 // pointers are twice as big
816 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
817 #endif
818
819 // Start at OptoReg::stack0()
820 STACK_ONLY_mask.Clear();
821 OptoReg::Name init = OptoReg::stack2reg(0);
822 // STACK_ONLY_mask is all stack bits
823 OptoReg::Name i;
824 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
825 STACK_ONLY_mask.Insert(i);
826 // Also set the "infinite stack" bit.
827 STACK_ONLY_mask.set_AllStack();
828
829 // Copy the register names over into the shared world
830 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
831 // SharedInfo::regName[i] = regName[i];
832 // Handy RegMasks per machine register
833 mreg2regmask[i].Insert(i);
834 }
835
836 // Grab the Frame Pointer
837 Node *fp = ret->in(TypeFunc::FramePtr);
838 Node *mem = ret->in(TypeFunc::Memory);
839 const TypePtr* atp = TypePtr::BOTTOM;
840 // Share frame pointer while making spill ops
841 set_shared(fp);
842
843 // Compute generic short-offset Loads
844 #ifdef _LP64
845 MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
846 #endif
847 MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
848 MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false));
849 MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
850 MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
851 MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
852 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
853 spillD != NULL && spillP != NULL, "");
854 // Get the ADLC notion of the right regmask, for each basic type.
855 #ifdef _LP64
856 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
857 #endif
858 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
859 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
860 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
861 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
862 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
863
864 // Vector regmasks.
865 if (Matcher::vector_size_supported(T_BYTE,4)) {
866 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
867 MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
868 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
869 }
870 if (Matcher::vector_size_supported(T_FLOAT,2)) {
871 MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
872 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
873 }
874 if (Matcher::vector_size_supported(T_FLOAT,4)) {
875 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
876 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
877 }
878 if (Matcher::vector_size_supported(T_FLOAT,8)) {
879 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
880 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
881 }
882 if (Matcher::vector_size_supported(T_FLOAT,16)) {
883 MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ));
884 idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask();
885 }
886 }
887
888 #ifdef ASSERT
889 static void match_alias_type(Compile* C, Node* n, Node* m) {
890 if (!VerifyAliases) return; // do not go looking for trouble by default
891 const TypePtr* nat = n->adr_type();
892 const TypePtr* mat = m->adr_type();
893 int nidx = C->get_alias_index(nat);
894 int midx = C->get_alias_index(mat);
895 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
896 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
897 for (uint i = 1; i < n->req(); i++) {
898 Node* n1 = n->in(i);
899 const TypePtr* n1at = n1->adr_type();
900 if (n1at != NULL) {
901 nat = n1at;
902 nidx = C->get_alias_index(n1at);
903 }
904 }
905 }
906 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
907 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
908 switch (n->Opcode()) {
909 case Op_PrefetchAllocation:
910 nidx = Compile::AliasIdxRaw;
911 nat = TypeRawPtr::BOTTOM;
912 break;
913 }
914 }
915 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
916 switch (n->Opcode()) {
917 case Op_ClearArray:
918 midx = Compile::AliasIdxRaw;
919 mat = TypeRawPtr::BOTTOM;
920 break;
921 }
922 }
923 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
924 switch (n->Opcode()) {
925 case Op_Return:
926 case Op_Rethrow:
927 case Op_Halt:
928 case Op_TailCall:
929 case Op_TailJump:
930 nidx = Compile::AliasIdxBot;
931 nat = TypePtr::BOTTOM;
932 break;
933 }
934 }
935 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
936 switch (n->Opcode()) {
937 case Op_StrComp:
938 case Op_StrEquals:
939 case Op_StrIndexOf:
940 case Op_StrIndexOfChar:
941 case Op_AryEq:
942 case Op_HasNegatives:
943 case Op_MemBarVolatile:
944 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
945 case Op_StrInflatedCopy:
946 case Op_StrCompressedCopy:
947 case Op_EncodeISOArray:
948 nidx = Compile::AliasIdxTop;
949 nat = NULL;
950 break;
951 }
952 }
953 if (nidx != midx) {
954 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
955 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
956 n->dump();
957 m->dump();
958 }
959 assert(C->subsume_loads() && C->must_alias(nat, midx),
960 "must not lose alias info when matching");
961 }
962 }
963 #endif
964
965
966 //------------------------------MStack-----------------------------------------
967 // State and MStack class used in xform() and find_shared() iterative methods.
968 enum Node_State { Pre_Visit, // node has to be pre-visited
969 Visit, // visit node
970 Post_Visit, // post-visit node
971 Alt_Post_Visit // alternative post-visit path
972 };
973
974 class MStack: public Node_Stack {
975 public:
976 MStack(int size) : Node_Stack(size) { }
977
978 void push(Node *n, Node_State ns) {
979 Node_Stack::push(n, (uint)ns);
980 }
981 void push(Node *n, Node_State ns, Node *parent, int indx) {
982 ++_inode_top;
983 if ((_inode_top + 1) >= _inode_max) grow();
984 _inode_top->node = parent;
985 _inode_top->indx = (uint)indx;
986 ++_inode_top;
987 _inode_top->node = n;
988 _inode_top->indx = (uint)ns;
989 }
990 Node *parent() {
991 pop();
992 return node();
993 }
994 Node_State state() const {
995 return (Node_State)index();
996 }
997 void set_state(Node_State ns) {
998 set_index((uint)ns);
999 }
1000 };
1001
1002
1003 //------------------------------xform------------------------------------------
1004 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
1005 // Node in new-space. Given a new-space Node, recursively walk his children.
1006 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
1007 Node *Matcher::xform( Node *n, int max_stack ) {
1008 // Use one stack to keep both: child's node/state and parent's node/index
1009 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1010 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
1011
1012 while (mstack.is_nonempty()) {
1013 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1014 if (C->failing()) return NULL;
1015 n = mstack.node(); // Leave node on stack
1016 Node_State nstate = mstack.state();
1017 if (nstate == Visit) {
1018 mstack.set_state(Post_Visit);
1019 Node *oldn = n;
1020 // Old-space or new-space check
1021 if (!C->node_arena()->contains(n)) {
1022 // Old space!
1023 Node* m;
1024 if (has_new_node(n)) { // Not yet Label/Reduced
1025 m = new_node(n);
1026 } else {
1027 if (!is_dontcare(n)) { // Matcher can match this guy
1028 // Calls match special. They match alone with no children.
1029 // Their children, the incoming arguments, match normally.
1030 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1031 if (C->failing()) return NULL;
1032 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1033 } else { // Nothing the matcher cares about
1034 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
1035 // Convert to machine-dependent projection
1036 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1037 #ifdef ASSERT
1038 _new2old_map.map(m->_idx, n);
1039 #endif
1040 if (m->in(0) != NULL) // m might be top
1041 collect_null_checks(m, n);
1042 } else { // Else just a regular 'ol guy
1043 m = n->clone(); // So just clone into new-space
1044 #ifdef ASSERT
1045 _new2old_map.map(m->_idx, n);
1046 #endif
1047 // Def-Use edges will be added incrementally as Uses
1048 // of this node are matched.
1049 assert(m->outcnt() == 0, "no Uses of this clone yet");
1050 }
1051 }
1052
1053 set_new_node(n, m); // Map old to new
1054 if (_old_node_note_array != NULL) {
1055 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1056 n->_idx);
1057 C->set_node_notes_at(m->_idx, nn);
1058 }
1059 debug_only(match_alias_type(C, n, m));
1060 }
1061 n = m; // n is now a new-space node
1062 mstack.set_node(n);
1063 }
1064
1065 // New space!
1066 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1067
1068 int i;
1069 // Put precedence edges on stack first (match them last).
1070 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1071 Node *m = oldn->in(i);
1072 if (m == NULL) break;
1073 // set -1 to call add_prec() instead of set_req() during Step1
1074 mstack.push(m, Visit, n, -1);
1075 }
1076
1077 // Handle precedence edges for interior nodes
1078 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1079 Node *m = n->in(i);
1080 if (m == NULL || C->node_arena()->contains(m)) continue;
1081 n->rm_prec(i);
1082 // set -1 to call add_prec() instead of set_req() during Step1
1083 mstack.push(m, Visit, n, -1);
1084 }
1085
1086 // For constant debug info, I'd rather have unmatched constants.
1087 int cnt = n->req();
1088 JVMState* jvms = n->jvms();
1089 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1090
1091 // Now do only debug info. Clone constants rather than matching.
1092 // Constants are represented directly in the debug info without
1093 // the need for executable machine instructions.
1094 // Monitor boxes are also represented directly.
1095 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1096 Node *m = n->in(i); // Get input
1097 int op = m->Opcode();
1098 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1099 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1100 op == Op_ConF || op == Op_ConD || op == Op_ConL
1101 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1102 ) {
1103 m = m->clone();
1104 #ifdef ASSERT
1105 _new2old_map.map(m->_idx, n);
1106 #endif
1107 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1108 mstack.push(m->in(0), Visit, m, 0);
1109 } else {
1110 mstack.push(m, Visit, n, i);
1111 }
1112 }
1113
1114 // And now walk his children, and convert his inputs to new-space.
1115 for( ; i >= 0; --i ) { // For all normal inputs do
1116 Node *m = n->in(i); // Get input
1117 if(m != NULL)
1118 mstack.push(m, Visit, n, i);
1119 }
1120
1121 }
1122 else if (nstate == Post_Visit) {
1123 // Set xformed input
1124 Node *p = mstack.parent();
1125 if (p != NULL) { // root doesn't have parent
1126 int i = (int)mstack.index();
1127 if (i >= 0)
1128 p->set_req(i, n); // required input
1129 else if (i == -1)
1130 p->add_prec(n); // precedence input
1131 else
1132 ShouldNotReachHere();
1133 }
1134 mstack.pop(); // remove processed node from stack
1135 }
1136 else {
1137 ShouldNotReachHere();
1138 }
1139 } // while (mstack.is_nonempty())
1140 return n; // Return new-space Node
1141 }
1142
1143 //------------------------------warp_outgoing_stk_arg------------------------
1144 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1145 // Convert outgoing argument location to a pre-biased stack offset
1146 if (reg->is_stack()) {
1147 OptoReg::Name warped = reg->reg2stack();
1148 // Adjust the stack slot offset to be the register number used
1149 // by the allocator.
1150 warped = OptoReg::add(begin_out_arg_area, warped);
1151 // Keep track of the largest numbered stack slot used for an arg.
1152 // Largest used slot per call-site indicates the amount of stack
1153 // that is killed by the call.
1154 if( warped >= out_arg_limit_per_call )
1155 out_arg_limit_per_call = OptoReg::add(warped,1);
1156 if (!RegMask::can_represent_arg(warped)) {
1157 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1158 return OptoReg::Bad;
1159 }
1160 return warped;
1161 }
1162 return OptoReg::as_OptoReg(reg);
1163 }
1164
1165
1166 //------------------------------match_sfpt-------------------------------------
1167 // Helper function to match call instructions. Calls match special.
1168 // They match alone with no children. Their children, the incoming
1169 // arguments, match normally.
1170 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1171 MachSafePointNode *msfpt = NULL;
1172 MachCallNode *mcall = NULL;
1173 uint cnt;
1174 // Split out case for SafePoint vs Call
1175 CallNode *call;
1176 const TypeTuple *domain;
1177 ciMethod* method = NULL;
1178 bool is_method_handle_invoke = false; // for special kill effects
1179 if( sfpt->is_Call() ) {
1180 call = sfpt->as_Call();
1181 domain = call->tf()->domain();
1182 cnt = domain->cnt();
1183
1184 // Match just the call, nothing else
1185 MachNode *m = match_tree(call);
1186 if (C->failing()) return NULL;
1187 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1188
1189 // Copy data from the Ideal SafePoint to the machine version
1190 mcall = m->as_MachCall();
1191
1192 mcall->set_tf( call->tf());
1193 mcall->set_entry_point(call->entry_point());
1194 mcall->set_cnt( call->cnt());
1195
1196 if( mcall->is_MachCallJava() ) {
1197 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1198 const CallJavaNode *call_java = call->as_CallJava();
1199 method = call_java->method();
1200 mcall_java->_method = method;
1201 mcall_java->_bci = call_java->_bci;
1202 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1203 is_method_handle_invoke = call_java->is_method_handle_invoke();
1204 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1205 mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
1206 if (is_method_handle_invoke) {
1207 C->set_has_method_handle_invokes(true);
1208 }
1209 if( mcall_java->is_MachCallStaticJava() )
1210 mcall_java->as_MachCallStaticJava()->_name =
1211 call_java->as_CallStaticJava()->_name;
1212 if( mcall_java->is_MachCallDynamicJava() )
1213 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1214 call_java->as_CallDynamicJava()->_vtable_index;
1215 }
1216 else if( mcall->is_MachCallRuntime() ) {
1217 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1218 }
1219 msfpt = mcall;
1220 }
1221 // This is a non-call safepoint
1222 else {
1223 call = NULL;
1224 domain = NULL;
1225 MachNode *mn = match_tree(sfpt);
1226 if (C->failing()) return NULL;
1227 msfpt = mn->as_MachSafePoint();
1228 cnt = TypeFunc::Parms;
1229 }
1230
1231 // Advertise the correct memory effects (for anti-dependence computation).
1232 msfpt->set_adr_type(sfpt->adr_type());
1233
1234 // Allocate a private array of RegMasks. These RegMasks are not shared.
1235 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1236 // Empty them all.
1237 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1238
1239 // Do all the pre-defined non-Empty register masks
1240 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1241 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1242
1243 // Place first outgoing argument can possibly be put.
1244 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1245 assert( is_even(begin_out_arg_area), "" );
1246 // Compute max outgoing register number per call site.
1247 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1248 // Calls to C may hammer extra stack slots above and beyond any arguments.
1249 // These are usually backing store for register arguments for varargs.
1250 if( call != NULL && call->is_CallRuntime() )
1251 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1252
1253
1254 // Do the normal argument list (parameters) register masks
1255 int argcnt = cnt - TypeFunc::Parms;
1256 if( argcnt > 0 ) { // Skip it all if we have no args
1257 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1258 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1259 int i;
1260 for( i = 0; i < argcnt; i++ ) {
1261 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1262 }
1263 // V-call to pick proper calling convention
1264 call->calling_convention( sig_bt, parm_regs, argcnt );
1265
1266 #ifdef ASSERT
1267 // Sanity check users' calling convention. Really handy during
1268 // the initial porting effort. Fairly expensive otherwise.
1269 { for (int i = 0; i<argcnt; i++) {
1270 if( !parm_regs[i].first()->is_valid() &&
1271 !parm_regs[i].second()->is_valid() ) continue;
1272 VMReg reg1 = parm_regs[i].first();
1273 VMReg reg2 = parm_regs[i].second();
1274 for (int j = 0; j < i; j++) {
1275 if( !parm_regs[j].first()->is_valid() &&
1276 !parm_regs[j].second()->is_valid() ) continue;
1277 VMReg reg3 = parm_regs[j].first();
1278 VMReg reg4 = parm_regs[j].second();
1279 if( !reg1->is_valid() ) {
1280 assert( !reg2->is_valid(), "valid halvsies" );
1281 } else if( !reg3->is_valid() ) {
1282 assert( !reg4->is_valid(), "valid halvsies" );
1283 } else {
1284 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1285 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1286 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1287 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1288 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1289 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1290 }
1291 }
1292 }
1293 }
1294 #endif
1295
1296 // Visit each argument. Compute its outgoing register mask.
1297 // Return results now can have 2 bits returned.
1298 // Compute max over all outgoing arguments both per call-site
1299 // and over the entire method.
1300 for( i = 0; i < argcnt; i++ ) {
1301 // Address of incoming argument mask to fill in
1302 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1303 if( !parm_regs[i].first()->is_valid() &&
1304 !parm_regs[i].second()->is_valid() ) {
1305 continue; // Avoid Halves
1306 }
1307 // Grab first register, adjust stack slots and insert in mask.
1308 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1309 if (OptoReg::is_valid(reg1))
1310 rm->Insert( reg1 );
1311 // Grab second register (if any), adjust stack slots and insert in mask.
1312 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1313 if (OptoReg::is_valid(reg2))
1314 rm->Insert( reg2 );
1315 } // End of for all arguments
1316
1317 // Compute number of stack slots needed to restore stack in case of
1318 // Pascal-style argument popping.
1319 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1320 }
1321
1322 // Compute the max stack slot killed by any call. These will not be
1323 // available for debug info, and will be used to adjust FIRST_STACK_mask
1324 // after all call sites have been visited.
1325 if( _out_arg_limit < out_arg_limit_per_call)
1326 _out_arg_limit = out_arg_limit_per_call;
1327
1328 if (mcall) {
1329 // Kill the outgoing argument area, including any non-argument holes and
1330 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1331 // Since the max-per-method covers the max-per-call-site and debug info
1332 // is excluded on the max-per-method basis, debug info cannot land in
1333 // this killed area.
1334 uint r_cnt = mcall->tf()->range()->cnt();
1335 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1336 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1337 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1338 } else {
1339 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1340 proj->_rout.Insert(OptoReg::Name(i));
1341 }
1342 if (proj->_rout.is_NotEmpty()) {
1343 push_projection(proj);
1344 }
1345 }
1346 // Transfer the safepoint information from the call to the mcall
1347 // Move the JVMState list
1348 msfpt->set_jvms(sfpt->jvms());
1349 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1350 jvms->set_map(sfpt);
1351 }
1352
1353 // Debug inputs begin just after the last incoming parameter
1354 assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1355 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1356
1357 // Move the OopMap
1358 msfpt->_oop_map = sfpt->_oop_map;
1359
1360 // Add additional edges.
1361 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1362 // For these calls we can not add MachConstantBase in expand(), as the
1363 // ins are not complete then.
1364 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1365 if (msfpt->jvms() &&
1366 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1367 // We added an edge before jvms, so we must adapt the position of the ins.
1368 msfpt->jvms()->adapt_position(+1);
1369 }
1370 }
1371
1372 // Registers killed by the call are set in the local scheduling pass
1373 // of Global Code Motion.
1374 return msfpt;
1375 }
1376
1377 //---------------------------match_tree----------------------------------------
1378 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1379 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1380 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1381 // a Load's result RegMask for memoization in idealreg2regmask[]
1382 MachNode *Matcher::match_tree( const Node *n ) {
1383 assert( n->Opcode() != Op_Phi, "cannot match" );
1384 assert( !n->is_block_start(), "cannot match" );
1385 // Set the mark for all locally allocated State objects.
1386 // When this call returns, the _states_arena arena will be reset
1387 // freeing all State objects.
1388 ResourceMark rm( &_states_arena );
1389
1390 LabelRootDepth = 0;
1391
1392 // StoreNodes require their Memory input to match any LoadNodes
1393 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1394 #ifdef ASSERT
1395 Node* save_mem_node = _mem_node;
1396 _mem_node = n->is_Store() ? (Node*)n : NULL;
1397 #endif
1398 // State object for root node of match tree
1399 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1400 State *s = new (&_states_arena) State;
1401 s->_kids[0] = NULL;
1402 s->_kids[1] = NULL;
1403 s->_leaf = (Node*)n;
1404 // Label the input tree, allocating labels from top-level arena
1405 Label_Root( n, s, n->in(0), mem );
1406 if (C->failing()) return NULL;
1407
1408 // The minimum cost match for the whole tree is found at the root State
1409 uint mincost = max_juint;
1410 uint cost = max_juint;
1411 uint i;
1412 for( i = 0; i < NUM_OPERANDS; i++ ) {
1413 if( s->valid(i) && // valid entry and
1414 s->_cost[i] < cost && // low cost and
1415 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1416 cost = s->_cost[mincost=i];
1417 }
1418 if (mincost == max_juint) {
1419 #ifndef PRODUCT
1420 tty->print("No matching rule for:");
1421 s->dump();
1422 #endif
1423 Matcher::soft_match_failure();
1424 return NULL;
1425 }
1426 // Reduce input tree based upon the state labels to machine Nodes
1427 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1428 #ifdef ASSERT
1429 _old2new_map.map(n->_idx, m);
1430 _new2old_map.map(m->_idx, (Node*)n);
1431 #endif
1432
1433 // Add any Matcher-ignored edges
1434 uint cnt = n->req();
1435 uint start = 1;
1436 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1437 if( n->is_AddP() ) {
1438 assert( mem == (Node*)1, "" );
1439 start = AddPNode::Base+1;
1440 }
1441 for( i = start; i < cnt; i++ ) {
1442 if( !n->match_edge(i) ) {
1443 if( i < m->req() )
1444 m->ins_req( i, n->in(i) );
1445 else
1446 m->add_req( n->in(i) );
1447 }
1448 }
1449
1450 debug_only( _mem_node = save_mem_node; )
1451 return m;
1452 }
1453
1454
1455 //------------------------------match_into_reg---------------------------------
1456 // Choose to either match this Node in a register or part of the current
1457 // match tree. Return true for requiring a register and false for matching
1458 // as part of the current match tree.
1459 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1460
1461 const Type *t = m->bottom_type();
1462
1463 if (t->singleton()) {
1464 // Never force constants into registers. Allow them to match as
1465 // constants or registers. Copies of the same value will share
1466 // the same register. See find_shared_node.
1467 return false;
1468 } else { // Not a constant
1469 // Stop recursion if they have different Controls.
1470 Node* m_control = m->in(0);
1471 // Control of load's memory can post-dominates load's control.
1472 // So use it since load can't float above its memory.
1473 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1474 if (control && m_control && control != m_control && control != mem_control) {
1475
1476 // Actually, we can live with the most conservative control we
1477 // find, if it post-dominates the others. This allows us to
1478 // pick up load/op/store trees where the load can float a little
1479 // above the store.
1480 Node *x = control;
1481 const uint max_scan = 6; // Arbitrary scan cutoff
1482 uint j;
1483 for (j=0; j<max_scan; j++) {
1484 if (x->is_Region()) // Bail out at merge points
1485 return true;
1486 x = x->in(0);
1487 if (x == m_control) // Does 'control' post-dominate
1488 break; // m->in(0)? If so, we can use it
1489 if (x == mem_control) // Does 'control' post-dominate
1490 break; // mem_control? If so, we can use it
1491 }
1492 if (j == max_scan) // No post-domination before scan end?
1493 return true; // Then break the match tree up
1494 }
1495 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1496 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1497 // These are commonly used in address expressions and can
1498 // efficiently fold into them on X64 in some cases.
1499 return false;
1500 }
1501 }
1502
1503 // Not forceable cloning. If shared, put it into a register.
1504 return shared;
1505 }
1506
1507
1508 //------------------------------Instruction Selection--------------------------
1509 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1510 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1511 // things the Matcher does not match (e.g., Memory), and things with different
1512 // Controls (hence forced into different blocks). We pass in the Control
1513 // selected for this entire State tree.
1514
1515 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1516 // Store and the Load must have identical Memories (as well as identical
1517 // pointers). Since the Matcher does not have anything for Memory (and
1518 // does not handle DAGs), I have to match the Memory input myself. If the
1519 // Tree root is a Store, I require all Loads to have the identical memory.
1520 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1521 // Since Label_Root is a recursive function, its possible that we might run
1522 // out of stack space. See bugs 6272980 & 6227033 for more info.
1523 LabelRootDepth++;
1524 if (LabelRootDepth > MaxLabelRootDepth) {
1525 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1526 return NULL;
1527 }
1528 uint care = 0; // Edges matcher cares about
1529 uint cnt = n->req();
1530 uint i = 0;
1531
1532 // Examine children for memory state
1533 // Can only subsume a child into your match-tree if that child's memory state
1534 // is not modified along the path to another input.
1535 // It is unsafe even if the other inputs are separate roots.
1536 Node *input_mem = NULL;
1537 for( i = 1; i < cnt; i++ ) {
1538 if( !n->match_edge(i) ) continue;
1539 Node *m = n->in(i); // Get ith input
1540 assert( m, "expect non-null children" );
1541 if( m->is_Load() ) {
1542 if( input_mem == NULL ) {
1543 input_mem = m->in(MemNode::Memory);
1544 } else if( input_mem != m->in(MemNode::Memory) ) {
1545 input_mem = NodeSentinel;
1546 }
1547 }
1548 }
1549
1550 for( i = 1; i < cnt; i++ ){// For my children
1551 if( !n->match_edge(i) ) continue;
1552 Node *m = n->in(i); // Get ith input
1553 // Allocate states out of a private arena
1554 State *s = new (&_states_arena) State;
1555 svec->_kids[care++] = s;
1556 assert( care <= 2, "binary only for now" );
1557
1558 // Recursively label the State tree.
1559 s->_kids[0] = NULL;
1560 s->_kids[1] = NULL;
1561 s->_leaf = m;
1562
1563 // Check for leaves of the State Tree; things that cannot be a part of
1564 // the current tree. If it finds any, that value is matched as a
1565 // register operand. If not, then the normal matching is used.
1566 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1567 //
1568 // Stop recursion if this is LoadNode and the root of this tree is a
1569 // StoreNode and the load & store have different memories.
1570 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1571 // Can NOT include the match of a subtree when its memory state
1572 // is used by any of the other subtrees
1573 (input_mem == NodeSentinel) ) {
1574 // Print when we exclude matching due to different memory states at input-loads
1575 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1576 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) {
1577 tty->print_cr("invalid input_mem");
1578 }
1579 // Switch to a register-only opcode; this value must be in a register
1580 // and cannot be subsumed as part of a larger instruction.
1581 s->DFA( m->ideal_reg(), m );
1582
1583 } else {
1584 // If match tree has no control and we do, adopt it for entire tree
1585 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1586 control = m->in(0); // Pick up control
1587 // Else match as a normal part of the match tree.
1588 control = Label_Root(m,s,control,mem);
1589 if (C->failing()) return NULL;
1590 }
1591 }
1592
1593
1594 // Call DFA to match this node, and return
1595 svec->DFA( n->Opcode(), n );
1596
1597 #ifdef ASSERT
1598 uint x;
1599 for( x = 0; x < _LAST_MACH_OPER; x++ )
1600 if( svec->valid(x) )
1601 break;
1602
1603 if (x >= _LAST_MACH_OPER) {
1604 n->dump();
1605 svec->dump();
1606 assert( false, "bad AD file" );
1607 }
1608 #endif
1609 return control;
1610 }
1611
1612
1613 // Con nodes reduced using the same rule can share their MachNode
1614 // which reduces the number of copies of a constant in the final
1615 // program. The register allocator is free to split uses later to
1616 // split live ranges.
1617 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1618 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1619
1620 // See if this Con has already been reduced using this rule.
1621 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1622 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1623 if (last != NULL && rule == last->rule()) {
1624 // Don't expect control change for DecodeN
1625 if (leaf->is_DecodeNarrowPtr())
1626 return last;
1627 // Get the new space root.
1628 Node* xroot = new_node(C->root());
1629 if (xroot == NULL) {
1630 // This shouldn't happen give the order of matching.
1631 return NULL;
1632 }
1633
1634 // Shared constants need to have their control be root so they
1635 // can be scheduled properly.
1636 Node* control = last->in(0);
1637 if (control != xroot) {
1638 if (control == NULL || control == C->root()) {
1639 last->set_req(0, xroot);
1640 } else {
1641 assert(false, "unexpected control");
1642 return NULL;
1643 }
1644 }
1645 return last;
1646 }
1647 return NULL;
1648 }
1649
1650
1651 //------------------------------ReduceInst-------------------------------------
1652 // Reduce a State tree (with given Control) into a tree of MachNodes.
1653 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1654 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1655 // Each MachNode has a number of complicated MachOper operands; each
1656 // MachOper also covers a further tree of Ideal Nodes.
1657
1658 // The root of the Ideal match tree is always an instruction, so we enter
1659 // the recursion here. After building the MachNode, we need to recurse
1660 // the tree checking for these cases:
1661 // (1) Child is an instruction -
1662 // Build the instruction (recursively), add it as an edge.
1663 // Build a simple operand (register) to hold the result of the instruction.
1664 // (2) Child is an interior part of an instruction -
1665 // Skip over it (do nothing)
1666 // (3) Child is the start of a operand -
1667 // Build the operand, place it inside the instruction
1668 // Call ReduceOper.
1669 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1670 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1671
1672 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1673 if (shared_node != NULL) {
1674 return shared_node;
1675 }
1676
1677 // Build the object to represent this state & prepare for recursive calls
1678 MachNode *mach = s->MachNodeGenerator(rule);
1679 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1680 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1681 Node *leaf = s->_leaf;
1682 // Check for instruction or instruction chain rule
1683 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1684 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1685 "duplicating node that's already been matched");
1686 // Instruction
1687 mach->add_req( leaf->in(0) ); // Set initial control
1688 // Reduce interior of complex instruction
1689 ReduceInst_Interior( s, rule, mem, mach, 1 );
1690 } else {
1691 // Instruction chain rules are data-dependent on their inputs
1692 mach->add_req(0); // Set initial control to none
1693 ReduceInst_Chain_Rule( s, rule, mem, mach );
1694 }
1695
1696 // If a Memory was used, insert a Memory edge
1697 if( mem != (Node*)1 ) {
1698 mach->ins_req(MemNode::Memory,mem);
1699 #ifdef ASSERT
1700 // Verify adr type after matching memory operation
1701 const MachOper* oper = mach->memory_operand();
1702 if (oper != NULL && oper != (MachOper*)-1) {
1703 // It has a unique memory operand. Find corresponding ideal mem node.
1704 Node* m = NULL;
1705 if (leaf->is_Mem()) {
1706 m = leaf;
1707 } else {
1708 m = _mem_node;
1709 assert(m != NULL && m->is_Mem(), "expecting memory node");
1710 }
1711 const Type* mach_at = mach->adr_type();
1712 // DecodeN node consumed by an address may have different type
1713 // then its input. Don't compare types for such case.
1714 if (m->adr_type() != mach_at &&
1715 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1716 m->in(MemNode::Address)->is_AddP() &&
1717 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1718 m->in(MemNode::Address)->is_AddP() &&
1719 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1720 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1721 mach_at = m->adr_type();
1722 }
1723 if (m->adr_type() != mach_at) {
1724 m->dump();
1725 tty->print_cr("mach:");
1726 mach->dump(1);
1727 }
1728 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1729 }
1730 #endif
1731 }
1732
1733 // If the _leaf is an AddP, insert the base edge
1734 if (leaf->is_AddP()) {
1735 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1736 }
1737
1738 uint number_of_projections_prior = number_of_projections();
1739
1740 // Perform any 1-to-many expansions required
1741 MachNode *ex = mach->Expand(s, _projection_list, mem);
1742 if (ex != mach) {
1743 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1744 if( ex->in(1)->is_Con() )
1745 ex->in(1)->set_req(0, C->root());
1746 // Remove old node from the graph
1747 for( uint i=0; i<mach->req(); i++ ) {
1748 mach->set_req(i,NULL);
1749 }
1750 #ifdef ASSERT
1751 _new2old_map.map(ex->_idx, s->_leaf);
1752 #endif
1753 }
1754
1755 // PhaseChaitin::fixup_spills will sometimes generate spill code
1756 // via the matcher. By the time, nodes have been wired into the CFG,
1757 // and any further nodes generated by expand rules will be left hanging
1758 // in space, and will not get emitted as output code. Catch this.
1759 // Also, catch any new register allocation constraints ("projections")
1760 // generated belatedly during spill code generation.
1761 if (_allocation_started) {
1762 guarantee(ex == mach, "no expand rules during spill generation");
1763 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1764 }
1765
1766 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1767 // Record the con for sharing
1768 _shared_nodes.map(leaf->_idx, ex);
1769 }
1770
1771 return ex;
1772 }
1773
1774 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1775 for (uint i = n->req(); i < n->len(); i++) {
1776 if (n->in(i) != NULL) {
1777 mach->add_prec(n->in(i));
1778 }
1779 }
1780 }
1781
1782 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1783 // 'op' is what I am expecting to receive
1784 int op = _leftOp[rule];
1785 // Operand type to catch childs result
1786 // This is what my child will give me.
1787 int opnd_class_instance = s->_rule[op];
1788 // Choose between operand class or not.
1789 // This is what I will receive.
1790 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1791 // New rule for child. Chase operand classes to get the actual rule.
1792 int newrule = s->_rule[catch_op];
1793
1794 if( newrule < NUM_OPERANDS ) {
1795 // Chain from operand or operand class, may be output of shared node
1796 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1797 "Bad AD file: Instruction chain rule must chain from operand");
1798 // Insert operand into array of operands for this instruction
1799 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1800
1801 ReduceOper( s, newrule, mem, mach );
1802 } else {
1803 // Chain from the result of an instruction
1804 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1805 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1806 Node *mem1 = (Node*)1;
1807 debug_only(Node *save_mem_node = _mem_node;)
1808 mach->add_req( ReduceInst(s, newrule, mem1) );
1809 debug_only(_mem_node = save_mem_node;)
1810 }
1811 return;
1812 }
1813
1814
1815 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1816 handle_precedence_edges(s->_leaf, mach);
1817
1818 if( s->_leaf->is_Load() ) {
1819 Node *mem2 = s->_leaf->in(MemNode::Memory);
1820 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1821 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1822 mem = mem2;
1823 }
1824 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1825 if( mach->in(0) == NULL )
1826 mach->set_req(0, s->_leaf->in(0));
1827 }
1828
1829 // Now recursively walk the state tree & add operand list.
1830 for( uint i=0; i<2; i++ ) { // binary tree
1831 State *newstate = s->_kids[i];
1832 if( newstate == NULL ) break; // Might only have 1 child
1833 // 'op' is what I am expecting to receive
1834 int op;
1835 if( i == 0 ) {
1836 op = _leftOp[rule];
1837 } else {
1838 op = _rightOp[rule];
1839 }
1840 // Operand type to catch childs result
1841 // This is what my child will give me.
1842 int opnd_class_instance = newstate->_rule[op];
1843 // Choose between operand class or not.
1844 // This is what I will receive.
1845 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1846 // New rule for child. Chase operand classes to get the actual rule.
1847 int newrule = newstate->_rule[catch_op];
1848
1849 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1850 // Operand/operandClass
1851 // Insert operand into array of operands for this instruction
1852 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
1853 ReduceOper( newstate, newrule, mem, mach );
1854
1855 } else { // Child is internal operand or new instruction
1856 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1857 // internal operand --> call ReduceInst_Interior
1858 // Interior of complex instruction. Do nothing but recurse.
1859 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1860 } else {
1861 // instruction --> call build operand( ) to catch result
1862 // --> ReduceInst( newrule )
1863 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
1864 Node *mem1 = (Node*)1;
1865 debug_only(Node *save_mem_node = _mem_node;)
1866 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1867 debug_only(_mem_node = save_mem_node;)
1868 }
1869 }
1870 assert( mach->_opnds[num_opnds-1], "" );
1871 }
1872 return num_opnds;
1873 }
1874
1875 // This routine walks the interior of possible complex operands.
1876 // At each point we check our children in the match tree:
1877 // (1) No children -
1878 // We are a leaf; add _leaf field as an input to the MachNode
1879 // (2) Child is an internal operand -
1880 // Skip over it ( do nothing )
1881 // (3) Child is an instruction -
1882 // Call ReduceInst recursively and
1883 // and instruction as an input to the MachNode
1884 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1885 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1886 State *kid = s->_kids[0];
1887 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1888
1889 // Leaf? And not subsumed?
1890 if( kid == NULL && !_swallowed[rule] ) {
1891 mach->add_req( s->_leaf ); // Add leaf pointer
1892 return; // Bail out
1893 }
1894
1895 if( s->_leaf->is_Load() ) {
1896 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1897 mem = s->_leaf->in(MemNode::Memory);
1898 debug_only(_mem_node = s->_leaf;)
1899 }
1900
1901 handle_precedence_edges(s->_leaf, mach);
1902
1903 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1904 if( !mach->in(0) )
1905 mach->set_req(0,s->_leaf->in(0));
1906 else {
1907 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1908 }
1909 }
1910
1911 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1912 int newrule;
1913 if( i == 0)
1914 newrule = kid->_rule[_leftOp[rule]];
1915 else
1916 newrule = kid->_rule[_rightOp[rule]];
1917
1918 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1919 // Internal operand; recurse but do nothing else
1920 ReduceOper( kid, newrule, mem, mach );
1921
1922 } else { // Child is a new instruction
1923 // Reduce the instruction, and add a direct pointer from this
1924 // machine instruction to the newly reduced one.
1925 Node *mem1 = (Node*)1;
1926 debug_only(Node *save_mem_node = _mem_node;)
1927 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1928 debug_only(_mem_node = save_mem_node;)
1929 }
1930 }
1931 }
1932
1933
1934 // -------------------------------------------------------------------------
1935 // Java-Java calling convention
1936 // (what you use when Java calls Java)
1937
1938 //------------------------------find_receiver----------------------------------
1939 // For a given signature, return the OptoReg for parameter 0.
1940 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1941 VMRegPair regs;
1942 BasicType sig_bt = T_OBJECT;
1943 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1944 // Return argument 0 register. In the LP64 build pointers
1945 // take 2 registers, but the VM wants only the 'main' name.
1946 return OptoReg::as_OptoReg(regs.first());
1947 }
1948
1949 // This function identifies sub-graphs in which a 'load' node is
1950 // input to two different nodes, and such that it can be matched
1951 // with BMI instructions like blsi, blsr, etc.
1952 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1953 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1954 // refers to the same node.
1955 #ifdef X86
1956 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1957 // This is a temporary solution until we make DAGs expressible in ADL.
1958 template<typename ConType>
1959 class FusedPatternMatcher {
1960 Node* _op1_node;
1961 Node* _mop_node;
1962 int _con_op;
1963
1964 static int match_next(Node* n, int next_op, int next_op_idx) {
1965 if (n->in(1) == NULL || n->in(2) == NULL) {
1966 return -1;
1967 }
1968
1969 if (next_op_idx == -1) { // n is commutative, try rotations
1970 if (n->in(1)->Opcode() == next_op) {
1971 return 1;
1972 } else if (n->in(2)->Opcode() == next_op) {
1973 return 2;
1974 }
1975 } else {
1976 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1977 if (n->in(next_op_idx)->Opcode() == next_op) {
1978 return next_op_idx;
1979 }
1980 }
1981 return -1;
1982 }
1983 public:
1984 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1985 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1986
1987 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1988 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
1989 typename ConType::NativeType con_value) {
1990 if (_op1_node->Opcode() != op1) {
1991 return false;
1992 }
1993 if (_mop_node->outcnt() > 2) {
1994 return false;
1995 }
1996 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1997 if (op1_op2_idx == -1) {
1998 return false;
1999 }
2000 // Memory operation must be the other edge
2001 int op1_mop_idx = (op1_op2_idx & 1) + 1;
2002
2003 // Check that the mop node is really what we want
2004 if (_op1_node->in(op1_mop_idx) == _mop_node) {
2005 Node *op2_node = _op1_node->in(op1_op2_idx);
2006 if (op2_node->outcnt() > 1) {
2007 return false;
2008 }
2009 assert(op2_node->Opcode() == op2, "Should be");
2010 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
2011 if (op2_con_idx == -1) {
2012 return false;
2013 }
2014 // Memory operation must be the other edge
2015 int op2_mop_idx = (op2_con_idx & 1) + 1;
2016 // Check that the memory operation is the same node
2017 if (op2_node->in(op2_mop_idx) == _mop_node) {
2018 // Now check the constant
2019 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
2020 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
2021 return true;
2022 }
2023 }
2024 }
2025 return false;
2026 }
2027 };
2028
2029
2030 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2031 if (n != NULL && m != NULL) {
2032 if (m->Opcode() == Op_LoadI) {
2033 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2034 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) ||
2035 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) ||
2036 bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2037 } else if (m->Opcode() == Op_LoadL) {
2038 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2039 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) ||
2040 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2041 bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2042 }
2043 }
2044 return false;
2045 }
2046 #endif // X86
2047
2048 // A method-klass-holder may be passed in the inline_cache_reg
2049 // and then expanded into the inline_cache_reg and a method_oop register
2050 // defined in ad_<arch>.cpp
2051
2052 // Check for shift by small constant as well
2053 static bool clone_shift(Node* shift, Matcher* matcher, MStack& mstack, VectorSet& address_visited) {
2054 if (shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2055 shift->in(2)->get_int() <= 3 &&
2056 // Are there other uses besides address expressions?
2057 !matcher->is_visited(shift)) {
2058 address_visited.set(shift->_idx); // Flag as address_visited
2059 mstack.push(shift->in(2), Visit);
2060 Node *conv = shift->in(1);
2061 #ifdef _LP64
2062 // Allow Matcher to match the rule which bypass
2063 // ConvI2L operation for an array index on LP64
2064 // if the index value is positive.
2065 if (conv->Opcode() == Op_ConvI2L &&
2066 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2067 // Are there other uses besides address expressions?
2068 !matcher->is_visited(conv)) {
2069 address_visited.set(conv->_idx); // Flag as address_visited
2070 mstack.push(conv->in(1), Pre_Visit);
2071 } else
2072 #endif
2073 mstack.push(conv, Pre_Visit);
2074 return true;
2075 }
2076 return false;
2077 }
2078
2079
2080 //------------------------------find_shared------------------------------------
2081 // Set bits if Node is shared or otherwise a root
2082 void Matcher::find_shared( Node *n ) {
2083 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2084 MStack mstack(C->live_nodes() * 2);
2085 // Mark nodes as address_visited if they are inputs to an address expression
2086 VectorSet address_visited(Thread::current()->resource_area());
2087 mstack.push(n, Visit); // Don't need to pre-visit root node
2088 while (mstack.is_nonempty()) {
2089 n = mstack.node(); // Leave node on stack
2090 Node_State nstate = mstack.state();
2091 uint nop = n->Opcode();
2092 if (nstate == Pre_Visit) {
2093 if (address_visited.test(n->_idx)) { // Visited in address already?
2094 // Flag as visited and shared now.
2095 set_visited(n);
2096 }
2097 if (is_visited(n)) { // Visited already?
2098 // Node is shared and has no reason to clone. Flag it as shared.
2099 // This causes it to match into a register for the sharing.
2100 set_shared(n); // Flag as shared and
2101 mstack.pop(); // remove node from stack
2102 continue;
2103 }
2104 nstate = Visit; // Not already visited; so visit now
2105 }
2106 if (nstate == Visit) {
2107 mstack.set_state(Post_Visit);
2108 set_visited(n); // Flag as visited now
2109 bool mem_op = false;
2110
2111 switch( nop ) { // Handle some opcodes special
2112 case Op_Phi: // Treat Phis as shared roots
2113 case Op_Parm:
2114 case Op_Proj: // All handled specially during matching
2115 case Op_SafePointScalarObject:
2116 set_shared(n);
2117 set_dontcare(n);
2118 break;
2119 case Op_If:
2120 case Op_CountedLoopEnd:
2121 mstack.set_state(Alt_Post_Visit); // Alternative way
2122 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2123 // with matching cmp/branch in 1 instruction. The Matcher needs the
2124 // Bool and CmpX side-by-side, because it can only get at constants
2125 // that are at the leaves of Match trees, and the Bool's condition acts
2126 // as a constant here.
2127 mstack.push(n->in(1), Visit); // Clone the Bool
2128 mstack.push(n->in(0), Pre_Visit); // Visit control input
2129 continue; // while (mstack.is_nonempty())
2130 case Op_ConvI2D: // These forms efficiently match with a prior
2131 case Op_ConvI2F: // Load but not a following Store
2132 if( n->in(1)->is_Load() && // Prior load
2133 n->outcnt() == 1 && // Not already shared
2134 n->unique_out()->is_Store() ) // Following store
2135 set_shared(n); // Force it to be a root
2136 break;
2137 case Op_ReverseBytesI:
2138 case Op_ReverseBytesL:
2139 if( n->in(1)->is_Load() && // Prior load
2140 n->outcnt() == 1 ) // Not already shared
2141 set_shared(n); // Force it to be a root
2142 break;
2143 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
2144 case Op_IfFalse:
2145 case Op_IfTrue:
2146 case Op_MachProj:
2147 case Op_MergeMem:
2148 case Op_Catch:
2149 case Op_CatchProj:
2150 case Op_CProj:
2151 case Op_JumpProj:
2152 case Op_JProj:
2153 case Op_NeverBranch:
2154 set_dontcare(n);
2155 break;
2156 case Op_Jump:
2157 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2158 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2159 continue; // while (mstack.is_nonempty())
2160 case Op_StrComp:
2161 case Op_StrEquals:
2162 case Op_StrIndexOf:
2163 case Op_StrIndexOfChar:
2164 case Op_AryEq:
2165 case Op_HasNegatives:
2166 case Op_StrInflatedCopy:
2167 case Op_StrCompressedCopy:
2168 case Op_EncodeISOArray:
2169 set_shared(n); // Force result into register (it will be anyways)
2170 break;
2171 case Op_ConP: { // Convert pointers above the centerline to NUL
2172 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2173 const TypePtr* tp = tn->type()->is_ptr();
2174 if (tp->_ptr == TypePtr::AnyNull) {
2175 tn->set_type(TypePtr::NULL_PTR);
2176 }
2177 break;
2178 }
2179 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2180 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2181 const TypePtr* tp = tn->type()->make_ptr();
2182 if (tp && tp->_ptr == TypePtr::AnyNull) {
2183 tn->set_type(TypeNarrowOop::NULL_PTR);
2184 }
2185 break;
2186 }
2187 case Op_Binary: // These are introduced in the Post_Visit state.
2188 ShouldNotReachHere();
2189 break;
2190 case Op_ClearArray:
2191 case Op_SafePoint:
2192 mem_op = true;
2193 break;
2194 default:
2195 if( n->is_Store() ) {
2196 // Do match stores, despite no ideal reg
2197 mem_op = true;
2198 break;
2199 }
2200 if( n->is_Mem() ) { // Loads and LoadStores
2201 mem_op = true;
2202 // Loads must be root of match tree due to prior load conflict
2203 if( C->subsume_loads() == false )
2204 set_shared(n);
2205 }
2206 // Fall into default case
2207 if( !n->ideal_reg() )
2208 set_dontcare(n); // Unmatchable Nodes
2209 } // end_switch
2210
2211 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2212 Node *m = n->in(i); // Get ith input
2213 if (m == NULL) continue; // Ignore NULLs
2214 uint mop = m->Opcode();
2215
2216 // Must clone all producers of flags, or we will not match correctly.
2217 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2218 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2219 // are also there, so we may match a float-branch to int-flags and
2220 // expect the allocator to haul the flags from the int-side to the
2221 // fp-side. No can do.
2222 if( _must_clone[mop] ) {
2223 mstack.push(m, Visit);
2224 continue; // for(int i = ...)
2225 }
2226
2227 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2228 // Bases used in addresses must be shared but since
2229 // they are shared through a DecodeN they may appear
2230 // to have a single use so force sharing here.
2231 set_shared(m->in(AddPNode::Base)->in(1));
2232 }
2233
2234 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2235 #ifdef X86
2236 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2237 mstack.push(m, Visit);
2238 continue;
2239 }
2240 #endif
2241
2242 // Clone addressing expressions as they are "free" in memory access instructions
2243 if (mem_op && i == MemNode::Address && mop == Op_AddP &&
2244 // When there are other uses besides address expressions
2245 // put it on stack and mark as shared.
2246 !is_visited(m)) {
2247 // Some inputs for address expression are not put on stack
2248 // to avoid marking them as shared and forcing them into register
2249 // if they are used only in address expressions.
2250 // But they should be marked as shared if there are other uses
2251 // besides address expressions.
2252
2253 Node *off = m->in(AddPNode::Offset);
2254 if (off->is_Con()) {
2255 address_visited.test_set(m->_idx); // Flag as address_visited
2256 Node *adr = m->in(AddPNode::Address);
2257
2258 // Intel, ARM and friends can handle 2 adds in addressing mode
2259 if( clone_shift_expressions && adr->is_AddP() &&
2260 // AtomicAdd is not an addressing expression.
2261 // Cheap to find it by looking for screwy base.
2262 !adr->in(AddPNode::Base)->is_top() &&
2263 // Are there other uses besides address expressions?
2264 !is_visited(adr) ) {
2265 address_visited.set(adr->_idx); // Flag as address_visited
2266 Node *shift = adr->in(AddPNode::Offset);
2267 if (!clone_shift(shift, this, mstack, address_visited)) {
2268 mstack.push(shift, Pre_Visit);
2269 }
2270 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2271 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2272 } else { // Sparc, Alpha, PPC and friends
2273 mstack.push(adr, Pre_Visit);
2274 }
2275
2276 // Clone X+offset as it also folds into most addressing expressions
2277 mstack.push(off, Visit);
2278 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2279 continue; // for(int i = ...)
2280 } else if (clone_shift_expressions &&
2281 clone_shift(off, this, mstack, address_visited)) {
2282 address_visited.test_set(m->_idx); // Flag as address_visited
2283 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2284 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2285 continue;
2286 } // if( off->is_Con() )
2287 } // if( mem_op &&
2288 mstack.push(m, Pre_Visit);
2289 } // for(int i = ...)
2290 }
2291 else if (nstate == Alt_Post_Visit) {
2292 mstack.pop(); // Remove node from stack
2293 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2294 // shared and all users of the Bool need to move the Cmp in parallel.
2295 // This leaves both the Bool and the If pointing at the Cmp. To
2296 // prevent the Matcher from trying to Match the Cmp along both paths
2297 // BoolNode::match_edge always returns a zero.
2298
2299 // We reorder the Op_If in a pre-order manner, so we can visit without
2300 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2301 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2302 }
2303 else if (nstate == Post_Visit) {
2304 mstack.pop(); // Remove node from stack
2305
2306 // Now hack a few special opcodes
2307 switch( n->Opcode() ) { // Handle some opcodes special
2308 case Op_StorePConditional:
2309 case Op_StoreIConditional:
2310 case Op_StoreLConditional:
2311 case Op_CompareAndExchangeI:
2312 case Op_CompareAndExchangeL:
2313 case Op_CompareAndExchangeP:
2314 case Op_CompareAndExchangeN:
2315 case Op_WeakCompareAndSwapI:
2316 case Op_WeakCompareAndSwapL:
2317 case Op_WeakCompareAndSwapP:
2318 case Op_WeakCompareAndSwapN:
2319 case Op_CompareAndSwapI:
2320 case Op_CompareAndSwapL:
2321 case Op_CompareAndSwapP:
2322 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2323 Node *newval = n->in(MemNode::ValueIn );
2324 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2325 Node *pair = new BinaryNode( oldval, newval );
2326 n->set_req(MemNode::ValueIn,pair);
2327 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2328 break;
2329 }
2330 case Op_CMoveD: // Convert trinary to binary-tree
2331 case Op_CMoveF:
2332 case Op_CMoveI:
2333 case Op_CMoveL:
2334 case Op_CMoveN:
2335 case Op_CMoveP:
2336 case Op_CMoveVD: {
2337 // Restructure into a binary tree for Matching. It's possible that
2338 // we could move this code up next to the graph reshaping for IfNodes
2339 // or vice-versa, but I do not want to debug this for Ladybird.
2340 // 10/2/2000 CNC.
2341 Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
2342 n->set_req(1,pair1);
2343 Node *pair2 = new BinaryNode(n->in(2),n->in(3));
2344 n->set_req(2,pair2);
2345 n->del_req(3);
2346 break;
2347 }
2348 case Op_LoopLimit: {
2349 Node *pair1 = new BinaryNode(n->in(1),n->in(2));
2350 n->set_req(1,pair1);
2351 n->set_req(2,n->in(3));
2352 n->del_req(3);
2353 break;
2354 }
2355 case Op_StrEquals:
2356 case Op_StrIndexOfChar: {
2357 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2358 n->set_req(2,pair1);
2359 n->set_req(3,n->in(4));
2360 n->del_req(4);
2361 break;
2362 }
2363 case Op_StrComp:
2364 case Op_StrIndexOf: {
2365 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2366 n->set_req(2,pair1);
2367 Node *pair2 = new BinaryNode(n->in(4),n->in(5));
2368 n->set_req(3,pair2);
2369 n->del_req(5);
2370 n->del_req(4);
2371 break;
2372 }
2373 case Op_StrCompressedCopy:
2374 case Op_StrInflatedCopy:
2375 case Op_EncodeISOArray: {
2376 // Restructure into a binary tree for Matching.
2377 Node* pair = new BinaryNode(n->in(3), n->in(4));
2378 n->set_req(3, pair);
2379 n->del_req(4);
2380 break;
2381 }
2382 default:
2383 break;
2384 }
2385 }
2386 else {
2387 ShouldNotReachHere();
2388 }
2389 } // end of while (mstack.is_nonempty())
2390 }
2391
2392 #ifdef ASSERT
2393 // machine-independent root to machine-dependent root
2394 void Matcher::dump_old2new_map() {
2395 _old2new_map.dump();
2396 }
2397 #endif
2398
2399 //---------------------------collect_null_checks-------------------------------
2400 // Find null checks in the ideal graph; write a machine-specific node for
2401 // it. Used by later implicit-null-check handling. Actually collects
2402 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2403 // value being tested.
2404 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2405 Node *iff = proj->in(0);
2406 if( iff->Opcode() == Op_If ) {
2407 // During matching If's have Bool & Cmp side-by-side
2408 BoolNode *b = iff->in(1)->as_Bool();
2409 Node *cmp = iff->in(2);
2410 int opc = cmp->Opcode();
2411 if (opc != Op_CmpP && opc != Op_CmpN) return;
2412
2413 const Type* ct = cmp->in(2)->bottom_type();
2414 if (ct == TypePtr::NULL_PTR ||
2415 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2416
2417 bool push_it = false;
2418 if( proj->Opcode() == Op_IfTrue ) {
2419 #ifndef PRODUCT
2420 extern int all_null_checks_found;
2421 all_null_checks_found++;
2422 #endif
2423 if( b->_test._test == BoolTest::ne ) {
2424 push_it = true;
2425 }
2426 } else {
2427 assert( proj->Opcode() == Op_IfFalse, "" );
2428 if( b->_test._test == BoolTest::eq ) {
2429 push_it = true;
2430 }
2431 }
2432 if( push_it ) {
2433 _null_check_tests.push(proj);
2434 Node* val = cmp->in(1);
2435 #ifdef _LP64
2436 if (val->bottom_type()->isa_narrowoop() &&
2437 !Matcher::narrow_oop_use_complex_address()) {
2438 //
2439 // Look for DecodeN node which should be pinned to orig_proj.
2440 // On platforms (Sparc) which can not handle 2 adds
2441 // in addressing mode we have to keep a DecodeN node and
2442 // use it to do implicit NULL check in address.
2443 //
2444 // DecodeN node was pinned to non-null path (orig_proj) during
2445 // CastPP transformation in final_graph_reshaping_impl().
2446 //
2447 uint cnt = orig_proj->outcnt();
2448 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2449 Node* d = orig_proj->raw_out(i);
2450 if (d->is_DecodeN() && d->in(1) == val) {
2451 val = d;
2452 val->set_req(0, NULL); // Unpin now.
2453 // Mark this as special case to distinguish from
2454 // a regular case: CmpP(DecodeN, NULL).
2455 val = (Node*)(((intptr_t)val) | 1);
2456 break;
2457 }
2458 }
2459 }
2460 #endif
2461 _null_check_tests.push(val);
2462 }
2463 }
2464 }
2465 }
2466
2467 //---------------------------validate_null_checks------------------------------
2468 // Its possible that the value being NULL checked is not the root of a match
2469 // tree. If so, I cannot use the value in an implicit null check.
2470 void Matcher::validate_null_checks( ) {
2471 uint cnt = _null_check_tests.size();
2472 for( uint i=0; i < cnt; i+=2 ) {
2473 Node *test = _null_check_tests[i];
2474 Node *val = _null_check_tests[i+1];
2475 bool is_decoden = ((intptr_t)val) & 1;
2476 val = (Node*)(((intptr_t)val) & ~1);
2477 if (has_new_node(val)) {
2478 Node* new_val = new_node(val);
2479 if (is_decoden) {
2480 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2481 // Note: new_val may have a control edge if
2482 // the original ideal node DecodeN was matched before
2483 // it was unpinned in Matcher::collect_null_checks().
2484 // Unpin the mach node and mark it.
2485 new_val->set_req(0, NULL);
2486 new_val = (Node*)(((intptr_t)new_val) | 1);
2487 }
2488 // Is a match-tree root, so replace with the matched value
2489 _null_check_tests.map(i+1, new_val);
2490 } else {
2491 // Yank from candidate list
2492 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2493 _null_check_tests.map(i,_null_check_tests[--cnt]);
2494 _null_check_tests.pop();
2495 _null_check_tests.pop();
2496 i-=2;
2497 }
2498 }
2499 }
2500
2501 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2502 // atomic instruction acting as a store_load barrier without any
2503 // intervening volatile load, and thus we don't need a barrier here.
2504 // We retain the Node to act as a compiler ordering barrier.
2505 bool Matcher::post_store_load_barrier(const Node* vmb) {
2506 Compile* C = Compile::current();
2507 assert(vmb->is_MemBar(), "");
2508 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2509 const MemBarNode* membar = vmb->as_MemBar();
2510
2511 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2512 Node* ctrl = NULL;
2513 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2514 Node* p = membar->fast_out(i);
2515 assert(p->is_Proj(), "only projections here");
2516 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2517 !C->node_arena()->contains(p)) { // Unmatched old-space only
2518 ctrl = p;
2519 break;
2520 }
2521 }
2522 assert((ctrl != NULL), "missing control projection");
2523
2524 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2525 Node *x = ctrl->fast_out(j);
2526 int xop = x->Opcode();
2527
2528 // We don't need current barrier if we see another or a lock
2529 // before seeing volatile load.
2530 //
2531 // Op_Fastunlock previously appeared in the Op_* list below.
2532 // With the advent of 1-0 lock operations we're no longer guaranteed
2533 // that a monitor exit operation contains a serializing instruction.
2534
2535 if (xop == Op_MemBarVolatile ||
2536 xop == Op_CompareAndExchangeI ||
2537 xop == Op_CompareAndExchangeL ||
2538 xop == Op_CompareAndExchangeP ||
2539 xop == Op_CompareAndExchangeN ||
2540 xop == Op_WeakCompareAndSwapL ||
2541 xop == Op_WeakCompareAndSwapP ||
2542 xop == Op_WeakCompareAndSwapN ||
2543 xop == Op_WeakCompareAndSwapI ||
2544 xop == Op_CompareAndSwapL ||
2545 xop == Op_CompareAndSwapP ||
2546 xop == Op_CompareAndSwapN ||
2547 xop == Op_CompareAndSwapI) {
2548 return true;
2549 }
2550
2551 // Op_FastLock previously appeared in the Op_* list above.
2552 // With biased locking we're no longer guaranteed that a monitor
2553 // enter operation contains a serializing instruction.
2554 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2555 return true;
2556 }
2557
2558 if (x->is_MemBar()) {
2559 // We must retain this membar if there is an upcoming volatile
2560 // load, which will be followed by acquire membar.
2561 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2562 return false;
2563 } else {
2564 // For other kinds of barriers, check by pretending we
2565 // are them, and seeing if we can be removed.
2566 return post_store_load_barrier(x->as_MemBar());
2567 }
2568 }
2569
2570 // probably not necessary to check for these
2571 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2572 return false;
2573 }
2574 }
2575 return false;
2576 }
2577
2578 // Check whether node n is a branch to an uncommon trap that we could
2579 // optimize as test with very high branch costs in case of going to
2580 // the uncommon trap. The code must be able to be recompiled to use
2581 // a cheaper test.
2582 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2583 // Don't do it for natives, adapters, or runtime stubs
2584 Compile *C = Compile::current();
2585 if (!C->is_method_compilation()) return false;
2586
2587 assert(n->is_If(), "You should only call this on if nodes.");
2588 IfNode *ifn = n->as_If();
2589
2590 Node *ifFalse = NULL;
2591 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2592 if (ifn->fast_out(i)->is_IfFalse()) {
2593 ifFalse = ifn->fast_out(i);
2594 break;
2595 }
2596 }
2597 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2598
2599 Node *reg = ifFalse;
2600 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
2601 // Alternatively use visited set? Seems too expensive.
2602 while (reg != NULL && cnt > 0) {
2603 CallNode *call = NULL;
2604 RegionNode *nxt_reg = NULL;
2605 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2606 Node *o = reg->fast_out(i);
2607 if (o->is_Call()) {
2608 call = o->as_Call();
2609 }
2610 if (o->is_Region()) {
2611 nxt_reg = o->as_Region();
2612 }
2613 }
2614
2615 if (call &&
2616 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2617 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2618 if (trtype->isa_int() && trtype->is_int()->is_con()) {
2619 jint tr_con = trtype->is_int()->get_con();
2620 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2621 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2622 assert((int)reason < (int)BitsPerInt, "recode bit map");
2623
2624 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2625 && action != Deoptimization::Action_none) {
2626 // This uncommon trap is sure to recompile, eventually.
2627 // When that happens, C->too_many_traps will prevent
2628 // this transformation from happening again.
2629 return true;
2630 }
2631 }
2632 }
2633
2634 reg = nxt_reg;
2635 cnt--;
2636 }
2637
2638 return false;
2639 }
2640
2641 //=============================================================================
2642 //---------------------------State---------------------------------------------
2643 State::State(void) {
2644 #ifdef ASSERT
2645 _id = 0;
2646 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2647 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2648 //memset(_cost, -1, sizeof(_cost));
2649 //memset(_rule, -1, sizeof(_rule));
2650 #endif
2651 memset(_valid, 0, sizeof(_valid));
2652 }
2653
2654 #ifdef ASSERT
2655 State::~State() {
2656 _id = 99;
2657 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2658 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2659 memset(_cost, -3, sizeof(_cost));
2660 memset(_rule, -3, sizeof(_rule));
2661 }
2662 #endif
2663
2664 #ifndef PRODUCT
2665 //---------------------------dump----------------------------------------------
2666 void State::dump() {
2667 tty->print("\n");
2668 dump(0);
2669 }
2670
2671 void State::dump(int depth) {
2672 for( int j = 0; j < depth; j++ )
2673 tty->print(" ");
2674 tty->print("--N: ");
2675 _leaf->dump();
2676 uint i;
2677 for( i = 0; i < _LAST_MACH_OPER; i++ )
2678 // Check for valid entry
2679 if( valid(i) ) {
2680 for( int j = 0; j < depth; j++ )
2681 tty->print(" ");
2682 assert(_cost[i] != max_juint, "cost must be a valid value");
2683 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2684 tty->print_cr("%s %d %s",
2685 ruleName[i], _cost[i], ruleName[_rule[i]] );
2686 }
2687 tty->cr();
2688
2689 for( i=0; i<2; i++ )
2690 if( _kids[i] )
2691 _kids[i]->dump(depth+1);
2692 }
2693 #endif