1 /*
   2  * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "libadt/vectset.hpp"
  27 #include "memory/allocation.inline.hpp"
  28 #include "opto/addnode.hpp"
  29 #include "opto/c2compiler.hpp"
  30 #include "opto/callnode.hpp"
  31 #include "opto/cfgnode.hpp"
  32 #include "opto/chaitin.hpp"
  33 #include "opto/loopnode.hpp"
  34 #include "opto/machnode.hpp"
  35 
  36 //------------------------------Split--------------------------------------
  37 // Walk the graph in RPO and for each lrg which spills, propagate reaching
  38 // definitions.  During propagation, split the live range around regions of
  39 // High Register Pressure (HRP).  If a Def is in a region of Low Register
  40 // Pressure (LRP), it will not get spilled until we encounter a region of
  41 // HRP between it and one of its uses.  We will spill at the transition
  42 // point between LRP and HRP.  Uses in the HRP region will use the spilled
  43 // Def.  The first Use outside the HRP region will generate a SpillCopy to
  44 // hoist the live range back up into a register, and all subsequent uses
  45 // will use that new Def until another HRP region is encountered.  Defs in
  46 // HRP regions will get trailing SpillCopies to push the LRG down into the
  47 // stack immediately.
  48 //
  49 // As a side effect, unlink from (hence make dead) coalesced copies.
  50 //
  51 
  52 static const char out_of_nodes[] = "out of nodes during split";
  53 
  54 //------------------------------get_spillcopy_wide-----------------------------
  55 // Get a SpillCopy node with wide-enough masks.  Use the 'wide-mask', the
  56 // wide ideal-register spill-mask if possible.  If the 'wide-mask' does
  57 // not cover the input (or output), use the input (or output) mask instead.
  58 Node *PhaseChaitin::get_spillcopy_wide(MachSpillCopyNode::SpillType spill_type, Node *def, Node *use, uint uidx) {
  59   // If ideal reg doesn't exist we've got a bad schedule happening
  60   // that is forcing us to spill something that isn't spillable.
  61   // Bail rather than abort
  62   int ireg = def->ideal_reg();
  63   if (ireg == 0 || ireg == Op_RegFlags) {
  64     assert(false, "attempted to spill a non-spillable item: %d: %s <- %d: %s, ireg = %d, spill_type: %s",
  65            def->_idx, def->Name(), use->_idx, use->Name(), ireg,
  66            MachSpillCopyNode::spill_type(spill_type));
  67     C->record_method_not_compilable("attempted to spill a non-spillable item");
  68     return NULL;
  69   }
  70   if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
  71     return NULL;
  72   }
  73   const RegMask *i_mask = &def->out_RegMask();
  74   const RegMask *w_mask = C->matcher()->idealreg2spillmask[ireg];
  75   const RegMask *o_mask = use ? &use->in_RegMask(uidx) : w_mask;
  76   const RegMask *w_i_mask = w_mask->overlap( *i_mask ) ? w_mask : i_mask;
  77   const RegMask *w_o_mask;
  78 
  79   int num_regs = RegMask::num_registers(ireg);
  80   bool is_vect = RegMask::is_vector(ireg);
  81   if( w_mask->overlap( *o_mask ) && // Overlap AND
  82       ((num_regs == 1) // Single use or aligned
  83         ||  is_vect    // or vector
  84         || !is_vect && o_mask->is_aligned_pairs()) ) {
  85     assert(!is_vect || o_mask->is_aligned_sets(num_regs), "vectors are aligned");
  86     // Don't come here for mis-aligned doubles
  87     w_o_mask = w_mask;
  88   } else {                      // wide ideal mask does not overlap with o_mask
  89     // Mis-aligned doubles come here and XMM->FPR moves on x86.
  90     w_o_mask = o_mask;          // Must target desired registers
  91     // Does the ideal-reg-mask overlap with o_mask?  I.e., can I use
  92     // a reg-reg move or do I need a trip across register classes
  93     // (and thus through memory)?
  94     if( !C->matcher()->idealreg2regmask[ireg]->overlap( *o_mask) && o_mask->is_UP() )
  95       // Here we assume a trip through memory is required.
  96       w_i_mask = &C->FIRST_STACK_mask();
  97   }
  98   return new MachSpillCopyNode(spill_type, def, *w_i_mask, *w_o_mask );
  99 }
 100 
 101 //------------------------------insert_proj------------------------------------
 102 // Insert the spill at chosen location.  Skip over any intervening Proj's or
 103 // Phis.  Skip over a CatchNode and projs, inserting in the fall-through block
 104 // instead.  Update high-pressure indices.  Create a new live range.
 105 void PhaseChaitin::insert_proj( Block *b, uint i, Node *spill, uint maxlrg ) {
 106   // Skip intervening ProjNodes.  Do not insert between a ProjNode and
 107   // its definer.
 108   while( i < b->number_of_nodes() &&
 109          (b->get_node(i)->is_Proj() ||
 110           b->get_node(i)->is_Phi() ) )
 111     i++;
 112 
 113   // Do not insert between a call and his Catch
 114   if( b->get_node(i)->is_Catch() ) {
 115     // Put the instruction at the top of the fall-thru block.
 116     // Find the fall-thru projection
 117     while( 1 ) {
 118       const CatchProjNode *cp = b->get_node(++i)->as_CatchProj();
 119       if( cp->_con == CatchProjNode::fall_through_index )
 120         break;
 121     }
 122     int sidx = i - b->end_idx()-1;
 123     b = b->_succs[sidx];        // Switch to successor block
 124     i = 1;                      // Right at start of block
 125   }
 126 
 127   b->insert_node(spill, i);    // Insert node in block
 128   _cfg.map_node_to_block(spill,  b); // Update node->block mapping to reflect
 129   // Adjust the point where we go hi-pressure
 130   if( i <= b->_ihrp_index ) b->_ihrp_index++;
 131   if( i <= b->_fhrp_index ) b->_fhrp_index++;
 132 
 133   // Assign a new Live Range Number to the SpillCopy and grow
 134   // the node->live range mapping.
 135   new_lrg(spill,maxlrg);
 136 }
 137 
 138 //------------------------------split_DEF--------------------------------------
 139 // There are four categories of Split; UP/DOWN x DEF/USE
 140 // Only three of these really occur as DOWN/USE will always color
 141 // Any Split with a DEF cannot CISC-Spill now.  Thus we need
 142 // two helper routines, one for Split DEFS (insert after instruction),
 143 // one for Split USES (insert before instruction).  DEF insertion
 144 // happens inside Split, where the Leaveblock array is updated.
 145 uint PhaseChaitin::split_DEF( Node *def, Block *b, int loc, uint maxlrg, Node **Reachblock, Node **debug_defs, GrowableArray<uint> splits, int slidx ) {
 146 #ifdef ASSERT
 147   // Increment the counter for this lrg
 148   splits.at_put(slidx, splits.at(slidx)+1);
 149 #endif
 150   // If we are spilling the memory op for an implicit null check, at the
 151   // null check location (ie - null check is in HRP block) we need to do
 152   // the null-check first, then spill-down in the following block.
 153   // (The implicit_null_check function ensures the use is also dominated
 154   // by the branch-not-taken block.)
 155   Node *be = b->end();
 156   if( be->is_MachNullCheck() && be->in(1) == def && def == b->get_node(loc)) {
 157     // Spill goes in the branch-not-taken block
 158     b = b->_succs[b->get_node(b->end_idx()+1)->Opcode() == Op_IfTrue];
 159     loc = 0;                    // Just past the Region
 160   }
 161   assert( loc >= 0, "must insert past block head" );
 162 
 163   // Get a def-side SpillCopy
 164   Node *spill = get_spillcopy_wide(MachSpillCopyNode::Definition, def, NULL, 0);
 165   // Did we fail to split?, then bail
 166   if (!spill) {
 167     return 0;
 168   }
 169 
 170   // Insert the spill at chosen location
 171   insert_proj( b, loc+1, spill, maxlrg++);
 172 
 173   // Insert new node into Reaches array
 174   Reachblock[slidx] = spill;
 175   // Update debug list of reaching down definitions by adding this one
 176   debug_defs[slidx] = spill;
 177 
 178   // return updated count of live ranges
 179   return maxlrg;
 180 }
 181 
 182 //------------------------------split_USE--------------------------------------
 183 // Splits at uses can involve redeffing the LRG, so no CISC Spilling there.
 184 // Debug uses want to know if def is already stack enabled.
 185 uint PhaseChaitin::split_USE(MachSpillCopyNode::SpillType spill_type, Node *def, Block *b, Node *use, uint useidx, uint maxlrg, bool def_down, bool cisc_sp, GrowableArray<uint> splits, int slidx ) {
 186 #ifdef ASSERT
 187   // Increment the counter for this lrg
 188   splits.at_put(slidx, splits.at(slidx)+1);
 189 #endif
 190 
 191   // Some setup stuff for handling debug node uses
 192   JVMState* jvms = use->jvms();
 193   uint debug_start = jvms ? jvms->debug_start() : 999999;
 194   uint debug_end   = jvms ? jvms->debug_end()   : 999999;
 195 
 196   //-------------------------------------------
 197   // Check for use of debug info
 198   if (useidx >= debug_start && useidx < debug_end) {
 199     // Actually it's perfectly legal for constant debug info to appear
 200     // just unlikely.  In this case the optimizer left a ConI of a 4
 201     // as both inputs to a Phi with only a debug use.  It's a single-def
 202     // live range of a rematerializable value.  The live range spills,
 203     // rematerializes and now the ConI directly feeds into the debug info.
 204     // assert(!def->is_Con(), "constant debug info already constructed directly");
 205 
 206     // Special split handling for Debug Info
 207     // If DEF is DOWN, just hook the edge and return
 208     // If DEF is UP, Split it DOWN for this USE.
 209     if( def->is_Mach() ) {
 210       if( def_down ) {
 211         // DEF is DOWN, so connect USE directly to the DEF
 212         use->set_req(useidx, def);
 213       } else {
 214         // Block and index where the use occurs.
 215         Block *b = _cfg.get_block_for_node(use);
 216         // Put the clone just prior to use
 217         int bindex = b->find_node(use);
 218         // DEF is UP, so must copy it DOWN and hook in USE
 219         // Insert SpillCopy before the USE, which uses DEF as its input,
 220         // and defs a new live range, which is used by this node.
 221         Node *spill = get_spillcopy_wide(spill_type, def,use,useidx);
 222         // did we fail to split?
 223         if (!spill) {
 224           // Bail
 225           return 0;
 226         }
 227         // insert into basic block
 228         insert_proj( b, bindex, spill, maxlrg++ );
 229         // Use the new split
 230         use->set_req(useidx,spill);
 231       }
 232       // No further split handling needed for this use
 233       return maxlrg;
 234     }  // End special splitting for debug info live range
 235   }  // If debug info
 236 
 237   // CISC-SPILLING
 238   // Finally, check to see if USE is CISC-Spillable, and if so,
 239   // gather_lrg_masks will add the flags bit to its mask, and
 240   // no use side copy is needed.  This frees up the live range
 241   // register choices without causing copy coalescing, etc.
 242   if( UseCISCSpill && cisc_sp ) {
 243     int inp = use->cisc_operand();
 244     if( inp != AdlcVMDeps::Not_cisc_spillable )
 245       // Convert operand number to edge index number
 246       inp = use->as_Mach()->operand_index(inp);
 247     if( inp == (int)useidx ) {
 248       use->set_req(useidx, def);
 249 #ifndef PRODUCT
 250       if( TraceCISCSpill ) {
 251         tty->print("  set_split: ");
 252         use->dump();
 253       }
 254 #endif
 255       return maxlrg;
 256     }
 257   }
 258 
 259   //-------------------------------------------
 260   // Insert a Copy before the use
 261 
 262   // Block and index where the use occurs.
 263   int bindex;
 264   // Phi input spill-copys belong at the end of the prior block
 265   if( use->is_Phi() ) {
 266     b = _cfg.get_block_for_node(b->pred(useidx));
 267     bindex = b->end_idx();
 268   } else {
 269     // Put the clone just prior to use
 270     bindex = b->find_node(use);
 271   }
 272 
 273   Node *spill = get_spillcopy_wide(spill_type, def, use, useidx );
 274   if( !spill ) return 0;        // Bailed out
 275   // Insert SpillCopy before the USE, which uses the reaching DEF as
 276   // its input, and defs a new live range, which is used by this node.
 277   insert_proj( b, bindex, spill, maxlrg++ );
 278   // Use the spill/clone
 279   use->set_req(useidx,spill);
 280 
 281   // return updated live range count
 282   return maxlrg;
 283 }
 284 
 285 //------------------------------clone_node----------------------------
 286 // Clone node with anti dependence check.
 287 Node* clone_node(Node* def, Block *b, Compile* C) {
 288   if (def->needs_anti_dependence_check()) {
 289 #ifdef ASSERT
 290     if (Verbose) {
 291       tty->print_cr("RA attempts to clone node with anti_dependence:");
 292       def->dump(-1); tty->cr();
 293       tty->print_cr("into block:");
 294       b->dump();
 295     }
 296 #endif
 297     if (C->subsume_loads() == true && !C->failing()) {
 298       // Retry with subsume_loads == false
 299       // If this is the first failure, the sentinel string will "stick"
 300       // to the Compile object, and the C2Compiler will see it and retry.
 301       C->record_failure(C2Compiler::retry_no_subsuming_loads());
 302     } else {
 303       // Bailout without retry
 304       C->record_method_not_compilable("RA Split failed: attempt to clone node with anti_dependence");
 305     }
 306     return 0;
 307   }
 308   return def->clone();
 309 }
 310 
 311 //------------------------------split_Rematerialize----------------------------
 312 // Clone a local copy of the def.
 313 Node *PhaseChaitin::split_Rematerialize(Node *def, Block *b, uint insidx, uint &maxlrg,
 314                                         GrowableArray<uint> splits, int slidx, uint *lrg2reach,
 315                                         Node **Reachblock, bool walkThru) {
 316   // The input live ranges will be stretched to the site of the new
 317   // instruction.  They might be stretched past a def and will thus
 318   // have the old and new values of the same live range alive at the
 319   // same time - a definite no-no.  Split out private copies of
 320   // the inputs.
 321   if (def->req() > 1) {
 322     for (uint i = 1; i < def->req(); i++) {
 323       Node *in = def->in(i);
 324       uint lidx = _lrg_map.live_range_id(in);
 325       // We do not need this for live ranges that are only defined once.
 326       // However, this is not true for spill copies that are added in this
 327       // Split() pass, since they might get coalesced later on in this pass.
 328       if (lidx < _lrg_map.max_lrg_id() && lrgs(lidx).is_singledef()) {
 329         continue;
 330       }
 331 
 332       Block *b_def = _cfg.get_block_for_node(def);
 333       int idx_def = b_def->find_node(def);
 334       // Cannot spill Op_RegFlags.
 335       Node *in_spill;
 336       if (in->ideal_reg() != Op_RegFlags) {
 337         in_spill = get_spillcopy_wide(MachSpillCopyNode::InputToRematerialization, in, def, i);
 338         if (!in_spill) { return 0; } // Bailed out
 339         insert_proj(b_def, idx_def, in_spill, maxlrg++);
 340         if (b_def == b) {
 341           insidx++;
 342         }
 343         def->set_req(i, in_spill);
 344       } else {
 345         // The 'in' defines a flag register. Flag registers can not be spilled.
 346         // Register allocation handles live ranges with flag registers
 347         // by rematerializing the def (in this case 'in'). Thus, this is not
 348         // critical if the input can be rematerialized, too.
 349         if (!in->rematerialize()) {
 350           assert(false, "Can not rematerialize %d: %s. Prolongs RegFlags live"
 351                  " range and defining node %d: %s may not be rematerialized.",
 352                  def->_idx, def->Name(), in->_idx, in->Name());
 353           C->record_method_not_compilable("attempted to spill a non-spillable item with RegFlags input");
 354           return 0; // Bailed out
 355         }
 356       }
 357     }
 358   }
 359 
 360   Node *spill = clone_node(def, b, C);
 361   if (spill == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
 362     // Check when generating nodes
 363     return 0;
 364   }
 365 
 366   // See if any inputs are currently being spilled, and take the
 367   // latest copy of spilled inputs.
 368   if( spill->req() > 1 ) {
 369     for( uint i = 1; i < spill->req(); i++ ) {
 370       Node *in = spill->in(i);
 371       uint lidx = _lrg_map.find_id(in);
 372 
 373       // Walk backwards thru spill copy node intermediates
 374       if (walkThru) {
 375         while (in->is_SpillCopy() && lidx >= _lrg_map.max_lrg_id()) {
 376           in = in->in(1);
 377           lidx = _lrg_map.find_id(in);
 378         }
 379 
 380         if (lidx < _lrg_map.max_lrg_id() && lrgs(lidx).is_multidef()) {
 381           // walkThru found a multidef LRG, which is unsafe to use, so
 382           // just keep the original def used in the clone.
 383           in = spill->in(i);
 384           lidx = _lrg_map.find_id(in);
 385         }
 386       }
 387 
 388       if (lidx < _lrg_map.max_lrg_id() && lrgs(lidx).reg() >= LRG::SPILL_REG) {
 389         Node *rdef = Reachblock[lrg2reach[lidx]];
 390         if (rdef) {
 391           spill->set_req(i, rdef);
 392         }
 393       }
 394     }
 395   }
 396 
 397 
 398   assert( spill->out_RegMask().is_UP(), "rematerialize to a reg" );
 399   // Rematerialized op is def->spilled+1
 400   set_was_spilled(spill);
 401   if( _spilled_once.test(def->_idx) )
 402     set_was_spilled(spill);
 403 
 404   insert_proj( b, insidx, spill, maxlrg++ );
 405 #ifdef ASSERT
 406   // Increment the counter for this lrg
 407   splits.at_put(slidx, splits.at(slidx)+1);
 408 #endif
 409   // See if the cloned def kills any flags, and copy those kills as well
 410   uint i = insidx+1;
 411   int found_projs = clone_projs( b, i, def, spill, maxlrg);
 412   if (found_projs > 0) {
 413     // Adjust the point where we go hi-pressure
 414     if (i <= b->_ihrp_index) {
 415       b->_ihrp_index += found_projs;
 416     }
 417     if (i <= b->_fhrp_index) {
 418       b->_fhrp_index += found_projs;
 419     }
 420   }
 421 
 422   return spill;
 423 }
 424 
 425 //------------------------------is_high_pressure-------------------------------
 426 // Function to compute whether or not this live range is "high pressure"
 427 // in this block - whether it spills eagerly or not.
 428 bool PhaseChaitin::is_high_pressure( Block *b, LRG *lrg, uint insidx ) {
 429   if( lrg->_was_spilled1 ) return true;
 430   // Forced spilling due to conflict?  Then split only at binding uses
 431   // or defs, not for supposed capacity problems.
 432   // CNC - Turned off 7/8/99, causes too much spilling
 433   // if( lrg->_is_bound ) return false;
 434 
 435   // Use float pressure numbers for vectors.
 436   bool is_float_or_vector = lrg->_is_float || lrg->_is_vector;
 437   // Not yet reached the high-pressure cutoff point, so low pressure
 438   uint hrp_idx = is_float_or_vector ? b->_fhrp_index : b->_ihrp_index;
 439   if( insidx < hrp_idx ) return false;
 440   // Register pressure for the block as a whole depends on reg class
 441   int block_pres = is_float_or_vector ? b->_freg_pressure : b->_reg_pressure;
 442   // Bound live ranges will split at the binding points first;
 443   // Intermediate splits should assume the live range's register set
 444   // got "freed up" and that num_regs will become INT_PRESSURE.
 445   int bound_pres = is_float_or_vector ? FLOATPRESSURE : INTPRESSURE;
 446   // Effective register pressure limit.
 447   int lrg_pres = (lrg->get_invalid_mask_size() > lrg->num_regs())
 448     ? (lrg->get_invalid_mask_size() >> (lrg->num_regs()-1)) : bound_pres;
 449   // High pressure if block pressure requires more register freedom
 450   // than live range has.
 451   return block_pres >= lrg_pres;
 452 }
 453 
 454 
 455 //------------------------------prompt_use---------------------------------
 456 // True if lidx is used before any real register is def'd in the block
 457 bool PhaseChaitin::prompt_use( Block *b, uint lidx ) {
 458   if (lrgs(lidx)._was_spilled2) {
 459     return false;
 460   }
 461 
 462   // Scan block for 1st use.
 463   for( uint i = 1; i <= b->end_idx(); i++ ) {
 464     Node *n = b->get_node(i);
 465     // Ignore PHI use, these can be up or down
 466     if (n->is_Phi()) {
 467       continue;
 468     }
 469     for (uint j = 1; j < n->req(); j++) {
 470       if (_lrg_map.find_id(n->in(j)) == lidx) {
 471         return true;          // Found 1st use!
 472       }
 473     }
 474     if (n->out_RegMask().is_NotEmpty()) {
 475       return false;
 476     }
 477   }
 478   return false;
 479 }
 480 
 481 //------------------------------Split--------------------------------------
 482 //----------Split Routine----------
 483 // ***** NEW SPLITTING HEURISTIC *****
 484 // DEFS: If the DEF is in a High Register Pressure(HRP) Block, split there.
 485 //        Else, no split unless there is a HRP block between a DEF and
 486 //        one of its uses, and then split at the HRP block.
 487 //
 488 // USES: If USE is in HRP, split at use to leave main LRG on stack.
 489 //       Else, hoist LRG back up to register only (ie - split is also DEF)
 490 // We will compute a new maxlrg as we go
 491 uint PhaseChaitin::Split(uint maxlrg, ResourceArea* split_arena) {
 492   Compile::TracePhase tp("regAllocSplit", &timers[_t_regAllocSplit]);
 493 
 494   // Free thread local resources used by this method on exit.
 495   ResourceMark rm(split_arena);
 496 
 497   uint                 bidx, pidx, slidx, insidx, inpidx, twoidx;
 498   uint                 non_phi = 1, spill_cnt = 0;
 499   Node                *n1, *n2, *n3;
 500   Node_List           *defs,*phis;
 501   bool                *UPblock;
 502   bool                 u1, u2, u3;
 503   Block               *b, *pred;
 504   PhiNode             *phi;
 505   GrowableArray<uint>  lidxs(split_arena, maxlrg, 0, 0);
 506 
 507   // Array of counters to count splits per live range
 508   GrowableArray<uint>  splits(split_arena, maxlrg, 0, 0);
 509 
 510 #define NEW_SPLIT_ARRAY(type, size)\
 511   (type*) split_arena->allocate_bytes((size) * sizeof(type))
 512 
 513   //----------Setup Code----------
 514   // Create a convenient mapping from lrg numbers to reaches/leaves indices
 515   uint *lrg2reach = NEW_SPLIT_ARRAY(uint, maxlrg);
 516   // Keep track of DEFS & Phis for later passes
 517   defs = new Node_List();
 518   phis = new Node_List();
 519   // Gather info on which LRG's are spilling, and build maps
 520   for (bidx = 1; bidx < maxlrg; bidx++) {
 521     if (lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG) {
 522       assert(!lrgs(bidx).mask().is_AllStack(),"AllStack should color");
 523       lrg2reach[bidx] = spill_cnt;
 524       spill_cnt++;
 525       lidxs.append(bidx);
 526 #ifdef ASSERT
 527       // Initialize the split counts to zero
 528       splits.append(0);
 529 #endif
 530       if (PrintOpto && WizardMode && lrgs(bidx)._was_spilled1) {
 531         tty->print_cr("Warning, 2nd spill of L%d",bidx);
 532       }
 533     }
 534   }
 535 
 536   // Create side arrays for propagating reaching defs info.
 537   // Each block needs a node pointer for each spilling live range for the
 538   // Def which is live into the block.  Phi nodes handle multiple input
 539   // Defs by querying the output of their predecessor blocks and resolving
 540   // them to a single Def at the phi.  The pointer is updated for each
 541   // Def in the block, and then becomes the output for the block when
 542   // processing of the block is complete.  We also need to track whether
 543   // a Def is UP or DOWN.  UP means that it should get a register (ie -
 544   // it is always in LRP regions), and DOWN means that it is probably
 545   // on the stack (ie - it crosses HRP regions).
 546   Node ***Reaches     = NEW_SPLIT_ARRAY( Node**, _cfg.number_of_blocks() + 1);
 547   bool  **UP          = NEW_SPLIT_ARRAY( bool*, _cfg.number_of_blocks() + 1);
 548   Node  **debug_defs  = NEW_SPLIT_ARRAY( Node*, spill_cnt );
 549   VectorSet **UP_entry= NEW_SPLIT_ARRAY( VectorSet*, spill_cnt );
 550 
 551   // Initialize Reaches & UP
 552   for (bidx = 0; bidx < _cfg.number_of_blocks() + 1; bidx++) {
 553     Reaches[bidx]     = NEW_SPLIT_ARRAY( Node*, spill_cnt );
 554     UP[bidx]          = NEW_SPLIT_ARRAY( bool, spill_cnt );
 555     Node **Reachblock = Reaches[bidx];
 556     bool *UPblock     = UP[bidx];
 557     for( slidx = 0; slidx < spill_cnt; slidx++ ) {
 558       UPblock[slidx] = true;     // Assume they start in registers
 559       Reachblock[slidx] = NULL;  // Assume that no def is present
 560     }
 561   }
 562 
 563 #undef NEW_SPLIT_ARRAY
 564 
 565   // Initialize to array of empty vectorsets
 566   for( slidx = 0; slidx < spill_cnt; slidx++ )
 567     UP_entry[slidx] = new VectorSet(split_arena);
 568 
 569   //----------PASS 1----------
 570   //----------Propagation & Node Insertion Code----------
 571   // Walk the Blocks in RPO for DEF & USE info
 572   for( bidx = 0; bidx < _cfg.number_of_blocks(); bidx++ ) {
 573 
 574     if (C->check_node_count(spill_cnt, out_of_nodes)) {
 575       return 0;
 576     }
 577 
 578     b  = _cfg.get_block(bidx);
 579     // Reaches & UP arrays for this block
 580     Node** Reachblock = Reaches[b->_pre_order];
 581     UPblock    = UP[b->_pre_order];
 582     // Reset counter of start of non-Phi nodes in block
 583     non_phi = 1;
 584     //----------Block Entry Handling----------
 585     // Check for need to insert a new phi
 586     // Cycle through this block's predecessors, collecting Reaches
 587     // info for each spilled LRG.  If they are identical, no phi is
 588     // needed.  If they differ, check for a phi, and insert if missing,
 589     // or update edges if present.  Set current block's Reaches set to
 590     // be either the phi's or the reaching def, as appropriate.
 591     // If no Phi is needed, check if the LRG needs to spill on entry
 592     // to the block due to HRP.
 593     for( slidx = 0; slidx < spill_cnt; slidx++ ) {
 594       // Grab the live range number
 595       uint lidx = lidxs.at(slidx);
 596       // Do not bother splitting or putting in Phis for single-def
 597       // rematerialized live ranges.  This happens alot to constants
 598       // with long live ranges.
 599       if( lrgs(lidx).is_singledef() &&
 600           lrgs(lidx)._def->rematerialize() ) {
 601         // reset the Reaches & UP entries
 602         Reachblock[slidx] = lrgs(lidx)._def;
 603         UPblock[slidx] = true;
 604         // Record following instruction in case 'n' rematerializes and
 605         // kills flags
 606         Block *pred1 = _cfg.get_block_for_node(b->pred(1));
 607         continue;
 608       }
 609 
 610       // Initialize needs_phi and needs_split
 611       bool needs_phi = false;
 612       bool needs_split = false;
 613       bool has_phi = false;
 614       // Walk the predecessor blocks to check inputs for that live range
 615       // Grab predecessor block header
 616       n1 = b->pred(1);
 617       // Grab the appropriate reaching def info for inpidx
 618       pred = _cfg.get_block_for_node(n1);
 619       pidx = pred->_pre_order;
 620       Node **Ltmp = Reaches[pidx];
 621       bool  *Utmp = UP[pidx];
 622       n1 = Ltmp[slidx];
 623       u1 = Utmp[slidx];
 624       // Initialize node for saving type info
 625       n3 = n1;
 626       u3 = u1;
 627 
 628       // Compare inputs to see if a Phi is needed
 629       for( inpidx = 2; inpidx < b->num_preds(); inpidx++ ) {
 630         // Grab predecessor block headers
 631         n2 = b->pred(inpidx);
 632         // Grab the appropriate reaching def info for inpidx
 633         pred = _cfg.get_block_for_node(n2);
 634         pidx = pred->_pre_order;
 635         Ltmp = Reaches[pidx];
 636         Utmp = UP[pidx];
 637         n2 = Ltmp[slidx];
 638         u2 = Utmp[slidx];
 639         // For each LRG, decide if a phi is necessary
 640         if( n1 != n2 ) {
 641           needs_phi = true;
 642         }
 643         // See if the phi has mismatched inputs, UP vs. DOWN
 644         if( n1 && n2 && (u1 != u2) ) {
 645           needs_split = true;
 646         }
 647         // Move n2/u2 to n1/u1 for next iteration
 648         n1 = n2;
 649         u1 = u2;
 650         // Preserve a non-NULL predecessor for later type referencing
 651         if( (n3 == NULL) && (n2 != NULL) ){
 652           n3 = n2;
 653           u3 = u2;
 654         }
 655       }  // End for all potential Phi inputs
 656 
 657       // check block for appropriate phinode & update edges
 658       for( insidx = 1; insidx <= b->end_idx(); insidx++ ) {
 659         n1 = b->get_node(insidx);
 660         // bail if this is not a phi
 661         phi = n1->is_Phi() ? n1->as_Phi() : NULL;
 662         if( phi == NULL ) {
 663           // Keep track of index of first non-PhiNode instruction in block
 664           non_phi = insidx;
 665           // break out of the for loop as we have handled all phi nodes
 666           break;
 667         }
 668         // must be looking at a phi
 669         if (_lrg_map.find_id(n1) == lidxs.at(slidx)) {
 670           // found the necessary phi
 671           needs_phi = false;
 672           has_phi = true;
 673           // initialize the Reaches entry for this LRG
 674           Reachblock[slidx] = phi;
 675           break;
 676         }  // end if found correct phi
 677       }  // end for all phi's
 678 
 679       // If a phi is needed or exist, check for it
 680       if( needs_phi || has_phi ) {
 681         // add new phinode if one not already found
 682         if( needs_phi ) {
 683           // create a new phi node and insert it into the block
 684           // type is taken from left over pointer to a predecessor
 685           assert(n3,"No non-NULL reaching DEF for a Phi");
 686           phi = new PhiNode(b->head(), n3->bottom_type());
 687           // initialize the Reaches entry for this LRG
 688           Reachblock[slidx] = phi;
 689 
 690           // add node to block & node_to_block mapping
 691           insert_proj(b, insidx++, phi, maxlrg++);
 692           non_phi++;
 693           // Reset new phi's mapping to be the spilling live range
 694           _lrg_map.map(phi->_idx, lidx);
 695           assert(_lrg_map.find_id(phi) == lidx, "Bad update on Union-Find mapping");
 696         }  // end if not found correct phi
 697         // Here you have either found or created the Phi, so record it
 698         assert(phi != NULL,"Must have a Phi Node here");
 699         phis->push(phi);
 700         // PhiNodes should either force the LRG UP or DOWN depending
 701         // on its inputs and the register pressure in the Phi's block.
 702         UPblock[slidx] = true;  // Assume new DEF is UP
 703         // If entering a high-pressure area with no immediate use,
 704         // assume Phi is DOWN
 705         if( is_high_pressure( b, &lrgs(lidx), b->end_idx()) && !prompt_use(b,lidx) )
 706           UPblock[slidx] = false;
 707         // If we are not split up/down and all inputs are down, then we
 708         // are down
 709         if( !needs_split && !u3 )
 710           UPblock[slidx] = false;
 711       }  // end if phi is needed
 712 
 713       // Do not need a phi, so grab the reaching DEF
 714       else {
 715         // Grab predecessor block header
 716         n1 = b->pred(1);
 717         // Grab the appropriate reaching def info for k
 718         pred = _cfg.get_block_for_node(n1);
 719         pidx = pred->_pre_order;
 720         Node **Ltmp = Reaches[pidx];
 721         bool  *Utmp = UP[pidx];
 722         // reset the Reaches & UP entries
 723         Reachblock[slidx] = Ltmp[slidx];
 724         UPblock[slidx] = Utmp[slidx];
 725       }  // end else no Phi is needed
 726     }  // end for all spilling live ranges
 727     // DEBUG
 728 #ifndef PRODUCT
 729     if(trace_spilling()) {
 730       tty->print("/`\nBlock %d: ", b->_pre_order);
 731       tty->print("Reaching Definitions after Phi handling\n");
 732       for( uint x = 0; x < spill_cnt; x++ ) {
 733         tty->print("Spill Idx %d: UP %d: Node\n",x,UPblock[x]);
 734         if( Reachblock[x] )
 735           Reachblock[x]->dump();
 736         else
 737           tty->print("Undefined\n");
 738       }
 739     }
 740 #endif
 741 
 742     //----------Non-Phi Node Splitting----------
 743     // Since phi-nodes have now been handled, the Reachblock array for this
 744     // block is initialized with the correct starting value for the defs which
 745     // reach non-phi instructions in this block.  Thus, process non-phi
 746     // instructions normally, inserting SpillCopy nodes for all spill
 747     // locations.
 748 
 749     // Memoize any DOWN reaching definitions for use as DEBUG info
 750     for( insidx = 0; insidx < spill_cnt; insidx++ ) {
 751       debug_defs[insidx] = (UPblock[insidx]) ? NULL : Reachblock[insidx];
 752       if( UPblock[insidx] )     // Memoize UP decision at block start
 753         UP_entry[insidx]->set( b->_pre_order );
 754     }
 755 
 756     //----------Walk Instructions in the Block and Split----------
 757     // For all non-phi instructions in the block
 758     for( insidx = 1; insidx <= b->end_idx(); insidx++ ) {
 759       Node *n = b->get_node(insidx);
 760       // Find the defining Node's live range index
 761       uint defidx = _lrg_map.find_id(n);
 762       uint cnt = n->req();
 763 
 764       if (n->is_Phi()) {
 765         // Skip phi nodes after removing dead copies.
 766         if (defidx < _lrg_map.max_lrg_id()) {
 767           // Check for useless Phis.  These appear if we spill, then
 768           // coalesce away copies.  Dont touch Phis in spilling live
 769           // ranges; they are busy getting modifed in this pass.
 770           if( lrgs(defidx).reg() < LRG::SPILL_REG ) {
 771             uint i;
 772             Node *u = NULL;
 773             // Look for the Phi merging 2 unique inputs
 774             for( i = 1; i < cnt; i++ ) {
 775               // Ignore repeats and self
 776               if( n->in(i) != u && n->in(i) != n ) {
 777                 // Found a unique input
 778                 if( u != NULL ) // If it's the 2nd, bail out
 779                   break;
 780                 u = n->in(i);   // Else record it
 781               }
 782             }
 783             assert( u, "at least 1 valid input expected" );
 784             if (i >= cnt) {    // Found one unique input
 785               assert(_lrg_map.find_id(n) == _lrg_map.find_id(u), "should be the same lrg");
 786               n->replace_by(u); // Then replace with unique input
 787               n->disconnect_inputs(NULL, C);
 788               b->remove_node(insidx);
 789               insidx--;
 790               b->_ihrp_index--;
 791               b->_fhrp_index--;
 792             }
 793           }
 794         }
 795         continue;
 796       }
 797       assert( insidx > b->_ihrp_index ||
 798               (b->_reg_pressure < (uint)INTPRESSURE) ||
 799               b->_ihrp_index > 4000000 ||
 800               b->_ihrp_index >= b->end_idx() ||
 801               !b->get_node(b->_ihrp_index)->is_Proj(), "" );
 802       assert( insidx > b->_fhrp_index ||
 803               (b->_freg_pressure < (uint)FLOATPRESSURE) ||
 804               b->_fhrp_index > 4000000 ||
 805               b->_fhrp_index >= b->end_idx() ||
 806               !b->get_node(b->_fhrp_index)->is_Proj(), "" );
 807 
 808       // ********** Handle Crossing HRP Boundry **********
 809       if( (insidx == b->_ihrp_index) || (insidx == b->_fhrp_index) ) {
 810         for( slidx = 0; slidx < spill_cnt; slidx++ ) {
 811           // Check for need to split at HRP boundary - split if UP
 812           n1 = Reachblock[slidx];
 813           // bail out if no reaching DEF
 814           if( n1 == NULL ) continue;
 815           // bail out if live range is 'isolated' around inner loop
 816           uint lidx = lidxs.at(slidx);
 817           // If live range is currently UP
 818           if( UPblock[slidx] ) {
 819             // set location to insert spills at
 820             // SPLIT DOWN HERE - NO CISC SPILL
 821             if( is_high_pressure( b, &lrgs(lidx), insidx ) &&
 822                 !n1->rematerialize() ) {
 823               // If there is already a valid stack definition available, use it
 824               if( debug_defs[slidx] != NULL ) {
 825                 Reachblock[slidx] = debug_defs[slidx];
 826               }
 827               else {
 828                 // Insert point is just past last use or def in the block
 829                 int insert_point = insidx-1;
 830                 while( insert_point > 0 ) {
 831                   Node *n = b->get_node(insert_point);
 832                   // Hit top of block?  Quit going backwards
 833                   if (n->is_Phi()) {
 834                     break;
 835                   }
 836                   // Found a def?  Better split after it.
 837                   if (_lrg_map.live_range_id(n) == lidx) {
 838                     break;
 839                   }
 840                   // Look for a use
 841                   uint i;
 842                   for( i = 1; i < n->req(); i++ ) {
 843                     if (_lrg_map.live_range_id(n->in(i)) == lidx) {
 844                       break;
 845                     }
 846                   }
 847                   // Found a use?  Better split after it.
 848                   if (i < n->req()) {
 849                     break;
 850                   }
 851                   insert_point--;
 852                 }
 853                 uint orig_eidx = b->end_idx();
 854                 maxlrg = split_DEF( n1, b, insert_point, maxlrg, Reachblock, debug_defs, splits, slidx);
 855                 // If it wasn't split bail
 856                 if (!maxlrg) {
 857                   return 0;
 858                 }
 859                 // Spill of NULL check mem op goes into the following block.
 860                 if (b->end_idx() > orig_eidx) {
 861                   insidx++;
 862                 }
 863               }
 864               // This is a new DEF, so update UP
 865               UPblock[slidx] = false;
 866 #ifndef PRODUCT
 867               // DEBUG
 868               if( trace_spilling() ) {
 869                 tty->print("\nNew Split DOWN DEF of Spill Idx ");
 870                 tty->print("%d, UP %d:\n",slidx,false);
 871                 n1->dump();
 872               }
 873 #endif
 874             }
 875           }  // end if LRG is UP
 876         }  // end for all spilling live ranges
 877         assert( b->get_node(insidx) == n, "got insidx set incorrectly" );
 878       }  // end if crossing HRP Boundry
 879 
 880       // If the LRG index is oob, then this is a new spillcopy, skip it.
 881       if (defidx >= _lrg_map.max_lrg_id()) {
 882         continue;
 883       }
 884       LRG &deflrg = lrgs(defidx);
 885       uint copyidx = n->is_Copy();
 886       // Remove coalesced copy from CFG
 887       if (copyidx && defidx == _lrg_map.live_range_id(n->in(copyidx))) {
 888         n->replace_by( n->in(copyidx) );
 889         n->set_req( copyidx, NULL );
 890         b->remove_node(insidx--);
 891         b->_ihrp_index--; // Adjust the point where we go hi-pressure
 892         b->_fhrp_index--;
 893         continue;
 894       }
 895 
 896 #define DERIVED 0
 897 
 898       // ********** Handle USES **********
 899       bool nullcheck = false;
 900       // Implicit null checks never use the spilled value
 901       if( n->is_MachNullCheck() )
 902         nullcheck = true;
 903       if( !nullcheck ) {
 904         // Search all inputs for a Spill-USE
 905         JVMState* jvms = n->jvms();
 906         uint oopoff = jvms ? jvms->oopoff() : cnt;
 907         uint old_last = cnt - 1;
 908         for( inpidx = 1; inpidx < cnt; inpidx++ ) {
 909           // Derived/base pairs may be added to our inputs during this loop.
 910           // If inpidx > old_last, then one of these new inputs is being
 911           // handled. Skip the derived part of the pair, but process
 912           // the base like any other input.
 913           if (inpidx > old_last && ((inpidx - oopoff) & 1) == DERIVED) {
 914             continue;  // skip derived_debug added below
 915           }
 916           // Get lidx of input
 917           uint useidx = _lrg_map.find_id(n->in(inpidx));
 918           // Not a brand-new split, and it is a spill use
 919           if (useidx < _lrg_map.max_lrg_id() && lrgs(useidx).reg() >= LRG::SPILL_REG) {
 920             // Check for valid reaching DEF
 921             slidx = lrg2reach[useidx];
 922             Node *def = Reachblock[slidx];
 923             assert( def != NULL, "Using Undefined Value in Split()\n");
 924 
 925             // (+++) %%%% remove this in favor of pre-pass in matcher.cpp
 926             // monitor references do not care where they live, so just hook
 927             if ( jvms && jvms->is_monitor_use(inpidx) ) {
 928               // The effect of this clone is to drop the node out of the block,
 929               // so that the allocator does not see it anymore, and therefore
 930               // does not attempt to assign it a register.
 931               def = clone_node(def, b, C);
 932               if (def == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
 933                 return 0;
 934               }
 935               _lrg_map.extend(def->_idx, 0);
 936               _cfg.map_node_to_block(def, b);
 937               n->set_req(inpidx, def);
 938               continue;
 939             }
 940 
 941             // Rematerializable?  Then clone def at use site instead
 942             // of store/load
 943             if( def->rematerialize() ) {
 944               int old_size = b->number_of_nodes();
 945               def = split_Rematerialize( def, b, insidx, maxlrg, splits, slidx, lrg2reach, Reachblock, true );
 946               if( !def ) return 0; // Bail out
 947               insidx += b->number_of_nodes()-old_size;
 948             }
 949 
 950             MachNode *mach = n->is_Mach() ? n->as_Mach() : NULL;
 951             // Base pointers and oopmap references do not care where they live.
 952             if ((inpidx >= oopoff) ||
 953                 (mach && mach->ideal_Opcode() == Op_AddP && inpidx == AddPNode::Base)) {
 954               if (def->rematerialize() && lrgs(useidx)._was_spilled2) {
 955                 // This def has been rematerialized a couple of times without
 956                 // progress. It doesn't care if it lives UP or DOWN, so
 957                 // spill it down now.
 958                 maxlrg = split_USE(MachSpillCopyNode::BasePointerToMem, def,b,n,inpidx,maxlrg,false,false,splits,slidx);
 959                 // If it wasn't split bail
 960                 if (!maxlrg) {
 961                   return 0;
 962                 }
 963                 insidx++;  // Reset iterator to skip USE side split
 964               } else {
 965                 // Just hook the def edge
 966                 n->set_req(inpidx, def);
 967               }
 968 
 969               if (inpidx >= oopoff) {
 970                 // After oopoff, we have derived/base pairs.  We must mention all
 971                 // derived pointers here as derived/base pairs for GC.  If the
 972                 // derived value is spilling and we have a copy both in Reachblock
 973                 // (called here 'def') and debug_defs[slidx] we need to mention
 974                 // both in derived/base pairs or kill one.
 975                 Node *derived_debug = debug_defs[slidx];
 976                 if( ((inpidx - oopoff) & 1) == DERIVED && // derived vs base?
 977                     mach && mach->ideal_Opcode() != Op_Halt &&
 978                     derived_debug != NULL &&
 979                     derived_debug != def ) { // Actual 2nd value appears
 980                   // We have already set 'def' as a derived value.
 981                   // Also set debug_defs[slidx] as a derived value.
 982                   uint k;
 983                   for( k = oopoff; k < cnt; k += 2 )
 984                     if( n->in(k) == derived_debug )
 985                       break;      // Found an instance of debug derived
 986                   if( k == cnt ) {// No instance of debug_defs[slidx]
 987                     // Add a derived/base pair to cover the debug info.
 988                     // We have to process the added base later since it is not
 989                     // handled yet at this point but skip derived part.
 990                     assert(((n->req() - oopoff) & 1) == DERIVED,
 991                            "must match skip condition above");
 992                     n->add_req( derived_debug );   // this will be skipped above
 993                     n->add_req( n->in(inpidx+1) ); // this will be processed
 994                     // Increment cnt to handle added input edges on
 995                     // subsequent iterations.
 996                     cnt += 2;
 997                   }
 998                 }
 999               }
1000               continue;
1001             }
1002             // Special logic for DEBUG info
1003             if( jvms && b->_freq > BLOCK_FREQUENCY(0.5) ) {
1004               uint debug_start = jvms->debug_start();
1005               // If this is debug info use & there is a reaching DOWN def
1006               if ((debug_start <= inpidx) && (debug_defs[slidx] != NULL)) {
1007                 assert(inpidx < oopoff, "handle only debug info here");
1008                 // Just hook it in & move on
1009                 n->set_req(inpidx, debug_defs[slidx]);
1010                 // (Note that this can make two sides of a split live at the
1011                 // same time: The debug def on stack, and another def in a
1012                 // register.  The GC needs to know about both of them, but any
1013                 // derived pointers after oopoff will refer to only one of the
1014                 // two defs and the GC would therefore miss the other.  Thus
1015                 // this hack is only allowed for debug info which is Java state
1016                 // and therefore never a derived pointer.)
1017                 continue;
1018               }
1019             }
1020             // Grab register mask info
1021             const RegMask &dmask = def->out_RegMask();
1022             const RegMask &umask = n->in_RegMask(inpidx);
1023             bool is_vect = RegMask::is_vector(def->ideal_reg());
1024             assert(inpidx < oopoff, "cannot use-split oop map info");
1025 
1026             bool dup = UPblock[slidx];
1027             bool uup = umask.is_UP();
1028 
1029             // Need special logic to handle bound USES. Insert a split at this
1030             // bound use if we can't rematerialize the def, or if we need the
1031             // split to form a misaligned pair.
1032             if( !umask.is_AllStack() &&
1033                 (int)umask.Size() <= lrgs(useidx).num_regs() &&
1034                 (!def->rematerialize() ||
1035                  !is_vect && umask.is_misaligned_pair())) {
1036               // These need a Split regardless of overlap or pressure
1037               // SPLIT - NO DEF - NO CISC SPILL
1038               maxlrg = split_USE(MachSpillCopyNode::Bound, def,b,n,inpidx,maxlrg,dup,false, splits,slidx);
1039               // If it wasn't split bail
1040               if (!maxlrg) {
1041                 return 0;
1042               }
1043               insidx++;  // Reset iterator to skip USE side split
1044               continue;
1045             }
1046 
1047             if (UseFPUForSpilling && n->is_MachCall() && !uup && !dup ) {
1048               // The use at the call can force the def down so insert
1049               // a split before the use to allow the def more freedom.
1050               maxlrg = split_USE(MachSpillCopyNode::CallUse, def,b,n,inpidx,maxlrg,dup,false, splits,slidx);
1051               // If it wasn't split bail
1052               if (!maxlrg) {
1053                 return 0;
1054               }
1055               insidx++;  // Reset iterator to skip USE side split
1056               continue;
1057             }
1058 
1059             // Here is the logic chart which describes USE Splitting:
1060             // 0 = false or DOWN, 1 = true or UP
1061             //
1062             // Overlap | DEF | USE | Action
1063             //-------------------------------------------------------
1064             //    0    |  0  |  0  | Copy - mem -> mem
1065             //    0    |  0  |  1  | Split-UP - Check HRP
1066             //    0    |  1  |  0  | Split-DOWN - Debug Info?
1067             //    0    |  1  |  1  | Copy - reg -> reg
1068             //    1    |  0  |  0  | Reset Input Edge (no Split)
1069             //    1    |  0  |  1  | Split-UP - Check HRP
1070             //    1    |  1  |  0  | Split-DOWN - Debug Info?
1071             //    1    |  1  |  1  | Reset Input Edge (no Split)
1072             //
1073             // So, if (dup == uup), then overlap test determines action,
1074             // with true being no split, and false being copy. Else,
1075             // if DEF is DOWN, Split-UP, and check HRP to decide on
1076             // resetting DEF. Finally if DEF is UP, Split-DOWN, with
1077             // special handling for Debug Info.
1078             if( dup == uup ) {
1079               if( dmask.overlap(umask) ) {
1080                 // Both are either up or down, and there is overlap, No Split
1081                 n->set_req(inpidx, def);
1082               }
1083               else {  // Both are either up or down, and there is no overlap
1084                 if( dup ) {  // If UP, reg->reg copy
1085                   // COPY ACROSS HERE - NO DEF - NO CISC SPILL
1086                   maxlrg = split_USE(MachSpillCopyNode::RegToReg, def,b,n,inpidx,maxlrg,false,false, splits,slidx);
1087                   // If it wasn't split bail
1088                   if (!maxlrg) {
1089                     return 0;
1090                   }
1091                   insidx++;  // Reset iterator to skip USE side split
1092                 }
1093                 else {       // DOWN, mem->mem copy
1094                   // COPY UP & DOWN HERE - NO DEF - NO CISC SPILL
1095                   // First Split-UP to move value into Register
1096                   uint def_ideal = def->ideal_reg();
1097                   const RegMask* tmp_rm = Matcher::idealreg2regmask[def_ideal];
1098                   Node *spill = new MachSpillCopyNode(MachSpillCopyNode::MemToReg, def, dmask, *tmp_rm);
1099                   insert_proj( b, insidx, spill, maxlrg );
1100                   // Then Split-DOWN as if previous Split was DEF
1101                   maxlrg = split_USE(MachSpillCopyNode::RegToMem, spill,b,n,inpidx,maxlrg,false,false, splits,slidx);
1102                   // If it wasn't split bail
1103                   if (!maxlrg) {
1104                     return 0;
1105                   }
1106                   insidx += 2;  // Reset iterator to skip USE side splits
1107                 }
1108               }  // End else no overlap
1109             }  // End if dup == uup
1110             // dup != uup, so check dup for direction of Split
1111             else {
1112               if( dup ) {  // If UP, Split-DOWN and check Debug Info
1113                 // If this node is already a SpillCopy, just patch the edge
1114                 // except the case of spilling to stack.
1115                 if( n->is_SpillCopy() ) {
1116                   RegMask tmp_rm(umask);
1117                   tmp_rm.SUBTRACT(Matcher::STACK_ONLY_mask);
1118                   if( dmask.overlap(tmp_rm) ) {
1119                     if( def != n->in(inpidx) ) {
1120                       n->set_req(inpidx, def);
1121                     }
1122                     continue;
1123                   }
1124                 }
1125                 // COPY DOWN HERE - NO DEF - NO CISC SPILL
1126                 maxlrg = split_USE(MachSpillCopyNode::RegToMem, def,b,n,inpidx,maxlrg,false,false, splits,slidx);
1127                 // If it wasn't split bail
1128                 if (!maxlrg) {
1129                   return 0;
1130                 }
1131                 insidx++;  // Reset iterator to skip USE side split
1132                 // Check for debug-info split.  Capture it for later
1133                 // debug splits of the same value
1134                 if (jvms && jvms->debug_start() <= inpidx && inpidx < oopoff)
1135                   debug_defs[slidx] = n->in(inpidx);
1136 
1137               }
1138               else {       // DOWN, Split-UP and check register pressure
1139                 if( is_high_pressure( b, &lrgs(useidx), insidx ) ) {
1140                   // COPY UP HERE - NO DEF - CISC SPILL
1141                   maxlrg = split_USE(MachSpillCopyNode::MemToReg, def,b,n,inpidx,maxlrg,true,true, splits,slidx);
1142                   // If it wasn't split bail
1143                   if (!maxlrg) {
1144                     return 0;
1145                   }
1146                   insidx++;  // Reset iterator to skip USE side split
1147                 } else {                          // LRP
1148                   // COPY UP HERE - WITH DEF - NO CISC SPILL
1149                   maxlrg = split_USE(MachSpillCopyNode::MemToReg, def,b,n,inpidx,maxlrg,true,false, splits,slidx);
1150                   // If it wasn't split bail
1151                   if (!maxlrg) {
1152                     return 0;
1153                   }
1154                   // Flag this lift-up in a low-pressure block as
1155                   // already-spilled, so if it spills again it will
1156                   // spill hard (instead of not spilling hard and
1157                   // coalescing away).
1158                   set_was_spilled(n->in(inpidx));
1159                   // Since this is a new DEF, update Reachblock & UP
1160                   Reachblock[slidx] = n->in(inpidx);
1161                   UPblock[slidx] = true;
1162                   insidx++;  // Reset iterator to skip USE side split
1163                 }
1164               }  // End else DOWN
1165             }  // End dup != uup
1166           }  // End if Spill USE
1167         }  // End For All Inputs
1168       }  // End If not nullcheck
1169 
1170       // ********** Handle DEFS **********
1171       // DEFS either Split DOWN in HRP regions or when the LRG is bound, or
1172       // just reset the Reaches info in LRP regions.  DEFS must always update
1173       // UP info.
1174       if( deflrg.reg() >= LRG::SPILL_REG ) {    // Spilled?
1175         uint slidx = lrg2reach[defidx];
1176         // Add to defs list for later assignment of new live range number
1177         defs->push(n);
1178         // Set a flag on the Node indicating it has already spilled.
1179         // Only do it for capacity spills not conflict spills.
1180         if( !deflrg._direct_conflict )
1181           set_was_spilled(n);
1182         assert(!n->is_Phi(),"Cannot insert Phi into DEFS list");
1183         // Grab UP info for DEF
1184         const RegMask &dmask = n->out_RegMask();
1185         bool defup = dmask.is_UP();
1186         int ireg = n->ideal_reg();
1187         bool is_vect = RegMask::is_vector(ireg);
1188         // Only split at Def if this is a HRP block or bound (and spilled once)
1189         if( !n->rematerialize() &&
1190             (((dmask.is_bound(ireg) || !is_vect && dmask.is_misaligned_pair()) &&
1191               (deflrg._direct_conflict || deflrg._must_spill)) ||
1192              // Check for LRG being up in a register and we are inside a high
1193              // pressure area.  Spill it down immediately.
1194              (defup && is_high_pressure(b,&deflrg,insidx))) ) {
1195           assert( !n->rematerialize(), "" );
1196           assert( !n->is_SpillCopy(), "" );
1197           // Do a split at the def site.
1198           maxlrg = split_DEF( n, b, insidx, maxlrg, Reachblock, debug_defs, splits, slidx );
1199           // If it wasn't split bail
1200           if (!maxlrg) {
1201             return 0;
1202           }
1203           // Split DEF's Down
1204           UPblock[slidx] = 0;
1205 #ifndef PRODUCT
1206           // DEBUG
1207           if( trace_spilling() ) {
1208             tty->print("\nNew Split DOWN DEF of Spill Idx ");
1209             tty->print("%d, UP %d:\n",slidx,false);
1210             n->dump();
1211           }
1212 #endif
1213         }
1214         else {                  // Neither bound nor HRP, must be LRP
1215           // otherwise, just record the def
1216           Reachblock[slidx] = n;
1217           // UP should come from the outRegmask() of the DEF
1218           UPblock[slidx] = defup;
1219           // Update debug list of reaching down definitions, kill if DEF is UP
1220           debug_defs[slidx] = defup ? NULL : n;
1221 #ifndef PRODUCT
1222           // DEBUG
1223           if( trace_spilling() ) {
1224             tty->print("\nNew DEF of Spill Idx ");
1225             tty->print("%d, UP %d:\n",slidx,defup);
1226             n->dump();
1227           }
1228 #endif
1229         }  // End else LRP
1230       }  // End if spill def
1231 
1232       // ********** Split Left Over Mem-Mem Moves **********
1233       // Check for mem-mem copies and split them now.  Do not do this
1234       // to copies about to be spilled; they will be Split shortly.
1235       if (copyidx) {
1236         Node *use = n->in(copyidx);
1237         uint useidx = _lrg_map.find_id(use);
1238         if (useidx < _lrg_map.max_lrg_id() &&       // This is not a new split
1239             OptoReg::is_stack(deflrg.reg()) &&
1240             deflrg.reg() < LRG::SPILL_REG ) { // And DEF is from stack
1241           LRG &uselrg = lrgs(useidx);
1242           if( OptoReg::is_stack(uselrg.reg()) &&
1243               uselrg.reg() < LRG::SPILL_REG && // USE is from stack
1244               deflrg.reg() != uselrg.reg() ) { // Not trivially removed
1245             uint def_ideal_reg = n->bottom_type()->ideal_reg();
1246             const RegMask &def_rm = *Matcher::idealreg2regmask[def_ideal_reg];
1247             const RegMask &use_rm = n->in_RegMask(copyidx);
1248             if( def_rm.overlap(use_rm) && n->is_SpillCopy() ) {  // Bug 4707800, 'n' may be a storeSSL
1249               if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {  // Check when generating nodes
1250                 return 0;
1251               }
1252               Node *spill = new MachSpillCopyNode(MachSpillCopyNode::MemToReg, use,use_rm,def_rm);
1253               n->set_req(copyidx,spill);
1254               n->as_MachSpillCopy()->set_in_RegMask(def_rm);
1255               // Put the spill just before the copy
1256               insert_proj( b, insidx++, spill, maxlrg++ );
1257             }
1258           }
1259         }
1260       }
1261     }  // End For All Instructions in Block - Non-PHI Pass
1262 
1263     // Check if each LRG is live out of this block so as not to propagate
1264     // beyond the last use of a LRG.
1265     for( slidx = 0; slidx < spill_cnt; slidx++ ) {
1266       uint defidx = lidxs.at(slidx);
1267       IndexSet *liveout = _live->live(b);
1268       if( !liveout->member(defidx) ) {
1269 #ifdef ASSERT
1270         // The index defidx is not live.  Check the liveout array to ensure that
1271         // it contains no members which compress to defidx.  Finding such an
1272         // instance may be a case to add liveout adjustment in compress_uf_map().
1273         // See 5063219.
1274         uint member;
1275         IndexSetIterator isi(liveout);
1276         while ((member = isi.next()) != 0) {
1277           assert(defidx != _lrg_map.find_const(member), "Live out member has not been compressed");
1278         }
1279 #endif
1280         Reachblock[slidx] = NULL;
1281       } else {
1282         assert(Reachblock[slidx] != NULL,"No reaching definition for liveout value");
1283       }
1284     }
1285 #ifndef PRODUCT
1286     if( trace_spilling() )
1287       b->dump();
1288 #endif
1289   }  // End For All Blocks
1290 
1291   //----------PASS 2----------
1292   // Reset all DEF live range numbers here
1293   for( insidx = 0; insidx < defs->size(); insidx++ ) {
1294     // Grab the def
1295     n1 = defs->at(insidx);
1296     // Set new lidx for DEF
1297     new_lrg(n1, maxlrg++);
1298   }
1299   //----------Phi Node Splitting----------
1300   // Clean up a phi here, and assign a new live range number
1301   // Cycle through this block's predecessors, collecting Reaches
1302   // info for each spilled LRG and update edges.
1303   // Walk the phis list to patch inputs, split phis, and name phis
1304   uint lrgs_before_phi_split = maxlrg;
1305   for( insidx = 0; insidx < phis->size(); insidx++ ) {
1306     Node *phi = phis->at(insidx);
1307     assert(phi->is_Phi(),"This list must only contain Phi Nodes");
1308     Block *b = _cfg.get_block_for_node(phi);
1309     // Grab the live range number
1310     uint lidx = _lrg_map.find_id(phi);
1311     uint slidx = lrg2reach[lidx];
1312     // Update node to lidx map
1313     new_lrg(phi, maxlrg++);
1314     // Get PASS1's up/down decision for the block.
1315     int phi_up = !!UP_entry[slidx]->test(b->_pre_order);
1316 
1317     // Force down if double-spilling live range
1318     if( lrgs(lidx)._was_spilled1 )
1319       phi_up = false;
1320 
1321     // When splitting a Phi we an split it normal or "inverted".
1322     // An inverted split makes the splits target the Phi's UP/DOWN
1323     // sense inverted; then the Phi is followed by a final def-side
1324     // split to invert back.  It changes which blocks the spill code
1325     // goes in.
1326 
1327     // Walk the predecessor blocks and assign the reaching def to the Phi.
1328     // Split Phi nodes by placing USE side splits wherever the reaching
1329     // DEF has the wrong UP/DOWN value.
1330     for( uint i = 1; i < b->num_preds(); i++ ) {
1331       // Get predecessor block pre-order number
1332       Block *pred = _cfg.get_block_for_node(b->pred(i));
1333       pidx = pred->_pre_order;
1334       // Grab reaching def
1335       Node *def = Reaches[pidx][slidx];
1336       Node** Reachblock = Reaches[pidx];
1337       assert( def, "must have reaching def" );
1338       // If input up/down sense and reg-pressure DISagree
1339       if (def->rematerialize()) {
1340         // Place the rematerialized node above any MSCs created during
1341         // phi node splitting.  end_idx points at the insertion point
1342         // so look at the node before it.
1343         int insert = pred->end_idx();
1344         while (insert >= 1 &&
1345                pred->get_node(insert - 1)->is_SpillCopy() &&
1346                _lrg_map.find(pred->get_node(insert - 1)) >= lrgs_before_phi_split) {
1347           insert--;
1348         }
1349         def = split_Rematerialize(def, pred, insert, maxlrg, splits, slidx, lrg2reach, Reachblock, false);
1350         if (!def) {
1351           return 0;    // Bail out
1352         }
1353       }
1354       // Update the Phi's input edge array
1355       phi->set_req(i,def);
1356       // Grab the UP/DOWN sense for the input
1357       u1 = UP[pidx][slidx];
1358       if( u1 != (phi_up != 0)) {
1359         maxlrg = split_USE(MachSpillCopyNode::PhiLocationDifferToInputLocation, def, b, phi, i, maxlrg, !u1, false, splits,slidx);
1360         // If it wasn't split bail
1361         if (!maxlrg) {
1362           return 0;
1363         }
1364       }
1365     }  // End for all inputs to the Phi
1366   }  // End for all Phi Nodes
1367   // Update _maxlrg to save Union asserts
1368   _lrg_map.set_max_lrg_id(maxlrg);
1369 
1370 
1371   //----------PASS 3----------
1372   // Pass over all Phi's to union the live ranges
1373   for( insidx = 0; insidx < phis->size(); insidx++ ) {
1374     Node *phi = phis->at(insidx);
1375     assert(phi->is_Phi(),"This list must only contain Phi Nodes");
1376     // Walk all inputs to Phi and Union input live range with Phi live range
1377     for( uint i = 1; i < phi->req(); i++ ) {
1378       // Grab the input node
1379       Node *n = phi->in(i);
1380       assert(n, "node should exist");
1381       uint lidx = _lrg_map.find(n);
1382       uint pidx = _lrg_map.find(phi);
1383       if (lidx < pidx) {
1384         Union(n, phi);
1385       }
1386       else if(lidx > pidx) {
1387         Union(phi, n);
1388       }
1389     }  // End for all inputs to the Phi Node
1390   }  // End for all Phi Nodes
1391   // Now union all two address instructions
1392   for (insidx = 0; insidx < defs->size(); insidx++) {
1393     // Grab the def
1394     n1 = defs->at(insidx);
1395     // Set new lidx for DEF & handle 2-addr instructions
1396     if (n1->is_Mach() && ((twoidx = n1->as_Mach()->two_adr()) != 0)) {
1397       assert(_lrg_map.find(n1->in(twoidx)) < maxlrg,"Assigning bad live range index");
1398       // Union the input and output live ranges
1399       uint lr1 = _lrg_map.find(n1);
1400       uint lr2 = _lrg_map.find(n1->in(twoidx));
1401       if (lr1 < lr2) {
1402         Union(n1, n1->in(twoidx));
1403       }
1404       else if (lr1 > lr2) {
1405         Union(n1->in(twoidx), n1);
1406       }
1407     }  // End if two address
1408   }  // End for all defs
1409   // DEBUG
1410 #ifdef ASSERT
1411   // Validate all live range index assignments
1412   for (bidx = 0; bidx < _cfg.number_of_blocks(); bidx++) {
1413     b  = _cfg.get_block(bidx);
1414     for (insidx = 0; insidx <= b->end_idx(); insidx++) {
1415       Node *n = b->get_node(insidx);
1416       uint defidx = _lrg_map.find(n);
1417       assert(defidx < _lrg_map.max_lrg_id(), "Bad live range index in Split");
1418       assert(defidx < maxlrg,"Bad live range index in Split");
1419     }
1420   }
1421   // Issue a warning if splitting made no progress
1422   int noprogress = 0;
1423   for (slidx = 0; slidx < spill_cnt; slidx++) {
1424     if (PrintOpto && WizardMode && splits.at(slidx) == 0) {
1425       tty->print_cr("Failed to split live range %d", lidxs.at(slidx));
1426       //BREAKPOINT;
1427     }
1428     else {
1429       noprogress++;
1430     }
1431   }
1432   if(!noprogress) {
1433     tty->print_cr("Failed to make progress in Split");
1434     //BREAKPOINT;
1435   }
1436 #endif
1437   // Return updated count of live ranges
1438   return maxlrg;
1439 }