44 //
45 // We define four primitive memory barrier operations.
46 //
47 // LoadLoad: Load1(s); LoadLoad; Load2
48 //
49 // Ensures that Load1 completes (obtains the value it loads from memory)
50 // before Load2 and any subsequent load operations. Loads before Load1
51 // may *not* float below Load2 and any subsequent load operations.
52 //
53 // StoreStore: Store1(s); StoreStore; Store2
54 //
55 // Ensures that Store1 completes (the effect on memory of Store1 is made
56 // visible to other processors) before Store2 and any subsequent store
57 // operations. Stores before Store1 may *not* float below Store2 and any
58 // subsequent store operations.
59 //
60 // LoadStore: Load1(s); LoadStore; Store2
61 //
62 // Ensures that Load1 completes before Store2 and any subsequent store
63 // operations. Loads before Load1 may *not* float below Store2 and any
64 // subseqeuent store operations.
65 //
66 // StoreLoad: Store1(s); StoreLoad; Load2
67 //
68 // Ensures that Store1 completes before Load2 and any subsequent load
69 // operations. Stores before Store1 may *not* float below Load2 and any
70 // subseqeuent load operations.
71 //
72 //
73 // We define two further operations, 'release' and 'acquire'. They are
74 // mirror images of each other.
75 //
76 // Execution by a processor of release makes the effect of all memory
77 // accesses issued by it previous to the release visible to all
78 // processors *before* the release completes. The effect of subsequent
79 // memory accesses issued by it *may* be made visible *before* the
80 // release. I.e., subsequent memory accesses may float above the
81 // release, but prior ones may not float below it.
82 //
83 // Execution by a processor of acquire makes the effect of all memory
84 // accesses issued by it subsequent to the acquire visible to all
85 // processors *after* the acquire completes. The effect of prior memory
86 // accesses issued by it *may* be made visible *after* the acquire.
87 // I.e., prior memory accesses may float below the acquire, but
88 // subsequent ones may not float above it.
89 //
90 // Finally, we define a 'fence' operation, which conceptually is a
159 // accesses (including the new thread state) are visible to other threads.
160 //
161 //
162 // C++ Volatility
163 //
164 // C++ guarantees ordering at operations termed 'sequence points' (defined
165 // to be volatile accesses and calls to library I/O functions). 'Side
166 // effects' (defined as volatile accesses, calls to library I/O functions
167 // and object modification) previous to a sequence point must be visible
168 // at that sequence point. See the C++ standard, section 1.9, titled
169 // "Program Execution". This means that all barrier implementations,
170 // including standalone loadload, storestore, loadstore, storeload, acquire
171 // and release must include a sequence point, usually via a volatile memory
172 // access. Other ways to guarantee a sequence point are, e.g., use of
173 // indirect calls and linux's __asm__ volatile.
174 // Note: as of 6973570, we have replaced the originally static "dummy" field
175 // (see above) by a volatile store to the stack. All of the versions of the
176 // compilers that we currently use (SunStudio, gcc and VC++) respect the
177 // semantics of volatile here. If you build HotSpot using other
178 // compilers, you may need to verify that no compiler reordering occurs
179 // across the sequence point respresented by the volatile access.
180 //
181 //
182 // os::is_MP Considered Redundant
183 //
184 // Callers of this interface do not need to test os::is_MP() before
185 // issuing an operation. The test is taken care of by the implementation
186 // of the interface (depending on the vm version and platform, the test
187 // may or may not be actually done by the implementation).
188 //
189 //
190 // A Note on Memory Ordering and Cache Coherency
191 //
192 // Cache coherency and memory ordering are orthogonal concepts, though they
193 // interact. E.g., all existing itanium machines are cache-coherent, but
194 // the hardware can freely reorder loads wrt other loads unless it sees a
195 // load-acquire instruction. All existing sparc machines are cache-coherent
196 // and, unlike itanium, TSO guarantees that the hardware orders loads wrt
197 // loads and stores, and stores wrt to each other.
198 //
199 // Consider the implementation of loadload. *If* your platform *isn't*
294 static void store_ptr_fence(intptr_t* p, intptr_t v);
295 static void store_ptr_fence(void** p, void* v);
296
297 static void release_store_fence(volatile jbyte* p, jbyte v);
298 static void release_store_fence(volatile jshort* p, jshort v);
299 static void release_store_fence(volatile jint* p, jint v);
300 static void release_store_fence(volatile jlong* p, jlong v);
301 static void release_store_fence(volatile jubyte* p, jubyte v);
302 static void release_store_fence(volatile jushort* p, jushort v);
303 static void release_store_fence(volatile juint* p, juint v);
304 static void release_store_fence(volatile julong* p, julong v);
305 static void release_store_fence(volatile jfloat* p, jfloat v);
306 static void release_store_fence(volatile jdouble* p, jdouble v);
307
308 static void release_store_ptr_fence(volatile intptr_t* p, intptr_t v);
309 static void release_store_ptr_fence(volatile void* p, void* v);
310
311 private:
312 // This is a helper that invokes the StubRoutines::fence_entry()
313 // routine if it exists, It should only be used by platforms that
314 // don't another way to do the inline eassembly.
315 static void StubRoutines_fence();
316 };
317
318 #endif // SHARE_VM_RUNTIME_ORDERACCESS_HPP
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44 //
45 // We define four primitive memory barrier operations.
46 //
47 // LoadLoad: Load1(s); LoadLoad; Load2
48 //
49 // Ensures that Load1 completes (obtains the value it loads from memory)
50 // before Load2 and any subsequent load operations. Loads before Load1
51 // may *not* float below Load2 and any subsequent load operations.
52 //
53 // StoreStore: Store1(s); StoreStore; Store2
54 //
55 // Ensures that Store1 completes (the effect on memory of Store1 is made
56 // visible to other processors) before Store2 and any subsequent store
57 // operations. Stores before Store1 may *not* float below Store2 and any
58 // subsequent store operations.
59 //
60 // LoadStore: Load1(s); LoadStore; Store2
61 //
62 // Ensures that Load1 completes before Store2 and any subsequent store
63 // operations. Loads before Load1 may *not* float below Store2 and any
64 // subsequent store operations.
65 //
66 // StoreLoad: Store1(s); StoreLoad; Load2
67 //
68 // Ensures that Store1 completes before Load2 and any subsequent load
69 // operations. Stores before Store1 may *not* float below Load2 and any
70 // subsequent load operations.
71 //
72 //
73 // We define two further operations, 'release' and 'acquire'. They are
74 // mirror images of each other.
75 //
76 // Execution by a processor of release makes the effect of all memory
77 // accesses issued by it previous to the release visible to all
78 // processors *before* the release completes. The effect of subsequent
79 // memory accesses issued by it *may* be made visible *before* the
80 // release. I.e., subsequent memory accesses may float above the
81 // release, but prior ones may not float below it.
82 //
83 // Execution by a processor of acquire makes the effect of all memory
84 // accesses issued by it subsequent to the acquire visible to all
85 // processors *after* the acquire completes. The effect of prior memory
86 // accesses issued by it *may* be made visible *after* the acquire.
87 // I.e., prior memory accesses may float below the acquire, but
88 // subsequent ones may not float above it.
89 //
90 // Finally, we define a 'fence' operation, which conceptually is a
159 // accesses (including the new thread state) are visible to other threads.
160 //
161 //
162 // C++ Volatility
163 //
164 // C++ guarantees ordering at operations termed 'sequence points' (defined
165 // to be volatile accesses and calls to library I/O functions). 'Side
166 // effects' (defined as volatile accesses, calls to library I/O functions
167 // and object modification) previous to a sequence point must be visible
168 // at that sequence point. See the C++ standard, section 1.9, titled
169 // "Program Execution". This means that all barrier implementations,
170 // including standalone loadload, storestore, loadstore, storeload, acquire
171 // and release must include a sequence point, usually via a volatile memory
172 // access. Other ways to guarantee a sequence point are, e.g., use of
173 // indirect calls and linux's __asm__ volatile.
174 // Note: as of 6973570, we have replaced the originally static "dummy" field
175 // (see above) by a volatile store to the stack. All of the versions of the
176 // compilers that we currently use (SunStudio, gcc and VC++) respect the
177 // semantics of volatile here. If you build HotSpot using other
178 // compilers, you may need to verify that no compiler reordering occurs
179 // across the sequence point represented by the volatile access.
180 //
181 //
182 // os::is_MP Considered Redundant
183 //
184 // Callers of this interface do not need to test os::is_MP() before
185 // issuing an operation. The test is taken care of by the implementation
186 // of the interface (depending on the vm version and platform, the test
187 // may or may not be actually done by the implementation).
188 //
189 //
190 // A Note on Memory Ordering and Cache Coherency
191 //
192 // Cache coherency and memory ordering are orthogonal concepts, though they
193 // interact. E.g., all existing itanium machines are cache-coherent, but
194 // the hardware can freely reorder loads wrt other loads unless it sees a
195 // load-acquire instruction. All existing sparc machines are cache-coherent
196 // and, unlike itanium, TSO guarantees that the hardware orders loads wrt
197 // loads and stores, and stores wrt to each other.
198 //
199 // Consider the implementation of loadload. *If* your platform *isn't*
294 static void store_ptr_fence(intptr_t* p, intptr_t v);
295 static void store_ptr_fence(void** p, void* v);
296
297 static void release_store_fence(volatile jbyte* p, jbyte v);
298 static void release_store_fence(volatile jshort* p, jshort v);
299 static void release_store_fence(volatile jint* p, jint v);
300 static void release_store_fence(volatile jlong* p, jlong v);
301 static void release_store_fence(volatile jubyte* p, jubyte v);
302 static void release_store_fence(volatile jushort* p, jushort v);
303 static void release_store_fence(volatile juint* p, juint v);
304 static void release_store_fence(volatile julong* p, julong v);
305 static void release_store_fence(volatile jfloat* p, jfloat v);
306 static void release_store_fence(volatile jdouble* p, jdouble v);
307
308 static void release_store_ptr_fence(volatile intptr_t* p, intptr_t v);
309 static void release_store_ptr_fence(volatile void* p, void* v);
310
311 private:
312 // This is a helper that invokes the StubRoutines::fence_entry()
313 // routine if it exists, It should only be used by platforms that
314 // don't have another way to do the inline assembly.
315 static void StubRoutines_fence();
316 };
317
318 #endif // SHARE_VM_RUNTIME_ORDERACCESS_HPP
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