src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.aarch64/src/org/graalvm/compiler/asm/aarch64/AArch64MacroAssembler.java

*** 31,40 ****
--- 31,43 ----
  import static org.graalvm.compiler.asm.aarch64.AArch64Address.AddressingMode.IMMEDIATE_UNSCALED;
  import static org.graalvm.compiler.asm.aarch64.AArch64Address.AddressingMode.REGISTER_OFFSET;
  import static org.graalvm.compiler.asm.aarch64.AArch64MacroAssembler.AddressGenerationPlan.WorkPlan.ADD_TO_BASE;
  import static org.graalvm.compiler.asm.aarch64.AArch64MacroAssembler.AddressGenerationPlan.WorkPlan.ADD_TO_INDEX;
  import static org.graalvm.compiler.asm.aarch64.AArch64MacroAssembler.AddressGenerationPlan.WorkPlan.NO_WORK;
+ 
+ import org.graalvm.compiler.asm.BranchTargetOutOfBoundsException;
+ 
  import static jdk.vm.ci.aarch64.AArch64.CPU;
  import static jdk.vm.ci.aarch64.AArch64.r8;
  import static jdk.vm.ci.aarch64.AArch64.r9;
  import static jdk.vm.ci.aarch64.AArch64.sp;
  import static jdk.vm.ci.aarch64.AArch64.zr;
*** 1450,1460 ****
      /**
       * Test a single bit and branch if the bit is nonzero.
       *
       * @param cmp general purpose register. May not be null, zero-register or stackpointer.
       * @param uimm6 Unsigned 6-bit bit index.
!      * @param label Can only handle 21-bit word-aligned offsets for now. May be unbound. Non null.
       */
      public void tbnz(Register cmp, int uimm6, Label label) {
          assert NumUtil.isUnsignedNbit(6, uimm6);
          if (label.isBound()) {
              int offset = label.position() - position();
--- 1453,1463 ----
      /**
       * Test a single bit and branch if the bit is nonzero.
       *
       * @param cmp general purpose register. May not be null, zero-register or stackpointer.
       * @param uimm6 Unsigned 6-bit bit index.
!      * @param label Can only handle 16-bit word-aligned offsets for now. May be unbound. Non null.
       */
      public void tbnz(Register cmp, int uimm6, Label label) {
          assert NumUtil.isUnsignedNbit(6, uimm6);
          if (label.isBound()) {
              int offset = label.position() - position();
*** 1470,1480 ****
      /**
       * Test a single bit and branch if the bit is zero.
       *
       * @param cmp general purpose register. May not be null, zero-register or stackpointer.
       * @param uimm6 Unsigned 6-bit bit index.
!      * @param label Can only handle 21-bit word-aligned offsets for now. May be unbound. Non null.
       */
      public void tbz(Register cmp, int uimm6, Label label) {
          assert NumUtil.isUnsignedNbit(6, uimm6);
          if (label.isBound()) {
              int offset = label.position() - position();
--- 1473,1483 ----
      /**
       * Test a single bit and branch if the bit is zero.
       *
       * @param cmp general purpose register. May not be null, zero-register or stackpointer.
       * @param uimm6 Unsigned 6-bit bit index.
!      * @param label Can only handle 16-bit word-aligned offsets for now. May be unbound. Non null.
       */
      public void tbz(Register cmp, int uimm6, Label label) {
          assert NumUtil.isUnsignedNbit(6, uimm6);
          if (label.isBound()) {
              int offset = label.position() - position();
*** 1679,1688 ****
--- 1682,1694 ----
              case BRANCH_BIT_ZERO: {
                  int information = instruction >>> PatchLabelKind.INFORMATION_OFFSET;
                  int sizeEncoding = information & NumUtil.getNbitNumberInt(6);
                  int regEncoding = information >>> 6;
                  Register reg = AArch64.cpuRegisters.get(regEncoding);
+                 if (!NumUtil.isSignedNbit(16, branchOffset)) {
+                     throw new BranchTargetOutOfBoundsException(true, "Branch target %d out of bounds", branchOffset);
+                 }
                  switch (type) {
                      case BRANCH_BIT_NONZERO:
                          super.tbnz(reg, sizeEncoding, branchOffset, branch);
                          break;
                      case BRANCH_BIT_ZERO: