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src/jdk.internal.vm.compiler/share/classes/org.graalvm.compiler.asm.amd64/src/org/graalvm/compiler/asm/amd64/AMD64Assembler.java
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*** 681,691 ****
asm.emitModRM(ext, dst);
int immPos = asm.position();
emitImmediate(asm, size, imm);
int nextInsnPos = asm.position();
if (annotateImm && asm.codePatchingAnnotationConsumer != null) {
! asm.codePatchingAnnotationConsumer.accept(new ImmediateOperandAnnotation(insnPos, immPos, nextInsnPos - immPos, nextInsnPos));
}
}
public final void emit(AMD64Assembler asm, OperandSize size, AMD64Address dst, int imm) {
emit(asm, size, dst, imm, false);
--- 681,691 ----
asm.emitModRM(ext, dst);
int immPos = asm.position();
emitImmediate(asm, size, imm);
int nextInsnPos = asm.position();
if (annotateImm && asm.codePatchingAnnotationConsumer != null) {
! asm.codePatchingAnnotationConsumer.accept(new OperandDataAnnotation(insnPos, immPos, nextInsnPos - immPos, nextInsnPos));
}
}
public final void emit(AMD64Assembler asm, OperandSize size, AMD64Address dst, int imm) {
emit(asm, size, dst, imm, false);
*** 698,708 ****
asm.emitOperandHelper(ext, dst, immediateSize(size));
int immPos = asm.position();
emitImmediate(asm, size, imm);
int nextInsnPos = asm.position();
if (annotateImm && asm.codePatchingAnnotationConsumer != null) {
! asm.codePatchingAnnotationConsumer.accept(new ImmediateOperandAnnotation(insnPos, immPos, nextInsnPos - immPos, nextInsnPos));
}
}
}
/**
--- 698,708 ----
asm.emitOperandHelper(ext, dst, immediateSize(size));
int immPos = asm.position();
emitImmediate(asm, size, imm);
int nextInsnPos = asm.position();
if (annotateImm && asm.codePatchingAnnotationConsumer != null) {
! asm.codePatchingAnnotationConsumer.accept(new OperandDataAnnotation(insnPos, immPos, nextInsnPos - immPos, nextInsnPos));
}
}
}
/**
*** 2021,2031 ****
emitByte(0xB8 + encode(dst));
int immPos = position();
emitInt(imm32);
int nextInsnPos = position();
if (annotateImm && codePatchingAnnotationConsumer != null) {
! codePatchingAnnotationConsumer.accept(new ImmediateOperandAnnotation(insnPos, immPos, nextInsnPos - immPos, nextInsnPos));
}
}
public final void movl(Register dst, Register src) {
prefix(dst, src);
--- 2021,2031 ----
emitByte(0xB8 + encode(dst));
int immPos = position();
emitInt(imm32);
int nextInsnPos = position();
if (annotateImm && codePatchingAnnotationConsumer != null) {
! codePatchingAnnotationConsumer.accept(new OperandDataAnnotation(insnPos, immPos, nextInsnPos - immPos, nextInsnPos));
}
}
public final void movl(Register dst, Register src) {
prefix(dst, src);
*** 2199,2212 ****
public final void mulss(Register dst, Register src) {
SSEOp.MUL.emit(this, SS, dst, src);
}
public final void movswl(Register dst, AMD64Address src) {
! prefix(src, dst);
! emitByte(0x0F);
! emitByte(0xBF);
! emitOperandHelper(dst, src, 0);
}
public final void movw(AMD64Address dst, int imm16) {
emitByte(0x66); // switch to 16-bit mode
prefix(dst);
--- 2199,2213 ----
public final void mulss(Register dst, Register src) {
SSEOp.MUL.emit(this, SS, dst, src);
}
public final void movswl(Register dst, AMD64Address src) {
! AMD64RMOp.MOVSX.emit(this, DWORD, dst, src);
! }
!
! public final void movswq(Register dst, AMD64Address src) {
! AMD64RMOp.MOVSX.emit(this, QWORD, dst, src);
}
public final void movw(AMD64Address dst, int imm16) {
emitByte(0x66); // switch to 16-bit mode
prefix(dst);
*** 2220,2229 ****
--- 2221,2237 ----
prefix(dst, src);
emitByte(0x89);
emitOperandHelper(src, dst, 0);
}
+ public final void movw(Register dst, AMD64Address src) {
+ emitByte(0x66);
+ prefix(src, dst);
+ emitByte(0x8B);
+ emitOperandHelper(dst, src, 0);
+ }
+
public final void movzbl(Register dst, AMD64Address src) {
prefix(src, dst);
emitByte(0x0F);
emitByte(0xB6);
emitOperandHelper(dst, src, 0);
*** 2235,2249 ****
public final void movzbq(Register dst, Register src) {
AMD64RMOp.MOVZXB.emit(this, QWORD, dst, src);
}
public final void movzwl(Register dst, AMD64Address src) {
! prefix(src, dst);
! emitByte(0x0F);
! emitByte(0xB7);
! emitOperandHelper(dst, src, 0);
}
public final void negl(Register dst) {
NEG.emit(this, DWORD, dst);
}
--- 2243,2262 ----
public final void movzbq(Register dst, Register src) {
AMD64RMOp.MOVZXB.emit(this, QWORD, dst, src);
}
+ public final void movzbq(Register dst, AMD64Address src) {
+ AMD64RMOp.MOVZXB.emit(this, QWORD, dst, src);
+ }
+
public final void movzwl(Register dst, AMD64Address src) {
! AMD64RMOp.MOVZX.emit(this, DWORD, dst, src);
! }
!
! public final void movzwq(Register dst, AMD64Address src) {
! AMD64RMOp.MOVZX.emit(this, QWORD, dst, src);
}
public final void negl(Register dst) {
NEG.emit(this, DWORD, dst);
}
*** 2555,2574 ****
simdPrefix(dst, Register.None, src, PD, P_0F, false);
emitByte(0xD7);
emitModRM(dst, src);
}
! // Insn: VPMOVZXBW xmm1, xmm2/m64
!
! public final void pmovzxbw(Register dst, AMD64Address src) {
assert supports(CPUFeature.SSE4_1);
assert inRC(XMM, dst);
simdPrefix(dst, Register.None, src, PD, P_0F38, false);
! emitByte(0x30);
emitOperandHelper(dst, src, 0);
}
public final void pmovzxbw(Register dst, Register src) {
assert supports(CPUFeature.SSE4_1);
assert inRC(XMM, dst) && inRC(XMM, src);
simdPrefix(dst, Register.None, src, PD, P_0F38, false);
emitByte(0x30);
--- 2568,2634 ----
simdPrefix(dst, Register.None, src, PD, P_0F, false);
emitByte(0xD7);
emitModRM(dst, src);
}
! private void pmovSZx(Register dst, AMD64Address src, int op) {
assert supports(CPUFeature.SSE4_1);
assert inRC(XMM, dst);
simdPrefix(dst, Register.None, src, PD, P_0F38, false);
! emitByte(op);
emitOperandHelper(dst, src, 0);
}
+ public final void pmovsxbw(Register dst, AMD64Address src) {
+ pmovSZx(dst, src, 0x20);
+ }
+
+ public final void pmovsxbd(Register dst, AMD64Address src) {
+ pmovSZx(dst, src, 0x21);
+ }
+
+ public final void pmovsxbq(Register dst, AMD64Address src) {
+ pmovSZx(dst, src, 0x22);
+ }
+
+ public final void pmovsxwd(Register dst, AMD64Address src) {
+ pmovSZx(dst, src, 0x23);
+ }
+
+ public final void pmovsxwq(Register dst, AMD64Address src) {
+ pmovSZx(dst, src, 0x24);
+ }
+
+ public final void pmovsxdq(Register dst, AMD64Address src) {
+ pmovSZx(dst, src, 0x25);
+ }
+
+ // Insn: VPMOVZXBW xmm1, xmm2/m64
+ public final void pmovzxbw(Register dst, AMD64Address src) {
+ pmovSZx(dst, src, 0x30);
+ }
+
+ public final void pmovzxbd(Register dst, AMD64Address src) {
+ pmovSZx(dst, src, 0x31);
+ }
+
+ public final void pmovzxbq(Register dst, AMD64Address src) {
+ pmovSZx(dst, src, 0x32);
+ }
+
+ public final void pmovzxwd(Register dst, AMD64Address src) {
+ pmovSZx(dst, src, 0x33);
+ }
+
+ public final void pmovzxwq(Register dst, AMD64Address src) {
+ pmovSZx(dst, src, 0x34);
+ }
+
+ public final void pmovzxdq(Register dst, AMD64Address src) {
+ pmovSZx(dst, src, 0x35);
+ }
+
public final void pmovzxbw(Register dst, Register src) {
assert supports(CPUFeature.SSE4_1);
assert inRC(XMM, dst) && inRC(XMM, src);
simdPrefix(dst, Register.None, src, PD, P_0F38, false);
emitByte(0x30);
*** 2879,2888 ****
--- 2939,2952 ----
public final void xorl(Register dst, Register src) {
XOR.rmOp.emit(this, DWORD, dst, src);
}
+ public final void xorq(Register dst, Register src) {
+ XOR.rmOp.emit(this, QWORD, dst, src);
+ }
+
public final void xorpd(Register dst, Register src) {
SSEOp.XOR.emit(this, PD, dst, src);
}
public final void xorps(Register dst, Register src) {
*** 3043,3053 ****
emitByte(0xB8 + encode(dst));
int immPos = position();
emitLong(imm64);
int nextInsnPos = position();
if (annotateImm && codePatchingAnnotationConsumer != null) {
! codePatchingAnnotationConsumer.accept(new ImmediateOperandAnnotation(insnPos, immPos, nextInsnPos - immPos, nextInsnPos));
}
}
public final void movslq(Register dst, int imm32) {
prefixq(dst);
--- 3107,3117 ----
emitByte(0xB8 + encode(dst));
int immPos = position();
emitLong(imm64);
int nextInsnPos = position();
if (annotateImm && codePatchingAnnotationConsumer != null) {
! codePatchingAnnotationConsumer.accept(new OperandDataAnnotation(insnPos, immPos, nextInsnPos - immPos, nextInsnPos));
}
}
public final void movslq(Register dst, int imm32) {
prefixq(dst);
*** 3187,3196 ****
--- 3251,3273 ----
emitByte(0xD3);
// Unsigned divide dst by 2, CL times.
emitModRM(5, dst);
}
+ public final void sarq(Register dst, int imm8) {
+ assert isShiftCount(imm8 >> 1) : "illegal shift count";
+ prefixq(dst);
+ if (imm8 == 1) {
+ emitByte(0xD1);
+ emitModRM(7, dst);
+ } else {
+ emitByte(0xC1);
+ emitModRM(7, dst);
+ emitByte(imm8);
+ }
+ }
+
public final void sbbq(Register dst, Register src) {
SBB.rmOp.emit(this, QWORD, dst, src);
}
public final void subq(Register dst, int imm32) {
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