120 this.y = y;
121 }
122
123 @Override
124 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
125 AllocatableValue input;
126 if (sameRegister(result, y)) {
127 input = x;
128 } else {
129 AMD64Move.move(crb, masm, result, x);
130 input = y;
131 }
132
133 if (isRegister(input)) {
134 opcode.emit(masm, size, asRegister(result), asRegister(input));
135 } else {
136 assert isStackSlot(input);
137 opcode.emit(masm, size, asRegister(result), (AMD64Address) crb.asAddress(input));
138 }
139 }
140 }
141
142 /**
143 * Instruction that has one {@link AllocatableValue} operand and one 32-bit immediate operand.
144 */
145 public static class ConstOp extends AMD64LIRInstruction {
146 public static final LIRInstructionClass<ConstOp> TYPE = LIRInstructionClass.create(ConstOp.class);
147
148 @Opcode private final AMD64MIOp opcode;
149 private final OperandSize size;
150
151 @Def({REG, HINT}) protected AllocatableValue result;
152 @Use({REG}) protected AllocatableValue x;
153 private final int y;
154
155 public ConstOp(AMD64BinaryArithmetic opcode, OperandSize size, AllocatableValue result, AllocatableValue x, int y) {
156 this(opcode.getMIOpcode(size, NumUtil.isByte(y)), size, result, x, y);
157 }
158
159 public ConstOp(AMD64MIOp opcode, OperandSize size, AllocatableValue result, AllocatableValue x, int y) {
246 if (state != null) {
247 crb.recordImplicitException(masm.position(), state);
248 }
249 opcode.emit(masm, size, asRegister(result), y.toAddress());
250 }
251
252 @Override
253 public void verify() {
254 super.verify();
255 assert differentRegisters(result, y) || sameRegister(x, y);
256 }
257
258 @Override
259 public boolean makeNullCheckFor(Value value, LIRFrameState nullCheckState, int implicitNullCheckLimit) {
260 if (state == null && y.isValidImplicitNullCheckFor(value, implicitNullCheckLimit)) {
261 state = nullCheckState;
262 return true;
263 }
264 return false;
265 }
266 }
267
268 /**
269 * Instruction with a separate result operand, one {@link AllocatableValue} input and one 32-bit
270 * immediate input.
271 */
272 public static class RMIOp extends AMD64LIRInstruction {
273 public static final LIRInstructionClass<RMIOp> TYPE = LIRInstructionClass.create(RMIOp.class);
274
275 @Opcode private final AMD64RMIOp opcode;
276 private final OperandSize size;
277
278 @Def({REG}) protected AllocatableValue result;
279 @Use({REG, STACK}) protected AllocatableValue x;
280 private final int y;
281
282 public RMIOp(AMD64RMIOp opcode, OperandSize size, AllocatableValue result, AllocatableValue x, int y) {
283 super(TYPE);
284 this.opcode = opcode;
285 this.size = size;
|
120 this.y = y;
121 }
122
123 @Override
124 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
125 AllocatableValue input;
126 if (sameRegister(result, y)) {
127 input = x;
128 } else {
129 AMD64Move.move(crb, masm, result, x);
130 input = y;
131 }
132
133 if (isRegister(input)) {
134 opcode.emit(masm, size, asRegister(result), asRegister(input));
135 } else {
136 assert isStackSlot(input);
137 opcode.emit(masm, size, asRegister(result), (AMD64Address) crb.asAddress(input));
138 }
139 }
140
141 public AMD64RMOp getOpcode() {
142 return opcode;
143 }
144
145 }
146
147 /**
148 * Instruction that has one {@link AllocatableValue} operand and one 32-bit immediate operand.
149 */
150 public static class ConstOp extends AMD64LIRInstruction {
151 public static final LIRInstructionClass<ConstOp> TYPE = LIRInstructionClass.create(ConstOp.class);
152
153 @Opcode private final AMD64MIOp opcode;
154 private final OperandSize size;
155
156 @Def({REG, HINT}) protected AllocatableValue result;
157 @Use({REG}) protected AllocatableValue x;
158 private final int y;
159
160 public ConstOp(AMD64BinaryArithmetic opcode, OperandSize size, AllocatableValue result, AllocatableValue x, int y) {
161 this(opcode.getMIOpcode(size, NumUtil.isByte(y)), size, result, x, y);
162 }
163
164 public ConstOp(AMD64MIOp opcode, OperandSize size, AllocatableValue result, AllocatableValue x, int y) {
251 if (state != null) {
252 crb.recordImplicitException(masm.position(), state);
253 }
254 opcode.emit(masm, size, asRegister(result), y.toAddress());
255 }
256
257 @Override
258 public void verify() {
259 super.verify();
260 assert differentRegisters(result, y) || sameRegister(x, y);
261 }
262
263 @Override
264 public boolean makeNullCheckFor(Value value, LIRFrameState nullCheckState, int implicitNullCheckLimit) {
265 if (state == null && y.isValidImplicitNullCheckFor(value, implicitNullCheckLimit)) {
266 state = nullCheckState;
267 return true;
268 }
269 return false;
270 }
271
272 public AMD64RMOp getOpcode() {
273 return opcode;
274 }
275
276 }
277
278 /**
279 * Instruction with a separate result operand, one {@link AllocatableValue} input and one 32-bit
280 * immediate input.
281 */
282 public static class RMIOp extends AMD64LIRInstruction {
283 public static final LIRInstructionClass<RMIOp> TYPE = LIRInstructionClass.create(RMIOp.class);
284
285 @Opcode private final AMD64RMIOp opcode;
286 private final OperandSize size;
287
288 @Def({REG}) protected AllocatableValue result;
289 @Use({REG, STACK}) protected AllocatableValue x;
290 private final int y;
291
292 public RMIOp(AMD64RMIOp opcode, OperandSize size, AllocatableValue result, AllocatableValue x, int y) {
293 super(TYPE);
294 this.opcode = opcode;
295 this.size = size;
|