1 /* 2 * Copyright (c) 2019, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 */ 23 24 25 package org.graalvm.compiler.lir.amd64; 26 27 import static jdk.vm.ci.code.ValueUtil.asRegister; 28 import static jdk.vm.ci.code.ValueUtil.isRegister; 29 import static jdk.vm.ci.code.ValueUtil.isStackSlot; 30 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.HINT; 31 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.REG; 32 import static org.graalvm.compiler.lir.LIRInstruction.OperandFlag.STACK; 33 34 import org.graalvm.compiler.asm.amd64.AMD64Address; 35 import org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRVMOp; 36 import org.graalvm.compiler.asm.amd64.AMD64MacroAssembler; 37 import org.graalvm.compiler.asm.amd64.AVXKind.AVXSize; 38 import org.graalvm.compiler.lir.LIRInstructionClass; 39 import org.graalvm.compiler.lir.Opcode; 40 import org.graalvm.compiler.lir.asm.CompilationResultBuilder; 41 42 import jdk.vm.ci.meta.AllocatableValue; 43 44 /** 45 * AMD64 LIR instructions that have three inputs and one output. 46 */ 47 public class AMD64Ternary { 48 49 /** 50 * Instruction that has two {@link AllocatableValue} operands. 51 */ 52 public static class ThreeOp extends AMD64LIRInstruction { 53 public static final LIRInstructionClass<ThreeOp> TYPE = LIRInstructionClass.create(ThreeOp.class); 54 55 @Opcode private final VexRVMOp opcode; 56 private final AVXSize size; 57 58 @Def({REG, HINT}) protected AllocatableValue result; 59 @Use({REG}) protected AllocatableValue x; 60 /** 61 * This argument must be Alive to ensure that result and y are not assigned to the same 62 * register, which would break the code generation by destroying y too early. 63 */ 64 @Alive({REG}) protected AllocatableValue y; 65 @Alive({REG, STACK}) protected AllocatableValue z; 66 67 public ThreeOp(VexRVMOp opcode, AVXSize size, AllocatableValue result, AllocatableValue x, AllocatableValue y, AllocatableValue z) { 68 super(TYPE); 69 this.opcode = opcode; 70 this.size = size; 71 72 this.result = result; 73 this.x = x; 74 this.y = y; 75 this.z = z; 76 } 77 78 @Override 79 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) { 80 AMD64Move.move(crb, masm, result, x); 81 if (isRegister(z)) { 82 opcode.emit(masm, size, asRegister(result), asRegister(y), asRegister(z)); 83 } else { 84 assert isStackSlot(z); 85 opcode.emit(masm, size, asRegister(result), asRegister(y), (AMD64Address) crb.asAddress(z)); 86 } 87 } 88 } 89 }