1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc_interface/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/cardTableModRefBS.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "prims/methodHandles.hpp"
35 #include "runtime/biasedLocking.hpp"
36 #include "runtime/interfaceSupport.hpp"
37 #include "runtime/objectMonitor.hpp"
38 #include "runtime/os.hpp"
39 #include "runtime/sharedRuntime.hpp"
40 #include "runtime/stubRoutines.hpp"
41 #include "utilities/macros.hpp"
42 #if INCLUDE_ALL_GCS
43 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
44 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
45 #include "gc_implementation/g1/heapRegion.hpp"
46 #endif // INCLUDE_ALL_GCS
47
48 #ifdef PRODUCT
49 #define BLOCK_COMMENT(str) /* nothing */
50 #define STOP(error) stop(error)
51 #else
52 #define BLOCK_COMMENT(str) block_comment(str)
53 #define STOP(error) block_comment(error); stop(error)
54 #endif
55
56 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
57
58 PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC
59
60 #ifdef ASSERT
61 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
62 #endif
63
64 static Assembler::Condition reverse[] = {
65 Assembler::noOverflow /* overflow = 0x0 */ ,
66 Assembler::overflow /* noOverflow = 0x1 */ ,
67 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
68 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
69 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
70 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
71 Assembler::above /* belowEqual = 0x6 */ ,
72 Assembler::belowEqual /* above = 0x7 */ ,
73 Assembler::positive /* negative = 0x8 */ ,
74 Assembler::negative /* positive = 0x9 */ ,
75 Assembler::noParity /* parity = 0xa */ ,
76 Assembler::parity /* noParity = 0xb */ ,
77 Assembler::greaterEqual /* less = 0xc */ ,
78 Assembler::less /* greaterEqual = 0xd */ ,
79 Assembler::greater /* lessEqual = 0xe */ ,
80 Assembler::lessEqual /* greater = 0xf, */
81
82 };
83
84
85 // Implementation of MacroAssembler
86
87 // First all the versions that have distinct versions depending on 32/64 bit
88 // Unless the difference is trivial (1 line or so).
89
90 #ifndef _LP64
91
92 // 32bit versions
93
94 Address MacroAssembler::as_Address(AddressLiteral adr) {
95 return Address(adr.target(), adr.rspec());
96 }
97
98 Address MacroAssembler::as_Address(ArrayAddress adr) {
99 return Address::make_array(adr);
100 }
101
102 void MacroAssembler::call_VM_leaf_base(address entry_point,
103 int number_of_arguments) {
104 call(RuntimeAddress(entry_point));
105 increment(rsp, number_of_arguments * wordSize);
106 }
107
108 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
109 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
110 }
111
112 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
114 }
115
116 void MacroAssembler::cmpoop(Address src1, jobject obj) {
117 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
118 }
119
120 void MacroAssembler::cmpoop(Register src1, jobject obj) {
121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
122 }
123
124 void MacroAssembler::extend_sign(Register hi, Register lo) {
125 // According to Intel Doc. AP-526, "Integer Divide", p.18.
126 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
127 cdql();
128 } else {
129 movl(hi, lo);
130 sarl(hi, 31);
131 }
132 }
133
134 void MacroAssembler::jC2(Register tmp, Label& L) {
135 // set parity bit if FPU flag C2 is set (via rax)
136 save_rax(tmp);
137 fwait(); fnstsw_ax();
138 sahf();
139 restore_rax(tmp);
140 // branch
141 jcc(Assembler::parity, L);
142 }
143
144 void MacroAssembler::jnC2(Register tmp, Label& L) {
145 // set parity bit if FPU flag C2 is set (via rax)
146 save_rax(tmp);
147 fwait(); fnstsw_ax();
148 sahf();
149 restore_rax(tmp);
150 // branch
151 jcc(Assembler::noParity, L);
152 }
153
154 // 32bit can do a case table jump in one instruction but we no longer allow the base
155 // to be installed in the Address class
156 void MacroAssembler::jump(ArrayAddress entry) {
157 jmp(as_Address(entry));
158 }
159
160 // Note: y_lo will be destroyed
161 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
162 // Long compare for Java (semantics as described in JVM spec.)
163 Label high, low, done;
164
165 cmpl(x_hi, y_hi);
166 jcc(Assembler::less, low);
167 jcc(Assembler::greater, high);
168 // x_hi is the return register
169 xorl(x_hi, x_hi);
170 cmpl(x_lo, y_lo);
171 jcc(Assembler::below, low);
172 jcc(Assembler::equal, done);
173
174 bind(high);
175 xorl(x_hi, x_hi);
176 increment(x_hi);
177 jmp(done);
178
179 bind(low);
180 xorl(x_hi, x_hi);
181 decrementl(x_hi);
182
183 bind(done);
184 }
185
186 void MacroAssembler::lea(Register dst, AddressLiteral src) {
187 mov_literal32(dst, (int32_t)src.target(), src.rspec());
188 }
189
190 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
191 // leal(dst, as_Address(adr));
192 // see note in movl as to why we must use a move
193 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
194 }
195
196 void MacroAssembler::leave() {
197 mov(rsp, rbp);
198 pop(rbp);
199 }
200
201 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
202 // Multiplication of two Java long values stored on the stack
203 // as illustrated below. Result is in rdx:rax.
204 //
205 // rsp ---> [ ?? ] \ \
206 // .... | y_rsp_offset |
207 // [ y_lo ] / (in bytes) | x_rsp_offset
208 // [ y_hi ] | (in bytes)
209 // .... |
210 // [ x_lo ] /
211 // [ x_hi ]
212 // ....
213 //
214 // Basic idea: lo(result) = lo(x_lo * y_lo)
215 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
216 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
217 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
218 Label quick;
219 // load x_hi, y_hi and check if quick
220 // multiplication is possible
221 movl(rbx, x_hi);
222 movl(rcx, y_hi);
223 movl(rax, rbx);
224 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
225 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
226 // do full multiplication
227 // 1st step
228 mull(y_lo); // x_hi * y_lo
229 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
230 // 2nd step
231 movl(rax, x_lo);
232 mull(rcx); // x_lo * y_hi
233 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
234 // 3rd step
235 bind(quick); // note: rbx, = 0 if quick multiply!
236 movl(rax, x_lo);
237 mull(y_lo); // x_lo * y_lo
238 addl(rdx, rbx); // correct hi(x_lo * y_lo)
239 }
240
241 void MacroAssembler::lneg(Register hi, Register lo) {
242 negl(lo);
243 adcl(hi, 0);
244 negl(hi);
245 }
246
247 void MacroAssembler::lshl(Register hi, Register lo) {
248 // Java shift left long support (semantics as described in JVM spec., p.305)
249 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
250 // shift value is in rcx !
251 assert(hi != rcx, "must not use rcx");
252 assert(lo != rcx, "must not use rcx");
253 const Register s = rcx; // shift count
254 const int n = BitsPerWord;
255 Label L;
256 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
257 cmpl(s, n); // if (s < n)
258 jcc(Assembler::less, L); // else (s >= n)
259 movl(hi, lo); // x := x << n
260 xorl(lo, lo);
261 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
262 bind(L); // s (mod n) < n
263 shldl(hi, lo); // x := x << s
264 shll(lo);
265 }
266
267
268 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
269 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
270 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
271 assert(hi != rcx, "must not use rcx");
272 assert(lo != rcx, "must not use rcx");
273 const Register s = rcx; // shift count
274 const int n = BitsPerWord;
275 Label L;
276 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
277 cmpl(s, n); // if (s < n)
278 jcc(Assembler::less, L); // else (s >= n)
279 movl(lo, hi); // x := x >> n
280 if (sign_extension) sarl(hi, 31);
281 else xorl(hi, hi);
282 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
283 bind(L); // s (mod n) < n
284 shrdl(lo, hi); // x := x >> s
285 if (sign_extension) sarl(hi);
286 else shrl(hi);
287 }
288
289 void MacroAssembler::movoop(Register dst, jobject obj) {
290 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
291 }
292
293 void MacroAssembler::movoop(Address dst, jobject obj) {
294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
295 }
296
297 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
298 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
299 }
300
301 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
303 }
304
305 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
306 // scratch register is not used,
307 // it is defined to match parameters of 64-bit version of this method.
308 if (src.is_lval()) {
309 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
310 } else {
311 movl(dst, as_Address(src));
312 }
313 }
314
315 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
316 movl(as_Address(dst), src);
317 }
318
319 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
320 movl(dst, as_Address(src));
321 }
322
323 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
324 void MacroAssembler::movptr(Address dst, intptr_t src) {
325 movl(dst, src);
326 }
327
328
329 void MacroAssembler::pop_callee_saved_registers() {
330 pop(rcx);
331 pop(rdx);
332 pop(rdi);
333 pop(rsi);
334 }
335
336 void MacroAssembler::pop_fTOS() {
337 fld_d(Address(rsp, 0));
338 addl(rsp, 2 * wordSize);
339 }
340
341 void MacroAssembler::push_callee_saved_registers() {
342 push(rsi);
343 push(rdi);
344 push(rdx);
345 push(rcx);
346 }
347
348 void MacroAssembler::push_fTOS() {
349 subl(rsp, 2 * wordSize);
350 fstp_d(Address(rsp, 0));
351 }
352
353
354 void MacroAssembler::pushoop(jobject obj) {
355 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
356 }
357
358 void MacroAssembler::pushklass(Metadata* obj) {
359 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
360 }
361
362 void MacroAssembler::pushptr(AddressLiteral src) {
363 if (src.is_lval()) {
364 push_literal32((int32_t)src.target(), src.rspec());
365 } else {
366 pushl(as_Address(src));
367 }
368 }
369
370 void MacroAssembler::set_word_if_not_zero(Register dst) {
371 xorl(dst, dst);
372 set_byte_if_not_zero(dst);
373 }
374
375 static void pass_arg0(MacroAssembler* masm, Register arg) {
376 masm->push(arg);
377 }
378
379 static void pass_arg1(MacroAssembler* masm, Register arg) {
380 masm->push(arg);
381 }
382
383 static void pass_arg2(MacroAssembler* masm, Register arg) {
384 masm->push(arg);
385 }
386
387 static void pass_arg3(MacroAssembler* masm, Register arg) {
388 masm->push(arg);
389 }
390
391 #ifndef PRODUCT
392 extern "C" void findpc(intptr_t x);
393 #endif
394
395 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
396 // In order to get locks to work, we need to fake a in_VM state
397 JavaThread* thread = JavaThread::current();
398 JavaThreadState saved_state = thread->thread_state();
399 thread->set_thread_state(_thread_in_vm);
400 if (ShowMessageBoxOnError) {
401 JavaThread* thread = JavaThread::current();
402 JavaThreadState saved_state = thread->thread_state();
403 thread->set_thread_state(_thread_in_vm);
404 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
405 ttyLocker ttyl;
406 BytecodeCounter::print();
407 }
408 // To see where a verify_oop failed, get $ebx+40/X for this frame.
409 // This is the value of eip which points to where verify_oop will return.
410 if (os::message_box(msg, "Execution stopped, print registers?")) {
411 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
412 BREAKPOINT;
413 }
414 } else {
415 ttyLocker ttyl;
416 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
417 }
418 // Don't assert holding the ttyLock
419 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
420 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
421 }
422
423 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
424 ttyLocker ttyl;
425 FlagSetting fs(Debugging, true);
426 tty->print_cr("eip = 0x%08x", eip);
427 #ifndef PRODUCT
428 if ((WizardMode || Verbose) && PrintMiscellaneous) {
429 tty->cr();
430 findpc(eip);
431 tty->cr();
432 }
433 #endif
434 #define PRINT_REG(rax) \
435 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
436 PRINT_REG(rax);
437 PRINT_REG(rbx);
438 PRINT_REG(rcx);
439 PRINT_REG(rdx);
440 PRINT_REG(rdi);
441 PRINT_REG(rsi);
442 PRINT_REG(rbp);
443 PRINT_REG(rsp);
444 #undef PRINT_REG
445 // Print some words near top of staack.
446 int* dump_sp = (int*) rsp;
447 for (int col1 = 0; col1 < 8; col1++) {
448 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
449 os::print_location(tty, *dump_sp++);
450 }
451 for (int row = 0; row < 16; row++) {
452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
453 for (int col = 0; col < 8; col++) {
454 tty->print(" 0x%08x", *dump_sp++);
455 }
456 tty->cr();
457 }
458 // Print some instructions around pc:
459 Disassembler::decode((address)eip-64, (address)eip);
460 tty->print_cr("--------");
461 Disassembler::decode((address)eip, (address)eip+32);
462 }
463
464 void MacroAssembler::stop(const char* msg) {
465 ExternalAddress message((address)msg);
466 // push address of message
467 pushptr(message.addr());
468 { Label L; call(L, relocInfo::none); bind(L); } // push eip
469 pusha(); // push registers
470 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
471 hlt();
472 }
473
474 void MacroAssembler::warn(const char* msg) {
475 push_CPU_state();
476
477 ExternalAddress message((address) msg);
478 // push address of message
479 pushptr(message.addr());
480
481 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
482 addl(rsp, wordSize); // discard argument
483 pop_CPU_state();
484 }
485
486 void MacroAssembler::print_state() {
487 { Label L; call(L, relocInfo::none); bind(L); } // push eip
488 pusha(); // push registers
489
490 push_CPU_state();
491 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
492 pop_CPU_state();
493
494 popa();
495 addl(rsp, wordSize);
496 }
497
498 #else // _LP64
499
500 // 64 bit versions
501
502 Address MacroAssembler::as_Address(AddressLiteral adr) {
503 // amd64 always does this as a pc-rel
504 // we can be absolute or disp based on the instruction type
505 // jmp/call are displacements others are absolute
506 assert(!adr.is_lval(), "must be rval");
507 assert(reachable(adr), "must be");
508 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
509
510 }
511
512 Address MacroAssembler::as_Address(ArrayAddress adr) {
513 AddressLiteral base = adr.base();
514 lea(rscratch1, base);
515 Address index = adr.index();
516 assert(index._disp == 0, "must not have disp"); // maybe it can?
517 Address array(rscratch1, index._index, index._scale, index._disp);
518 return array;
519 }
520
521 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
522 Label L, E;
523
524 #ifdef _WIN64
525 // Windows always allocates space for it's register args
526 assert(num_args <= 4, "only register arguments supported");
527 subq(rsp, frame::arg_reg_save_area_bytes);
528 #endif
529
530 // Align stack if necessary
531 testl(rsp, 15);
532 jcc(Assembler::zero, L);
533
534 subq(rsp, 8);
535 {
536 call(RuntimeAddress(entry_point));
537 }
538 addq(rsp, 8);
539 jmp(E);
540
541 bind(L);
542 {
543 call(RuntimeAddress(entry_point));
544 }
545
546 bind(E);
547
548 #ifdef _WIN64
549 // restore stack pointer
550 addq(rsp, frame::arg_reg_save_area_bytes);
551 #endif
552
553 }
554
555 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
556 assert(!src2.is_lval(), "should use cmpptr");
557
558 if (reachable(src2)) {
559 cmpq(src1, as_Address(src2));
560 } else {
561 lea(rscratch1, src2);
562 Assembler::cmpq(src1, Address(rscratch1, 0));
563 }
564 }
565
566 int MacroAssembler::corrected_idivq(Register reg) {
567 // Full implementation of Java ldiv and lrem; checks for special
568 // case as described in JVM spec., p.243 & p.271. The function
569 // returns the (pc) offset of the idivl instruction - may be needed
570 // for implicit exceptions.
571 //
572 // normal case special case
573 //
574 // input : rax: dividend min_long
575 // reg: divisor (may not be eax/edx) -1
576 //
577 // output: rax: quotient (= rax idiv reg) min_long
578 // rdx: remainder (= rax irem reg) 0
579 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
580 static const int64_t min_long = 0x8000000000000000;
581 Label normal_case, special_case;
582
583 // check for special case
584 cmp64(rax, ExternalAddress((address) &min_long));
585 jcc(Assembler::notEqual, normal_case);
586 xorl(rdx, rdx); // prepare rdx for possible special case (where
587 // remainder = 0)
588 cmpq(reg, -1);
589 jcc(Assembler::equal, special_case);
590
591 // handle normal case
592 bind(normal_case);
593 cdqq();
594 int idivq_offset = offset();
595 idivq(reg);
596
597 // normal and special case exit
598 bind(special_case);
599
600 return idivq_offset;
601 }
602
603 void MacroAssembler::decrementq(Register reg, int value) {
604 if (value == min_jint) { subq(reg, value); return; }
605 if (value < 0) { incrementq(reg, -value); return; }
606 if (value == 0) { ; return; }
607 if (value == 1 && UseIncDec) { decq(reg) ; return; }
608 /* else */ { subq(reg, value) ; return; }
609 }
610
611 void MacroAssembler::decrementq(Address dst, int value) {
612 if (value == min_jint) { subq(dst, value); return; }
613 if (value < 0) { incrementq(dst, -value); return; }
614 if (value == 0) { ; return; }
615 if (value == 1 && UseIncDec) { decq(dst) ; return; }
616 /* else */ { subq(dst, value) ; return; }
617 }
618
619 void MacroAssembler::incrementq(AddressLiteral dst) {
620 if (reachable(dst)) {
621 incrementq(as_Address(dst));
622 } else {
623 lea(rscratch1, dst);
624 incrementq(Address(rscratch1, 0));
625 }
626 }
627
628 void MacroAssembler::incrementq(Register reg, int value) {
629 if (value == min_jint) { addq(reg, value); return; }
630 if (value < 0) { decrementq(reg, -value); return; }
631 if (value == 0) { ; return; }
632 if (value == 1 && UseIncDec) { incq(reg) ; return; }
633 /* else */ { addq(reg, value) ; return; }
634 }
635
636 void MacroAssembler::incrementq(Address dst, int value) {
637 if (value == min_jint) { addq(dst, value); return; }
638 if (value < 0) { decrementq(dst, -value); return; }
639 if (value == 0) { ; return; }
640 if (value == 1 && UseIncDec) { incq(dst) ; return; }
641 /* else */ { addq(dst, value) ; return; }
642 }
643
644 // 32bit can do a case table jump in one instruction but we no longer allow the base
645 // to be installed in the Address class
646 void MacroAssembler::jump(ArrayAddress entry) {
647 lea(rscratch1, entry.base());
648 Address dispatch = entry.index();
649 assert(dispatch._base == noreg, "must be");
650 dispatch._base = rscratch1;
651 jmp(dispatch);
652 }
653
654 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
655 ShouldNotReachHere(); // 64bit doesn't use two regs
656 cmpq(x_lo, y_lo);
657 }
658
659 void MacroAssembler::lea(Register dst, AddressLiteral src) {
660 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
661 }
662
663 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
664 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
665 movptr(dst, rscratch1);
666 }
667
668 void MacroAssembler::leave() {
669 // %%% is this really better? Why not on 32bit too?
670 emit_int8((unsigned char)0xC9); // LEAVE
671 }
672
673 void MacroAssembler::lneg(Register hi, Register lo) {
674 ShouldNotReachHere(); // 64bit doesn't use two regs
675 negq(lo);
676 }
677
678 void MacroAssembler::movoop(Register dst, jobject obj) {
679 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
680 }
681
682 void MacroAssembler::movoop(Address dst, jobject obj) {
683 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
684 movq(dst, rscratch1);
685 }
686
687 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
688 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
689 }
690
691 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
692 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
693 movq(dst, rscratch1);
694 }
695
696 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
697 if (src.is_lval()) {
698 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
699 } else {
700 if (reachable(src)) {
701 movq(dst, as_Address(src));
702 } else {
703 lea(scratch, src);
704 movq(dst, Address(scratch, 0));
705 }
706 }
707 }
708
709 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
710 movq(as_Address(dst), src);
711 }
712
713 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
714 movq(dst, as_Address(src));
715 }
716
717 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
718 void MacroAssembler::movptr(Address dst, intptr_t src) {
719 mov64(rscratch1, src);
720 movq(dst, rscratch1);
721 }
722
723 // These are mostly for initializing NULL
724 void MacroAssembler::movptr(Address dst, int32_t src) {
725 movslq(dst, src);
726 }
727
728 void MacroAssembler::movptr(Register dst, int32_t src) {
729 mov64(dst, (intptr_t)src);
730 }
731
732 void MacroAssembler::pushoop(jobject obj) {
733 movoop(rscratch1, obj);
734 push(rscratch1);
735 }
736
737 void MacroAssembler::pushklass(Metadata* obj) {
738 mov_metadata(rscratch1, obj);
739 push(rscratch1);
740 }
741
742 void MacroAssembler::pushptr(AddressLiteral src) {
743 lea(rscratch1, src);
744 if (src.is_lval()) {
745 push(rscratch1);
746 } else {
747 pushq(Address(rscratch1, 0));
748 }
749 }
750
751 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
752 bool clear_pc) {
753 // we must set sp to zero to clear frame
754 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
755 // must clear fp, so that compiled frames are not confused; it is
756 // possible that we need it only for debugging
757 if (clear_fp) {
758 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
759 }
760
761 if (clear_pc) {
762 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
763 }
764 }
765
766 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
767 Register last_java_fp,
768 address last_java_pc) {
769 // determine last_java_sp register
770 if (!last_java_sp->is_valid()) {
771 last_java_sp = rsp;
772 }
773
774 // last_java_fp is optional
775 if (last_java_fp->is_valid()) {
776 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
777 last_java_fp);
778 }
779
780 // last_java_pc is optional
781 if (last_java_pc != NULL) {
782 Address java_pc(r15_thread,
783 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
784 lea(rscratch1, InternalAddress(last_java_pc));
785 movptr(java_pc, rscratch1);
786 }
787
788 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
789 }
790
791 static void pass_arg0(MacroAssembler* masm, Register arg) {
792 if (c_rarg0 != arg ) {
793 masm->mov(c_rarg0, arg);
794 }
795 }
796
797 static void pass_arg1(MacroAssembler* masm, Register arg) {
798 if (c_rarg1 != arg ) {
799 masm->mov(c_rarg1, arg);
800 }
801 }
802
803 static void pass_arg2(MacroAssembler* masm, Register arg) {
804 if (c_rarg2 != arg ) {
805 masm->mov(c_rarg2, arg);
806 }
807 }
808
809 static void pass_arg3(MacroAssembler* masm, Register arg) {
810 if (c_rarg3 != arg ) {
811 masm->mov(c_rarg3, arg);
812 }
813 }
814
815 void MacroAssembler::stop(const char* msg) {
816 address rip = pc();
817 pusha(); // get regs on stack
818 lea(c_rarg0, ExternalAddress((address) msg));
819 lea(c_rarg1, InternalAddress(rip));
820 movq(c_rarg2, rsp); // pass pointer to regs array
821 andq(rsp, -16); // align stack as required by ABI
822 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
823 hlt();
824 }
825
826 void MacroAssembler::warn(const char* msg) {
827 push(rbp);
828 movq(rbp, rsp);
829 andq(rsp, -16); // align stack as required by push_CPU_state and call
830 push_CPU_state(); // keeps alignment at 16 bytes
831 lea(c_rarg0, ExternalAddress((address) msg));
832 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
833 pop_CPU_state();
834 mov(rsp, rbp);
835 pop(rbp);
836 }
837
838 void MacroAssembler::print_state() {
839 address rip = pc();
840 pusha(); // get regs on stack
841 push(rbp);
842 movq(rbp, rsp);
843 andq(rsp, -16); // align stack as required by push_CPU_state and call
844 push_CPU_state(); // keeps alignment at 16 bytes
845
846 lea(c_rarg0, InternalAddress(rip));
847 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
848 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
849
850 pop_CPU_state();
851 mov(rsp, rbp);
852 pop(rbp);
853 popa();
854 }
855
856 #ifndef PRODUCT
857 extern "C" void findpc(intptr_t x);
858 #endif
859
860 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
861 // In order to get locks to work, we need to fake a in_VM state
862 if (ShowMessageBoxOnError) {
863 JavaThread* thread = JavaThread::current();
864 JavaThreadState saved_state = thread->thread_state();
865 thread->set_thread_state(_thread_in_vm);
866 #ifndef PRODUCT
867 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
868 ttyLocker ttyl;
869 BytecodeCounter::print();
870 }
871 #endif
872 // To see where a verify_oop failed, get $ebx+40/X for this frame.
873 // XXX correct this offset for amd64
874 // This is the value of eip which points to where verify_oop will return.
875 if (os::message_box(msg, "Execution stopped, print registers?")) {
876 print_state64(pc, regs);
877 BREAKPOINT;
878 assert(false, "start up GDB");
879 }
880 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
881 } else {
882 ttyLocker ttyl;
883 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
884 msg);
885 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
886 }
887 }
888
889 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
890 ttyLocker ttyl;
891 FlagSetting fs(Debugging, true);
892 tty->print_cr("rip = 0x%016lx", pc);
893 #ifndef PRODUCT
894 tty->cr();
895 findpc(pc);
896 tty->cr();
897 #endif
898 #define PRINT_REG(rax, value) \
899 { tty->print("%s = ", #rax); os::print_location(tty, value); }
900 PRINT_REG(rax, regs[15]);
901 PRINT_REG(rbx, regs[12]);
902 PRINT_REG(rcx, regs[14]);
903 PRINT_REG(rdx, regs[13]);
904 PRINT_REG(rdi, regs[8]);
905 PRINT_REG(rsi, regs[9]);
906 PRINT_REG(rbp, regs[10]);
907 PRINT_REG(rsp, regs[11]);
908 PRINT_REG(r8 , regs[7]);
909 PRINT_REG(r9 , regs[6]);
910 PRINT_REG(r10, regs[5]);
911 PRINT_REG(r11, regs[4]);
912 PRINT_REG(r12, regs[3]);
913 PRINT_REG(r13, regs[2]);
914 PRINT_REG(r14, regs[1]);
915 PRINT_REG(r15, regs[0]);
916 #undef PRINT_REG
917 // Print some words near top of staack.
918 int64_t* rsp = (int64_t*) regs[11];
919 int64_t* dump_sp = rsp;
920 for (int col1 = 0; col1 < 8; col1++) {
921 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
922 os::print_location(tty, *dump_sp++);
923 }
924 for (int row = 0; row < 25; row++) {
925 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
926 for (int col = 0; col < 4; col++) {
927 tty->print(" 0x%016lx", *dump_sp++);
928 }
929 tty->cr();
930 }
931 // Print some instructions around pc:
932 Disassembler::decode((address)pc-64, (address)pc);
933 tty->print_cr("--------");
934 Disassembler::decode((address)pc, (address)pc+32);
935 }
936
937 #endif // _LP64
938
939 // Now versions that are common to 32/64 bit
940
941 void MacroAssembler::addptr(Register dst, int32_t imm32) {
942 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
943 }
944
945 void MacroAssembler::addptr(Register dst, Register src) {
946 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
947 }
948
949 void MacroAssembler::addptr(Address dst, Register src) {
950 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
951 }
952
953 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
954 if (reachable(src)) {
955 Assembler::addsd(dst, as_Address(src));
956 } else {
957 lea(rscratch1, src);
958 Assembler::addsd(dst, Address(rscratch1, 0));
959 }
960 }
961
962 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
963 if (reachable(src)) {
964 addss(dst, as_Address(src));
965 } else {
966 lea(rscratch1, src);
967 addss(dst, Address(rscratch1, 0));
968 }
969 }
970
971 void MacroAssembler::align(int modulus) {
972 if (offset() % modulus != 0) {
973 nop(modulus - (offset() % modulus));
974 }
975 }
976
977 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
978 // Used in sign-masking with aligned address.
979 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
980 if (reachable(src)) {
981 Assembler::andpd(dst, as_Address(src));
982 } else {
983 lea(rscratch1, src);
984 Assembler::andpd(dst, Address(rscratch1, 0));
985 }
986 }
987
988 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
989 // Used in sign-masking with aligned address.
990 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
991 if (reachable(src)) {
992 Assembler::andps(dst, as_Address(src));
993 } else {
994 lea(rscratch1, src);
995 Assembler::andps(dst, Address(rscratch1, 0));
996 }
997 }
998
999 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1000 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1001 }
1002
1003 void MacroAssembler::atomic_incl(Address counter_addr) {
1004 if (os::is_MP())
1005 lock();
1006 incrementl(counter_addr);
1007 }
1008
1009 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1010 if (reachable(counter_addr)) {
1011 atomic_incl(as_Address(counter_addr));
1012 } else {
1013 lea(scr, counter_addr);
1014 atomic_incl(Address(scr, 0));
1015 }
1016 }
1017
1018 #ifdef _LP64
1019 void MacroAssembler::atomic_incq(Address counter_addr) {
1020 if (os::is_MP())
1021 lock();
1022 incrementq(counter_addr);
1023 }
1024
1025 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1026 if (reachable(counter_addr)) {
1027 atomic_incq(as_Address(counter_addr));
1028 } else {
1029 lea(scr, counter_addr);
1030 atomic_incq(Address(scr, 0));
1031 }
1032 }
1033 #endif
1034
1035 // Writes to stack successive pages until offset reached to check for
1036 // stack overflow + shadow pages. This clobbers tmp.
1037 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1038 movptr(tmp, rsp);
1039 // Bang stack for total size given plus shadow page size.
1040 // Bang one page at a time because large size can bang beyond yellow and
1041 // red zones.
1042 Label loop;
1043 bind(loop);
1044 movl(Address(tmp, (-os::vm_page_size())), size );
1045 subptr(tmp, os::vm_page_size());
1046 subl(size, os::vm_page_size());
1047 jcc(Assembler::greater, loop);
1048
1049 // Bang down shadow pages too.
1050 // At this point, (tmp-0) is the last address touched, so don't
1051 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1052 // was post-decremented.) Skip this address by starting at i=1, and
1053 // touch a few more pages below. N.B. It is important to touch all
1054 // the way down to and including i=StackShadowPages.
1055 for (int i = 1; i < StackShadowPages; i++) {
1056 // this could be any sized move but this is can be a debugging crumb
1057 // so the bigger the better.
1058 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1059 }
1060 }
1061
1062 int MacroAssembler::biased_locking_enter(Register lock_reg,
1063 Register obj_reg,
1064 Register swap_reg,
1065 Register tmp_reg,
1066 bool swap_reg_contains_mark,
1067 Label& done,
1068 Label* slow_case,
1069 BiasedLockingCounters* counters) {
1070 assert(UseBiasedLocking, "why call this otherwise?");
1071 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1072 LP64_ONLY( assert(tmp_reg != noreg, "tmp_reg must be supplied"); )
1073 bool need_tmp_reg = false;
1074 if (tmp_reg == noreg) {
1075 need_tmp_reg = true;
1076 tmp_reg = lock_reg;
1077 assert_different_registers(lock_reg, obj_reg, swap_reg);
1078 } else {
1079 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1080 }
1081 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1082 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1083 Address saved_mark_addr(lock_reg, 0);
1084
1085 if (PrintBiasedLockingStatistics && counters == NULL) {
1086 counters = BiasedLocking::counters();
1087 }
1088 // Biased locking
1089 // See whether the lock is currently biased toward our thread and
1090 // whether the epoch is still valid
1091 // Note that the runtime guarantees sufficient alignment of JavaThread
1092 // pointers to allow age to be placed into low bits
1093 // First check to see whether biasing is even enabled for this object
1094 Label cas_label;
1095 int null_check_offset = -1;
1096 if (!swap_reg_contains_mark) {
1097 null_check_offset = offset();
1098 movptr(swap_reg, mark_addr);
1099 }
1100 if (need_tmp_reg) {
1101 push(tmp_reg);
1102 }
1103 movptr(tmp_reg, swap_reg);
1104 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1105 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1106 if (need_tmp_reg) {
1107 pop(tmp_reg);
1108 }
1109 jcc(Assembler::notEqual, cas_label);
1110 // The bias pattern is present in the object's header. Need to check
1111 // whether the bias owner and the epoch are both still current.
1112 #ifndef _LP64
1113 // Note that because there is no current thread register on x86_32 we
1114 // need to store off the mark word we read out of the object to
1115 // avoid reloading it and needing to recheck invariants below. This
1116 // store is unfortunate but it makes the overall code shorter and
1117 // simpler.
1118 movptr(saved_mark_addr, swap_reg);
1119 #endif
1120 if (need_tmp_reg) {
1121 push(tmp_reg);
1122 }
1123 if (swap_reg_contains_mark) {
1124 null_check_offset = offset();
1125 }
1126 load_prototype_header(tmp_reg, obj_reg);
1127 #ifdef _LP64
1128 orptr(tmp_reg, r15_thread);
1129 xorptr(tmp_reg, swap_reg);
1130 Register header_reg = tmp_reg;
1131 #else
1132 xorptr(tmp_reg, swap_reg);
1133 get_thread(swap_reg);
1134 xorptr(swap_reg, tmp_reg);
1135 Register header_reg = swap_reg;
1136 #endif
1137 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1138 if (need_tmp_reg) {
1139 pop(tmp_reg);
1140 }
1141 if (counters != NULL) {
1142 cond_inc32(Assembler::zero,
1143 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1144 }
1145 jcc(Assembler::equal, done);
1146
1147 Label try_revoke_bias;
1148 Label try_rebias;
1149
1150 // At this point we know that the header has the bias pattern and
1151 // that we are not the bias owner in the current epoch. We need to
1152 // figure out more details about the state of the header in order to
1153 // know what operations can be legally performed on the object's
1154 // header.
1155
1156 // If the low three bits in the xor result aren't clear, that means
1157 // the prototype header is no longer biased and we have to revoke
1158 // the bias on this object.
1159 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1160 jccb(Assembler::notZero, try_revoke_bias);
1161
1162 // Biasing is still enabled for this data type. See whether the
1163 // epoch of the current bias is still valid, meaning that the epoch
1164 // bits of the mark word are equal to the epoch bits of the
1165 // prototype header. (Note that the prototype header's epoch bits
1166 // only change at a safepoint.) If not, attempt to rebias the object
1167 // toward the current thread. Note that we must be absolutely sure
1168 // that the current epoch is invalid in order to do this because
1169 // otherwise the manipulations it performs on the mark word are
1170 // illegal.
1171 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1172 jccb(Assembler::notZero, try_rebias);
1173
1174 // The epoch of the current bias is still valid but we know nothing
1175 // about the owner; it might be set or it might be clear. Try to
1176 // acquire the bias of the object using an atomic operation. If this
1177 // fails we will go in to the runtime to revoke the object's bias.
1178 // Note that we first construct the presumed unbiased header so we
1179 // don't accidentally blow away another thread's valid bias.
1180 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1181 andptr(swap_reg,
1182 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1183 if (need_tmp_reg) {
1184 push(tmp_reg);
1185 }
1186 #ifdef _LP64
1187 movptr(tmp_reg, swap_reg);
1188 orptr(tmp_reg, r15_thread);
1189 #else
1190 get_thread(tmp_reg);
1191 orptr(tmp_reg, swap_reg);
1192 #endif
1193 if (os::is_MP()) {
1194 lock();
1195 }
1196 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1197 if (need_tmp_reg) {
1198 pop(tmp_reg);
1199 }
1200 // If the biasing toward our thread failed, this means that
1201 // another thread succeeded in biasing it toward itself and we
1202 // need to revoke that bias. The revocation will occur in the
1203 // interpreter runtime in the slow case.
1204 if (counters != NULL) {
1205 cond_inc32(Assembler::zero,
1206 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1207 }
1208 if (slow_case != NULL) {
1209 jcc(Assembler::notZero, *slow_case);
1210 }
1211 jmp(done);
1212
1213 bind(try_rebias);
1214 // At this point we know the epoch has expired, meaning that the
1215 // current "bias owner", if any, is actually invalid. Under these
1216 // circumstances _only_, we are allowed to use the current header's
1217 // value as the comparison value when doing the cas to acquire the
1218 // bias in the current epoch. In other words, we allow transfer of
1219 // the bias from one thread to another directly in this situation.
1220 //
1221 // FIXME: due to a lack of registers we currently blow away the age
1222 // bits in this situation. Should attempt to preserve them.
1223 if (need_tmp_reg) {
1224 push(tmp_reg);
1225 }
1226 load_prototype_header(tmp_reg, obj_reg);
1227 #ifdef _LP64
1228 orptr(tmp_reg, r15_thread);
1229 #else
1230 get_thread(swap_reg);
1231 orptr(tmp_reg, swap_reg);
1232 movptr(swap_reg, saved_mark_addr);
1233 #endif
1234 if (os::is_MP()) {
1235 lock();
1236 }
1237 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1238 if (need_tmp_reg) {
1239 pop(tmp_reg);
1240 }
1241 // If the biasing toward our thread failed, then another thread
1242 // succeeded in biasing it toward itself and we need to revoke that
1243 // bias. The revocation will occur in the runtime in the slow case.
1244 if (counters != NULL) {
1245 cond_inc32(Assembler::zero,
1246 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1247 }
1248 if (slow_case != NULL) {
1249 jcc(Assembler::notZero, *slow_case);
1250 }
1251 jmp(done);
1252
1253 bind(try_revoke_bias);
1254 // The prototype mark in the klass doesn't have the bias bit set any
1255 // more, indicating that objects of this data type are not supposed
1256 // to be biased any more. We are going to try to reset the mark of
1257 // this object to the prototype value and fall through to the
1258 // CAS-based locking scheme. Note that if our CAS fails, it means
1259 // that another thread raced us for the privilege of revoking the
1260 // bias of this particular object, so it's okay to continue in the
1261 // normal locking code.
1262 //
1263 // FIXME: due to a lack of registers we currently blow away the age
1264 // bits in this situation. Should attempt to preserve them.
1265 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1266 if (need_tmp_reg) {
1267 push(tmp_reg);
1268 }
1269 load_prototype_header(tmp_reg, obj_reg);
1270 if (os::is_MP()) {
1271 lock();
1272 }
1273 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1274 if (need_tmp_reg) {
1275 pop(tmp_reg);
1276 }
1277 // Fall through to the normal CAS-based lock, because no matter what
1278 // the result of the above CAS, some thread must have succeeded in
1279 // removing the bias bit from the object's header.
1280 if (counters != NULL) {
1281 cond_inc32(Assembler::zero,
1282 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1283 }
1284
1285 bind(cas_label);
1286
1287 return null_check_offset;
1288 }
1289
1290 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1291 assert(UseBiasedLocking, "why call this otherwise?");
1292
1293 // Check for biased locking unlock case, which is a no-op
1294 // Note: we do not have to check the thread ID for two reasons.
1295 // First, the interpreter checks for IllegalMonitorStateException at
1296 // a higher level. Second, if the bias was revoked while we held the
1297 // lock, the object could not be rebiased toward another thread, so
1298 // the bias bit would be clear.
1299 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1300 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1301 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1302 jcc(Assembler::equal, done);
1303 }
1304
1305 #ifdef COMPILER2
1306
1307 #if INCLUDE_RTM_OPT
1308
1309 // Update rtm_counters based on abort status
1310 // input: abort_status
1311 // rtm_counters (RTMLockingCounters*)
1312 // flags are killed
1313 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1314
1315 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1316 if (PrintPreciseRTMLockingStatistics) {
1317 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1318 Label check_abort;
1319 testl(abort_status, (1<<i));
1320 jccb(Assembler::equal, check_abort);
1321 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1322 bind(check_abort);
1323 }
1324 }
1325 }
1326
1327 // Branch if (random & (count-1) != 0), count is 2^n
1328 // tmp, scr and flags are killed
1329 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1330 assert(tmp == rax, "");
1331 assert(scr == rdx, "");
1332 rdtsc(); // modifies EDX:EAX
1333 andptr(tmp, count-1);
1334 jccb(Assembler::notZero, brLabel);
1335 }
1336
1337 // Perform abort ratio calculation, set no_rtm bit if high ratio
1338 // input: rtm_counters_Reg (RTMLockingCounters* address)
1339 // tmpReg, rtm_counters_Reg and flags are killed
1340 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1341 Register rtm_counters_Reg,
1342 RTMLockingCounters* rtm_counters,
1343 Metadata* method_data) {
1344 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1345
1346 if (RTMLockingCalculationDelay > 0) {
1347 // Delay calculation
1348 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1349 testptr(tmpReg, tmpReg);
1350 jccb(Assembler::equal, L_done);
1351 }
1352 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1353 // Aborted transactions = abort_count * 100
1354 // All transactions = total_count * RTMTotalCountIncrRate
1355 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1356
1357 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1358 cmpptr(tmpReg, RTMAbortThreshold);
1359 jccb(Assembler::below, L_check_always_rtm2);
1360 imulptr(tmpReg, tmpReg, 100);
1361
1362 Register scrReg = rtm_counters_Reg;
1363 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1364 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1365 imulptr(scrReg, scrReg, RTMAbortRatio);
1366 cmpptr(tmpReg, scrReg);
1367 jccb(Assembler::below, L_check_always_rtm1);
1368 if (method_data != NULL) {
1369 // set rtm_state to "no rtm" in MDO
1370 mov_metadata(tmpReg, method_data);
1371 if (os::is_MP()) {
1372 lock();
1373 }
1374 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1375 }
1376 jmpb(L_done);
1377 bind(L_check_always_rtm1);
1378 // Reload RTMLockingCounters* address
1379 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1380 bind(L_check_always_rtm2);
1381 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1382 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1383 jccb(Assembler::below, L_done);
1384 if (method_data != NULL) {
1385 // set rtm_state to "always rtm" in MDO
1386 mov_metadata(tmpReg, method_data);
1387 if (os::is_MP()) {
1388 lock();
1389 }
1390 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1391 }
1392 bind(L_done);
1393 }
1394
1395 // Update counters and perform abort ratio calculation
1396 // input: abort_status_Reg
1397 // rtm_counters_Reg, flags are killed
1398 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1399 Register rtm_counters_Reg,
1400 RTMLockingCounters* rtm_counters,
1401 Metadata* method_data,
1402 bool profile_rtm) {
1403
1404 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1405 // update rtm counters based on rax value at abort
1406 // reads abort_status_Reg, updates flags
1407 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1408 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1409 if (profile_rtm) {
1410 // Save abort status because abort_status_Reg is used by following code.
1411 if (RTMRetryCount > 0) {
1412 push(abort_status_Reg);
1413 }
1414 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1415 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1416 // restore abort status
1417 if (RTMRetryCount > 0) {
1418 pop(abort_status_Reg);
1419 }
1420 }
1421 }
1422
1423 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1424 // inputs: retry_count_Reg
1425 // : abort_status_Reg
1426 // output: retry_count_Reg decremented by 1
1427 // flags are killed
1428 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1429 Label doneRetry;
1430 assert(abort_status_Reg == rax, "");
1431 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1432 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1433 // if reason is in 0x6 and retry count != 0 then retry
1434 andptr(abort_status_Reg, 0x6);
1435 jccb(Assembler::zero, doneRetry);
1436 testl(retry_count_Reg, retry_count_Reg);
1437 jccb(Assembler::zero, doneRetry);
1438 pause();
1439 decrementl(retry_count_Reg);
1440 jmp(retryLabel);
1441 bind(doneRetry);
1442 }
1443
1444 // Spin and retry if lock is busy,
1445 // inputs: box_Reg (monitor address)
1446 // : retry_count_Reg
1447 // output: retry_count_Reg decremented by 1
1448 // : clear z flag if retry count exceeded
1449 // tmp_Reg, scr_Reg, flags are killed
1450 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1451 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1452 Label SpinLoop, SpinExit, doneRetry;
1453 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1454
1455 testl(retry_count_Reg, retry_count_Reg);
1456 jccb(Assembler::zero, doneRetry);
1457 decrementl(retry_count_Reg);
1458 movptr(scr_Reg, RTMSpinLoopCount);
1459
1460 bind(SpinLoop);
1461 pause();
1462 decrementl(scr_Reg);
1463 jccb(Assembler::lessEqual, SpinExit);
1464 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1465 testptr(tmp_Reg, tmp_Reg);
1466 jccb(Assembler::notZero, SpinLoop);
1467
1468 bind(SpinExit);
1469 jmp(retryLabel);
1470 bind(doneRetry);
1471 incrementl(retry_count_Reg); // clear z flag
1472 }
1473
1474 // Use RTM for normal stack locks
1475 // Input: objReg (object to lock)
1476 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1477 Register retry_on_abort_count_Reg,
1478 RTMLockingCounters* stack_rtm_counters,
1479 Metadata* method_data, bool profile_rtm,
1480 Label& DONE_LABEL, Label& IsInflated) {
1481 assert(UseRTMForStackLocks, "why call this otherwise?");
1482 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1483 assert(tmpReg == rax, "");
1484 assert(scrReg == rdx, "");
1485 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1486
1487 if (RTMRetryCount > 0) {
1488 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1489 bind(L_rtm_retry);
1490 }
1491 movptr(tmpReg, Address(objReg, 0));
1492 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1493 jcc(Assembler::notZero, IsInflated);
1494
1495 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1496 Label L_noincrement;
1497 if (RTMTotalCountIncrRate > 1) {
1498 // tmpReg, scrReg and flags are killed
1499 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1500 }
1501 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1502 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1503 bind(L_noincrement);
1504 }
1505 xbegin(L_on_abort);
1506 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1507 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1508 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1509 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1510
1511 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1512 if (UseRTMXendForLockBusy) {
1513 xend();
1514 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1515 jmp(L_decrement_retry);
1516 }
1517 else {
1518 xabort(0);
1519 }
1520 bind(L_on_abort);
1521 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1522 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1523 }
1524 bind(L_decrement_retry);
1525 if (RTMRetryCount > 0) {
1526 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1527 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1528 }
1529 }
1530
1531 // Use RTM for inflating locks
1532 // inputs: objReg (object to lock)
1533 // boxReg (on-stack box address (displaced header location) - KILLED)
1534 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1535 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1536 Register scrReg, Register retry_on_busy_count_Reg,
1537 Register retry_on_abort_count_Reg,
1538 RTMLockingCounters* rtm_counters,
1539 Metadata* method_data, bool profile_rtm,
1540 Label& DONE_LABEL) {
1541 assert(UseRTMLocking, "why call this otherwise?");
1542 assert(tmpReg == rax, "");
1543 assert(scrReg == rdx, "");
1544 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1545 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1546
1547 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1548 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1549 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1550
1551 if (RTMRetryCount > 0) {
1552 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1553 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1554 bind(L_rtm_retry);
1555 }
1556 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1557 Label L_noincrement;
1558 if (RTMTotalCountIncrRate > 1) {
1559 // tmpReg, scrReg and flags are killed
1560 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1561 }
1562 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1563 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1564 bind(L_noincrement);
1565 }
1566 xbegin(L_on_abort);
1567 movptr(tmpReg, Address(objReg, 0));
1568 movptr(tmpReg, Address(tmpReg, owner_offset));
1569 testptr(tmpReg, tmpReg);
1570 jcc(Assembler::zero, DONE_LABEL);
1571 if (UseRTMXendForLockBusy) {
1572 xend();
1573 jmp(L_decrement_retry);
1574 }
1575 else {
1576 xabort(0);
1577 }
1578 bind(L_on_abort);
1579 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1580 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1581 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1582 }
1583 if (RTMRetryCount > 0) {
1584 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1585 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1586 }
1587
1588 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1589 testptr(tmpReg, tmpReg) ;
1590 jccb(Assembler::notZero, L_decrement_retry) ;
1591
1592 // Appears unlocked - try to swing _owner from null to non-null.
1593 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1594 #ifdef _LP64
1595 Register threadReg = r15_thread;
1596 #else
1597 get_thread(scrReg);
1598 Register threadReg = scrReg;
1599 #endif
1600 if (os::is_MP()) {
1601 lock();
1602 }
1603 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1604
1605 if (RTMRetryCount > 0) {
1606 // success done else retry
1607 jccb(Assembler::equal, DONE_LABEL) ;
1608 bind(L_decrement_retry);
1609 // Spin and retry if lock is busy.
1610 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1611 }
1612 else {
1613 bind(L_decrement_retry);
1614 }
1615 }
1616
1617 #endif // INCLUDE_RTM_OPT
1618
1619 // Fast_Lock and Fast_Unlock used by C2
1620
1621 // Because the transitions from emitted code to the runtime
1622 // monitorenter/exit helper stubs are so slow it's critical that
1623 // we inline both the stack-locking fast-path and the inflated fast path.
1624 //
1625 // See also: cmpFastLock and cmpFastUnlock.
1626 //
1627 // What follows is a specialized inline transliteration of the code
1628 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1629 // another option would be to emit TrySlowEnter and TrySlowExit methods
1630 // at startup-time. These methods would accept arguments as
1631 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1632 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1633 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1634 // In practice, however, the # of lock sites is bounded and is usually small.
1635 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1636 // if the processor uses simple bimodal branch predictors keyed by EIP
1637 // Since the helper routines would be called from multiple synchronization
1638 // sites.
1639 //
1640 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1641 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1642 // to those specialized methods. That'd give us a mostly platform-independent
1643 // implementation that the JITs could optimize and inline at their pleasure.
1644 // Done correctly, the only time we'd need to cross to native could would be
1645 // to park() or unpark() threads. We'd also need a few more unsafe operators
1646 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1647 // (b) explicit barriers or fence operations.
1648 //
1649 // TODO:
1650 //
1651 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1652 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1653 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1654 // the lock operators would typically be faster than reifying Self.
1655 //
1656 // * Ideally I'd define the primitives as:
1657 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1658 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1659 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1660 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1661 // Furthermore the register assignments are overconstrained, possibly resulting in
1662 // sub-optimal code near the synchronization site.
1663 //
1664 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1665 // Alternately, use a better sp-proximity test.
1666 //
1667 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1668 // Either one is sufficient to uniquely identify a thread.
1669 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1670 //
1671 // * Intrinsify notify() and notifyAll() for the common cases where the
1672 // object is locked by the calling thread but the waitlist is empty.
1673 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1674 //
1675 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1676 // But beware of excessive branch density on AMD Opterons.
1677 //
1678 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1679 // or failure of the fast-path. If the fast-path fails then we pass
1680 // control to the slow-path, typically in C. In Fast_Lock and
1681 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1682 // will emit a conditional branch immediately after the node.
1683 // So we have branches to branches and lots of ICC.ZF games.
1684 // Instead, it might be better to have C2 pass a "FailureLabel"
1685 // into Fast_Lock and Fast_Unlock. In the case of success, control
1686 // will drop through the node. ICC.ZF is undefined at exit.
1687 // In the case of failure, the node will branch directly to the
1688 // FailureLabel
1689
1690
1691 // obj: object to lock
1692 // box: on-stack box address (displaced header location) - KILLED
1693 // rax,: tmp -- KILLED
1694 // scr: tmp -- KILLED
1695 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1696 Register scrReg, Register cx1Reg, Register cx2Reg,
1697 BiasedLockingCounters* counters,
1698 RTMLockingCounters* rtm_counters,
1699 RTMLockingCounters* stack_rtm_counters,
1700 Metadata* method_data,
1701 bool use_rtm, bool profile_rtm) {
1702 // Ensure the register assignents are disjoint
1703 assert(tmpReg == rax, "");
1704
1705 if (use_rtm) {
1706 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1707 } else {
1708 assert(cx1Reg == noreg, "");
1709 assert(cx2Reg == noreg, "");
1710 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1711 }
1712
1713 if (counters != NULL) {
1714 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1715 }
1716 if (EmitSync & 1) {
1717 // set box->dhw = markOopDesc::unused_mark()
1718 // Force all sync thru slow-path: slow_enter() and slow_exit()
1719 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1720 cmpptr (rsp, (int32_t)NULL_WORD);
1721 } else
1722 if (EmitSync & 2) {
1723 Label DONE_LABEL ;
1724 if (UseBiasedLocking) {
1725 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
1726 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1727 }
1728
1729 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1730 orptr (tmpReg, 0x1);
1731 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1732 if (os::is_MP()) {
1733 lock();
1734 }
1735 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1736 jccb(Assembler::equal, DONE_LABEL);
1737 // Recursive locking
1738 subptr(tmpReg, rsp);
1739 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1740 movptr(Address(boxReg, 0), tmpReg);
1741 bind(DONE_LABEL);
1742 } else {
1743 // Possible cases that we'll encounter in fast_lock
1744 // ------------------------------------------------
1745 // * Inflated
1746 // -- unlocked
1747 // -- Locked
1748 // = by self
1749 // = by other
1750 // * biased
1751 // -- by Self
1752 // -- by other
1753 // * neutral
1754 // * stack-locked
1755 // -- by self
1756 // = sp-proximity test hits
1757 // = sp-proximity test generates false-negative
1758 // -- by other
1759 //
1760
1761 Label IsInflated, DONE_LABEL;
1762
1763 // it's stack-locked, biased or neutral
1764 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1765 // order to reduce the number of conditional branches in the most common cases.
1766 // Beware -- there's a subtle invariant that fetch of the markword
1767 // at [FETCH], below, will never observe a biased encoding (*101b).
1768 // If this invariant is not held we risk exclusion (safety) failure.
1769 if (UseBiasedLocking && !UseOptoBiasInlining) {
1770 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1771 }
1772
1773 #if INCLUDE_RTM_OPT
1774 if (UseRTMForStackLocks && use_rtm) {
1775 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1776 stack_rtm_counters, method_data, profile_rtm,
1777 DONE_LABEL, IsInflated);
1778 }
1779 #endif // INCLUDE_RTM_OPT
1780
1781 movptr(tmpReg, Address(objReg, 0)); // [FETCH]
1782 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1783 jccb(Assembler::notZero, IsInflated);
1784
1785 // Attempt stack-locking ...
1786 orptr (tmpReg, markOopDesc::unlocked_value);
1787 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1788 if (os::is_MP()) {
1789 lock();
1790 }
1791 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1792 if (counters != NULL) {
1793 cond_inc32(Assembler::equal,
1794 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1795 }
1796 jcc(Assembler::equal, DONE_LABEL); // Success
1797
1798 // Recursive locking.
1799 // The object is stack-locked: markword contains stack pointer to BasicLock.
1800 // Locked by current thread if difference with current SP is less than one page.
1801 subptr(tmpReg, rsp);
1802 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1803 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1804 movptr(Address(boxReg, 0), tmpReg);
1805 if (counters != NULL) {
1806 cond_inc32(Assembler::equal,
1807 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1808 }
1809 jmp(DONE_LABEL);
1810
1811 bind(IsInflated);
1812 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1813
1814 #if INCLUDE_RTM_OPT
1815 // Use the same RTM locking code in 32- and 64-bit VM.
1816 if (use_rtm) {
1817 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1818 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1819 } else {
1820 #endif // INCLUDE_RTM_OPT
1821
1822 #ifndef _LP64
1823 // The object is inflated.
1824
1825 // boxReg refers to the on-stack BasicLock in the current frame.
1826 // We'd like to write:
1827 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1828 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1829 // additional latency as we have another ST in the store buffer that must drain.
1830
1831 if (EmitSync & 8192) {
1832 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1833 get_thread (scrReg);
1834 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1835 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1836 if (os::is_MP()) {
1837 lock();
1838 }
1839 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1840 } else
1841 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1842 movptr(scrReg, boxReg);
1843 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1844
1845 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1846 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1847 // prefetchw [eax + Offset(_owner)-2]
1848 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1849 }
1850
1851 if ((EmitSync & 64) == 0) {
1852 // Optimistic form: consider XORL tmpReg,tmpReg
1853 movptr(tmpReg, NULL_WORD);
1854 } else {
1855 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1856 // Test-And-CAS instead of CAS
1857 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1858 testptr(tmpReg, tmpReg); // Locked ?
1859 jccb (Assembler::notZero, DONE_LABEL);
1860 }
1861
1862 // Appears unlocked - try to swing _owner from null to non-null.
1863 // Ideally, I'd manifest "Self" with get_thread and then attempt
1864 // to CAS the register containing Self into m->Owner.
1865 // But we don't have enough registers, so instead we can either try to CAS
1866 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1867 // we later store "Self" into m->Owner. Transiently storing a stack address
1868 // (rsp or the address of the box) into m->owner is harmless.
1869 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1870 if (os::is_MP()) {
1871 lock();
1872 }
1873 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1874 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1875 jccb (Assembler::notZero, DONE_LABEL);
1876 get_thread (scrReg); // beware: clobbers ICCs
1877 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1878 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1879
1880 // If the CAS fails we can either retry or pass control to the slow-path.
1881 // We use the latter tactic.
1882 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1883 // If the CAS was successful ...
1884 // Self has acquired the lock
1885 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1886 // Intentional fall-through into DONE_LABEL ...
1887 } else {
1888 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1889 movptr(boxReg, tmpReg);
1890
1891 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1892 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1893 // prefetchw [eax + Offset(_owner)-2]
1894 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1895 }
1896
1897 if ((EmitSync & 64) == 0) {
1898 // Optimistic form
1899 xorptr (tmpReg, tmpReg);
1900 } else {
1901 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1902 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1903 testptr(tmpReg, tmpReg); // Locked ?
1904 jccb (Assembler::notZero, DONE_LABEL);
1905 }
1906
1907 // Appears unlocked - try to swing _owner from null to non-null.
1908 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1909 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1910 get_thread (scrReg);
1911 if (os::is_MP()) {
1912 lock();
1913 }
1914 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1915
1916 // If the CAS fails we can either retry or pass control to the slow-path.
1917 // We use the latter tactic.
1918 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1919 // If the CAS was successful ...
1920 // Self has acquired the lock
1921 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1922 // Intentional fall-through into DONE_LABEL ...
1923 }
1924 #else // _LP64
1925 // It's inflated
1926
1927 // TODO: someday avoid the ST-before-CAS penalty by
1928 // relocating (deferring) the following ST.
1929 // We should also think about trying a CAS without having
1930 // fetched _owner. If the CAS is successful we may
1931 // avoid an RTO->RTS upgrade on the $line.
1932
1933 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1934 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1935
1936 movptr (boxReg, tmpReg);
1937 movptr(tmpReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1938 testptr(tmpReg, tmpReg);
1939 jccb (Assembler::notZero, DONE_LABEL);
1940
1941 // It's inflated and appears unlocked
1942 if (os::is_MP()) {
1943 lock();
1944 }
1945 cmpxchgptr(r15_thread, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1946 // Intentional fall-through into DONE_LABEL ...
1947 #endif // _LP64
1948
1949 #if INCLUDE_RTM_OPT
1950 } // use_rtm()
1951 #endif
1952 // DONE_LABEL is a hot target - we'd really like to place it at the
1953 // start of cache line by padding with NOPs.
1954 // See the AMD and Intel software optimization manuals for the
1955 // most efficient "long" NOP encodings.
1956 // Unfortunately none of our alignment mechanisms suffice.
1957 bind(DONE_LABEL);
1958
1959 // At DONE_LABEL the icc ZFlag is set as follows ...
1960 // Fast_Unlock uses the same protocol.
1961 // ZFlag == 1 -> Success
1962 // ZFlag == 0 -> Failure - force control through the slow-path
1963 }
1964 }
1965
1966 // obj: object to unlock
1967 // box: box address (displaced header location), killed. Must be EAX.
1968 // tmp: killed, cannot be obj nor box.
1969 //
1970 // Some commentary on balanced locking:
1971 //
1972 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1973 // Methods that don't have provably balanced locking are forced to run in the
1974 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1975 // The interpreter provides two properties:
1976 // I1: At return-time the interpreter automatically and quietly unlocks any
1977 // objects acquired the current activation (frame). Recall that the
1978 // interpreter maintains an on-stack list of locks currently held by
1979 // a frame.
1980 // I2: If a method attempts to unlock an object that is not held by the
1981 // the frame the interpreter throws IMSX.
1982 //
1983 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1984 // B() doesn't have provably balanced locking so it runs in the interpreter.
1985 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1986 // is still locked by A().
1987 //
1988 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1989 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1990 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1991 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1992
1993 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1994 assert(boxReg == rax, "");
1995 assert_different_registers(objReg, boxReg, tmpReg);
1996
1997 if (EmitSync & 4) {
1998 // Disable - inhibit all inlining. Force control through the slow-path
1999 cmpptr (rsp, 0);
2000 } else
2001 if (EmitSync & 8) {
2002 Label DONE_LABEL;
2003 if (UseBiasedLocking) {
2004 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2005 }
2006 // Classic stack-locking code ...
2007 // Check whether the displaced header is 0
2008 //(=> recursive unlock)
2009 movptr(tmpReg, Address(boxReg, 0));
2010 testptr(tmpReg, tmpReg);
2011 jccb(Assembler::zero, DONE_LABEL);
2012 // If not recursive lock, reset the header to displaced header
2013 if (os::is_MP()) {
2014 lock();
2015 }
2016 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2017 bind(DONE_LABEL);
2018 } else {
2019 Label DONE_LABEL, Stacked, CheckSucc;
2020
2021 // Critically, the biased locking test must have precedence over
2022 // and appear before the (box->dhw == 0) recursive stack-lock test.
2023 if (UseBiasedLocking && !UseOptoBiasInlining) {
2024 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
2025 }
2026
2027 #if INCLUDE_RTM_OPT
2028 if (UseRTMForStackLocks && use_rtm) {
2029 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
2030 Label L_regular_unlock;
2031 movptr(tmpReg, Address(objReg, 0)); // fetch markword
2032 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
2033 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
2034 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
2035 xend(); // otherwise end...
2036 jmp(DONE_LABEL); // ... and we're done
2037 bind(L_regular_unlock);
2038 }
2039 #endif
2040
2041 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
2042 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
2043 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword
2044 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2045 jccb (Assembler::zero, Stacked);
2046
2047 // It's inflated.
2048 #if INCLUDE_RTM_OPT
2049 if (use_rtm) {
2050 Label L_regular_inflated_unlock;
2051 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2052 movptr(boxReg, Address(tmpReg, owner_offset));
2053 testptr(boxReg, boxReg);
2054 jccb(Assembler::notZero, L_regular_inflated_unlock);
2055 xend();
2056 jmpb(DONE_LABEL);
2057 bind(L_regular_inflated_unlock);
2058 }
2059 #endif
2060
2061 // Despite our balanced locking property we still check that m->_owner == Self
2062 // as java routines or native JNI code called by this thread might
2063 // have released the lock.
2064 // Refer to the comments in synchronizer.cpp for how we might encode extra
2065 // state in _succ so we can avoid fetching EntryList|cxq.
2066 //
2067 // I'd like to add more cases in fast_lock() and fast_unlock() --
2068 // such as recursive enter and exit -- but we have to be wary of
2069 // I$ bloat, T$ effects and BP$ effects.
2070 //
2071 // If there's no contention try a 1-0 exit. That is, exit without
2072 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2073 // we detect and recover from the race that the 1-0 exit admits.
2074 //
2075 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2076 // before it STs null into _owner, releasing the lock. Updates
2077 // to data protected by the critical section must be visible before
2078 // we drop the lock (and thus before any other thread could acquire
2079 // the lock and observe the fields protected by the lock).
2080 // IA32's memory-model is SPO, so STs are ordered with respect to
2081 // each other and there's no need for an explicit barrier (fence).
2082 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2083 #ifndef _LP64
2084 get_thread (boxReg);
2085 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2086 // prefetchw [ebx + Offset(_owner)-2]
2087 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2088 }
2089
2090 // Note that we could employ various encoding schemes to reduce
2091 // the number of loads below (currently 4) to just 2 or 3.
2092 // Refer to the comments in synchronizer.cpp.
2093 // In practice the chain of fetches doesn't seem to impact performance, however.
2094 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2095 // Attempt to reduce branch density - AMD's branch predictor.
2096 xorptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2097 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2098 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2099 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2100 jccb (Assembler::notZero, DONE_LABEL);
2101 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2102 jmpb (DONE_LABEL);
2103 } else {
2104 xorptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2105 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2106 jccb (Assembler::notZero, DONE_LABEL);
2107 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2108 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2109 jccb (Assembler::notZero, CheckSucc);
2110 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2111 jmpb (DONE_LABEL);
2112 }
2113
2114 // The Following code fragment (EmitSync & 65536) improves the performance of
2115 // contended applications and contended synchronization microbenchmarks.
2116 // Unfortunately the emission of the code - even though not executed - causes regressions
2117 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2118 // with an equal number of never-executed NOPs results in the same regression.
2119 // We leave it off by default.
2120
2121 if ((EmitSync & 65536) != 0) {
2122 Label LSuccess, LGoSlowPath ;
2123
2124 bind (CheckSucc);
2125
2126 // Optional pre-test ... it's safe to elide this
2127 if ((EmitSync & 16) == 0) {
2128 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2129 jccb (Assembler::zero, LGoSlowPath);
2130 }
2131
2132 // We have a classic Dekker-style idiom:
2133 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2134 // There are a number of ways to implement the barrier:
2135 // (1) lock:andl &m->_owner, 0
2136 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2137 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2138 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2139 // (2) If supported, an explicit MFENCE is appealing.
2140 // In older IA32 processors MFENCE is slower than lock:add or xchg
2141 // particularly if the write-buffer is full as might be the case if
2142 // if stores closely precede the fence or fence-equivalent instruction.
2143 // In more modern implementations MFENCE appears faster, however.
2144 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2145 // The $lines underlying the top-of-stack should be in M-state.
2146 // The locked add instruction is serializing, of course.
2147 // (4) Use xchg, which is serializing
2148 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2149 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2150 // The integer condition codes will tell us if succ was 0.
2151 // Since _succ and _owner should reside in the same $line and
2152 // we just stored into _owner, it's likely that the $line
2153 // remains in M-state for the lock:orl.
2154 //
2155 // We currently use (3), although it's likely that switching to (2)
2156 // is correct for the future.
2157
2158 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2159 if (os::is_MP()) {
2160 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
2161 mfence();
2162 } else {
2163 lock (); addptr(Address(rsp, 0), 0);
2164 }
2165 }
2166 // Ratify _succ remains non-null
2167 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2168 jccb (Assembler::notZero, LSuccess);
2169
2170 xorptr(boxReg, boxReg); // box is really EAX
2171 if (os::is_MP()) { lock(); }
2172 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2173 jccb (Assembler::notEqual, LSuccess);
2174 // Since we're low on registers we installed rsp as a placeholding in _owner.
2175 // Now install Self over rsp. This is safe as we're transitioning from
2176 // non-null to non=null
2177 get_thread (boxReg);
2178 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2179 // Intentional fall-through into LGoSlowPath ...
2180
2181 bind (LGoSlowPath);
2182 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2183 jmpb (DONE_LABEL);
2184
2185 bind (LSuccess);
2186 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2187 jmpb (DONE_LABEL);
2188 }
2189
2190 bind (Stacked);
2191 // It's not inflated and it's not recursively stack-locked and it's not biased.
2192 // It must be stack-locked.
2193 // Try to reset the header to displaced header.
2194 // The "box" value on the stack is stable, so we can reload
2195 // and be assured we observe the same value as above.
2196 movptr(tmpReg, Address(boxReg, 0));
2197 if (os::is_MP()) {
2198 lock();
2199 }
2200 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2201 // Intention fall-thru into DONE_LABEL
2202
2203 // DONE_LABEL is a hot target - we'd really like to place it at the
2204 // start of cache line by padding with NOPs.
2205 // See the AMD and Intel software optimization manuals for the
2206 // most efficient "long" NOP encodings.
2207 // Unfortunately none of our alignment mechanisms suffice.
2208 if ((EmitSync & 65536) == 0) {
2209 bind (CheckSucc);
2210 }
2211 #else // _LP64
2212 // It's inflated
2213 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2214 xorptr(boxReg, r15_thread);
2215 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2216 jccb (Assembler::notZero, DONE_LABEL);
2217 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2218 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2219 jccb (Assembler::notZero, CheckSucc);
2220 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2221 jmpb (DONE_LABEL);
2222
2223 if ((EmitSync & 65536) == 0) {
2224 Label LSuccess, LGoSlowPath ;
2225 bind (CheckSucc);
2226 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2227 jccb (Assembler::zero, LGoSlowPath);
2228
2229 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
2230 // the explicit ST;MEMBAR combination, but masm doesn't currently support
2231 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
2232 // are all faster when the write buffer is populated.
2233 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2234 if (os::is_MP()) {
2235 lock (); addl (Address(rsp, 0), 0);
2236 }
2237 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2238 jccb (Assembler::notZero, LSuccess);
2239
2240 movptr (boxReg, (int32_t)NULL_WORD); // box is really EAX
2241 if (os::is_MP()) { lock(); }
2242 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2243 jccb (Assembler::notEqual, LSuccess);
2244 // Intentional fall-through into slow-path
2245
2246 bind (LGoSlowPath);
2247 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2248 jmpb (DONE_LABEL);
2249
2250 bind (LSuccess);
2251 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2252 jmpb (DONE_LABEL);
2253 }
2254
2255 bind (Stacked);
2256 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2257 if (os::is_MP()) { lock(); }
2258 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2259
2260 if (EmitSync & 65536) {
2261 bind (CheckSucc);
2262 }
2263 #endif
2264 bind(DONE_LABEL);
2265 // Avoid branch to branch on AMD processors
2266 if (EmitSync & 32768) {
2267 nop();
2268 }
2269 }
2270 }
2271 #endif // COMPILER2
2272
2273 void MacroAssembler::c2bool(Register x) {
2274 // implements x == 0 ? 0 : 1
2275 // note: must only look at least-significant byte of x
2276 // since C-style booleans are stored in one byte
2277 // only! (was bug)
2278 andl(x, 0xFF);
2279 setb(Assembler::notZero, x);
2280 }
2281
2282 // Wouldn't need if AddressLiteral version had new name
2283 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2284 Assembler::call(L, rtype);
2285 }
2286
2287 void MacroAssembler::call(Register entry) {
2288 Assembler::call(entry);
2289 }
2290
2291 void MacroAssembler::call(AddressLiteral entry) {
2292 if (reachable(entry)) {
2293 Assembler::call_literal(entry.target(), entry.rspec());
2294 } else {
2295 lea(rscratch1, entry);
2296 Assembler::call(rscratch1);
2297 }
2298 }
2299
2300 void MacroAssembler::ic_call(address entry) {
2301 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2302 movptr(rax, (intptr_t)Universe::non_oop_word());
2303 call(AddressLiteral(entry, rh));
2304 }
2305
2306 // Implementation of call_VM versions
2307
2308 void MacroAssembler::call_VM(Register oop_result,
2309 address entry_point,
2310 bool check_exceptions) {
2311 Label C, E;
2312 call(C, relocInfo::none);
2313 jmp(E);
2314
2315 bind(C);
2316 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2317 ret(0);
2318
2319 bind(E);
2320 }
2321
2322 void MacroAssembler::call_VM(Register oop_result,
2323 address entry_point,
2324 Register arg_1,
2325 bool check_exceptions) {
2326 Label C, E;
2327 call(C, relocInfo::none);
2328 jmp(E);
2329
2330 bind(C);
2331 pass_arg1(this, arg_1);
2332 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2333 ret(0);
2334
2335 bind(E);
2336 }
2337
2338 void MacroAssembler::call_VM(Register oop_result,
2339 address entry_point,
2340 Register arg_1,
2341 Register arg_2,
2342 bool check_exceptions) {
2343 Label C, E;
2344 call(C, relocInfo::none);
2345 jmp(E);
2346
2347 bind(C);
2348
2349 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2350
2351 pass_arg2(this, arg_2);
2352 pass_arg1(this, arg_1);
2353 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2354 ret(0);
2355
2356 bind(E);
2357 }
2358
2359 void MacroAssembler::call_VM(Register oop_result,
2360 address entry_point,
2361 Register arg_1,
2362 Register arg_2,
2363 Register arg_3,
2364 bool check_exceptions) {
2365 Label C, E;
2366 call(C, relocInfo::none);
2367 jmp(E);
2368
2369 bind(C);
2370
2371 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2372 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2373 pass_arg3(this, arg_3);
2374
2375 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2376 pass_arg2(this, arg_2);
2377
2378 pass_arg1(this, arg_1);
2379 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2380 ret(0);
2381
2382 bind(E);
2383 }
2384
2385 void MacroAssembler::call_VM(Register oop_result,
2386 Register last_java_sp,
2387 address entry_point,
2388 int number_of_arguments,
2389 bool check_exceptions) {
2390 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2391 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2392 }
2393
2394 void MacroAssembler::call_VM(Register oop_result,
2395 Register last_java_sp,
2396 address entry_point,
2397 Register arg_1,
2398 bool check_exceptions) {
2399 pass_arg1(this, arg_1);
2400 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2401 }
2402
2403 void MacroAssembler::call_VM(Register oop_result,
2404 Register last_java_sp,
2405 address entry_point,
2406 Register arg_1,
2407 Register arg_2,
2408 bool check_exceptions) {
2409
2410 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2411 pass_arg2(this, arg_2);
2412 pass_arg1(this, arg_1);
2413 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2414 }
2415
2416 void MacroAssembler::call_VM(Register oop_result,
2417 Register last_java_sp,
2418 address entry_point,
2419 Register arg_1,
2420 Register arg_2,
2421 Register arg_3,
2422 bool check_exceptions) {
2423 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2424 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2425 pass_arg3(this, arg_3);
2426 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2427 pass_arg2(this, arg_2);
2428 pass_arg1(this, arg_1);
2429 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2430 }
2431
2432 void MacroAssembler::super_call_VM(Register oop_result,
2433 Register last_java_sp,
2434 address entry_point,
2435 int number_of_arguments,
2436 bool check_exceptions) {
2437 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2438 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2439 }
2440
2441 void MacroAssembler::super_call_VM(Register oop_result,
2442 Register last_java_sp,
2443 address entry_point,
2444 Register arg_1,
2445 bool check_exceptions) {
2446 pass_arg1(this, arg_1);
2447 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2448 }
2449
2450 void MacroAssembler::super_call_VM(Register oop_result,
2451 Register last_java_sp,
2452 address entry_point,
2453 Register arg_1,
2454 Register arg_2,
2455 bool check_exceptions) {
2456
2457 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2458 pass_arg2(this, arg_2);
2459 pass_arg1(this, arg_1);
2460 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2461 }
2462
2463 void MacroAssembler::super_call_VM(Register oop_result,
2464 Register last_java_sp,
2465 address entry_point,
2466 Register arg_1,
2467 Register arg_2,
2468 Register arg_3,
2469 bool check_exceptions) {
2470 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2471 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2472 pass_arg3(this, arg_3);
2473 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2474 pass_arg2(this, arg_2);
2475 pass_arg1(this, arg_1);
2476 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2477 }
2478
2479 void MacroAssembler::call_VM_base(Register oop_result,
2480 Register java_thread,
2481 Register last_java_sp,
2482 address entry_point,
2483 int number_of_arguments,
2484 bool check_exceptions) {
2485 // determine java_thread register
2486 if (!java_thread->is_valid()) {
2487 #ifdef _LP64
2488 java_thread = r15_thread;
2489 #else
2490 java_thread = rdi;
2491 get_thread(java_thread);
2492 #endif // LP64
2493 }
2494 // determine last_java_sp register
2495 if (!last_java_sp->is_valid()) {
2496 last_java_sp = rsp;
2497 }
2498 // debugging support
2499 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2500 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2501 #ifdef ASSERT
2502 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2503 // r12 is the heapbase.
2504 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2505 #endif // ASSERT
2506
2507 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2508 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2509
2510 // push java thread (becomes first argument of C function)
2511
2512 NOT_LP64(push(java_thread); number_of_arguments++);
2513 LP64_ONLY(mov(c_rarg0, r15_thread));
2514
2515 // set last Java frame before call
2516 assert(last_java_sp != rbp, "can't use ebp/rbp");
2517
2518 // Only interpreter should have to set fp
2519 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2520
2521 // do the call, remove parameters
2522 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2523
2524 // restore the thread (cannot use the pushed argument since arguments
2525 // may be overwritten by C code generated by an optimizing compiler);
2526 // however can use the register value directly if it is callee saved.
2527 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2528 // rdi & rsi (also r15) are callee saved -> nothing to do
2529 #ifdef ASSERT
2530 guarantee(java_thread != rax, "change this code");
2531 push(rax);
2532 { Label L;
2533 get_thread(rax);
2534 cmpptr(java_thread, rax);
2535 jcc(Assembler::equal, L);
2536 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2537 bind(L);
2538 }
2539 pop(rax);
2540 #endif
2541 } else {
2542 get_thread(java_thread);
2543 }
2544 // reset last Java frame
2545 // Only interpreter should have to clear fp
2546 reset_last_Java_frame(java_thread, true, false);
2547
2548 #ifndef CC_INTERP
2549 // C++ interp handles this in the interpreter
2550 check_and_handle_popframe(java_thread);
2551 check_and_handle_earlyret(java_thread);
2552 #endif /* CC_INTERP */
2553
2554 if (check_exceptions) {
2555 // check for pending exceptions (java_thread is set upon return)
2556 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2557 #ifndef _LP64
2558 jump_cc(Assembler::notEqual,
2559 RuntimeAddress(StubRoutines::forward_exception_entry()));
2560 #else
2561 // This used to conditionally jump to forward_exception however it is
2562 // possible if we relocate that the branch will not reach. So we must jump
2563 // around so we can always reach
2564
2565 Label ok;
2566 jcc(Assembler::equal, ok);
2567 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2568 bind(ok);
2569 #endif // LP64
2570 }
2571
2572 // get oop result if there is one and reset the value in the thread
2573 if (oop_result->is_valid()) {
2574 get_vm_result(oop_result, java_thread);
2575 }
2576 }
2577
2578 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2579
2580 // Calculate the value for last_Java_sp
2581 // somewhat subtle. call_VM does an intermediate call
2582 // which places a return address on the stack just under the
2583 // stack pointer as the user finsihed with it. This allows
2584 // use to retrieve last_Java_pc from last_Java_sp[-1].
2585 // On 32bit we then have to push additional args on the stack to accomplish
2586 // the actual requested call. On 64bit call_VM only can use register args
2587 // so the only extra space is the return address that call_VM created.
2588 // This hopefully explains the calculations here.
2589
2590 #ifdef _LP64
2591 // We've pushed one address, correct last_Java_sp
2592 lea(rax, Address(rsp, wordSize));
2593 #else
2594 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2595 #endif // LP64
2596
2597 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2598
2599 }
2600
2601 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2602 call_VM_leaf_base(entry_point, number_of_arguments);
2603 }
2604
2605 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2606 pass_arg0(this, arg_0);
2607 call_VM_leaf(entry_point, 1);
2608 }
2609
2610 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2611
2612 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2613 pass_arg1(this, arg_1);
2614 pass_arg0(this, arg_0);
2615 call_VM_leaf(entry_point, 2);
2616 }
2617
2618 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2619 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2620 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2621 pass_arg2(this, arg_2);
2622 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2623 pass_arg1(this, arg_1);
2624 pass_arg0(this, arg_0);
2625 call_VM_leaf(entry_point, 3);
2626 }
2627
2628 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2629 pass_arg0(this, arg_0);
2630 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2631 }
2632
2633 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2634
2635 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2636 pass_arg1(this, arg_1);
2637 pass_arg0(this, arg_0);
2638 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2639 }
2640
2641 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2642 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2643 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2644 pass_arg2(this, arg_2);
2645 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2646 pass_arg1(this, arg_1);
2647 pass_arg0(this, arg_0);
2648 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2649 }
2650
2651 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2652 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2653 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2654 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2655 pass_arg3(this, arg_3);
2656 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2657 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2658 pass_arg2(this, arg_2);
2659 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2660 pass_arg1(this, arg_1);
2661 pass_arg0(this, arg_0);
2662 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2663 }
2664
2665 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2666 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2667 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2668 verify_oop(oop_result, "broken oop in call_VM_base");
2669 }
2670
2671 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2672 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2673 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2674 }
2675
2676 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2677 }
2678
2679 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2680 }
2681
2682 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2683 if (reachable(src1)) {
2684 cmpl(as_Address(src1), imm);
2685 } else {
2686 lea(rscratch1, src1);
2687 cmpl(Address(rscratch1, 0), imm);
2688 }
2689 }
2690
2691 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2692 assert(!src2.is_lval(), "use cmpptr");
2693 if (reachable(src2)) {
2694 cmpl(src1, as_Address(src2));
2695 } else {
2696 lea(rscratch1, src2);
2697 cmpl(src1, Address(rscratch1, 0));
2698 }
2699 }
2700
2701 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2702 Assembler::cmpl(src1, imm);
2703 }
2704
2705 void MacroAssembler::cmp32(Register src1, Address src2) {
2706 Assembler::cmpl(src1, src2);
2707 }
2708
2709 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2710 ucomisd(opr1, opr2);
2711
2712 Label L;
2713 if (unordered_is_less) {
2714 movl(dst, -1);
2715 jcc(Assembler::parity, L);
2716 jcc(Assembler::below , L);
2717 movl(dst, 0);
2718 jcc(Assembler::equal , L);
2719 increment(dst);
2720 } else { // unordered is greater
2721 movl(dst, 1);
2722 jcc(Assembler::parity, L);
2723 jcc(Assembler::above , L);
2724 movl(dst, 0);
2725 jcc(Assembler::equal , L);
2726 decrementl(dst);
2727 }
2728 bind(L);
2729 }
2730
2731 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2732 ucomiss(opr1, opr2);
2733
2734 Label L;
2735 if (unordered_is_less) {
2736 movl(dst, -1);
2737 jcc(Assembler::parity, L);
2738 jcc(Assembler::below , L);
2739 movl(dst, 0);
2740 jcc(Assembler::equal , L);
2741 increment(dst);
2742 } else { // unordered is greater
2743 movl(dst, 1);
2744 jcc(Assembler::parity, L);
2745 jcc(Assembler::above , L);
2746 movl(dst, 0);
2747 jcc(Assembler::equal , L);
2748 decrementl(dst);
2749 }
2750 bind(L);
2751 }
2752
2753
2754 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2755 if (reachable(src1)) {
2756 cmpb(as_Address(src1), imm);
2757 } else {
2758 lea(rscratch1, src1);
2759 cmpb(Address(rscratch1, 0), imm);
2760 }
2761 }
2762
2763 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2764 #ifdef _LP64
2765 if (src2.is_lval()) {
2766 movptr(rscratch1, src2);
2767 Assembler::cmpq(src1, rscratch1);
2768 } else if (reachable(src2)) {
2769 cmpq(src1, as_Address(src2));
2770 } else {
2771 lea(rscratch1, src2);
2772 Assembler::cmpq(src1, Address(rscratch1, 0));
2773 }
2774 #else
2775 if (src2.is_lval()) {
2776 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2777 } else {
2778 cmpl(src1, as_Address(src2));
2779 }
2780 #endif // _LP64
2781 }
2782
2783 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2784 assert(src2.is_lval(), "not a mem-mem compare");
2785 #ifdef _LP64
2786 // moves src2's literal address
2787 movptr(rscratch1, src2);
2788 Assembler::cmpq(src1, rscratch1);
2789 #else
2790 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2791 #endif // _LP64
2792 }
2793
2794 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2795 if (reachable(adr)) {
2796 if (os::is_MP())
2797 lock();
2798 cmpxchgptr(reg, as_Address(adr));
2799 } else {
2800 lea(rscratch1, adr);
2801 if (os::is_MP())
2802 lock();
2803 cmpxchgptr(reg, Address(rscratch1, 0));
2804 }
2805 }
2806
2807 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2808 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2809 }
2810
2811 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2812 if (reachable(src)) {
2813 Assembler::comisd(dst, as_Address(src));
2814 } else {
2815 lea(rscratch1, src);
2816 Assembler::comisd(dst, Address(rscratch1, 0));
2817 }
2818 }
2819
2820 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2821 if (reachable(src)) {
2822 Assembler::comiss(dst, as_Address(src));
2823 } else {
2824 lea(rscratch1, src);
2825 Assembler::comiss(dst, Address(rscratch1, 0));
2826 }
2827 }
2828
2829
2830 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2831 Condition negated_cond = negate_condition(cond);
2832 Label L;
2833 jcc(negated_cond, L);
2834 pushf(); // Preserve flags
2835 atomic_incl(counter_addr);
2836 popf();
2837 bind(L);
2838 }
2839
2840 int MacroAssembler::corrected_idivl(Register reg) {
2841 // Full implementation of Java idiv and irem; checks for
2842 // special case as described in JVM spec., p.243 & p.271.
2843 // The function returns the (pc) offset of the idivl
2844 // instruction - may be needed for implicit exceptions.
2845 //
2846 // normal case special case
2847 //
2848 // input : rax,: dividend min_int
2849 // reg: divisor (may not be rax,/rdx) -1
2850 //
2851 // output: rax,: quotient (= rax, idiv reg) min_int
2852 // rdx: remainder (= rax, irem reg) 0
2853 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2854 const int min_int = 0x80000000;
2855 Label normal_case, special_case;
2856
2857 // check for special case
2858 cmpl(rax, min_int);
2859 jcc(Assembler::notEqual, normal_case);
2860 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2861 cmpl(reg, -1);
2862 jcc(Assembler::equal, special_case);
2863
2864 // handle normal case
2865 bind(normal_case);
2866 cdql();
2867 int idivl_offset = offset();
2868 idivl(reg);
2869
2870 // normal and special case exit
2871 bind(special_case);
2872
2873 return idivl_offset;
2874 }
2875
2876
2877
2878 void MacroAssembler::decrementl(Register reg, int value) {
2879 if (value == min_jint) {subl(reg, value) ; return; }
2880 if (value < 0) { incrementl(reg, -value); return; }
2881 if (value == 0) { ; return; }
2882 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2883 /* else */ { subl(reg, value) ; return; }
2884 }
2885
2886 void MacroAssembler::decrementl(Address dst, int value) {
2887 if (value == min_jint) {subl(dst, value) ; return; }
2888 if (value < 0) { incrementl(dst, -value); return; }
2889 if (value == 0) { ; return; }
2890 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2891 /* else */ { subl(dst, value) ; return; }
2892 }
2893
2894 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2895 assert (shift_value > 0, "illegal shift value");
2896 Label _is_positive;
2897 testl (reg, reg);
2898 jcc (Assembler::positive, _is_positive);
2899 int offset = (1 << shift_value) - 1 ;
2900
2901 if (offset == 1) {
2902 incrementl(reg);
2903 } else {
2904 addl(reg, offset);
2905 }
2906
2907 bind (_is_positive);
2908 sarl(reg, shift_value);
2909 }
2910
2911 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2912 if (reachable(src)) {
2913 Assembler::divsd(dst, as_Address(src));
2914 } else {
2915 lea(rscratch1, src);
2916 Assembler::divsd(dst, Address(rscratch1, 0));
2917 }
2918 }
2919
2920 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2921 if (reachable(src)) {
2922 Assembler::divss(dst, as_Address(src));
2923 } else {
2924 lea(rscratch1, src);
2925 Assembler::divss(dst, Address(rscratch1, 0));
2926 }
2927 }
2928
2929 // !defined(COMPILER2) is because of stupid core builds
2930 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2)
2931 void MacroAssembler::empty_FPU_stack() {
2932 if (VM_Version::supports_mmx()) {
2933 emms();
2934 } else {
2935 for (int i = 8; i-- > 0; ) ffree(i);
2936 }
2937 }
2938 #endif // !LP64 || C1 || !C2
2939
2940
2941 // Defines obj, preserves var_size_in_bytes
2942 void MacroAssembler::eden_allocate(Register obj,
2943 Register var_size_in_bytes,
2944 int con_size_in_bytes,
2945 Register t1,
2946 Label& slow_case) {
2947 assert(obj == rax, "obj must be in rax, for cmpxchg");
2948 assert_different_registers(obj, var_size_in_bytes, t1);
2949 if (!Universe::heap()->supports_inline_contig_alloc()) {
2950 jmp(slow_case);
2951 } else {
2952 Register end = t1;
2953 Label retry;
2954 bind(retry);
2955 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2956 movptr(obj, heap_top);
2957 if (var_size_in_bytes == noreg) {
2958 lea(end, Address(obj, con_size_in_bytes));
2959 } else {
2960 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2961 }
2962 // if end < obj then we wrapped around => object too long => slow case
2963 cmpptr(end, obj);
2964 jcc(Assembler::below, slow_case);
2965 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2966 jcc(Assembler::above, slow_case);
2967 // Compare obj with the top addr, and if still equal, store the new top addr in
2968 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2969 // it otherwise. Use lock prefix for atomicity on MPs.
2970 locked_cmpxchgptr(end, heap_top);
2971 jcc(Assembler::notEqual, retry);
2972 }
2973 }
2974
2975 void MacroAssembler::enter() {
2976 push(rbp);
2977 mov(rbp, rsp);
2978 }
2979
2980 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2981 void MacroAssembler::fat_nop() {
2982 if (UseAddressNop) {
2983 addr_nop_5();
2984 } else {
2985 emit_int8(0x26); // es:
2986 emit_int8(0x2e); // cs:
2987 emit_int8(0x64); // fs:
2988 emit_int8(0x65); // gs:
2989 emit_int8((unsigned char)0x90);
2990 }
2991 }
2992
2993 void MacroAssembler::fcmp(Register tmp) {
2994 fcmp(tmp, 1, true, true);
2995 }
2996
2997 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2998 assert(!pop_right || pop_left, "usage error");
2999 if (VM_Version::supports_cmov()) {
3000 assert(tmp == noreg, "unneeded temp");
3001 if (pop_left) {
3002 fucomip(index);
3003 } else {
3004 fucomi(index);
3005 }
3006 if (pop_right) {
3007 fpop();
3008 }
3009 } else {
3010 assert(tmp != noreg, "need temp");
3011 if (pop_left) {
3012 if (pop_right) {
3013 fcompp();
3014 } else {
3015 fcomp(index);
3016 }
3017 } else {
3018 fcom(index);
3019 }
3020 // convert FPU condition into eflags condition via rax,
3021 save_rax(tmp);
3022 fwait(); fnstsw_ax();
3023 sahf();
3024 restore_rax(tmp);
3025 }
3026 // condition codes set as follows:
3027 //
3028 // CF (corresponds to C0) if x < y
3029 // PF (corresponds to C2) if unordered
3030 // ZF (corresponds to C3) if x = y
3031 }
3032
3033 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3034 fcmp2int(dst, unordered_is_less, 1, true, true);
3035 }
3036
3037 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3038 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3039 Label L;
3040 if (unordered_is_less) {
3041 movl(dst, -1);
3042 jcc(Assembler::parity, L);
3043 jcc(Assembler::below , L);
3044 movl(dst, 0);
3045 jcc(Assembler::equal , L);
3046 increment(dst);
3047 } else { // unordered is greater
3048 movl(dst, 1);
3049 jcc(Assembler::parity, L);
3050 jcc(Assembler::above , L);
3051 movl(dst, 0);
3052 jcc(Assembler::equal , L);
3053 decrementl(dst);
3054 }
3055 bind(L);
3056 }
3057
3058 void MacroAssembler::fld_d(AddressLiteral src) {
3059 fld_d(as_Address(src));
3060 }
3061
3062 void MacroAssembler::fld_s(AddressLiteral src) {
3063 fld_s(as_Address(src));
3064 }
3065
3066 void MacroAssembler::fld_x(AddressLiteral src) {
3067 Assembler::fld_x(as_Address(src));
3068 }
3069
3070 void MacroAssembler::fldcw(AddressLiteral src) {
3071 Assembler::fldcw(as_Address(src));
3072 }
3073
3074 void MacroAssembler::pow_exp_core_encoding() {
3075 // kills rax, rcx, rdx
3076 subptr(rsp,sizeof(jdouble));
3077 // computes 2^X. Stack: X ...
3078 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and
3079 // keep it on the thread's stack to compute 2^int(X) later
3080 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1)
3081 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X))
3082 fld_s(0); // Stack: X X ...
3083 frndint(); // Stack: int(X) X ...
3084 fsuba(1); // Stack: int(X) X-int(X) ...
3085 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ...
3086 f2xm1(); // Stack: 2^(X-int(X))-1 ...
3087 fld1(); // Stack: 1 2^(X-int(X))-1 ...
3088 faddp(1); // Stack: 2^(X-int(X))
3089 // computes 2^(int(X)): add exponent bias (1023) to int(X), then
3090 // shift int(X)+1023 to exponent position.
3091 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11
3092 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent
3093 // values so detect them and set result to NaN.
3094 movl(rax,Address(rsp,0));
3095 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding
3096 addl(rax, 1023);
3097 movl(rdx,rax);
3098 shll(rax,20);
3099 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN.
3100 addl(rdx,1);
3101 // Check that 1 < int(X)+1023+1 < 2048
3102 // in 3 steps:
3103 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048
3104 // 2- (int(X)+1023+1)&-2048 != 0
3105 // 3- (int(X)+1023+1)&-2048 != 1
3106 // Do 2- first because addl just updated the flags.
3107 cmov32(Assembler::equal,rax,rcx);
3108 cmpl(rdx,1);
3109 cmov32(Assembler::equal,rax,rcx);
3110 testl(rdx,rcx);
3111 cmov32(Assembler::notEqual,rax,rcx);
3112 movl(Address(rsp,4),rax);
3113 movl(Address(rsp,0),0);
3114 fmul_d(Address(rsp,0)); // Stack: 2^X ...
3115 addptr(rsp,sizeof(jdouble));
3116 }
3117
3118 void MacroAssembler::increase_precision() {
3119 subptr(rsp, BytesPerWord);
3120 fnstcw(Address(rsp, 0));
3121 movl(rax, Address(rsp, 0));
3122 orl(rax, 0x300);
3123 push(rax);
3124 fldcw(Address(rsp, 0));
3125 pop(rax);
3126 }
3127
3128 void MacroAssembler::restore_precision() {
3129 fldcw(Address(rsp, 0));
3130 addptr(rsp, BytesPerWord);
3131 }
3132
3133 void MacroAssembler::fast_pow() {
3134 // computes X^Y = 2^(Y * log2(X))
3135 // if fast computation is not possible, result is NaN. Requires
3136 // fallback from user of this macro.
3137 // increase precision for intermediate steps of the computation
3138 BLOCK_COMMENT("fast_pow {");
3139 increase_precision();
3140 fyl2x(); // Stack: (Y*log2(X)) ...
3141 pow_exp_core_encoding(); // Stack: exp(X) ...
3142 restore_precision();
3143 BLOCK_COMMENT("} fast_pow");
3144 }
3145
3146 void MacroAssembler::fast_exp() {
3147 // computes exp(X) = 2^(X * log2(e))
3148 // if fast computation is not possible, result is NaN. Requires
3149 // fallback from user of this macro.
3150 // increase precision for intermediate steps of the computation
3151 increase_precision();
3152 fldl2e(); // Stack: log2(e) X ...
3153 fmulp(1); // Stack: (X*log2(e)) ...
3154 pow_exp_core_encoding(); // Stack: exp(X) ...
3155 restore_precision();
3156 }
3157
3158 void MacroAssembler::pow_or_exp(bool is_exp, int num_fpu_regs_in_use) {
3159 // kills rax, rcx, rdx
3160 // pow and exp needs 2 extra registers on the fpu stack.
3161 Label slow_case, done;
3162 Register tmp = noreg;
3163 if (!VM_Version::supports_cmov()) {
3164 // fcmp needs a temporary so preserve rdx,
3165 tmp = rdx;
3166 }
3167 Register tmp2 = rax;
3168 Register tmp3 = rcx;
3169
3170 if (is_exp) {
3171 // Stack: X
3172 fld_s(0); // duplicate argument for runtime call. Stack: X X
3173 fast_exp(); // Stack: exp(X) X
3174 fcmp(tmp, 0, false, false); // Stack: exp(X) X
3175 // exp(X) not equal to itself: exp(X) is NaN go to slow case.
3176 jcc(Assembler::parity, slow_case);
3177 // get rid of duplicate argument. Stack: exp(X)
3178 if (num_fpu_regs_in_use > 0) {
3179 fxch();
3180 fpop();
3181 } else {
3182 ffree(1);
3183 }
3184 jmp(done);
3185 } else {
3186 // Stack: X Y
3187 Label x_negative, y_not_2;
3188
3189 static double two = 2.0;
3190 ExternalAddress two_addr((address)&two);
3191
3192 // constant maybe too far on 64 bit
3193 lea(tmp2, two_addr);
3194 fld_d(Address(tmp2, 0)); // Stack: 2 X Y
3195 fcmp(tmp, 2, true, false); // Stack: X Y
3196 jcc(Assembler::parity, y_not_2);
3197 jcc(Assembler::notEqual, y_not_2);
3198
3199 fxch(); fpop(); // Stack: X
3200 fmul(0); // Stack: X*X
3201
3202 jmp(done);
3203
3204 bind(y_not_2);
3205
3206 fldz(); // Stack: 0 X Y
3207 fcmp(tmp, 1, true, false); // Stack: X Y
3208 jcc(Assembler::above, x_negative);
3209
3210 // X >= 0
3211
3212 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3213 fld_s(1); // Stack: X Y X Y
3214 fast_pow(); // Stack: X^Y X Y
3215 fcmp(tmp, 0, false, false); // Stack: X^Y X Y
3216 // X^Y not equal to itself: X^Y is NaN go to slow case.
3217 jcc(Assembler::parity, slow_case);
3218 // get rid of duplicate arguments. Stack: X^Y
3219 if (num_fpu_regs_in_use > 0) {
3220 fxch(); fpop();
3221 fxch(); fpop();
3222 } else {
3223 ffree(2);
3224 ffree(1);
3225 }
3226 jmp(done);
3227
3228 // X <= 0
3229 bind(x_negative);
3230
3231 fld_s(1); // Stack: Y X Y
3232 frndint(); // Stack: int(Y) X Y
3233 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y
3234 jcc(Assembler::notEqual, slow_case);
3235
3236 subptr(rsp, 8);
3237
3238 // For X^Y, when X < 0, Y has to be an integer and the final
3239 // result depends on whether it's odd or even. We just checked
3240 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit
3241 // integer to test its parity. If int(Y) is huge and doesn't fit
3242 // in the 64 bit integer range, the integer indefinite value will
3243 // end up in the gp registers. Huge numbers are all even, the
3244 // integer indefinite number is even so it's fine.
3245
3246 #ifdef ASSERT
3247 // Let's check we don't end up with an integer indefinite number
3248 // when not expected. First test for huge numbers: check whether
3249 // int(Y)+1 == int(Y) which is true for very large numbers and
3250 // those are all even. A 64 bit integer is guaranteed to not
3251 // overflow for numbers where y+1 != y (when precision is set to
3252 // double precision).
3253 Label y_not_huge;
3254
3255 fld1(); // Stack: 1 int(Y) X Y
3256 fadd(1); // Stack: 1+int(Y) int(Y) X Y
3257
3258 #ifdef _LP64
3259 // trip to memory to force the precision down from double extended
3260 // precision
3261 fstp_d(Address(rsp, 0));
3262 fld_d(Address(rsp, 0));
3263 #endif
3264
3265 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y
3266 #endif
3267
3268 // move int(Y) as 64 bit integer to thread's stack
3269 fistp_d(Address(rsp,0)); // Stack: X Y
3270
3271 #ifdef ASSERT
3272 jcc(Assembler::notEqual, y_not_huge);
3273
3274 // Y is huge so we know it's even. It may not fit in a 64 bit
3275 // integer and we don't want the debug code below to see the
3276 // integer indefinite value so overwrite int(Y) on the thread's
3277 // stack with 0.
3278 movl(Address(rsp, 0), 0);
3279 movl(Address(rsp, 4), 0);
3280
3281 bind(y_not_huge);
3282 #endif
3283
3284 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3285 fld_s(1); // Stack: X Y X Y
3286 fabs(); // Stack: abs(X) Y X Y
3287 fast_pow(); // Stack: abs(X)^Y X Y
3288 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y
3289 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case.
3290
3291 pop(tmp2);
3292 NOT_LP64(pop(tmp3));
3293 jcc(Assembler::parity, slow_case);
3294
3295 #ifdef ASSERT
3296 // Check that int(Y) is not integer indefinite value (int
3297 // overflow). Shouldn't happen because for values that would
3298 // overflow, 1+int(Y)==Y which was tested earlier.
3299 #ifndef _LP64
3300 {
3301 Label integer;
3302 testl(tmp2, tmp2);
3303 jcc(Assembler::notZero, integer);
3304 cmpl(tmp3, 0x80000000);
3305 jcc(Assembler::notZero, integer);
3306 STOP("integer indefinite value shouldn't be seen here");
3307 bind(integer);
3308 }
3309 #else
3310 {
3311 Label integer;
3312 mov(tmp3, tmp2); // preserve tmp2 for parity check below
3313 shlq(tmp3, 1);
3314 jcc(Assembler::carryClear, integer);
3315 jcc(Assembler::notZero, integer);
3316 STOP("integer indefinite value shouldn't be seen here");
3317 bind(integer);
3318 }
3319 #endif
3320 #endif
3321
3322 // get rid of duplicate arguments. Stack: X^Y
3323 if (num_fpu_regs_in_use > 0) {
3324 fxch(); fpop();
3325 fxch(); fpop();
3326 } else {
3327 ffree(2);
3328 ffree(1);
3329 }
3330
3331 testl(tmp2, 1);
3332 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y
3333 // X <= 0, Y even: X^Y = -abs(X)^Y
3334
3335 fchs(); // Stack: -abs(X)^Y Y
3336 jmp(done);
3337 }
3338
3339 // slow case: runtime call
3340 bind(slow_case);
3341
3342 fpop(); // pop incorrect result or int(Y)
3343
3344 fp_runtime_fallback(is_exp ? CAST_FROM_FN_PTR(address, SharedRuntime::dexp) : CAST_FROM_FN_PTR(address, SharedRuntime::dpow),
3345 is_exp ? 1 : 2, num_fpu_regs_in_use);
3346
3347 // Come here with result in F-TOS
3348 bind(done);
3349 }
3350
3351 void MacroAssembler::fpop() {
3352 ffree();
3353 fincstp();
3354 }
3355
3356 void MacroAssembler::fremr(Register tmp) {
3357 save_rax(tmp);
3358 { Label L;
3359 bind(L);
3360 fprem();
3361 fwait(); fnstsw_ax();
3362 #ifdef _LP64
3363 testl(rax, 0x400);
3364 jcc(Assembler::notEqual, L);
3365 #else
3366 sahf();
3367 jcc(Assembler::parity, L);
3368 #endif // _LP64
3369 }
3370 restore_rax(tmp);
3371 // Result is in ST0.
3372 // Note: fxch & fpop to get rid of ST1
3373 // (otherwise FPU stack could overflow eventually)
3374 fxch(1);
3375 fpop();
3376 }
3377
3378
3379 void MacroAssembler::incrementl(AddressLiteral dst) {
3380 if (reachable(dst)) {
3381 incrementl(as_Address(dst));
3382 } else {
3383 lea(rscratch1, dst);
3384 incrementl(Address(rscratch1, 0));
3385 }
3386 }
3387
3388 void MacroAssembler::incrementl(ArrayAddress dst) {
3389 incrementl(as_Address(dst));
3390 }
3391
3392 void MacroAssembler::incrementl(Register reg, int value) {
3393 if (value == min_jint) {addl(reg, value) ; return; }
3394 if (value < 0) { decrementl(reg, -value); return; }
3395 if (value == 0) { ; return; }
3396 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3397 /* else */ { addl(reg, value) ; return; }
3398 }
3399
3400 void MacroAssembler::incrementl(Address dst, int value) {
3401 if (value == min_jint) {addl(dst, value) ; return; }
3402 if (value < 0) { decrementl(dst, -value); return; }
3403 if (value == 0) { ; return; }
3404 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3405 /* else */ { addl(dst, value) ; return; }
3406 }
3407
3408 void MacroAssembler::jump(AddressLiteral dst) {
3409 if (reachable(dst)) {
3410 jmp_literal(dst.target(), dst.rspec());
3411 } else {
3412 lea(rscratch1, dst);
3413 jmp(rscratch1);
3414 }
3415 }
3416
3417 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3418 if (reachable(dst)) {
3419 InstructionMark im(this);
3420 relocate(dst.reloc());
3421 const int short_size = 2;
3422 const int long_size = 6;
3423 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3424 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3425 // 0111 tttn #8-bit disp
3426 emit_int8(0x70 | cc);
3427 emit_int8((offs - short_size) & 0xFF);
3428 } else {
3429 // 0000 1111 1000 tttn #32-bit disp
3430 emit_int8(0x0F);
3431 emit_int8((unsigned char)(0x80 | cc));
3432 emit_int32(offs - long_size);
3433 }
3434 } else {
3435 #ifdef ASSERT
3436 warning("reversing conditional branch");
3437 #endif /* ASSERT */
3438 Label skip;
3439 jccb(reverse[cc], skip);
3440 lea(rscratch1, dst);
3441 Assembler::jmp(rscratch1);
3442 bind(skip);
3443 }
3444 }
3445
3446 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3447 if (reachable(src)) {
3448 Assembler::ldmxcsr(as_Address(src));
3449 } else {
3450 lea(rscratch1, src);
3451 Assembler::ldmxcsr(Address(rscratch1, 0));
3452 }
3453 }
3454
3455 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3456 int off;
3457 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3458 off = offset();
3459 movsbl(dst, src); // movsxb
3460 } else {
3461 off = load_unsigned_byte(dst, src);
3462 shll(dst, 24);
3463 sarl(dst, 24);
3464 }
3465 return off;
3466 }
3467
3468 // Note: load_signed_short used to be called load_signed_word.
3469 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3470 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3471 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3472 int MacroAssembler::load_signed_short(Register dst, Address src) {
3473 int off;
3474 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3475 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3476 // version but this is what 64bit has always done. This seems to imply
3477 // that users are only using 32bits worth.
3478 off = offset();
3479 movswl(dst, src); // movsxw
3480 } else {
3481 off = load_unsigned_short(dst, src);
3482 shll(dst, 16);
3483 sarl(dst, 16);
3484 }
3485 return off;
3486 }
3487
3488 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3489 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3490 // and "3.9 Partial Register Penalties", p. 22).
3491 int off;
3492 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3493 off = offset();
3494 movzbl(dst, src); // movzxb
3495 } else {
3496 xorl(dst, dst);
3497 off = offset();
3498 movb(dst, src);
3499 }
3500 return off;
3501 }
3502
3503 // Note: load_unsigned_short used to be called load_unsigned_word.
3504 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3505 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3506 // and "3.9 Partial Register Penalties", p. 22).
3507 int off;
3508 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3509 off = offset();
3510 movzwl(dst, src); // movzxw
3511 } else {
3512 xorl(dst, dst);
3513 off = offset();
3514 movw(dst, src);
3515 }
3516 return off;
3517 }
3518
3519 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3520 switch (size_in_bytes) {
3521 #ifndef _LP64
3522 case 8:
3523 assert(dst2 != noreg, "second dest register required");
3524 movl(dst, src);
3525 movl(dst2, src.plus_disp(BytesPerInt));
3526 break;
3527 #else
3528 case 8: movq(dst, src); break;
3529 #endif
3530 case 4: movl(dst, src); break;
3531 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3532 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3533 default: ShouldNotReachHere();
3534 }
3535 }
3536
3537 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3538 switch (size_in_bytes) {
3539 #ifndef _LP64
3540 case 8:
3541 assert(src2 != noreg, "second source register required");
3542 movl(dst, src);
3543 movl(dst.plus_disp(BytesPerInt), src2);
3544 break;
3545 #else
3546 case 8: movq(dst, src); break;
3547 #endif
3548 case 4: movl(dst, src); break;
3549 case 2: movw(dst, src); break;
3550 case 1: movb(dst, src); break;
3551 default: ShouldNotReachHere();
3552 }
3553 }
3554
3555 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3556 if (reachable(dst)) {
3557 movl(as_Address(dst), src);
3558 } else {
3559 lea(rscratch1, dst);
3560 movl(Address(rscratch1, 0), src);
3561 }
3562 }
3563
3564 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3565 if (reachable(src)) {
3566 movl(dst, as_Address(src));
3567 } else {
3568 lea(rscratch1, src);
3569 movl(dst, Address(rscratch1, 0));
3570 }
3571 }
3572
3573 // C++ bool manipulation
3574
3575 void MacroAssembler::movbool(Register dst, Address src) {
3576 if(sizeof(bool) == 1)
3577 movb(dst, src);
3578 else if(sizeof(bool) == 2)
3579 movw(dst, src);
3580 else if(sizeof(bool) == 4)
3581 movl(dst, src);
3582 else
3583 // unsupported
3584 ShouldNotReachHere();
3585 }
3586
3587 void MacroAssembler::movbool(Address dst, bool boolconst) {
3588 if(sizeof(bool) == 1)
3589 movb(dst, (int) boolconst);
3590 else if(sizeof(bool) == 2)
3591 movw(dst, (int) boolconst);
3592 else if(sizeof(bool) == 4)
3593 movl(dst, (int) boolconst);
3594 else
3595 // unsupported
3596 ShouldNotReachHere();
3597 }
3598
3599 void MacroAssembler::movbool(Address dst, Register src) {
3600 if(sizeof(bool) == 1)
3601 movb(dst, src);
3602 else if(sizeof(bool) == 2)
3603 movw(dst, src);
3604 else if(sizeof(bool) == 4)
3605 movl(dst, src);
3606 else
3607 // unsupported
3608 ShouldNotReachHere();
3609 }
3610
3611 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3612 movb(as_Address(dst), src);
3613 }
3614
3615 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3616 if (reachable(src)) {
3617 movdl(dst, as_Address(src));
3618 } else {
3619 lea(rscratch1, src);
3620 movdl(dst, Address(rscratch1, 0));
3621 }
3622 }
3623
3624 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3625 if (reachable(src)) {
3626 movq(dst, as_Address(src));
3627 } else {
3628 lea(rscratch1, src);
3629 movq(dst, Address(rscratch1, 0));
3630 }
3631 }
3632
3633 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3634 if (reachable(src)) {
3635 if (UseXmmLoadAndClearUpper) {
3636 movsd (dst, as_Address(src));
3637 } else {
3638 movlpd(dst, as_Address(src));
3639 }
3640 } else {
3641 lea(rscratch1, src);
3642 if (UseXmmLoadAndClearUpper) {
3643 movsd (dst, Address(rscratch1, 0));
3644 } else {
3645 movlpd(dst, Address(rscratch1, 0));
3646 }
3647 }
3648 }
3649
3650 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3651 if (reachable(src)) {
3652 movss(dst, as_Address(src));
3653 } else {
3654 lea(rscratch1, src);
3655 movss(dst, Address(rscratch1, 0));
3656 }
3657 }
3658
3659 void MacroAssembler::movptr(Register dst, Register src) {
3660 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3661 }
3662
3663 void MacroAssembler::movptr(Register dst, Address src) {
3664 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3665 }
3666
3667 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3668 void MacroAssembler::movptr(Register dst, intptr_t src) {
3669 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3670 }
3671
3672 void MacroAssembler::movptr(Address dst, Register src) {
3673 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3674 }
3675
3676 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
3677 if (reachable(src)) {
3678 Assembler::movdqu(dst, as_Address(src));
3679 } else {
3680 lea(rscratch1, src);
3681 Assembler::movdqu(dst, Address(rscratch1, 0));
3682 }
3683 }
3684
3685 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3686 if (reachable(src)) {
3687 Assembler::movdqa(dst, as_Address(src));
3688 } else {
3689 lea(rscratch1, src);
3690 Assembler::movdqa(dst, Address(rscratch1, 0));
3691 }
3692 }
3693
3694 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3695 if (reachable(src)) {
3696 Assembler::movsd(dst, as_Address(src));
3697 } else {
3698 lea(rscratch1, src);
3699 Assembler::movsd(dst, Address(rscratch1, 0));
3700 }
3701 }
3702
3703 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3704 if (reachable(src)) {
3705 Assembler::movss(dst, as_Address(src));
3706 } else {
3707 lea(rscratch1, src);
3708 Assembler::movss(dst, Address(rscratch1, 0));
3709 }
3710 }
3711
3712 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3713 if (reachable(src)) {
3714 Assembler::mulsd(dst, as_Address(src));
3715 } else {
3716 lea(rscratch1, src);
3717 Assembler::mulsd(dst, Address(rscratch1, 0));
3718 }
3719 }
3720
3721 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3722 if (reachable(src)) {
3723 Assembler::mulss(dst, as_Address(src));
3724 } else {
3725 lea(rscratch1, src);
3726 Assembler::mulss(dst, Address(rscratch1, 0));
3727 }
3728 }
3729
3730 void MacroAssembler::null_check(Register reg, int offset) {
3731 if (needs_explicit_null_check(offset)) {
3732 // provoke OS NULL exception if reg = NULL by
3733 // accessing M[reg] w/o changing any (non-CC) registers
3734 // NOTE: cmpl is plenty here to provoke a segv
3735 cmpptr(rax, Address(reg, 0));
3736 // Note: should probably use testl(rax, Address(reg, 0));
3737 // may be shorter code (however, this version of
3738 // testl needs to be implemented first)
3739 } else {
3740 // nothing to do, (later) access of M[reg + offset]
3741 // will provoke OS NULL exception if reg = NULL
3742 }
3743 }
3744
3745 void MacroAssembler::os_breakpoint() {
3746 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3747 // (e.g., MSVC can't call ps() otherwise)
3748 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3749 }
3750
3751 void MacroAssembler::pop_CPU_state() {
3752 pop_FPU_state();
3753 pop_IU_state();
3754 }
3755
3756 void MacroAssembler::pop_FPU_state() {
3757 NOT_LP64(frstor(Address(rsp, 0));)
3758 LP64_ONLY(fxrstor(Address(rsp, 0));)
3759 addptr(rsp, FPUStateSizeInWords * wordSize);
3760 }
3761
3762 void MacroAssembler::pop_IU_state() {
3763 popa();
3764 LP64_ONLY(addq(rsp, 8));
3765 popf();
3766 }
3767
3768 // Save Integer and Float state
3769 // Warning: Stack must be 16 byte aligned (64bit)
3770 void MacroAssembler::push_CPU_state() {
3771 push_IU_state();
3772 push_FPU_state();
3773 }
3774
3775 void MacroAssembler::push_FPU_state() {
3776 subptr(rsp, FPUStateSizeInWords * wordSize);
3777 #ifndef _LP64
3778 fnsave(Address(rsp, 0));
3779 fwait();
3780 #else
3781 fxsave(Address(rsp, 0));
3782 #endif // LP64
3783 }
3784
3785 void MacroAssembler::push_IU_state() {
3786 // Push flags first because pusha kills them
3787 pushf();
3788 // Make sure rsp stays 16-byte aligned
3789 LP64_ONLY(subq(rsp, 8));
3790 pusha();
3791 }
3792
3793 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
3794 // determine java_thread register
3795 if (!java_thread->is_valid()) {
3796 java_thread = rdi;
3797 get_thread(java_thread);
3798 }
3799 // we must set sp to zero to clear frame
3800 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3801 if (clear_fp) {
3802 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3803 }
3804
3805 if (clear_pc)
3806 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3807
3808 }
3809
3810 void MacroAssembler::restore_rax(Register tmp) {
3811 if (tmp == noreg) pop(rax);
3812 else if (tmp != rax) mov(rax, tmp);
3813 }
3814
3815 void MacroAssembler::round_to(Register reg, int modulus) {
3816 addptr(reg, modulus - 1);
3817 andptr(reg, -modulus);
3818 }
3819
3820 void MacroAssembler::save_rax(Register tmp) {
3821 if (tmp == noreg) push(rax);
3822 else if (tmp != rax) mov(tmp, rax);
3823 }
3824
3825 // Write serialization page so VM thread can do a pseudo remote membar.
3826 // We use the current thread pointer to calculate a thread specific
3827 // offset to write to within the page. This minimizes bus traffic
3828 // due to cache line collision.
3829 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3830 movl(tmp, thread);
3831 shrl(tmp, os::get_serialize_page_shift_count());
3832 andl(tmp, (os::vm_page_size() - sizeof(int)));
3833
3834 Address index(noreg, tmp, Address::times_1);
3835 ExternalAddress page(os::get_memory_serialize_page());
3836
3837 // Size of store must match masking code above
3838 movl(as_Address(ArrayAddress(page, index)), tmp);
3839 }
3840
3841 // Calls to C land
3842 //
3843 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3844 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3845 // has to be reset to 0. This is required to allow proper stack traversal.
3846 void MacroAssembler::set_last_Java_frame(Register java_thread,
3847 Register last_java_sp,
3848 Register last_java_fp,
3849 address last_java_pc) {
3850 // determine java_thread register
3851 if (!java_thread->is_valid()) {
3852 java_thread = rdi;
3853 get_thread(java_thread);
3854 }
3855 // determine last_java_sp register
3856 if (!last_java_sp->is_valid()) {
3857 last_java_sp = rsp;
3858 }
3859
3860 // last_java_fp is optional
3861
3862 if (last_java_fp->is_valid()) {
3863 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3864 }
3865
3866 // last_java_pc is optional
3867
3868 if (last_java_pc != NULL) {
3869 lea(Address(java_thread,
3870 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3871 InternalAddress(last_java_pc));
3872
3873 }
3874 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3875 }
3876
3877 void MacroAssembler::shlptr(Register dst, int imm8) {
3878 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3879 }
3880
3881 void MacroAssembler::shrptr(Register dst, int imm8) {
3882 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3883 }
3884
3885 void MacroAssembler::sign_extend_byte(Register reg) {
3886 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3887 movsbl(reg, reg); // movsxb
3888 } else {
3889 shll(reg, 24);
3890 sarl(reg, 24);
3891 }
3892 }
3893
3894 void MacroAssembler::sign_extend_short(Register reg) {
3895 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3896 movswl(reg, reg); // movsxw
3897 } else {
3898 shll(reg, 16);
3899 sarl(reg, 16);
3900 }
3901 }
3902
3903 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3904 assert(reachable(src), "Address should be reachable");
3905 testl(dst, as_Address(src));
3906 }
3907
3908 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3909 if (reachable(src)) {
3910 Assembler::sqrtsd(dst, as_Address(src));
3911 } else {
3912 lea(rscratch1, src);
3913 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3914 }
3915 }
3916
3917 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3918 if (reachable(src)) {
3919 Assembler::sqrtss(dst, as_Address(src));
3920 } else {
3921 lea(rscratch1, src);
3922 Assembler::sqrtss(dst, Address(rscratch1, 0));
3923 }
3924 }
3925
3926 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3927 if (reachable(src)) {
3928 Assembler::subsd(dst, as_Address(src));
3929 } else {
3930 lea(rscratch1, src);
3931 Assembler::subsd(dst, Address(rscratch1, 0));
3932 }
3933 }
3934
3935 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3936 if (reachable(src)) {
3937 Assembler::subss(dst, as_Address(src));
3938 } else {
3939 lea(rscratch1, src);
3940 Assembler::subss(dst, Address(rscratch1, 0));
3941 }
3942 }
3943
3944 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3945 if (reachable(src)) {
3946 Assembler::ucomisd(dst, as_Address(src));
3947 } else {
3948 lea(rscratch1, src);
3949 Assembler::ucomisd(dst, Address(rscratch1, 0));
3950 }
3951 }
3952
3953 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3954 if (reachable(src)) {
3955 Assembler::ucomiss(dst, as_Address(src));
3956 } else {
3957 lea(rscratch1, src);
3958 Assembler::ucomiss(dst, Address(rscratch1, 0));
3959 }
3960 }
3961
3962 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
3963 // Used in sign-bit flipping with aligned address.
3964 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3965 if (reachable(src)) {
3966 Assembler::xorpd(dst, as_Address(src));
3967 } else {
3968 lea(rscratch1, src);
3969 Assembler::xorpd(dst, Address(rscratch1, 0));
3970 }
3971 }
3972
3973 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
3974 // Used in sign-bit flipping with aligned address.
3975 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3976 if (reachable(src)) {
3977 Assembler::xorps(dst, as_Address(src));
3978 } else {
3979 lea(rscratch1, src);
3980 Assembler::xorps(dst, Address(rscratch1, 0));
3981 }
3982 }
3983
3984 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3985 // Used in sign-bit flipping with aligned address.
3986 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3987 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3988 if (reachable(src)) {
3989 Assembler::pshufb(dst, as_Address(src));
3990 } else {
3991 lea(rscratch1, src);
3992 Assembler::pshufb(dst, Address(rscratch1, 0));
3993 }
3994 }
3995
3996 // AVX 3-operands instructions
3997
3998 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3999 if (reachable(src)) {
4000 vaddsd(dst, nds, as_Address(src));
4001 } else {
4002 lea(rscratch1, src);
4003 vaddsd(dst, nds, Address(rscratch1, 0));
4004 }
4005 }
4006
4007 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4008 if (reachable(src)) {
4009 vaddss(dst, nds, as_Address(src));
4010 } else {
4011 lea(rscratch1, src);
4012 vaddss(dst, nds, Address(rscratch1, 0));
4013 }
4014 }
4015
4016 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4017 if (reachable(src)) {
4018 vandpd(dst, nds, as_Address(src), vector256);
4019 } else {
4020 lea(rscratch1, src);
4021 vandpd(dst, nds, Address(rscratch1, 0), vector256);
4022 }
4023 }
4024
4025 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4026 if (reachable(src)) {
4027 vandps(dst, nds, as_Address(src), vector256);
4028 } else {
4029 lea(rscratch1, src);
4030 vandps(dst, nds, Address(rscratch1, 0), vector256);
4031 }
4032 }
4033
4034 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4035 if (reachable(src)) {
4036 vdivsd(dst, nds, as_Address(src));
4037 } else {
4038 lea(rscratch1, src);
4039 vdivsd(dst, nds, Address(rscratch1, 0));
4040 }
4041 }
4042
4043 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4044 if (reachable(src)) {
4045 vdivss(dst, nds, as_Address(src));
4046 } else {
4047 lea(rscratch1, src);
4048 vdivss(dst, nds, Address(rscratch1, 0));
4049 }
4050 }
4051
4052 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4053 if (reachable(src)) {
4054 vmulsd(dst, nds, as_Address(src));
4055 } else {
4056 lea(rscratch1, src);
4057 vmulsd(dst, nds, Address(rscratch1, 0));
4058 }
4059 }
4060
4061 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4062 if (reachable(src)) {
4063 vmulss(dst, nds, as_Address(src));
4064 } else {
4065 lea(rscratch1, src);
4066 vmulss(dst, nds, Address(rscratch1, 0));
4067 }
4068 }
4069
4070 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4071 if (reachable(src)) {
4072 vsubsd(dst, nds, as_Address(src));
4073 } else {
4074 lea(rscratch1, src);
4075 vsubsd(dst, nds, Address(rscratch1, 0));
4076 }
4077 }
4078
4079 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4080 if (reachable(src)) {
4081 vsubss(dst, nds, as_Address(src));
4082 } else {
4083 lea(rscratch1, src);
4084 vsubss(dst, nds, Address(rscratch1, 0));
4085 }
4086 }
4087
4088 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4089 if (reachable(src)) {
4090 vxorpd(dst, nds, as_Address(src), vector256);
4091 } else {
4092 lea(rscratch1, src);
4093 vxorpd(dst, nds, Address(rscratch1, 0), vector256);
4094 }
4095 }
4096
4097 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
4098 if (reachable(src)) {
4099 vxorps(dst, nds, as_Address(src), vector256);
4100 } else {
4101 lea(rscratch1, src);
4102 vxorps(dst, nds, Address(rscratch1, 0), vector256);
4103 }
4104 }
4105
4106
4107 //////////////////////////////////////////////////////////////////////////////////
4108 #if INCLUDE_ALL_GCS
4109
4110 void MacroAssembler::g1_write_barrier_pre(Register obj,
4111 Register pre_val,
4112 Register thread,
4113 Register tmp,
4114 bool tosca_live,
4115 bool expand_call) {
4116
4117 // If expand_call is true then we expand the call_VM_leaf macro
4118 // directly to skip generating the check by
4119 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
4120
4121 #ifdef _LP64
4122 assert(thread == r15_thread, "must be");
4123 #endif // _LP64
4124
4125 Label done;
4126 Label runtime;
4127
4128 assert(pre_val != noreg, "check this code");
4129
4130 if (obj != noreg) {
4131 assert_different_registers(obj, pre_val, tmp);
4132 assert(pre_val != rax, "check this code");
4133 }
4134
4135 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4136 PtrQueue::byte_offset_of_active()));
4137 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4138 PtrQueue::byte_offset_of_index()));
4139 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4140 PtrQueue::byte_offset_of_buf()));
4141
4142
4143 // Is marking active?
4144 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4145 cmpl(in_progress, 0);
4146 } else {
4147 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
4148 cmpb(in_progress, 0);
4149 }
4150 jcc(Assembler::equal, done);
4151
4152 // Do we need to load the previous value?
4153 if (obj != noreg) {
4154 load_heap_oop(pre_val, Address(obj, 0));
4155 }
4156
4157 // Is the previous value null?
4158 cmpptr(pre_val, (int32_t) NULL_WORD);
4159 jcc(Assembler::equal, done);
4160
4161 // Can we store original value in the thread's buffer?
4162 // Is index == 0?
4163 // (The index field is typed as size_t.)
4164
4165 movptr(tmp, index); // tmp := *index_adr
4166 cmpptr(tmp, 0); // tmp == 0?
4167 jcc(Assembler::equal, runtime); // If yes, goto runtime
4168
4169 subptr(tmp, wordSize); // tmp := tmp - wordSize
4170 movptr(index, tmp); // *index_adr := tmp
4171 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
4172
4173 // Record the previous value
4174 movptr(Address(tmp, 0), pre_val);
4175 jmp(done);
4176
4177 bind(runtime);
4178 // save the live input values
4179 if(tosca_live) push(rax);
4180
4181 if (obj != noreg && obj != rax)
4182 push(obj);
4183
4184 if (pre_val != rax)
4185 push(pre_val);
4186
4187 // Calling the runtime using the regular call_VM_leaf mechanism generates
4188 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
4189 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
4190 //
4191 // If we care generating the pre-barrier without a frame (e.g. in the
4192 // intrinsified Reference.get() routine) then ebp might be pointing to
4193 // the caller frame and so this check will most likely fail at runtime.
4194 //
4195 // Expanding the call directly bypasses the generation of the check.
4196 // So when we do not have have a full interpreter frame on the stack
4197 // expand_call should be passed true.
4198
4199 NOT_LP64( push(thread); )
4200
4201 if (expand_call) {
4202 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
4203 pass_arg1(this, thread);
4204 pass_arg0(this, pre_val);
4205 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
4206 } else {
4207 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
4208 }
4209
4210 NOT_LP64( pop(thread); )
4211
4212 // save the live input values
4213 if (pre_val != rax)
4214 pop(pre_val);
4215
4216 if (obj != noreg && obj != rax)
4217 pop(obj);
4218
4219 if(tosca_live) pop(rax);
4220
4221 bind(done);
4222 }
4223
4224 void MacroAssembler::g1_write_barrier_post(Register store_addr,
4225 Register new_val,
4226 Register thread,
4227 Register tmp,
4228 Register tmp2) {
4229 #ifdef _LP64
4230 assert(thread == r15_thread, "must be");
4231 #endif // _LP64
4232
4233 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4234 PtrQueue::byte_offset_of_index()));
4235 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4236 PtrQueue::byte_offset_of_buf()));
4237
4238 CardTableModRefBS* ct =
4239 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
4240 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4241
4242 Label done;
4243 Label runtime;
4244
4245 // Does store cross heap regions?
4246
4247 movptr(tmp, store_addr);
4248 xorptr(tmp, new_val);
4249 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
4250 jcc(Assembler::equal, done);
4251
4252 // crosses regions, storing NULL?
4253
4254 cmpptr(new_val, (int32_t) NULL_WORD);
4255 jcc(Assembler::equal, done);
4256
4257 // storing region crossing non-NULL, is card already dirty?
4258
4259 const Register card_addr = tmp;
4260 const Register cardtable = tmp2;
4261
4262 movptr(card_addr, store_addr);
4263 shrptr(card_addr, CardTableModRefBS::card_shift);
4264 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
4265 // a valid address and therefore is not properly handled by the relocation code.
4266 movptr(cardtable, (intptr_t)ct->byte_map_base);
4267 addptr(card_addr, cardtable);
4268
4269 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
4270 jcc(Assembler::equal, done);
4271
4272 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4273 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4274 jcc(Assembler::equal, done);
4275
4276
4277 // storing a region crossing, non-NULL oop, card is clean.
4278 // dirty card and log.
4279
4280 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4281
4282 cmpl(queue_index, 0);
4283 jcc(Assembler::equal, runtime);
4284 subl(queue_index, wordSize);
4285 movptr(tmp2, buffer);
4286 #ifdef _LP64
4287 movslq(rscratch1, queue_index);
4288 addq(tmp2, rscratch1);
4289 movq(Address(tmp2, 0), card_addr);
4290 #else
4291 addl(tmp2, queue_index);
4292 movl(Address(tmp2, 0), card_addr);
4293 #endif
4294 jmp(done);
4295
4296 bind(runtime);
4297 // save the live input values
4298 push(store_addr);
4299 push(new_val);
4300 #ifdef _LP64
4301 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
4302 #else
4303 push(thread);
4304 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
4305 pop(thread);
4306 #endif
4307 pop(new_val);
4308 pop(store_addr);
4309
4310 bind(done);
4311 }
4312
4313 #endif // INCLUDE_ALL_GCS
4314 //////////////////////////////////////////////////////////////////////////////////
4315
4316
4317 void MacroAssembler::store_check(Register obj) {
4318 // Does a store check for the oop in register obj. The content of
4319 // register obj is destroyed afterwards.
4320 store_check_part_1(obj);
4321 store_check_part_2(obj);
4322 }
4323
4324 void MacroAssembler::store_check(Register obj, Address dst) {
4325 store_check(obj);
4326 }
4327
4328
4329 // split the store check operation so that other instructions can be scheduled inbetween
4330 void MacroAssembler::store_check_part_1(Register obj) {
4331 BarrierSet* bs = Universe::heap()->barrier_set();
4332 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4333 shrptr(obj, CardTableModRefBS::card_shift);
4334 }
4335
4336 void MacroAssembler::store_check_part_2(Register obj) {
4337 BarrierSet* bs = Universe::heap()->barrier_set();
4338 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
4339 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
4340 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4341
4342 // The calculation for byte_map_base is as follows:
4343 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
4344 // So this essentially converts an address to a displacement and it will
4345 // never need to be relocated. On 64bit however the value may be too
4346 // large for a 32bit displacement.
4347 intptr_t disp = (intptr_t) ct->byte_map_base;
4348 if (is_simm32(disp)) {
4349 Address cardtable(noreg, obj, Address::times_1, disp);
4350 movb(cardtable, 0);
4351 } else {
4352 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
4353 // displacement and done in a single instruction given favorable mapping and a
4354 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
4355 // entry and that entry is not properly handled by the relocation code.
4356 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
4357 Address index(noreg, obj, Address::times_1);
4358 movb(as_Address(ArrayAddress(cardtable, index)), 0);
4359 }
4360 }
4361
4362 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4363 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4364 }
4365
4366 // Force generation of a 4 byte immediate value even if it fits into 8bit
4367 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4368 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4369 }
4370
4371 void MacroAssembler::subptr(Register dst, Register src) {
4372 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4373 }
4374
4375 // C++ bool manipulation
4376 void MacroAssembler::testbool(Register dst) {
4377 if(sizeof(bool) == 1)
4378 testb(dst, 0xff);
4379 else if(sizeof(bool) == 2) {
4380 // testw implementation needed for two byte bools
4381 ShouldNotReachHere();
4382 } else if(sizeof(bool) == 4)
4383 testl(dst, dst);
4384 else
4385 // unsupported
4386 ShouldNotReachHere();
4387 }
4388
4389 void MacroAssembler::testptr(Register dst, Register src) {
4390 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4391 }
4392
4393 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4394 void MacroAssembler::tlab_allocate(Register obj,
4395 Register var_size_in_bytes,
4396 int con_size_in_bytes,
4397 Register t1,
4398 Register t2,
4399 Label& slow_case) {
4400 assert_different_registers(obj, t1, t2);
4401 assert_different_registers(obj, var_size_in_bytes, t1);
4402 Register end = t2;
4403 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
4404
4405 verify_tlab();
4406
4407 NOT_LP64(get_thread(thread));
4408
4409 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
4410 if (var_size_in_bytes == noreg) {
4411 lea(end, Address(obj, con_size_in_bytes));
4412 } else {
4413 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
4414 }
4415 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
4416 jcc(Assembler::above, slow_case);
4417
4418 // update the tlab top pointer
4419 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
4420
4421 // recover var_size_in_bytes if necessary
4422 if (var_size_in_bytes == end) {
4423 subptr(var_size_in_bytes, obj);
4424 }
4425 verify_tlab();
4426 }
4427
4428 // Preserves rbx, and rdx.
4429 Register MacroAssembler::tlab_refill(Label& retry,
4430 Label& try_eden,
4431 Label& slow_case) {
4432 Register top = rax;
4433 Register t1 = rcx;
4434 Register t2 = rsi;
4435 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
4436 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
4437 Label do_refill, discard_tlab;
4438
4439 if (!Universe::heap()->supports_inline_contig_alloc()) {
4440 // No allocation in the shared eden.
4441 jmp(slow_case);
4442 }
4443
4444 NOT_LP64(get_thread(thread_reg));
4445
4446 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4447 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4448
4449 // calculate amount of free space
4450 subptr(t1, top);
4451 shrptr(t1, LogHeapWordSize);
4452
4453 // Retain tlab and allocate object in shared space if
4454 // the amount free in the tlab is too large to discard.
4455 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
4456 jcc(Assembler::lessEqual, discard_tlab);
4457
4458 // Retain
4459 // %%% yuck as movptr...
4460 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
4461 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
4462 if (TLABStats) {
4463 // increment number of slow_allocations
4464 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
4465 }
4466 jmp(try_eden);
4467
4468 bind(discard_tlab);
4469 if (TLABStats) {
4470 // increment number of refills
4471 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
4472 // accumulate wastage -- t1 is amount free in tlab
4473 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
4474 }
4475
4476 // if tlab is currently allocated (top or end != null) then
4477 // fill [top, end + alignment_reserve) with array object
4478 testptr(top, top);
4479 jcc(Assembler::zero, do_refill);
4480
4481 // set up the mark word
4482 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
4483 // set the length to the remaining space
4484 subptr(t1, typeArrayOopDesc::header_size(T_INT));
4485 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
4486 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
4487 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
4488 // set klass to intArrayKlass
4489 // dubious reloc why not an oop reloc?
4490 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
4491 // store klass last. concurrent gcs assumes klass length is valid if
4492 // klass field is not null.
4493 store_klass(top, t1);
4494
4495 movptr(t1, top);
4496 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4497 incr_allocated_bytes(thread_reg, t1, 0);
4498
4499 // refill the tlab with an eden allocation
4500 bind(do_refill);
4501 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4502 shlptr(t1, LogHeapWordSize);
4503 // allocate new tlab, address returned in top
4504 eden_allocate(top, t1, 0, t2, slow_case);
4505
4506 // Check that t1 was preserved in eden_allocate.
4507 #ifdef ASSERT
4508 if (UseTLAB) {
4509 Label ok;
4510 Register tsize = rsi;
4511 assert_different_registers(tsize, thread_reg, t1);
4512 push(tsize);
4513 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4514 shlptr(tsize, LogHeapWordSize);
4515 cmpptr(t1, tsize);
4516 jcc(Assembler::equal, ok);
4517 STOP("assert(t1 != tlab size)");
4518 should_not_reach_here();
4519
4520 bind(ok);
4521 pop(tsize);
4522 }
4523 #endif
4524 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
4525 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
4526 addptr(top, t1);
4527 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
4528 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
4529 verify_tlab();
4530 jmp(retry);
4531
4532 return thread_reg; // for use by caller
4533 }
4534
4535 void MacroAssembler::incr_allocated_bytes(Register thread,
4536 Register var_size_in_bytes,
4537 int con_size_in_bytes,
4538 Register t1) {
4539 if (!thread->is_valid()) {
4540 #ifdef _LP64
4541 thread = r15_thread;
4542 #else
4543 assert(t1->is_valid(), "need temp reg");
4544 thread = t1;
4545 get_thread(thread);
4546 #endif
4547 }
4548
4549 #ifdef _LP64
4550 if (var_size_in_bytes->is_valid()) {
4551 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4552 } else {
4553 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4554 }
4555 #else
4556 if (var_size_in_bytes->is_valid()) {
4557 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4558 } else {
4559 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4560 }
4561 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
4562 #endif
4563 }
4564
4565 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
4566 pusha();
4567
4568 // if we are coming from c1, xmm registers may be live
4569 int off = 0;
4570 if (UseSSE == 1) {
4571 subptr(rsp, sizeof(jdouble)*8);
4572 movflt(Address(rsp,off++*sizeof(jdouble)),xmm0);
4573 movflt(Address(rsp,off++*sizeof(jdouble)),xmm1);
4574 movflt(Address(rsp,off++*sizeof(jdouble)),xmm2);
4575 movflt(Address(rsp,off++*sizeof(jdouble)),xmm3);
4576 movflt(Address(rsp,off++*sizeof(jdouble)),xmm4);
4577 movflt(Address(rsp,off++*sizeof(jdouble)),xmm5);
4578 movflt(Address(rsp,off++*sizeof(jdouble)),xmm6);
4579 movflt(Address(rsp,off++*sizeof(jdouble)),xmm7);
4580 } else if (UseSSE >= 2) {
4581 #ifdef COMPILER2
4582 if (MaxVectorSize > 16) {
4583 assert(UseAVX > 0, "256bit vectors are supported only with AVX");
4584 // Save upper half of YMM registes
4585 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4586 vextractf128h(Address(rsp, 0),xmm0);
4587 vextractf128h(Address(rsp, 16),xmm1);
4588 vextractf128h(Address(rsp, 32),xmm2);
4589 vextractf128h(Address(rsp, 48),xmm3);
4590 vextractf128h(Address(rsp, 64),xmm4);
4591 vextractf128h(Address(rsp, 80),xmm5);
4592 vextractf128h(Address(rsp, 96),xmm6);
4593 vextractf128h(Address(rsp,112),xmm7);
4594 #ifdef _LP64
4595 vextractf128h(Address(rsp,128),xmm8);
4596 vextractf128h(Address(rsp,144),xmm9);
4597 vextractf128h(Address(rsp,160),xmm10);
4598 vextractf128h(Address(rsp,176),xmm11);
4599 vextractf128h(Address(rsp,192),xmm12);
4600 vextractf128h(Address(rsp,208),xmm13);
4601 vextractf128h(Address(rsp,224),xmm14);
4602 vextractf128h(Address(rsp,240),xmm15);
4603 #endif
4604 }
4605 #endif
4606 // Save whole 128bit (16 bytes) XMM regiters
4607 subptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4608 movdqu(Address(rsp,off++*16),xmm0);
4609 movdqu(Address(rsp,off++*16),xmm1);
4610 movdqu(Address(rsp,off++*16),xmm2);
4611 movdqu(Address(rsp,off++*16),xmm3);
4612 movdqu(Address(rsp,off++*16),xmm4);
4613 movdqu(Address(rsp,off++*16),xmm5);
4614 movdqu(Address(rsp,off++*16),xmm6);
4615 movdqu(Address(rsp,off++*16),xmm7);
4616 #ifdef _LP64
4617 movdqu(Address(rsp,off++*16),xmm8);
4618 movdqu(Address(rsp,off++*16),xmm9);
4619 movdqu(Address(rsp,off++*16),xmm10);
4620 movdqu(Address(rsp,off++*16),xmm11);
4621 movdqu(Address(rsp,off++*16),xmm12);
4622 movdqu(Address(rsp,off++*16),xmm13);
4623 movdqu(Address(rsp,off++*16),xmm14);
4624 movdqu(Address(rsp,off++*16),xmm15);
4625 #endif
4626 }
4627
4628 // Preserve registers across runtime call
4629 int incoming_argument_and_return_value_offset = -1;
4630 if (num_fpu_regs_in_use > 1) {
4631 // Must preserve all other FPU regs (could alternatively convert
4632 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
4633 // FPU state, but can not trust C compiler)
4634 NEEDS_CLEANUP;
4635 // NOTE that in this case we also push the incoming argument(s) to
4636 // the stack and restore it later; we also use this stack slot to
4637 // hold the return value from dsin, dcos etc.
4638 for (int i = 0; i < num_fpu_regs_in_use; i++) {
4639 subptr(rsp, sizeof(jdouble));
4640 fstp_d(Address(rsp, 0));
4641 }
4642 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
4643 for (int i = nb_args-1; i >= 0; i--) {
4644 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
4645 }
4646 }
4647
4648 subptr(rsp, nb_args*sizeof(jdouble));
4649 for (int i = 0; i < nb_args; i++) {
4650 fstp_d(Address(rsp, i*sizeof(jdouble)));
4651 }
4652
4653 #ifdef _LP64
4654 if (nb_args > 0) {
4655 movdbl(xmm0, Address(rsp, 0));
4656 }
4657 if (nb_args > 1) {
4658 movdbl(xmm1, Address(rsp, sizeof(jdouble)));
4659 }
4660 assert(nb_args <= 2, "unsupported number of args");
4661 #endif // _LP64
4662
4663 // NOTE: we must not use call_VM_leaf here because that requires a
4664 // complete interpreter frame in debug mode -- same bug as 4387334
4665 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
4666 // do proper 64bit abi
4667
4668 NEEDS_CLEANUP;
4669 // Need to add stack banging before this runtime call if it needs to
4670 // be taken; however, there is no generic stack banging routine at
4671 // the MacroAssembler level
4672
4673 MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
4674
4675 #ifdef _LP64
4676 movsd(Address(rsp, 0), xmm0);
4677 fld_d(Address(rsp, 0));
4678 #endif // _LP64
4679 addptr(rsp, sizeof(jdouble) * nb_args);
4680 if (num_fpu_regs_in_use > 1) {
4681 // Must save return value to stack and then restore entire FPU
4682 // stack except incoming arguments
4683 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
4684 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
4685 fld_d(Address(rsp, 0));
4686 addptr(rsp, sizeof(jdouble));
4687 }
4688 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
4689 addptr(rsp, sizeof(jdouble) * nb_args);
4690 }
4691
4692 off = 0;
4693 if (UseSSE == 1) {
4694 movflt(xmm0, Address(rsp,off++*sizeof(jdouble)));
4695 movflt(xmm1, Address(rsp,off++*sizeof(jdouble)));
4696 movflt(xmm2, Address(rsp,off++*sizeof(jdouble)));
4697 movflt(xmm3, Address(rsp,off++*sizeof(jdouble)));
4698 movflt(xmm4, Address(rsp,off++*sizeof(jdouble)));
4699 movflt(xmm5, Address(rsp,off++*sizeof(jdouble)));
4700 movflt(xmm6, Address(rsp,off++*sizeof(jdouble)));
4701 movflt(xmm7, Address(rsp,off++*sizeof(jdouble)));
4702 addptr(rsp, sizeof(jdouble)*8);
4703 } else if (UseSSE >= 2) {
4704 // Restore whole 128bit (16 bytes) XMM regiters
4705 movdqu(xmm0, Address(rsp,off++*16));
4706 movdqu(xmm1, Address(rsp,off++*16));
4707 movdqu(xmm2, Address(rsp,off++*16));
4708 movdqu(xmm3, Address(rsp,off++*16));
4709 movdqu(xmm4, Address(rsp,off++*16));
4710 movdqu(xmm5, Address(rsp,off++*16));
4711 movdqu(xmm6, Address(rsp,off++*16));
4712 movdqu(xmm7, Address(rsp,off++*16));
4713 #ifdef _LP64
4714 movdqu(xmm8, Address(rsp,off++*16));
4715 movdqu(xmm9, Address(rsp,off++*16));
4716 movdqu(xmm10, Address(rsp,off++*16));
4717 movdqu(xmm11, Address(rsp,off++*16));
4718 movdqu(xmm12, Address(rsp,off++*16));
4719 movdqu(xmm13, Address(rsp,off++*16));
4720 movdqu(xmm14, Address(rsp,off++*16));
4721 movdqu(xmm15, Address(rsp,off++*16));
4722 #endif
4723 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4724 #ifdef COMPILER2
4725 if (MaxVectorSize > 16) {
4726 // Restore upper half of YMM registes.
4727 vinsertf128h(xmm0, Address(rsp, 0));
4728 vinsertf128h(xmm1, Address(rsp, 16));
4729 vinsertf128h(xmm2, Address(rsp, 32));
4730 vinsertf128h(xmm3, Address(rsp, 48));
4731 vinsertf128h(xmm4, Address(rsp, 64));
4732 vinsertf128h(xmm5, Address(rsp, 80));
4733 vinsertf128h(xmm6, Address(rsp, 96));
4734 vinsertf128h(xmm7, Address(rsp,112));
4735 #ifdef _LP64
4736 vinsertf128h(xmm8, Address(rsp,128));
4737 vinsertf128h(xmm9, Address(rsp,144));
4738 vinsertf128h(xmm10, Address(rsp,160));
4739 vinsertf128h(xmm11, Address(rsp,176));
4740 vinsertf128h(xmm12, Address(rsp,192));
4741 vinsertf128h(xmm13, Address(rsp,208));
4742 vinsertf128h(xmm14, Address(rsp,224));
4743 vinsertf128h(xmm15, Address(rsp,240));
4744 #endif
4745 addptr(rsp, 16 * LP64_ONLY(16) NOT_LP64(8));
4746 }
4747 #endif
4748 }
4749 popa();
4750 }
4751
4752 static const double pi_4 = 0.7853981633974483;
4753
4754 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
4755 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
4756 // was attempted in this code; unfortunately it appears that the
4757 // switch to 80-bit precision and back causes this to be
4758 // unprofitable compared with simply performing a runtime call if
4759 // the argument is out of the (-pi/4, pi/4) range.
4760
4761 Register tmp = noreg;
4762 if (!VM_Version::supports_cmov()) {
4763 // fcmp needs a temporary so preserve rbx,
4764 tmp = rbx;
4765 push(tmp);
4766 }
4767
4768 Label slow_case, done;
4769
4770 ExternalAddress pi4_adr = (address)&pi_4;
4771 if (reachable(pi4_adr)) {
4772 // x ?<= pi/4
4773 fld_d(pi4_adr);
4774 fld_s(1); // Stack: X PI/4 X
4775 fabs(); // Stack: |X| PI/4 X
4776 fcmp(tmp);
4777 jcc(Assembler::above, slow_case);
4778
4779 // fastest case: -pi/4 <= x <= pi/4
4780 switch(trig) {
4781 case 's':
4782 fsin();
4783 break;
4784 case 'c':
4785 fcos();
4786 break;
4787 case 't':
4788 ftan();
4789 break;
4790 default:
4791 assert(false, "bad intrinsic");
4792 break;
4793 }
4794 jmp(done);
4795 }
4796
4797 // slow case: runtime call
4798 bind(slow_case);
4799
4800 switch(trig) {
4801 case 's':
4802 {
4803 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
4804 }
4805 break;
4806 case 'c':
4807 {
4808 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
4809 }
4810 break;
4811 case 't':
4812 {
4813 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
4814 }
4815 break;
4816 default:
4817 assert(false, "bad intrinsic");
4818 break;
4819 }
4820
4821 // Come here with result in F-TOS
4822 bind(done);
4823
4824 if (tmp != noreg) {
4825 pop(tmp);
4826 }
4827 }
4828
4829
4830 // Look up the method for a megamorphic invokeinterface call.
4831 // The target method is determined by <intf_klass, itable_index>.
4832 // The receiver klass is in recv_klass.
4833 // On success, the result will be in method_result, and execution falls through.
4834 // On failure, execution transfers to the given label.
4835 void MacroAssembler::lookup_interface_method(Register recv_klass,
4836 Register intf_klass,
4837 RegisterOrConstant itable_index,
4838 Register method_result,
4839 Register scan_temp,
4840 Label& L_no_such_interface) {
4841 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
4842 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4843 "caller must use same register for non-constant itable index as for method");
4844
4845 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4846 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
4847 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4848 int scan_step = itableOffsetEntry::size() * wordSize;
4849 int vte_size = vtableEntry::size() * wordSize;
4850 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4851 assert(vte_size == wordSize, "else adjust times_vte_scale");
4852
4853 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
4854
4855 // %%% Could store the aligned, prescaled offset in the klassoop.
4856 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4857 if (HeapWordsPerLong > 1) {
4858 // Round up to align_object_offset boundary
4859 // see code for InstanceKlass::start_of_itable!
4860 round_to(scan_temp, BytesPerLong);
4861 }
4862
4863 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4864 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4865 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4866
4867 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4868 // if (scan->interface() == intf) {
4869 // result = (klass + scan->offset() + itable_index);
4870 // }
4871 // }
4872 Label search, found_method;
4873
4874 for (int peel = 1; peel >= 0; peel--) {
4875 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4876 cmpptr(intf_klass, method_result);
4877
4878 if (peel) {
4879 jccb(Assembler::equal, found_method);
4880 } else {
4881 jccb(Assembler::notEqual, search);
4882 // (invert the test to fall through to found_method...)
4883 }
4884
4885 if (!peel) break;
4886
4887 bind(search);
4888
4889 // Check that the previous entry is non-null. A null entry means that
4890 // the receiver class doesn't implement the interface, and wasn't the
4891 // same as when the caller was compiled.
4892 testptr(method_result, method_result);
4893 jcc(Assembler::zero, L_no_such_interface);
4894 addptr(scan_temp, scan_step);
4895 }
4896
4897 bind(found_method);
4898
4899 // Got a hit.
4900 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4901 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4902 }
4903
4904
4905 // virtual method calling
4906 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4907 RegisterOrConstant vtable_index,
4908 Register method_result) {
4909 const int base = InstanceKlass::vtable_start_offset() * wordSize;
4910 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4911 Address vtable_entry_addr(recv_klass,
4912 vtable_index, Address::times_ptr,
4913 base + vtableEntry::method_offset_in_bytes());
4914 movptr(method_result, vtable_entry_addr);
4915 }
4916
4917
4918 void MacroAssembler::check_klass_subtype(Register sub_klass,
4919 Register super_klass,
4920 Register temp_reg,
4921 Label& L_success) {
4922 Label L_failure;
4923 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
4924 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4925 bind(L_failure);
4926 }
4927
4928
4929 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4930 Register super_klass,
4931 Register temp_reg,
4932 Label* L_success,
4933 Label* L_failure,
4934 Label* L_slow_path,
4935 RegisterOrConstant super_check_offset) {
4936 assert_different_registers(sub_klass, super_klass, temp_reg);
4937 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4938 if (super_check_offset.is_register()) {
4939 assert_different_registers(sub_klass, super_klass,
4940 super_check_offset.as_register());
4941 } else if (must_load_sco) {
4942 assert(temp_reg != noreg, "supply either a temp or a register offset");
4943 }
4944
4945 Label L_fallthrough;
4946 int label_nulls = 0;
4947 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4948 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4949 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4950 assert(label_nulls <= 1, "at most one NULL in the batch");
4951
4952 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4953 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4954 Address super_check_offset_addr(super_klass, sco_offset);
4955
4956 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4957 // range of a jccb. If this routine grows larger, reconsider at
4958 // least some of these.
4959 #define local_jcc(assembler_cond, label) \
4960 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4961 else jcc( assembler_cond, label) /*omit semi*/
4962
4963 // Hacked jmp, which may only be used just before L_fallthrough.
4964 #define final_jmp(label) \
4965 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4966 else jmp(label) /*omit semi*/
4967
4968 // If the pointers are equal, we are done (e.g., String[] elements).
4969 // This self-check enables sharing of secondary supertype arrays among
4970 // non-primary types such as array-of-interface. Otherwise, each such
4971 // type would need its own customized SSA.
4972 // We move this check to the front of the fast path because many
4973 // type checks are in fact trivially successful in this manner,
4974 // so we get a nicely predicted branch right at the start of the check.
4975 cmpptr(sub_klass, super_klass);
4976 local_jcc(Assembler::equal, *L_success);
4977
4978 // Check the supertype display:
4979 if (must_load_sco) {
4980 // Positive movl does right thing on LP64.
4981 movl(temp_reg, super_check_offset_addr);
4982 super_check_offset = RegisterOrConstant(temp_reg);
4983 }
4984 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4985 cmpptr(super_klass, super_check_addr); // load displayed supertype
4986
4987 // This check has worked decisively for primary supers.
4988 // Secondary supers are sought in the super_cache ('super_cache_addr').
4989 // (Secondary supers are interfaces and very deeply nested subtypes.)
4990 // This works in the same check above because of a tricky aliasing
4991 // between the super_cache and the primary super display elements.
4992 // (The 'super_check_addr' can address either, as the case requires.)
4993 // Note that the cache is updated below if it does not help us find
4994 // what we need immediately.
4995 // So if it was a primary super, we can just fail immediately.
4996 // Otherwise, it's the slow path for us (no success at this point).
4997
4998 if (super_check_offset.is_register()) {
4999 local_jcc(Assembler::equal, *L_success);
5000 cmpl(super_check_offset.as_register(), sc_offset);
5001 if (L_failure == &L_fallthrough) {
5002 local_jcc(Assembler::equal, *L_slow_path);
5003 } else {
5004 local_jcc(Assembler::notEqual, *L_failure);
5005 final_jmp(*L_slow_path);
5006 }
5007 } else if (super_check_offset.as_constant() == sc_offset) {
5008 // Need a slow path; fast failure is impossible.
5009 if (L_slow_path == &L_fallthrough) {
5010 local_jcc(Assembler::equal, *L_success);
5011 } else {
5012 local_jcc(Assembler::notEqual, *L_slow_path);
5013 final_jmp(*L_success);
5014 }
5015 } else {
5016 // No slow path; it's a fast decision.
5017 if (L_failure == &L_fallthrough) {
5018 local_jcc(Assembler::equal, *L_success);
5019 } else {
5020 local_jcc(Assembler::notEqual, *L_failure);
5021 final_jmp(*L_success);
5022 }
5023 }
5024
5025 bind(L_fallthrough);
5026
5027 #undef local_jcc
5028 #undef final_jmp
5029 }
5030
5031
5032 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5033 Register super_klass,
5034 Register temp_reg,
5035 Register temp2_reg,
5036 Label* L_success,
5037 Label* L_failure,
5038 bool set_cond_codes) {
5039 assert_different_registers(sub_klass, super_klass, temp_reg);
5040 if (temp2_reg != noreg)
5041 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5042 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5043
5044 Label L_fallthrough;
5045 int label_nulls = 0;
5046 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5047 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5048 assert(label_nulls <= 1, "at most one NULL in the batch");
5049
5050 // a couple of useful fields in sub_klass:
5051 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5052 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5053 Address secondary_supers_addr(sub_klass, ss_offset);
5054 Address super_cache_addr( sub_klass, sc_offset);
5055
5056 // Do a linear scan of the secondary super-klass chain.
5057 // This code is rarely used, so simplicity is a virtue here.
5058 // The repne_scan instruction uses fixed registers, which we must spill.
5059 // Don't worry too much about pre-existing connections with the input regs.
5060
5061 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5062 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5063
5064 // Get super_klass value into rax (even if it was in rdi or rcx).
5065 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5066 if (super_klass != rax || UseCompressedOops) {
5067 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5068 mov(rax, super_klass);
5069 }
5070 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5071 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5072
5073 #ifndef PRODUCT
5074 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5075 ExternalAddress pst_counter_addr((address) pst_counter);
5076 NOT_LP64( incrementl(pst_counter_addr) );
5077 LP64_ONLY( lea(rcx, pst_counter_addr) );
5078 LP64_ONLY( incrementl(Address(rcx, 0)) );
5079 #endif //PRODUCT
5080
5081 // We will consult the secondary-super array.
5082 movptr(rdi, secondary_supers_addr);
5083 // Load the array length. (Positive movl does right thing on LP64.)
5084 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5085 // Skip to start of data.
5086 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5087
5088 // Scan RCX words at [RDI] for an occurrence of RAX.
5089 // Set NZ/Z based on last compare.
5090 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5091 // not change flags (only scas instruction which is repeated sets flags).
5092 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5093
5094 testptr(rax,rax); // Set Z = 0
5095 repne_scan();
5096
5097 // Unspill the temp. registers:
5098 if (pushed_rdi) pop(rdi);
5099 if (pushed_rcx) pop(rcx);
5100 if (pushed_rax) pop(rax);
5101
5102 if (set_cond_codes) {
5103 // Special hack for the AD files: rdi is guaranteed non-zero.
5104 assert(!pushed_rdi, "rdi must be left non-NULL");
5105 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5106 }
5107
5108 if (L_failure == &L_fallthrough)
5109 jccb(Assembler::notEqual, *L_failure);
5110 else jcc(Assembler::notEqual, *L_failure);
5111
5112 // Success. Cache the super we found and proceed in triumph.
5113 movptr(super_cache_addr, super_klass);
5114
5115 if (L_success != &L_fallthrough) {
5116 jmp(*L_success);
5117 }
5118
5119 #undef IS_A_TEMP
5120
5121 bind(L_fallthrough);
5122 }
5123
5124
5125 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5126 if (VM_Version::supports_cmov()) {
5127 cmovl(cc, dst, src);
5128 } else {
5129 Label L;
5130 jccb(negate_condition(cc), L);
5131 movl(dst, src);
5132 bind(L);
5133 }
5134 }
5135
5136 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5137 if (VM_Version::supports_cmov()) {
5138 cmovl(cc, dst, src);
5139 } else {
5140 Label L;
5141 jccb(negate_condition(cc), L);
5142 movl(dst, src);
5143 bind(L);
5144 }
5145 }
5146
5147 void MacroAssembler::verify_oop(Register reg, const char* s) {
5148 if (!VerifyOops) return;
5149
5150 // Pass register number to verify_oop_subroutine
5151 const char* b = NULL;
5152 {
5153 ResourceMark rm;
5154 stringStream ss;
5155 ss.print("verify_oop: %s: %s", reg->name(), s);
5156 b = code_string(ss.as_string());
5157 }
5158 BLOCK_COMMENT("verify_oop {");
5159 #ifdef _LP64
5160 push(rscratch1); // save r10, trashed by movptr()
5161 #endif
5162 push(rax); // save rax,
5163 push(reg); // pass register argument
5164 ExternalAddress buffer((address) b);
5165 // avoid using pushptr, as it modifies scratch registers
5166 // and our contract is not to modify anything
5167 movptr(rax, buffer.addr());
5168 push(rax);
5169 // call indirectly to solve generation ordering problem
5170 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5171 call(rax);
5172 // Caller pops the arguments (oop, message) and restores rax, r10
5173 BLOCK_COMMENT("} verify_oop");
5174 }
5175
5176
5177 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5178 Register tmp,
5179 int offset) {
5180 intptr_t value = *delayed_value_addr;
5181 if (value != 0)
5182 return RegisterOrConstant(value + offset);
5183
5184 // load indirectly to solve generation ordering problem
5185 movptr(tmp, ExternalAddress((address) delayed_value_addr));
5186
5187 #ifdef ASSERT
5188 { Label L;
5189 testptr(tmp, tmp);
5190 if (WizardMode) {
5191 const char* buf = NULL;
5192 {
5193 ResourceMark rm;
5194 stringStream ss;
5195 ss.print("DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]);
5196 buf = code_string(ss.as_string());
5197 }
5198 jcc(Assembler::notZero, L);
5199 STOP(buf);
5200 } else {
5201 jccb(Assembler::notZero, L);
5202 hlt();
5203 }
5204 bind(L);
5205 }
5206 #endif
5207
5208 if (offset != 0)
5209 addptr(tmp, offset);
5210
5211 return RegisterOrConstant(tmp);
5212 }
5213
5214
5215 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5216 int extra_slot_offset) {
5217 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5218 int stackElementSize = Interpreter::stackElementSize;
5219 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5220 #ifdef ASSERT
5221 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5222 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5223 #endif
5224 Register scale_reg = noreg;
5225 Address::ScaleFactor scale_factor = Address::no_scale;
5226 if (arg_slot.is_constant()) {
5227 offset += arg_slot.as_constant() * stackElementSize;
5228 } else {
5229 scale_reg = arg_slot.as_register();
5230 scale_factor = Address::times(stackElementSize);
5231 }
5232 offset += wordSize; // return PC is on stack
5233 return Address(rsp, scale_reg, scale_factor, offset);
5234 }
5235
5236
5237 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
5238 if (!VerifyOops) return;
5239
5240 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
5241 // Pass register number to verify_oop_subroutine
5242 const char* b = NULL;
5243 {
5244 ResourceMark rm;
5245 stringStream ss;
5246 ss.print("verify_oop_addr: %s", s);
5247 b = code_string(ss.as_string());
5248 }
5249 #ifdef _LP64
5250 push(rscratch1); // save r10, trashed by movptr()
5251 #endif
5252 push(rax); // save rax,
5253 // addr may contain rsp so we will have to adjust it based on the push
5254 // we just did (and on 64 bit we do two pushes)
5255 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5256 // stores rax into addr which is backwards of what was intended.
5257 if (addr.uses(rsp)) {
5258 lea(rax, addr);
5259 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5260 } else {
5261 pushptr(addr);
5262 }
5263
5264 ExternalAddress buffer((address) b);
5265 // pass msg argument
5266 // avoid using pushptr, as it modifies scratch registers
5267 // and our contract is not to modify anything
5268 movptr(rax, buffer.addr());
5269 push(rax);
5270
5271 // call indirectly to solve generation ordering problem
5272 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5273 call(rax);
5274 // Caller pops the arguments (addr, message) and restores rax, r10.
5275 }
5276
5277 void MacroAssembler::verify_tlab() {
5278 #ifdef ASSERT
5279 if (UseTLAB && VerifyOops) {
5280 Label next, ok;
5281 Register t1 = rsi;
5282 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5283
5284 push(t1);
5285 NOT_LP64(push(thread_reg));
5286 NOT_LP64(get_thread(thread_reg));
5287
5288 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5289 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5290 jcc(Assembler::aboveEqual, next);
5291 STOP("assert(top >= start)");
5292 should_not_reach_here();
5293
5294 bind(next);
5295 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5296 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5297 jcc(Assembler::aboveEqual, ok);
5298 STOP("assert(top <= end)");
5299 should_not_reach_here();
5300
5301 bind(ok);
5302 NOT_LP64(pop(thread_reg));
5303 pop(t1);
5304 }
5305 #endif
5306 }
5307
5308 class ControlWord {
5309 public:
5310 int32_t _value;
5311
5312 int rounding_control() const { return (_value >> 10) & 3 ; }
5313 int precision_control() const { return (_value >> 8) & 3 ; }
5314 bool precision() const { return ((_value >> 5) & 1) != 0; }
5315 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5316 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5317 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5318 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5319 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5320
5321 void print() const {
5322 // rounding control
5323 const char* rc;
5324 switch (rounding_control()) {
5325 case 0: rc = "round near"; break;
5326 case 1: rc = "round down"; break;
5327 case 2: rc = "round up "; break;
5328 case 3: rc = "chop "; break;
5329 };
5330 // precision control
5331 const char* pc;
5332 switch (precision_control()) {
5333 case 0: pc = "24 bits "; break;
5334 case 1: pc = "reserved"; break;
5335 case 2: pc = "53 bits "; break;
5336 case 3: pc = "64 bits "; break;
5337 };
5338 // flags
5339 char f[9];
5340 f[0] = ' ';
5341 f[1] = ' ';
5342 f[2] = (precision ()) ? 'P' : 'p';
5343 f[3] = (underflow ()) ? 'U' : 'u';
5344 f[4] = (overflow ()) ? 'O' : 'o';
5345 f[5] = (zero_divide ()) ? 'Z' : 'z';
5346 f[6] = (denormalized()) ? 'D' : 'd';
5347 f[7] = (invalid ()) ? 'I' : 'i';
5348 f[8] = '\x0';
5349 // output
5350 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5351 }
5352
5353 };
5354
5355 class StatusWord {
5356 public:
5357 int32_t _value;
5358
5359 bool busy() const { return ((_value >> 15) & 1) != 0; }
5360 bool C3() const { return ((_value >> 14) & 1) != 0; }
5361 bool C2() const { return ((_value >> 10) & 1) != 0; }
5362 bool C1() const { return ((_value >> 9) & 1) != 0; }
5363 bool C0() const { return ((_value >> 8) & 1) != 0; }
5364 int top() const { return (_value >> 11) & 7 ; }
5365 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5366 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5367 bool precision() const { return ((_value >> 5) & 1) != 0; }
5368 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5369 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5370 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5371 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5372 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5373
5374 void print() const {
5375 // condition codes
5376 char c[5];
5377 c[0] = (C3()) ? '3' : '-';
5378 c[1] = (C2()) ? '2' : '-';
5379 c[2] = (C1()) ? '1' : '-';
5380 c[3] = (C0()) ? '0' : '-';
5381 c[4] = '\x0';
5382 // flags
5383 char f[9];
5384 f[0] = (error_status()) ? 'E' : '-';
5385 f[1] = (stack_fault ()) ? 'S' : '-';
5386 f[2] = (precision ()) ? 'P' : '-';
5387 f[3] = (underflow ()) ? 'U' : '-';
5388 f[4] = (overflow ()) ? 'O' : '-';
5389 f[5] = (zero_divide ()) ? 'Z' : '-';
5390 f[6] = (denormalized()) ? 'D' : '-';
5391 f[7] = (invalid ()) ? 'I' : '-';
5392 f[8] = '\x0';
5393 // output
5394 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5395 }
5396
5397 };
5398
5399 class TagWord {
5400 public:
5401 int32_t _value;
5402
5403 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5404
5405 void print() const {
5406 printf("%04x", _value & 0xFFFF);
5407 }
5408
5409 };
5410
5411 class FPU_Register {
5412 public:
5413 int32_t _m0;
5414 int32_t _m1;
5415 int16_t _ex;
5416
5417 bool is_indefinite() const {
5418 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5419 }
5420
5421 void print() const {
5422 char sign = (_ex < 0) ? '-' : '+';
5423 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5424 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5425 };
5426
5427 };
5428
5429 class FPU_State {
5430 public:
5431 enum {
5432 register_size = 10,
5433 number_of_registers = 8,
5434 register_mask = 7
5435 };
5436
5437 ControlWord _control_word;
5438 StatusWord _status_word;
5439 TagWord _tag_word;
5440 int32_t _error_offset;
5441 int32_t _error_selector;
5442 int32_t _data_offset;
5443 int32_t _data_selector;
5444 int8_t _register[register_size * number_of_registers];
5445
5446 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5447 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5448
5449 const char* tag_as_string(int tag) const {
5450 switch (tag) {
5451 case 0: return "valid";
5452 case 1: return "zero";
5453 case 2: return "special";
5454 case 3: return "empty";
5455 }
5456 ShouldNotReachHere();
5457 return NULL;
5458 }
5459
5460 void print() const {
5461 // print computation registers
5462 { int t = _status_word.top();
5463 for (int i = 0; i < number_of_registers; i++) {
5464 int j = (i - t) & register_mask;
5465 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5466 st(j)->print();
5467 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5468 }
5469 }
5470 printf("\n");
5471 // print control registers
5472 printf("ctrl = "); _control_word.print(); printf("\n");
5473 printf("stat = "); _status_word .print(); printf("\n");
5474 printf("tags = "); _tag_word .print(); printf("\n");
5475 }
5476
5477 };
5478
5479 class Flag_Register {
5480 public:
5481 int32_t _value;
5482
5483 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5484 bool direction() const { return ((_value >> 10) & 1) != 0; }
5485 bool sign() const { return ((_value >> 7) & 1) != 0; }
5486 bool zero() const { return ((_value >> 6) & 1) != 0; }
5487 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5488 bool parity() const { return ((_value >> 2) & 1) != 0; }
5489 bool carry() const { return ((_value >> 0) & 1) != 0; }
5490
5491 void print() const {
5492 // flags
5493 char f[8];
5494 f[0] = (overflow ()) ? 'O' : '-';
5495 f[1] = (direction ()) ? 'D' : '-';
5496 f[2] = (sign ()) ? 'S' : '-';
5497 f[3] = (zero ()) ? 'Z' : '-';
5498 f[4] = (auxiliary_carry()) ? 'A' : '-';
5499 f[5] = (parity ()) ? 'P' : '-';
5500 f[6] = (carry ()) ? 'C' : '-';
5501 f[7] = '\x0';
5502 // output
5503 printf("%08x flags = %s", _value, f);
5504 }
5505
5506 };
5507
5508 class IU_Register {
5509 public:
5510 int32_t _value;
5511
5512 void print() const {
5513 printf("%08x %11d", _value, _value);
5514 }
5515
5516 };
5517
5518 class IU_State {
5519 public:
5520 Flag_Register _eflags;
5521 IU_Register _rdi;
5522 IU_Register _rsi;
5523 IU_Register _rbp;
5524 IU_Register _rsp;
5525 IU_Register _rbx;
5526 IU_Register _rdx;
5527 IU_Register _rcx;
5528 IU_Register _rax;
5529
5530 void print() const {
5531 // computation registers
5532 printf("rax, = "); _rax.print(); printf("\n");
5533 printf("rbx, = "); _rbx.print(); printf("\n");
5534 printf("rcx = "); _rcx.print(); printf("\n");
5535 printf("rdx = "); _rdx.print(); printf("\n");
5536 printf("rdi = "); _rdi.print(); printf("\n");
5537 printf("rsi = "); _rsi.print(); printf("\n");
5538 printf("rbp, = "); _rbp.print(); printf("\n");
5539 printf("rsp = "); _rsp.print(); printf("\n");
5540 printf("\n");
5541 // control registers
5542 printf("flgs = "); _eflags.print(); printf("\n");
5543 }
5544 };
5545
5546
5547 class CPU_State {
5548 public:
5549 FPU_State _fpu_state;
5550 IU_State _iu_state;
5551
5552 void print() const {
5553 printf("--------------------------------------------------\n");
5554 _iu_state .print();
5555 printf("\n");
5556 _fpu_state.print();
5557 printf("--------------------------------------------------\n");
5558 }
5559
5560 };
5561
5562
5563 static void _print_CPU_state(CPU_State* state) {
5564 state->print();
5565 };
5566
5567
5568 void MacroAssembler::print_CPU_state() {
5569 push_CPU_state();
5570 push(rsp); // pass CPU state
5571 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5572 addptr(rsp, wordSize); // discard argument
5573 pop_CPU_state();
5574 }
5575
5576
5577 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5578 static int counter = 0;
5579 FPU_State* fs = &state->_fpu_state;
5580 counter++;
5581 // For leaf calls, only verify that the top few elements remain empty.
5582 // We only need 1 empty at the top for C2 code.
5583 if( stack_depth < 0 ) {
5584 if( fs->tag_for_st(7) != 3 ) {
5585 printf("FPR7 not empty\n");
5586 state->print();
5587 assert(false, "error");
5588 return false;
5589 }
5590 return true; // All other stack states do not matter
5591 }
5592
5593 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5594 "bad FPU control word");
5595
5596 // compute stack depth
5597 int i = 0;
5598 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5599 int d = i;
5600 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5601 // verify findings
5602 if (i != FPU_State::number_of_registers) {
5603 // stack not contiguous
5604 printf("%s: stack not contiguous at ST%d\n", s, i);
5605 state->print();
5606 assert(false, "error");
5607 return false;
5608 }
5609 // check if computed stack depth corresponds to expected stack depth
5610 if (stack_depth < 0) {
5611 // expected stack depth is -stack_depth or less
5612 if (d > -stack_depth) {
5613 // too many elements on the stack
5614 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5615 state->print();
5616 assert(false, "error");
5617 return false;
5618 }
5619 } else {
5620 // expected stack depth is stack_depth
5621 if (d != stack_depth) {
5622 // wrong stack depth
5623 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5624 state->print();
5625 assert(false, "error");
5626 return false;
5627 }
5628 }
5629 // everything is cool
5630 return true;
5631 }
5632
5633
5634 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5635 if (!VerifyFPU) return;
5636 push_CPU_state();
5637 push(rsp); // pass CPU state
5638 ExternalAddress msg((address) s);
5639 // pass message string s
5640 pushptr(msg.addr());
5641 push(stack_depth); // pass stack depth
5642 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5643 addptr(rsp, 3 * wordSize); // discard arguments
5644 // check for error
5645 { Label L;
5646 testl(rax, rax);
5647 jcc(Assembler::notZero, L);
5648 int3(); // break if error condition
5649 bind(L);
5650 }
5651 pop_CPU_state();
5652 }
5653
5654 void MacroAssembler::restore_cpu_control_state_after_jni() {
5655 // Either restore the MXCSR register after returning from the JNI Call
5656 // or verify that it wasn't changed (with -Xcheck:jni flag).
5657 if (VM_Version::supports_sse()) {
5658 if (RestoreMXCSROnJNICalls) {
5659 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5660 } else if (CheckJNICalls) {
5661 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5662 }
5663 }
5664 if (VM_Version::supports_avx()) {
5665 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5666 vzeroupper();
5667 }
5668
5669 #ifndef _LP64
5670 // Either restore the x87 floating pointer control word after returning
5671 // from the JNI call or verify that it wasn't changed.
5672 if (CheckJNICalls) {
5673 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5674 }
5675 #endif // _LP64
5676 }
5677
5678
5679 void MacroAssembler::load_klass(Register dst, Register src) {
5680 #ifdef _LP64
5681 if (UseCompressedClassPointers) {
5682 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5683 decode_klass_not_null(dst);
5684 } else
5685 #endif
5686 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5687 }
5688
5689 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5690 load_klass(dst, src);
5691 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5692 }
5693
5694 void MacroAssembler::store_klass(Register dst, Register src) {
5695 #ifdef _LP64
5696 if (UseCompressedClassPointers) {
5697 encode_klass_not_null(src);
5698 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5699 } else
5700 #endif
5701 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5702 }
5703
5704 void MacroAssembler::load_heap_oop(Register dst, Address src) {
5705 #ifdef _LP64
5706 // FIXME: Must change all places where we try to load the klass.
5707 if (UseCompressedOops) {
5708 movl(dst, src);
5709 decode_heap_oop(dst);
5710 } else
5711 #endif
5712 movptr(dst, src);
5713 }
5714
5715 // Doesn't do verfication, generates fixed size code
5716 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
5717 #ifdef _LP64
5718 if (UseCompressedOops) {
5719 movl(dst, src);
5720 decode_heap_oop_not_null(dst);
5721 } else
5722 #endif
5723 movptr(dst, src);
5724 }
5725
5726 void MacroAssembler::store_heap_oop(Address dst, Register src) {
5727 #ifdef _LP64
5728 if (UseCompressedOops) {
5729 assert(!dst.uses(src), "not enough registers");
5730 encode_heap_oop(src);
5731 movl(dst, src);
5732 } else
5733 #endif
5734 movptr(dst, src);
5735 }
5736
5737 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
5738 assert_different_registers(src1, tmp);
5739 #ifdef _LP64
5740 if (UseCompressedOops) {
5741 bool did_push = false;
5742 if (tmp == noreg) {
5743 tmp = rax;
5744 push(tmp);
5745 did_push = true;
5746 assert(!src2.uses(rsp), "can't push");
5747 }
5748 load_heap_oop(tmp, src2);
5749 cmpptr(src1, tmp);
5750 if (did_push) pop(tmp);
5751 } else
5752 #endif
5753 cmpptr(src1, src2);
5754 }
5755
5756 // Used for storing NULLs.
5757 void MacroAssembler::store_heap_oop_null(Address dst) {
5758 #ifdef _LP64
5759 if (UseCompressedOops) {
5760 movl(dst, (int32_t)NULL_WORD);
5761 } else {
5762 movslq(dst, (int32_t)NULL_WORD);
5763 }
5764 #else
5765 movl(dst, (int32_t)NULL_WORD);
5766 #endif
5767 }
5768
5769 #ifdef _LP64
5770 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5771 if (UseCompressedClassPointers) {
5772 // Store to klass gap in destination
5773 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5774 }
5775 }
5776
5777 #ifdef ASSERT
5778 void MacroAssembler::verify_heapbase(const char* msg) {
5779 assert (UseCompressedOops, "should be compressed");
5780 assert (Universe::heap() != NULL, "java heap should be initialized");
5781 if (CheckCompressedOops) {
5782 Label ok;
5783 push(rscratch1); // cmpptr trashes rscratch1
5784 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5785 jcc(Assembler::equal, ok);
5786 STOP(msg);
5787 bind(ok);
5788 pop(rscratch1);
5789 }
5790 }
5791 #endif
5792
5793 // Algorithm must match oop.inline.hpp encode_heap_oop.
5794 void MacroAssembler::encode_heap_oop(Register r) {
5795 #ifdef ASSERT
5796 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5797 #endif
5798 verify_oop(r, "broken oop in encode_heap_oop");
5799 if (Universe::narrow_oop_base() == NULL) {
5800 if (Universe::narrow_oop_shift() != 0) {
5801 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5802 shrq(r, LogMinObjAlignmentInBytes);
5803 }
5804 return;
5805 }
5806 testq(r, r);
5807 cmovq(Assembler::equal, r, r12_heapbase);
5808 subq(r, r12_heapbase);
5809 shrq(r, LogMinObjAlignmentInBytes);
5810 }
5811
5812 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5813 #ifdef ASSERT
5814 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5815 if (CheckCompressedOops) {
5816 Label ok;
5817 testq(r, r);
5818 jcc(Assembler::notEqual, ok);
5819 STOP("null oop passed to encode_heap_oop_not_null");
5820 bind(ok);
5821 }
5822 #endif
5823 verify_oop(r, "broken oop in encode_heap_oop_not_null");
5824 if (Universe::narrow_oop_base() != NULL) {
5825 subq(r, r12_heapbase);
5826 }
5827 if (Universe::narrow_oop_shift() != 0) {
5828 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5829 shrq(r, LogMinObjAlignmentInBytes);
5830 }
5831 }
5832
5833 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5834 #ifdef ASSERT
5835 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5836 if (CheckCompressedOops) {
5837 Label ok;
5838 testq(src, src);
5839 jcc(Assembler::notEqual, ok);
5840 STOP("null oop passed to encode_heap_oop_not_null2");
5841 bind(ok);
5842 }
5843 #endif
5844 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5845 if (dst != src) {
5846 movq(dst, src);
5847 }
5848 if (Universe::narrow_oop_base() != NULL) {
5849 subq(dst, r12_heapbase);
5850 }
5851 if (Universe::narrow_oop_shift() != 0) {
5852 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5853 shrq(dst, LogMinObjAlignmentInBytes);
5854 }
5855 }
5856
5857 void MacroAssembler::decode_heap_oop(Register r) {
5858 #ifdef ASSERT
5859 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5860 #endif
5861 if (Universe::narrow_oop_base() == NULL) {
5862 if (Universe::narrow_oop_shift() != 0) {
5863 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5864 shlq(r, LogMinObjAlignmentInBytes);
5865 }
5866 } else {
5867 Label done;
5868 shlq(r, LogMinObjAlignmentInBytes);
5869 jccb(Assembler::equal, done);
5870 addq(r, r12_heapbase);
5871 bind(done);
5872 }
5873 verify_oop(r, "broken oop in decode_heap_oop");
5874 }
5875
5876 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5877 // Note: it will change flags
5878 assert (UseCompressedOops, "should only be used for compressed headers");
5879 assert (Universe::heap() != NULL, "java heap should be initialized");
5880 // Cannot assert, unverified entry point counts instructions (see .ad file)
5881 // vtableStubs also counts instructions in pd_code_size_limit.
5882 // Also do not verify_oop as this is called by verify_oop.
5883 if (Universe::narrow_oop_shift() != 0) {
5884 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5885 shlq(r, LogMinObjAlignmentInBytes);
5886 if (Universe::narrow_oop_base() != NULL) {
5887 addq(r, r12_heapbase);
5888 }
5889 } else {
5890 assert (Universe::narrow_oop_base() == NULL, "sanity");
5891 }
5892 }
5893
5894 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5895 // Note: it will change flags
5896 assert (UseCompressedOops, "should only be used for compressed headers");
5897 assert (Universe::heap() != NULL, "java heap should be initialized");
5898 // Cannot assert, unverified entry point counts instructions (see .ad file)
5899 // vtableStubs also counts instructions in pd_code_size_limit.
5900 // Also do not verify_oop as this is called by verify_oop.
5901 if (Universe::narrow_oop_shift() != 0) {
5902 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5903 if (LogMinObjAlignmentInBytes == Address::times_8) {
5904 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5905 } else {
5906 if (dst != src) {
5907 movq(dst, src);
5908 }
5909 shlq(dst, LogMinObjAlignmentInBytes);
5910 if (Universe::narrow_oop_base() != NULL) {
5911 addq(dst, r12_heapbase);
5912 }
5913 }
5914 } else {
5915 assert (Universe::narrow_oop_base() == NULL, "sanity");
5916 if (dst != src) {
5917 movq(dst, src);
5918 }
5919 }
5920 }
5921
5922 void MacroAssembler::encode_klass_not_null(Register r) {
5923 if (Universe::narrow_klass_base() != NULL) {
5924 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5925 assert(r != r12_heapbase, "Encoding a klass in r12");
5926 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5927 subq(r, r12_heapbase);
5928 }
5929 if (Universe::narrow_klass_shift() != 0) {
5930 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5931 shrq(r, LogKlassAlignmentInBytes);
5932 }
5933 if (Universe::narrow_klass_base() != NULL) {
5934 reinit_heapbase();
5935 }
5936 }
5937
5938 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5939 if (dst == src) {
5940 encode_klass_not_null(src);
5941 } else {
5942 if (Universe::narrow_klass_base() != NULL) {
5943 mov64(dst, (int64_t)Universe::narrow_klass_base());
5944 negq(dst);
5945 addq(dst, src);
5946 } else {
5947 movptr(dst, src);
5948 }
5949 if (Universe::narrow_klass_shift() != 0) {
5950 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5951 shrq(dst, LogKlassAlignmentInBytes);
5952 }
5953 }
5954 }
5955
5956 // Function instr_size_for_decode_klass_not_null() counts the instructions
5957 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5958 // when (Universe::heap() != NULL). Hence, if the instructions they
5959 // generate change, then this method needs to be updated.
5960 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5961 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5962 if (Universe::narrow_klass_base() != NULL) {
5963 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
5964 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
5965 } else {
5966 // longest load decode klass function, mov64, leaq
5967 return 16;
5968 }
5969 }
5970
5971 // !!! If the instructions that get generated here change then function
5972 // instr_size_for_decode_klass_not_null() needs to get updated.
5973 void MacroAssembler::decode_klass_not_null(Register r) {
5974 // Note: it will change flags
5975 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5976 assert(r != r12_heapbase, "Decoding a klass in r12");
5977 // Cannot assert, unverified entry point counts instructions (see .ad file)
5978 // vtableStubs also counts instructions in pd_code_size_limit.
5979 // Also do not verify_oop as this is called by verify_oop.
5980 if (Universe::narrow_klass_shift() != 0) {
5981 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5982 shlq(r, LogKlassAlignmentInBytes);
5983 }
5984 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5985 if (Universe::narrow_klass_base() != NULL) {
5986 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5987 addq(r, r12_heapbase);
5988 reinit_heapbase();
5989 }
5990 }
5991
5992 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5993 // Note: it will change flags
5994 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5995 if (dst == src) {
5996 decode_klass_not_null(dst);
5997 } else {
5998 // Cannot assert, unverified entry point counts instructions (see .ad file)
5999 // vtableStubs also counts instructions in pd_code_size_limit.
6000 // Also do not verify_oop as this is called by verify_oop.
6001 mov64(dst, (int64_t)Universe::narrow_klass_base());
6002 if (Universe::narrow_klass_shift() != 0) {
6003 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6004 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6005 leaq(dst, Address(dst, src, Address::times_8, 0));
6006 } else {
6007 addq(dst, src);
6008 }
6009 }
6010 }
6011
6012 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6013 assert (UseCompressedOops, "should only be used for compressed headers");
6014 assert (Universe::heap() != NULL, "java heap should be initialized");
6015 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6016 int oop_index = oop_recorder()->find_index(obj);
6017 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6018 mov_narrow_oop(dst, oop_index, rspec);
6019 }
6020
6021 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6022 assert (UseCompressedOops, "should only be used for compressed headers");
6023 assert (Universe::heap() != NULL, "java heap should be initialized");
6024 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6025 int oop_index = oop_recorder()->find_index(obj);
6026 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6027 mov_narrow_oop(dst, oop_index, rspec);
6028 }
6029
6030 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6031 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6032 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6033 int klass_index = oop_recorder()->find_index(k);
6034 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6035 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6036 }
6037
6038 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6039 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6040 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6041 int klass_index = oop_recorder()->find_index(k);
6042 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6043 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6044 }
6045
6046 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6047 assert (UseCompressedOops, "should only be used for compressed headers");
6048 assert (Universe::heap() != NULL, "java heap should be initialized");
6049 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6050 int oop_index = oop_recorder()->find_index(obj);
6051 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6052 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6053 }
6054
6055 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6056 assert (UseCompressedOops, "should only be used for compressed headers");
6057 assert (Universe::heap() != NULL, "java heap should be initialized");
6058 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6059 int oop_index = oop_recorder()->find_index(obj);
6060 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6061 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6062 }
6063
6064 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6065 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6066 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6067 int klass_index = oop_recorder()->find_index(k);
6068 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6069 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6070 }
6071
6072 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6073 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6074 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6075 int klass_index = oop_recorder()->find_index(k);
6076 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6077 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6078 }
6079
6080 void MacroAssembler::reinit_heapbase() {
6081 if (UseCompressedOops || UseCompressedClassPointers) {
6082 if (Universe::heap() != NULL) {
6083 if (Universe::narrow_oop_base() == NULL) {
6084 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6085 } else {
6086 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6087 }
6088 } else {
6089 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6090 }
6091 }
6092 }
6093
6094 #endif // _LP64
6095
6096
6097 // C2 compiled method's prolog code.
6098 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6099
6100 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6101 // NativeJump::patch_verified_entry will be able to patch out the entry
6102 // code safely. The push to verify stack depth is ok at 5 bytes,
6103 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6104 // stack bang then we must use the 6 byte frame allocation even if
6105 // we have no frame. :-(
6106 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6107
6108 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6109 // Remove word for return addr
6110 framesize -= wordSize;
6111 stack_bang_size -= wordSize;
6112
6113 // Calls to C2R adapters often do not accept exceptional returns.
6114 // We require that their callers must bang for them. But be careful, because
6115 // some VM calls (such as call site linkage) can use several kilobytes of
6116 // stack. But the stack safety zone should account for that.
6117 // See bugs 4446381, 4468289, 4497237.
6118 if (stack_bang_size > 0) {
6119 generate_stack_overflow_check(stack_bang_size);
6120
6121 // We always push rbp, so that on return to interpreter rbp, will be
6122 // restored correctly and we can correct the stack.
6123 push(rbp);
6124 // Remove word for ebp
6125 framesize -= wordSize;
6126
6127 // Create frame
6128 if (framesize) {
6129 subptr(rsp, framesize);
6130 }
6131 } else {
6132 // Create frame (force generation of a 4 byte immediate value)
6133 subptr_imm32(rsp, framesize);
6134
6135 // Save RBP register now.
6136 framesize -= wordSize;
6137 movptr(Address(rsp, framesize), rbp);
6138 }
6139
6140 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6141 framesize -= wordSize;
6142 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6143 }
6144
6145 #ifndef _LP64
6146 // If method sets FPU control word do it now
6147 if (fp_mode_24b) {
6148 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6149 }
6150 if (UseSSE >= 2 && VerifyFPU) {
6151 verify_FPU(0, "FPU stack must be clean on entry");
6152 }
6153 #endif
6154
6155 #ifdef ASSERT
6156 if (VerifyStackAtCalls) {
6157 Label L;
6158 push(rax);
6159 mov(rax, rsp);
6160 andptr(rax, StackAlignmentInBytes-1);
6161 cmpptr(rax, StackAlignmentInBytes-wordSize);
6162 pop(rax);
6163 jcc(Assembler::equal, L);
6164 STOP("Stack is not properly aligned!");
6165 bind(L);
6166 }
6167 #endif
6168
6169 }
6170
6171 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) {
6172 // cnt - number of qwords (8-byte words).
6173 // base - start address, qword aligned.
6174 assert(base==rdi, "base register must be edi for rep stos");
6175 assert(tmp==rax, "tmp register must be eax for rep stos");
6176 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6177
6178 xorptr(tmp, tmp);
6179 if (UseFastStosb) {
6180 shlptr(cnt,3); // convert to number of bytes
6181 rep_stosb();
6182 } else {
6183 NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM
6184 rep_stos();
6185 }
6186 }
6187
6188 // IndexOf for constant substrings with size >= 8 chars
6189 // which don't need to be loaded through stack.
6190 void MacroAssembler::string_indexofC8(Register str1, Register str2,
6191 Register cnt1, Register cnt2,
6192 int int_cnt2, Register result,
6193 XMMRegister vec, Register tmp) {
6194 ShortBranchVerifier sbv(this);
6195 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6196
6197 // This method uses pcmpestri instruction with bound registers
6198 // inputs:
6199 // xmm - substring
6200 // rax - substring length (elements count)
6201 // mem - scanned string
6202 // rdx - string length (elements count)
6203 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6204 // outputs:
6205 // rcx - matched index in string
6206 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6207
6208 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
6209 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
6210 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
6211
6212 // Note, inline_string_indexOf() generates checks:
6213 // if (substr.count > string.count) return -1;
6214 // if (substr.count == 0) return 0;
6215 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars");
6216
6217 // Load substring.
6218 movdqu(vec, Address(str2, 0));
6219 movl(cnt2, int_cnt2);
6220 movptr(result, str1); // string addr
6221
6222 if (int_cnt2 > 8) {
6223 jmpb(SCAN_TO_SUBSTR);
6224
6225 // Reload substr for rescan, this code
6226 // is executed only for large substrings (> 8 chars)
6227 bind(RELOAD_SUBSTR);
6228 movdqu(vec, Address(str2, 0));
6229 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6230
6231 bind(RELOAD_STR);
6232 // We came here after the beginning of the substring was
6233 // matched but the rest of it was not so we need to search
6234 // again. Start from the next element after the previous match.
6235
6236 // cnt2 is number of substring reminding elements and
6237 // cnt1 is number of string reminding elements when cmp failed.
6238 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6239 subl(cnt1, cnt2);
6240 addl(cnt1, int_cnt2);
6241 movl(cnt2, int_cnt2); // Now restore cnt2
6242
6243 decrementl(cnt1); // Shift to next element
6244 cmpl(cnt1, cnt2);
6245 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6246
6247 addptr(result, 2);
6248
6249 } // (int_cnt2 > 8)
6250
6251 // Scan string for start of substr in 16-byte vectors
6252 bind(SCAN_TO_SUBSTR);
6253 pcmpestri(vec, Address(result, 0), 0x0d);
6254 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6255 subl(cnt1, 8);
6256 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6257 cmpl(cnt1, cnt2);
6258 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6259 addptr(result, 16);
6260 jmpb(SCAN_TO_SUBSTR);
6261
6262 // Found a potential substr
6263 bind(FOUND_CANDIDATE);
6264 // Matched whole vector if first element matched (tmp(rcx) == 0).
6265 if (int_cnt2 == 8) {
6266 jccb(Assembler::overflow, RET_FOUND); // OF == 1
6267 } else { // int_cnt2 > 8
6268 jccb(Assembler::overflow, FOUND_SUBSTR);
6269 }
6270 // After pcmpestri tmp(rcx) contains matched element index
6271 // Compute start addr of substr
6272 lea(result, Address(result, tmp, Address::times_2));
6273
6274 // Make sure string is still long enough
6275 subl(cnt1, tmp);
6276 cmpl(cnt1, cnt2);
6277 if (int_cnt2 == 8) {
6278 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6279 } else { // int_cnt2 > 8
6280 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6281 }
6282 // Left less then substring.
6283
6284 bind(RET_NOT_FOUND);
6285 movl(result, -1);
6286 jmpb(EXIT);
6287
6288 if (int_cnt2 > 8) {
6289 // This code is optimized for the case when whole substring
6290 // is matched if its head is matched.
6291 bind(MATCH_SUBSTR_HEAD);
6292 pcmpestri(vec, Address(result, 0), 0x0d);
6293 // Reload only string if does not match
6294 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
6295
6296 Label CONT_SCAN_SUBSTR;
6297 // Compare the rest of substring (> 8 chars).
6298 bind(FOUND_SUBSTR);
6299 // First 8 chars are already matched.
6300 negptr(cnt2);
6301 addptr(cnt2, 8);
6302
6303 bind(SCAN_SUBSTR);
6304 subl(cnt1, 8);
6305 cmpl(cnt2, -8); // Do not read beyond substring
6306 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6307 // Back-up strings to avoid reading beyond substring:
6308 // cnt1 = cnt1 - cnt2 + 8
6309 addl(cnt1, cnt2); // cnt2 is negative
6310 addl(cnt1, 8);
6311 movl(cnt2, 8); negptr(cnt2);
6312 bind(CONT_SCAN_SUBSTR);
6313 if (int_cnt2 < (int)G) {
6314 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2));
6315 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d);
6316 } else {
6317 // calculate index in register to avoid integer overflow (int_cnt2*2)
6318 movl(tmp, int_cnt2);
6319 addptr(tmp, cnt2);
6320 movdqu(vec, Address(str2, tmp, Address::times_2, 0));
6321 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d);
6322 }
6323 // Need to reload strings pointers if not matched whole vector
6324 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6325 addptr(cnt2, 8);
6326 jcc(Assembler::negative, SCAN_SUBSTR);
6327 // Fall through if found full substring
6328
6329 } // (int_cnt2 > 8)
6330
6331 bind(RET_FOUND);
6332 // Found result if we matched full small substring.
6333 // Compute substr offset
6334 subptr(result, str1);
6335 shrl(result, 1); // index
6336 bind(EXIT);
6337
6338 } // string_indexofC8
6339
6340 // Small strings are loaded through stack if they cross page boundary.
6341 void MacroAssembler::string_indexof(Register str1, Register str2,
6342 Register cnt1, Register cnt2,
6343 int int_cnt2, Register result,
6344 XMMRegister vec, Register tmp) {
6345 ShortBranchVerifier sbv(this);
6346 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6347 //
6348 // int_cnt2 is length of small (< 8 chars) constant substring
6349 // or (-1) for non constant substring in which case its length
6350 // is in cnt2 register.
6351 //
6352 // Note, inline_string_indexOf() generates checks:
6353 // if (substr.count > string.count) return -1;
6354 // if (substr.count == 0) return 0;
6355 //
6356 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0");
6357
6358 // This method uses pcmpestri instruction with bound registers
6359 // inputs:
6360 // xmm - substring
6361 // rax - substring length (elements count)
6362 // mem - scanned string
6363 // rdx - string length (elements count)
6364 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6365 // outputs:
6366 // rcx - matched index in string
6367 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6368
6369 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6370 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6371 FOUND_CANDIDATE;
6372
6373 { //========================================================
6374 // We don't know where these strings are located
6375 // and we can't read beyond them. Load them through stack.
6376 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6377
6378 movptr(tmp, rsp); // save old SP
6379
6380 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6381 if (int_cnt2 == 1) { // One char
6382 load_unsigned_short(result, Address(str2, 0));
6383 movdl(vec, result); // move 32 bits
6384 } else if (int_cnt2 == 2) { // Two chars
6385 movdl(vec, Address(str2, 0)); // move 32 bits
6386 } else if (int_cnt2 == 4) { // Four chars
6387 movq(vec, Address(str2, 0)); // move 64 bits
6388 } else { // cnt2 = { 3, 5, 6, 7 }
6389 // Array header size is 12 bytes in 32-bit VM
6390 // + 6 bytes for 3 chars == 18 bytes,
6391 // enough space to load vec and shift.
6392 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6393 movdqu(vec, Address(str2, (int_cnt2*2)-16));
6394 psrldq(vec, 16-(int_cnt2*2));
6395 }
6396 } else { // not constant substring
6397 cmpl(cnt2, 8);
6398 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6399
6400 // We can read beyond string if srt+16 does not cross page boundary
6401 // since heaps are aligned and mapped by pages.
6402 assert(os::vm_page_size() < (int)G, "default page should be small");
6403 movl(result, str2); // We need only low 32 bits
6404 andl(result, (os::vm_page_size()-1));
6405 cmpl(result, (os::vm_page_size()-16));
6406 jccb(Assembler::belowEqual, CHECK_STR);
6407
6408 // Move small strings to stack to allow load 16 bytes into vec.
6409 subptr(rsp, 16);
6410 int stk_offset = wordSize-2;
6411 push(cnt2);
6412
6413 bind(COPY_SUBSTR);
6414 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2));
6415 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6416 decrement(cnt2);
6417 jccb(Assembler::notZero, COPY_SUBSTR);
6418
6419 pop(cnt2);
6420 movptr(str2, rsp); // New substring address
6421 } // non constant
6422
6423 bind(CHECK_STR);
6424 cmpl(cnt1, 8);
6425 jccb(Assembler::aboveEqual, BIG_STRINGS);
6426
6427 // Check cross page boundary.
6428 movl(result, str1); // We need only low 32 bits
6429 andl(result, (os::vm_page_size()-1));
6430 cmpl(result, (os::vm_page_size()-16));
6431 jccb(Assembler::belowEqual, BIG_STRINGS);
6432
6433 subptr(rsp, 16);
6434 int stk_offset = -2;
6435 if (int_cnt2 < 0) { // not constant
6436 push(cnt2);
6437 stk_offset += wordSize;
6438 }
6439 movl(cnt2, cnt1);
6440
6441 bind(COPY_STR);
6442 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2));
6443 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6444 decrement(cnt2);
6445 jccb(Assembler::notZero, COPY_STR);
6446
6447 if (int_cnt2 < 0) { // not constant
6448 pop(cnt2);
6449 }
6450 movptr(str1, rsp); // New string address
6451
6452 bind(BIG_STRINGS);
6453 // Load substring.
6454 if (int_cnt2 < 0) { // -1
6455 movdqu(vec, Address(str2, 0));
6456 push(cnt2); // substr count
6457 push(str2); // substr addr
6458 push(str1); // string addr
6459 } else {
6460 // Small (< 8 chars) constant substrings are loaded already.
6461 movl(cnt2, int_cnt2);
6462 }
6463 push(tmp); // original SP
6464
6465 } // Finished loading
6466
6467 //========================================================
6468 // Start search
6469 //
6470
6471 movptr(result, str1); // string addr
6472
6473 if (int_cnt2 < 0) { // Only for non constant substring
6474 jmpb(SCAN_TO_SUBSTR);
6475
6476 // SP saved at sp+0
6477 // String saved at sp+1*wordSize
6478 // Substr saved at sp+2*wordSize
6479 // Substr count saved at sp+3*wordSize
6480
6481 // Reload substr for rescan, this code
6482 // is executed only for large substrings (> 8 chars)
6483 bind(RELOAD_SUBSTR);
6484 movptr(str2, Address(rsp, 2*wordSize));
6485 movl(cnt2, Address(rsp, 3*wordSize));
6486 movdqu(vec, Address(str2, 0));
6487 // We came here after the beginning of the substring was
6488 // matched but the rest of it was not so we need to search
6489 // again. Start from the next element after the previous match.
6490 subptr(str1, result); // Restore counter
6491 shrl(str1, 1);
6492 addl(cnt1, str1);
6493 decrementl(cnt1); // Shift to next element
6494 cmpl(cnt1, cnt2);
6495 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6496
6497 addptr(result, 2);
6498 } // non constant
6499
6500 // Scan string for start of substr in 16-byte vectors
6501 bind(SCAN_TO_SUBSTR);
6502 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6503 pcmpestri(vec, Address(result, 0), 0x0d);
6504 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6505 subl(cnt1, 8);
6506 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6507 cmpl(cnt1, cnt2);
6508 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6509 addptr(result, 16);
6510
6511 bind(ADJUST_STR);
6512 cmpl(cnt1, 8); // Do not read beyond string
6513 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6514 // Back-up string to avoid reading beyond string.
6515 lea(result, Address(result, cnt1, Address::times_2, -16));
6516 movl(cnt1, 8);
6517 jmpb(SCAN_TO_SUBSTR);
6518
6519 // Found a potential substr
6520 bind(FOUND_CANDIDATE);
6521 // After pcmpestri tmp(rcx) contains matched element index
6522
6523 // Make sure string is still long enough
6524 subl(cnt1, tmp);
6525 cmpl(cnt1, cnt2);
6526 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6527 // Left less then substring.
6528
6529 bind(RET_NOT_FOUND);
6530 movl(result, -1);
6531 jmpb(CLEANUP);
6532
6533 bind(FOUND_SUBSTR);
6534 // Compute start addr of substr
6535 lea(result, Address(result, tmp, Address::times_2));
6536
6537 if (int_cnt2 > 0) { // Constant substring
6538 // Repeat search for small substring (< 8 chars)
6539 // from new point without reloading substring.
6540 // Have to check that we don't read beyond string.
6541 cmpl(tmp, 8-int_cnt2);
6542 jccb(Assembler::greater, ADJUST_STR);
6543 // Fall through if matched whole substring.
6544 } else { // non constant
6545 assert(int_cnt2 == -1, "should be != 0");
6546
6547 addl(tmp, cnt2);
6548 // Found result if we matched whole substring.
6549 cmpl(tmp, 8);
6550 jccb(Assembler::lessEqual, RET_FOUND);
6551
6552 // Repeat search for small substring (<= 8 chars)
6553 // from new point 'str1' without reloading substring.
6554 cmpl(cnt2, 8);
6555 // Have to check that we don't read beyond string.
6556 jccb(Assembler::lessEqual, ADJUST_STR);
6557
6558 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6559 // Compare the rest of substring (> 8 chars).
6560 movptr(str1, result);
6561
6562 cmpl(tmp, cnt2);
6563 // First 8 chars are already matched.
6564 jccb(Assembler::equal, CHECK_NEXT);
6565
6566 bind(SCAN_SUBSTR);
6567 pcmpestri(vec, Address(str1, 0), 0x0d);
6568 // Need to reload strings pointers if not matched whole vector
6569 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6570
6571 bind(CHECK_NEXT);
6572 subl(cnt2, 8);
6573 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6574 addptr(str1, 16);
6575 addptr(str2, 16);
6576 subl(cnt1, 8);
6577 cmpl(cnt2, 8); // Do not read beyond substring
6578 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6579 // Back-up strings to avoid reading beyond substring.
6580 lea(str2, Address(str2, cnt2, Address::times_2, -16));
6581 lea(str1, Address(str1, cnt2, Address::times_2, -16));
6582 subl(cnt1, cnt2);
6583 movl(cnt2, 8);
6584 addl(cnt1, 8);
6585 bind(CONT_SCAN_SUBSTR);
6586 movdqu(vec, Address(str2, 0));
6587 jmpb(SCAN_SUBSTR);
6588
6589 bind(RET_FOUND_LONG);
6590 movptr(str1, Address(rsp, wordSize));
6591 } // non constant
6592
6593 bind(RET_FOUND);
6594 // Compute substr offset
6595 subptr(result, str1);
6596 shrl(result, 1); // index
6597
6598 bind(CLEANUP);
6599 pop(rsp); // restore SP
6600
6601 } // string_indexof
6602
6603 // Compare strings.
6604 void MacroAssembler::string_compare(Register str1, Register str2,
6605 Register cnt1, Register cnt2, Register result,
6606 XMMRegister vec1) {
6607 ShortBranchVerifier sbv(this);
6608 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6609
6610 // Compute the minimum of the string lengths and the
6611 // difference of the string lengths (stack).
6612 // Do the conditional move stuff
6613 movl(result, cnt1);
6614 subl(cnt1, cnt2);
6615 push(cnt1);
6616 cmov32(Assembler::lessEqual, cnt2, result);
6617
6618 // Is the minimum length zero?
6619 testl(cnt2, cnt2);
6620 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6621
6622 // Compare first characters
6623 load_unsigned_short(result, Address(str1, 0));
6624 load_unsigned_short(cnt1, Address(str2, 0));
6625 subl(result, cnt1);
6626 jcc(Assembler::notZero, POP_LABEL);
6627 cmpl(cnt2, 1);
6628 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6629
6630 // Check if the strings start at the same location.
6631 cmpptr(str1, str2);
6632 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6633
6634 Address::ScaleFactor scale = Address::times_2;
6635 int stride = 8;
6636
6637 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6638 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6639 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6640 Label COMPARE_TAIL_LONG;
6641 int pcmpmask = 0x19;
6642
6643 // Setup to compare 16-chars (32-bytes) vectors,
6644 // start from first character again because it has aligned address.
6645 int stride2 = 16;
6646 int adr_stride = stride << scale;
6647
6648 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6649 // rax and rdx are used by pcmpestri as elements counters
6650 movl(result, cnt2);
6651 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6652 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6653
6654 // fast path : compare first 2 8-char vectors.
6655 bind(COMPARE_16_CHARS);
6656 movdqu(vec1, Address(str1, 0));
6657 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6658 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6659
6660 movdqu(vec1, Address(str1, adr_stride));
6661 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6662 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6663 addl(cnt1, stride);
6664
6665 // Compare the characters at index in cnt1
6666 bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character
6667 load_unsigned_short(result, Address(str1, cnt1, scale));
6668 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6669 subl(result, cnt2);
6670 jmp(POP_LABEL);
6671
6672 // Setup the registers to start vector comparison loop
6673 bind(COMPARE_WIDE_VECTORS);
6674 lea(str1, Address(str1, result, scale));
6675 lea(str2, Address(str2, result, scale));
6676 subl(result, stride2);
6677 subl(cnt2, stride2);
6678 jccb(Assembler::zero, COMPARE_WIDE_TAIL);
6679 negptr(result);
6680
6681 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6682 bind(COMPARE_WIDE_VECTORS_LOOP);
6683 vmovdqu(vec1, Address(str1, result, scale));
6684 vpxor(vec1, Address(str2, result, scale));
6685 vptest(vec1, vec1);
6686 jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
6687 addptr(result, stride2);
6688 subl(cnt2, stride2);
6689 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6690 // clean upper bits of YMM registers
6691 vzeroupper();
6692
6693 // compare wide vectors tail
6694 bind(COMPARE_WIDE_TAIL);
6695 testptr(result, result);
6696 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6697
6698 movl(result, stride2);
6699 movl(cnt2, result);
6700 negptr(result);
6701 jmpb(COMPARE_WIDE_VECTORS_LOOP);
6702
6703 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6704 bind(VECTOR_NOT_EQUAL);
6705 // clean upper bits of YMM registers
6706 vzeroupper();
6707 lea(str1, Address(str1, result, scale));
6708 lea(str2, Address(str2, result, scale));
6709 jmp(COMPARE_16_CHARS);
6710
6711 // Compare tail chars, length between 1 to 15 chars
6712 bind(COMPARE_TAIL_LONG);
6713 movl(cnt2, result);
6714 cmpl(cnt2, stride);
6715 jccb(Assembler::less, COMPARE_SMALL_STR);
6716
6717 movdqu(vec1, Address(str1, 0));
6718 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6719 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6720 subptr(cnt2, stride);
6721 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6722 lea(str1, Address(str1, result, scale));
6723 lea(str2, Address(str2, result, scale));
6724 negptr(cnt2);
6725 jmpb(WHILE_HEAD_LABEL);
6726
6727 bind(COMPARE_SMALL_STR);
6728 } else if (UseSSE42Intrinsics) {
6729 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6730 int pcmpmask = 0x19;
6731 // Setup to compare 8-char (16-byte) vectors,
6732 // start from first character again because it has aligned address.
6733 movl(result, cnt2);
6734 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6735 jccb(Assembler::zero, COMPARE_TAIL);
6736
6737 lea(str1, Address(str1, result, scale));
6738 lea(str2, Address(str2, result, scale));
6739 negptr(result);
6740
6741 // pcmpestri
6742 // inputs:
6743 // vec1- substring
6744 // rax - negative string length (elements count)
6745 // mem - scanned string
6746 // rdx - string length (elements count)
6747 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6748 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6749 // outputs:
6750 // rcx - first mismatched element index
6751 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6752
6753 bind(COMPARE_WIDE_VECTORS);
6754 movdqu(vec1, Address(str1, result, scale));
6755 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6756 // After pcmpestri cnt1(rcx) contains mismatched element index
6757
6758 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6759 addptr(result, stride);
6760 subptr(cnt2, stride);
6761 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6762
6763 // compare wide vectors tail
6764 testptr(result, result);
6765 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6766
6767 movl(cnt2, stride);
6768 movl(result, stride);
6769 negptr(result);
6770 movdqu(vec1, Address(str1, result, scale));
6771 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6772 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6773
6774 // Mismatched characters in the vectors
6775 bind(VECTOR_NOT_EQUAL);
6776 addptr(cnt1, result);
6777 load_unsigned_short(result, Address(str1, cnt1, scale));
6778 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6779 subl(result, cnt2);
6780 jmpb(POP_LABEL);
6781
6782 bind(COMPARE_TAIL); // limit is zero
6783 movl(cnt2, result);
6784 // Fallthru to tail compare
6785 }
6786 // Shift str2 and str1 to the end of the arrays, negate min
6787 lea(str1, Address(str1, cnt2, scale));
6788 lea(str2, Address(str2, cnt2, scale));
6789 decrementl(cnt2); // first character was compared already
6790 negptr(cnt2);
6791
6792 // Compare the rest of the elements
6793 bind(WHILE_HEAD_LABEL);
6794 load_unsigned_short(result, Address(str1, cnt2, scale, 0));
6795 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0));
6796 subl(result, cnt1);
6797 jccb(Assembler::notZero, POP_LABEL);
6798 increment(cnt2);
6799 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6800
6801 // Strings are equal up to min length. Return the length difference.
6802 bind(LENGTH_DIFF_LABEL);
6803 pop(result);
6804 jmpb(DONE_LABEL);
6805
6806 // Discard the stored length difference
6807 bind(POP_LABEL);
6808 pop(cnt1);
6809
6810 // That's it
6811 bind(DONE_LABEL);
6812 }
6813
6814 // Compare char[] arrays aligned to 4 bytes or substrings.
6815 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
6816 Register limit, Register result, Register chr,
6817 XMMRegister vec1, XMMRegister vec2) {
6818 ShortBranchVerifier sbv(this);
6819 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
6820
6821 int length_offset = arrayOopDesc::length_offset_in_bytes();
6822 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
6823
6824 // Check the input args
6825 cmpptr(ary1, ary2);
6826 jcc(Assembler::equal, TRUE_LABEL);
6827
6828 if (is_array_equ) {
6829 // Need additional checks for arrays_equals.
6830 testptr(ary1, ary1);
6831 jcc(Assembler::zero, FALSE_LABEL);
6832 testptr(ary2, ary2);
6833 jcc(Assembler::zero, FALSE_LABEL);
6834
6835 // Check the lengths
6836 movl(limit, Address(ary1, length_offset));
6837 cmpl(limit, Address(ary2, length_offset));
6838 jcc(Assembler::notEqual, FALSE_LABEL);
6839 }
6840
6841 // count == 0
6842 testl(limit, limit);
6843 jcc(Assembler::zero, TRUE_LABEL);
6844
6845 if (is_array_equ) {
6846 // Load array address
6847 lea(ary1, Address(ary1, base_offset));
6848 lea(ary2, Address(ary2, base_offset));
6849 }
6850
6851 shll(limit, 1); // byte count != 0
6852 movl(result, limit); // copy
6853
6854 if (UseAVX >= 2) {
6855 // With AVX2, use 32-byte vector compare
6856 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6857
6858 // Compare 32-byte vectors
6859 andl(result, 0x0000001e); // tail count (in bytes)
6860 andl(limit, 0xffffffe0); // vector count (in bytes)
6861 jccb(Assembler::zero, COMPARE_TAIL);
6862
6863 lea(ary1, Address(ary1, limit, Address::times_1));
6864 lea(ary2, Address(ary2, limit, Address::times_1));
6865 negptr(limit);
6866
6867 bind(COMPARE_WIDE_VECTORS);
6868 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
6869 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
6870 vpxor(vec1, vec2);
6871
6872 vptest(vec1, vec1);
6873 jccb(Assembler::notZero, FALSE_LABEL);
6874 addptr(limit, 32);
6875 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6876
6877 testl(result, result);
6878 jccb(Assembler::zero, TRUE_LABEL);
6879
6880 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6881 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
6882 vpxor(vec1, vec2);
6883
6884 vptest(vec1, vec1);
6885 jccb(Assembler::notZero, FALSE_LABEL);
6886 jmpb(TRUE_LABEL);
6887
6888 bind(COMPARE_TAIL); // limit is zero
6889 movl(limit, result);
6890 // Fallthru to tail compare
6891 } else if (UseSSE42Intrinsics) {
6892 // With SSE4.2, use double quad vector compare
6893 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6894
6895 // Compare 16-byte vectors
6896 andl(result, 0x0000000e); // tail count (in bytes)
6897 andl(limit, 0xfffffff0); // vector count (in bytes)
6898 jccb(Assembler::zero, COMPARE_TAIL);
6899
6900 lea(ary1, Address(ary1, limit, Address::times_1));
6901 lea(ary2, Address(ary2, limit, Address::times_1));
6902 negptr(limit);
6903
6904 bind(COMPARE_WIDE_VECTORS);
6905 movdqu(vec1, Address(ary1, limit, Address::times_1));
6906 movdqu(vec2, Address(ary2, limit, Address::times_1));
6907 pxor(vec1, vec2);
6908
6909 ptest(vec1, vec1);
6910 jccb(Assembler::notZero, FALSE_LABEL);
6911 addptr(limit, 16);
6912 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6913
6914 testl(result, result);
6915 jccb(Assembler::zero, TRUE_LABEL);
6916
6917 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
6918 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
6919 pxor(vec1, vec2);
6920
6921 ptest(vec1, vec1);
6922 jccb(Assembler::notZero, FALSE_LABEL);
6923 jmpb(TRUE_LABEL);
6924
6925 bind(COMPARE_TAIL); // limit is zero
6926 movl(limit, result);
6927 // Fallthru to tail compare
6928 }
6929
6930 // Compare 4-byte vectors
6931 andl(limit, 0xfffffffc); // vector count (in bytes)
6932 jccb(Assembler::zero, COMPARE_CHAR);
6933
6934 lea(ary1, Address(ary1, limit, Address::times_1));
6935 lea(ary2, Address(ary2, limit, Address::times_1));
6936 negptr(limit);
6937
6938 bind(COMPARE_VECTORS);
6939 movl(chr, Address(ary1, limit, Address::times_1));
6940 cmpl(chr, Address(ary2, limit, Address::times_1));
6941 jccb(Assembler::notEqual, FALSE_LABEL);
6942 addptr(limit, 4);
6943 jcc(Assembler::notZero, COMPARE_VECTORS);
6944
6945 // Compare trailing char (final 2 bytes), if any
6946 bind(COMPARE_CHAR);
6947 testl(result, 0x2); // tail char
6948 jccb(Assembler::zero, TRUE_LABEL);
6949 load_unsigned_short(chr, Address(ary1, 0));
6950 load_unsigned_short(limit, Address(ary2, 0));
6951 cmpl(chr, limit);
6952 jccb(Assembler::notEqual, FALSE_LABEL);
6953
6954 bind(TRUE_LABEL);
6955 movl(result, 1); // return true
6956 jmpb(DONE);
6957
6958 bind(FALSE_LABEL);
6959 xorl(result, result); // return false
6960
6961 // That's it
6962 bind(DONE);
6963 if (UseAVX >= 2) {
6964 // clean upper bits of YMM registers
6965 vzeroupper();
6966 }
6967 }
6968
6969 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6970 Register to, Register value, Register count,
6971 Register rtmp, XMMRegister xtmp) {
6972 ShortBranchVerifier sbv(this);
6973 assert_different_registers(to, value, count, rtmp);
6974 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
6975 Label L_fill_2_bytes, L_fill_4_bytes;
6976
6977 int shift = -1;
6978 switch (t) {
6979 case T_BYTE:
6980 shift = 2;
6981 break;
6982 case T_SHORT:
6983 shift = 1;
6984 break;
6985 case T_INT:
6986 shift = 0;
6987 break;
6988 default: ShouldNotReachHere();
6989 }
6990
6991 if (t == T_BYTE) {
6992 andl(value, 0xff);
6993 movl(rtmp, value);
6994 shll(rtmp, 8);
6995 orl(value, rtmp);
6996 }
6997 if (t == T_SHORT) {
6998 andl(value, 0xffff);
6999 }
7000 if (t == T_BYTE || t == T_SHORT) {
7001 movl(rtmp, value);
7002 shll(rtmp, 16);
7003 orl(value, rtmp);
7004 }
7005
7006 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7007 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7008 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7009 // align source address at 4 bytes address boundary
7010 if (t == T_BYTE) {
7011 // One byte misalignment happens only for byte arrays
7012 testptr(to, 1);
7013 jccb(Assembler::zero, L_skip_align1);
7014 movb(Address(to, 0), value);
7015 increment(to);
7016 decrement(count);
7017 BIND(L_skip_align1);
7018 }
7019 // Two bytes misalignment happens only for byte and short (char) arrays
7020 testptr(to, 2);
7021 jccb(Assembler::zero, L_skip_align2);
7022 movw(Address(to, 0), value);
7023 addptr(to, 2);
7024 subl(count, 1<<(shift-1));
7025 BIND(L_skip_align2);
7026 }
7027 if (UseSSE < 2) {
7028 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7029 // Fill 32-byte chunks
7030 subl(count, 8 << shift);
7031 jcc(Assembler::less, L_check_fill_8_bytes);
7032 align(16);
7033
7034 BIND(L_fill_32_bytes_loop);
7035
7036 for (int i = 0; i < 32; i += 4) {
7037 movl(Address(to, i), value);
7038 }
7039
7040 addptr(to, 32);
7041 subl(count, 8 << shift);
7042 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7043 BIND(L_check_fill_8_bytes);
7044 addl(count, 8 << shift);
7045 jccb(Assembler::zero, L_exit);
7046 jmpb(L_fill_8_bytes);
7047
7048 //
7049 // length is too short, just fill qwords
7050 //
7051 BIND(L_fill_8_bytes_loop);
7052 movl(Address(to, 0), value);
7053 movl(Address(to, 4), value);
7054 addptr(to, 8);
7055 BIND(L_fill_8_bytes);
7056 subl(count, 1 << (shift + 1));
7057 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7058 // fall through to fill 4 bytes
7059 } else {
7060 Label L_fill_32_bytes;
7061 if (!UseUnalignedLoadStores) {
7062 // align to 8 bytes, we know we are 4 byte aligned to start
7063 testptr(to, 4);
7064 jccb(Assembler::zero, L_fill_32_bytes);
7065 movl(Address(to, 0), value);
7066 addptr(to, 4);
7067 subl(count, 1<<shift);
7068 }
7069 BIND(L_fill_32_bytes);
7070 {
7071 assert( UseSSE >= 2, "supported cpu only" );
7072 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7073 movdl(xtmp, value);
7074 if (UseAVX >= 2 && UseUnalignedLoadStores) {
7075 // Fill 64-byte chunks
7076 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7077 vpbroadcastd(xtmp, xtmp);
7078
7079 subl(count, 16 << shift);
7080 jcc(Assembler::less, L_check_fill_32_bytes);
7081 align(16);
7082
7083 BIND(L_fill_64_bytes_loop);
7084 vmovdqu(Address(to, 0), xtmp);
7085 vmovdqu(Address(to, 32), xtmp);
7086 addptr(to, 64);
7087 subl(count, 16 << shift);
7088 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7089
7090 BIND(L_check_fill_32_bytes);
7091 addl(count, 8 << shift);
7092 jccb(Assembler::less, L_check_fill_8_bytes);
7093 vmovdqu(Address(to, 0), xtmp);
7094 addptr(to, 32);
7095 subl(count, 8 << shift);
7096
7097 BIND(L_check_fill_8_bytes);
7098 // clean upper bits of YMM registers
7099 vzeroupper();
7100 } else {
7101 // Fill 32-byte chunks
7102 pshufd(xtmp, xtmp, 0);
7103
7104 subl(count, 8 << shift);
7105 jcc(Assembler::less, L_check_fill_8_bytes);
7106 align(16);
7107
7108 BIND(L_fill_32_bytes_loop);
7109
7110 if (UseUnalignedLoadStores) {
7111 movdqu(Address(to, 0), xtmp);
7112 movdqu(Address(to, 16), xtmp);
7113 } else {
7114 movq(Address(to, 0), xtmp);
7115 movq(Address(to, 8), xtmp);
7116 movq(Address(to, 16), xtmp);
7117 movq(Address(to, 24), xtmp);
7118 }
7119
7120 addptr(to, 32);
7121 subl(count, 8 << shift);
7122 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7123
7124 BIND(L_check_fill_8_bytes);
7125 }
7126 addl(count, 8 << shift);
7127 jccb(Assembler::zero, L_exit);
7128 jmpb(L_fill_8_bytes);
7129
7130 //
7131 // length is too short, just fill qwords
7132 //
7133 BIND(L_fill_8_bytes_loop);
7134 movq(Address(to, 0), xtmp);
7135 addptr(to, 8);
7136 BIND(L_fill_8_bytes);
7137 subl(count, 1 << (shift + 1));
7138 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7139 }
7140 }
7141 // fill trailing 4 bytes
7142 BIND(L_fill_4_bytes);
7143 testl(count, 1<<shift);
7144 jccb(Assembler::zero, L_fill_2_bytes);
7145 movl(Address(to, 0), value);
7146 if (t == T_BYTE || t == T_SHORT) {
7147 addptr(to, 4);
7148 BIND(L_fill_2_bytes);
7149 // fill trailing 2 bytes
7150 testl(count, 1<<(shift-1));
7151 jccb(Assembler::zero, L_fill_byte);
7152 movw(Address(to, 0), value);
7153 if (t == T_BYTE) {
7154 addptr(to, 2);
7155 BIND(L_fill_byte);
7156 // fill trailing byte
7157 testl(count, 1);
7158 jccb(Assembler::zero, L_exit);
7159 movb(Address(to, 0), value);
7160 } else {
7161 BIND(L_fill_byte);
7162 }
7163 } else {
7164 BIND(L_fill_2_bytes);
7165 }
7166 BIND(L_exit);
7167 }
7168
7169 // encode char[] to byte[] in ISO_8859_1
7170 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7171 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7172 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7173 Register tmp5, Register result) {
7174 // rsi: src
7175 // rdi: dst
7176 // rdx: len
7177 // rcx: tmp5
7178 // rax: result
7179 ShortBranchVerifier sbv(this);
7180 assert_different_registers(src, dst, len, tmp5, result);
7181 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7182
7183 // set result
7184 xorl(result, result);
7185 // check for zero length
7186 testl(len, len);
7187 jcc(Assembler::zero, L_done);
7188 movl(result, len);
7189
7190 // Setup pointers
7191 lea(src, Address(src, len, Address::times_2)); // char[]
7192 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7193 negptr(len);
7194
7195 if (UseSSE42Intrinsics || UseAVX >= 2) {
7196 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
7197 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7198
7199 if (UseAVX >= 2) {
7200 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7201 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7202 movdl(tmp1Reg, tmp5);
7203 vpbroadcastd(tmp1Reg, tmp1Reg);
7204 jmpb(L_chars_32_check);
7205
7206 bind(L_copy_32_chars);
7207 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7208 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7209 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
7210 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7211 jccb(Assembler::notZero, L_copy_32_chars_exit);
7212 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector256 */ true);
7213 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector256 */ true);
7214 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7215
7216 bind(L_chars_32_check);
7217 addptr(len, 32);
7218 jccb(Assembler::lessEqual, L_copy_32_chars);
7219
7220 bind(L_copy_32_chars_exit);
7221 subptr(len, 16);
7222 jccb(Assembler::greater, L_copy_16_chars_exit);
7223
7224 } else if (UseSSE42Intrinsics) {
7225 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7226 movdl(tmp1Reg, tmp5);
7227 pshufd(tmp1Reg, tmp1Reg, 0);
7228 jmpb(L_chars_16_check);
7229 }
7230
7231 bind(L_copy_16_chars);
7232 if (UseAVX >= 2) {
7233 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7234 vptest(tmp2Reg, tmp1Reg);
7235 jccb(Assembler::notZero, L_copy_16_chars_exit);
7236 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector256 */ true);
7237 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector256 */ true);
7238 } else {
7239 if (UseAVX > 0) {
7240 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7241 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7242 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector256 */ false);
7243 } else {
7244 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7245 por(tmp2Reg, tmp3Reg);
7246 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7247 por(tmp2Reg, tmp4Reg);
7248 }
7249 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7250 jccb(Assembler::notZero, L_copy_16_chars_exit);
7251 packuswb(tmp3Reg, tmp4Reg);
7252 }
7253 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7254
7255 bind(L_chars_16_check);
7256 addptr(len, 16);
7257 jccb(Assembler::lessEqual, L_copy_16_chars);
7258
7259 bind(L_copy_16_chars_exit);
7260 if (UseAVX >= 2) {
7261 // clean upper bits of YMM registers
7262 vzeroupper();
7263 }
7264 subptr(len, 8);
7265 jccb(Assembler::greater, L_copy_8_chars_exit);
7266
7267 bind(L_copy_8_chars);
7268 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7269 ptest(tmp3Reg, tmp1Reg);
7270 jccb(Assembler::notZero, L_copy_8_chars_exit);
7271 packuswb(tmp3Reg, tmp1Reg);
7272 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7273 addptr(len, 8);
7274 jccb(Assembler::lessEqual, L_copy_8_chars);
7275
7276 bind(L_copy_8_chars_exit);
7277 subptr(len, 8);
7278 jccb(Assembler::zero, L_done);
7279 }
7280
7281 bind(L_copy_1_char);
7282 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7283 testl(tmp5, 0xff00); // check if Unicode char
7284 jccb(Assembler::notZero, L_copy_1_char_exit);
7285 movb(Address(dst, len, Address::times_1, 0), tmp5);
7286 addptr(len, 1);
7287 jccb(Assembler::less, L_copy_1_char);
7288
7289 bind(L_copy_1_char_exit);
7290 addptr(result, len); // len is negative count of not processed elements
7291 bind(L_done);
7292 }
7293
7294 #ifdef _LP64
7295 /**
7296 * Helper for multiply_to_len().
7297 */
7298 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7299 addq(dest_lo, src1);
7300 adcq(dest_hi, 0);
7301 addq(dest_lo, src2);
7302 adcq(dest_hi, 0);
7303 }
7304
7305 /**
7306 * Multiply 64 bit by 64 bit first loop.
7307 */
7308 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7309 Register y, Register y_idx, Register z,
7310 Register carry, Register product,
7311 Register idx, Register kdx) {
7312 //
7313 // jlong carry, x[], y[], z[];
7314 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7315 // huge_128 product = y[idx] * x[xstart] + carry;
7316 // z[kdx] = (jlong)product;
7317 // carry = (jlong)(product >>> 64);
7318 // }
7319 // z[xstart] = carry;
7320 //
7321
7322 Label L_first_loop, L_first_loop_exit;
7323 Label L_one_x, L_one_y, L_multiply;
7324
7325 decrementl(xstart);
7326 jcc(Assembler::negative, L_one_x);
7327
7328 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7329 rorq(x_xstart, 32); // convert big-endian to little-endian
7330
7331 bind(L_first_loop);
7332 decrementl(idx);
7333 jcc(Assembler::negative, L_first_loop_exit);
7334 decrementl(idx);
7335 jcc(Assembler::negative, L_one_y);
7336 movq(y_idx, Address(y, idx, Address::times_4, 0));
7337 rorq(y_idx, 32); // convert big-endian to little-endian
7338 bind(L_multiply);
7339 movq(product, x_xstart);
7340 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7341 addq(product, carry);
7342 adcq(rdx, 0);
7343 subl(kdx, 2);
7344 movl(Address(z, kdx, Address::times_4, 4), product);
7345 shrq(product, 32);
7346 movl(Address(z, kdx, Address::times_4, 0), product);
7347 movq(carry, rdx);
7348 jmp(L_first_loop);
7349
7350 bind(L_one_y);
7351 movl(y_idx, Address(y, 0));
7352 jmp(L_multiply);
7353
7354 bind(L_one_x);
7355 movl(x_xstart, Address(x, 0));
7356 jmp(L_first_loop);
7357
7358 bind(L_first_loop_exit);
7359 }
7360
7361 /**
7362 * Multiply 64 bit by 64 bit and add 128 bit.
7363 */
7364 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7365 Register yz_idx, Register idx,
7366 Register carry, Register product, int offset) {
7367 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7368 // z[kdx] = (jlong)product;
7369
7370 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7371 rorq(yz_idx, 32); // convert big-endian to little-endian
7372 movq(product, x_xstart);
7373 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7374 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7375 rorq(yz_idx, 32); // convert big-endian to little-endian
7376
7377 add2_with_carry(rdx, product, carry, yz_idx);
7378
7379 movl(Address(z, idx, Address::times_4, offset+4), product);
7380 shrq(product, 32);
7381 movl(Address(z, idx, Address::times_4, offset), product);
7382
7383 }
7384
7385 /**
7386 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7387 */
7388 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7389 Register yz_idx, Register idx, Register jdx,
7390 Register carry, Register product,
7391 Register carry2) {
7392 // jlong carry, x[], y[], z[];
7393 // int kdx = ystart+1;
7394 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7395 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7396 // z[kdx+idx+1] = (jlong)product;
7397 // jlong carry2 = (jlong)(product >>> 64);
7398 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7399 // z[kdx+idx] = (jlong)product;
7400 // carry = (jlong)(product >>> 64);
7401 // }
7402 // idx += 2;
7403 // if (idx > 0) {
7404 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7405 // z[kdx+idx] = (jlong)product;
7406 // carry = (jlong)(product >>> 64);
7407 // }
7408 //
7409
7410 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7411
7412 movl(jdx, idx);
7413 andl(jdx, 0xFFFFFFFC);
7414 shrl(jdx, 2);
7415
7416 bind(L_third_loop);
7417 subl(jdx, 1);
7418 jcc(Assembler::negative, L_third_loop_exit);
7419 subl(idx, 4);
7420
7421 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7422 movq(carry2, rdx);
7423
7424 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7425 movq(carry, rdx);
7426 jmp(L_third_loop);
7427
7428 bind (L_third_loop_exit);
7429
7430 andl (idx, 0x3);
7431 jcc(Assembler::zero, L_post_third_loop_done);
7432
7433 Label L_check_1;
7434 subl(idx, 2);
7435 jcc(Assembler::negative, L_check_1);
7436
7437 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7438 movq(carry, rdx);
7439
7440 bind (L_check_1);
7441 addl (idx, 0x2);
7442 andl (idx, 0x1);
7443 subl(idx, 1);
7444 jcc(Assembler::negative, L_post_third_loop_done);
7445
7446 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7447 movq(product, x_xstart);
7448 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7449 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7450
7451 add2_with_carry(rdx, product, yz_idx, carry);
7452
7453 movl(Address(z, idx, Address::times_4, 0), product);
7454 shrq(product, 32);
7455
7456 shlq(rdx, 32);
7457 orq(product, rdx);
7458 movq(carry, product);
7459
7460 bind(L_post_third_loop_done);
7461 }
7462
7463 /**
7464 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7465 *
7466 */
7467 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7468 Register carry, Register carry2,
7469 Register idx, Register jdx,
7470 Register yz_idx1, Register yz_idx2,
7471 Register tmp, Register tmp3, Register tmp4) {
7472 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7473
7474 // jlong carry, x[], y[], z[];
7475 // int kdx = ystart+1;
7476 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7477 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7478 // jlong carry2 = (jlong)(tmp3 >>> 64);
7479 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7480 // carry = (jlong)(tmp4 >>> 64);
7481 // z[kdx+idx+1] = (jlong)tmp3;
7482 // z[kdx+idx] = (jlong)tmp4;
7483 // }
7484 // idx += 2;
7485 // if (idx > 0) {
7486 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7487 // z[kdx+idx] = (jlong)yz_idx1;
7488 // carry = (jlong)(yz_idx1 >>> 64);
7489 // }
7490 //
7491
7492 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7493
7494 movl(jdx, idx);
7495 andl(jdx, 0xFFFFFFFC);
7496 shrl(jdx, 2);
7497
7498 bind(L_third_loop);
7499 subl(jdx, 1);
7500 jcc(Assembler::negative, L_third_loop_exit);
7501 subl(idx, 4);
7502
7503 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7504 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7505 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7506 rorxq(yz_idx2, yz_idx2, 32);
7507
7508 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7509 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7510
7511 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7512 rorxq(yz_idx1, yz_idx1, 32);
7513 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7514 rorxq(yz_idx2, yz_idx2, 32);
7515
7516 if (VM_Version::supports_adx()) {
7517 adcxq(tmp3, carry);
7518 adoxq(tmp3, yz_idx1);
7519
7520 adcxq(tmp4, tmp);
7521 adoxq(tmp4, yz_idx2);
7522
7523 movl(carry, 0); // does not affect flags
7524 adcxq(carry2, carry);
7525 adoxq(carry2, carry);
7526 } else {
7527 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7528 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7529 }
7530 movq(carry, carry2);
7531
7532 movl(Address(z, idx, Address::times_4, 12), tmp3);
7533 shrq(tmp3, 32);
7534 movl(Address(z, idx, Address::times_4, 8), tmp3);
7535
7536 movl(Address(z, idx, Address::times_4, 4), tmp4);
7537 shrq(tmp4, 32);
7538 movl(Address(z, idx, Address::times_4, 0), tmp4);
7539
7540 jmp(L_third_loop);
7541
7542 bind (L_third_loop_exit);
7543
7544 andl (idx, 0x3);
7545 jcc(Assembler::zero, L_post_third_loop_done);
7546
7547 Label L_check_1;
7548 subl(idx, 2);
7549 jcc(Assembler::negative, L_check_1);
7550
7551 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7552 rorxq(yz_idx1, yz_idx1, 32);
7553 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7554 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7555 rorxq(yz_idx2, yz_idx2, 32);
7556
7557 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7558
7559 movl(Address(z, idx, Address::times_4, 4), tmp3);
7560 shrq(tmp3, 32);
7561 movl(Address(z, idx, Address::times_4, 0), tmp3);
7562 movq(carry, tmp4);
7563
7564 bind (L_check_1);
7565 addl (idx, 0x2);
7566 andl (idx, 0x1);
7567 subl(idx, 1);
7568 jcc(Assembler::negative, L_post_third_loop_done);
7569 movl(tmp4, Address(y, idx, Address::times_4, 0));
7570 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7571 movl(tmp4, Address(z, idx, Address::times_4, 0));
7572
7573 add2_with_carry(carry2, tmp3, tmp4, carry);
7574
7575 movl(Address(z, idx, Address::times_4, 0), tmp3);
7576 shrq(tmp3, 32);
7577
7578 shlq(carry2, 32);
7579 orq(tmp3, carry2);
7580 movq(carry, tmp3);
7581
7582 bind(L_post_third_loop_done);
7583 }
7584
7585 /**
7586 * Code for BigInteger::multiplyToLen() instrinsic.
7587 *
7588 * rdi: x
7589 * rax: xlen
7590 * rsi: y
7591 * rcx: ylen
7592 * r8: z
7593 * r11: zlen
7594 * r12: tmp1
7595 * r13: tmp2
7596 * r14: tmp3
7597 * r15: tmp4
7598 * rbx: tmp5
7599 *
7600 */
7601 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7602 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7603 ShortBranchVerifier sbv(this);
7604 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7605
7606 push(tmp1);
7607 push(tmp2);
7608 push(tmp3);
7609 push(tmp4);
7610 push(tmp5);
7611
7612 push(xlen);
7613 push(zlen);
7614
7615 const Register idx = tmp1;
7616 const Register kdx = tmp2;
7617 const Register xstart = tmp3;
7618
7619 const Register y_idx = tmp4;
7620 const Register carry = tmp5;
7621 const Register product = xlen;
7622 const Register x_xstart = zlen; // reuse register
7623
7624 // First Loop.
7625 //
7626 // final static long LONG_MASK = 0xffffffffL;
7627 // int xstart = xlen - 1;
7628 // int ystart = ylen - 1;
7629 // long carry = 0;
7630 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7631 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7632 // z[kdx] = (int)product;
7633 // carry = product >>> 32;
7634 // }
7635 // z[xstart] = (int)carry;
7636 //
7637
7638 movl(idx, ylen); // idx = ylen;
7639 movl(kdx, zlen); // kdx = xlen+ylen;
7640 xorq(carry, carry); // carry = 0;
7641
7642 Label L_done;
7643
7644 movl(xstart, xlen);
7645 decrementl(xstart);
7646 jcc(Assembler::negative, L_done);
7647
7648 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7649
7650 Label L_second_loop;
7651 testl(kdx, kdx);
7652 jcc(Assembler::zero, L_second_loop);
7653
7654 Label L_carry;
7655 subl(kdx, 1);
7656 jcc(Assembler::zero, L_carry);
7657
7658 movl(Address(z, kdx, Address::times_4, 0), carry);
7659 shrq(carry, 32);
7660 subl(kdx, 1);
7661
7662 bind(L_carry);
7663 movl(Address(z, kdx, Address::times_4, 0), carry);
7664
7665 // Second and third (nested) loops.
7666 //
7667 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7668 // carry = 0;
7669 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7670 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7671 // (z[k] & LONG_MASK) + carry;
7672 // z[k] = (int)product;
7673 // carry = product >>> 32;
7674 // }
7675 // z[i] = (int)carry;
7676 // }
7677 //
7678 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7679
7680 const Register jdx = tmp1;
7681
7682 bind(L_second_loop);
7683 xorl(carry, carry); // carry = 0;
7684 movl(jdx, ylen); // j = ystart+1
7685
7686 subl(xstart, 1); // i = xstart-1;
7687 jcc(Assembler::negative, L_done);
7688
7689 push (z);
7690
7691 Label L_last_x;
7692 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7693 subl(xstart, 1); // i = xstart-1;
7694 jcc(Assembler::negative, L_last_x);
7695
7696 if (UseBMI2Instructions) {
7697 movq(rdx, Address(x, xstart, Address::times_4, 0));
7698 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7699 } else {
7700 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7701 rorq(x_xstart, 32); // convert big-endian to little-endian
7702 }
7703
7704 Label L_third_loop_prologue;
7705 bind(L_third_loop_prologue);
7706
7707 push (x);
7708 push (xstart);
7709 push (ylen);
7710
7711
7712 if (UseBMI2Instructions) {
7713 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7714 } else { // !UseBMI2Instructions
7715 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7716 }
7717
7718 pop(ylen);
7719 pop(xlen);
7720 pop(x);
7721 pop(z);
7722
7723 movl(tmp3, xlen);
7724 addl(tmp3, 1);
7725 movl(Address(z, tmp3, Address::times_4, 0), carry);
7726 subl(tmp3, 1);
7727 jccb(Assembler::negative, L_done);
7728
7729 shrq(carry, 32);
7730 movl(Address(z, tmp3, Address::times_4, 0), carry);
7731 jmp(L_second_loop);
7732
7733 // Next infrequent code is moved outside loops.
7734 bind(L_last_x);
7735 if (UseBMI2Instructions) {
7736 movl(rdx, Address(x, 0));
7737 } else {
7738 movl(x_xstart, Address(x, 0));
7739 }
7740 jmp(L_third_loop_prologue);
7741
7742 bind(L_done);
7743
7744 pop(zlen);
7745 pop(xlen);
7746
7747 pop(tmp5);
7748 pop(tmp4);
7749 pop(tmp3);
7750 pop(tmp2);
7751 pop(tmp1);
7752 }
7753 #endif
7754
7755 /**
7756 * Emits code to update CRC-32 with a byte value according to constants in table
7757 *
7758 * @param [in,out]crc Register containing the crc.
7759 * @param [in]val Register containing the byte to fold into the CRC.
7760 * @param [in]table Register containing the table of crc constants.
7761 *
7762 * uint32_t crc;
7763 * val = crc_table[(val ^ crc) & 0xFF];
7764 * crc = val ^ (crc >> 8);
7765 *
7766 */
7767 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
7768 xorl(val, crc);
7769 andl(val, 0xFF);
7770 shrl(crc, 8); // unsigned shift
7771 xorl(crc, Address(table, val, Address::times_4, 0));
7772 }
7773
7774 /**
7775 * Fold 128-bit data chunk
7776 */
7777 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
7778 if (UseAVX > 0) {
7779 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
7780 vpclmulldq(xcrc, xK, xcrc); // [63:0]
7781 vpxor(xcrc, xcrc, Address(buf, offset), false /* vector256 */);
7782 pxor(xcrc, xtmp);
7783 } else {
7784 movdqa(xtmp, xcrc);
7785 pclmulhdq(xtmp, xK); // [123:64]
7786 pclmulldq(xcrc, xK); // [63:0]
7787 pxor(xcrc, xtmp);
7788 movdqu(xtmp, Address(buf, offset));
7789 pxor(xcrc, xtmp);
7790 }
7791 }
7792
7793 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
7794 if (UseAVX > 0) {
7795 vpclmulhdq(xtmp, xK, xcrc);
7796 vpclmulldq(xcrc, xK, xcrc);
7797 pxor(xcrc, xbuf);
7798 pxor(xcrc, xtmp);
7799 } else {
7800 movdqa(xtmp, xcrc);
7801 pclmulhdq(xtmp, xK);
7802 pclmulldq(xcrc, xK);
7803 pxor(xcrc, xbuf);
7804 pxor(xcrc, xtmp);
7805 }
7806 }
7807
7808 /**
7809 * 8-bit folds to compute 32-bit CRC
7810 *
7811 * uint64_t xcrc;
7812 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
7813 */
7814 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
7815 movdl(tmp, xcrc);
7816 andl(tmp, 0xFF);
7817 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
7818 psrldq(xcrc, 1); // unsigned shift one byte
7819 pxor(xcrc, xtmp);
7820 }
7821
7822 /**
7823 * uint32_t crc;
7824 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
7825 */
7826 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
7827 movl(tmp, crc);
7828 andl(tmp, 0xFF);
7829 shrl(crc, 8);
7830 xorl(crc, Address(table, tmp, Address::times_4, 0));
7831 }
7832
7833 /**
7834 * @param crc register containing existing CRC (32-bit)
7835 * @param buf register pointing to input byte buffer (byte*)
7836 * @param len register containing number of bytes
7837 * @param table register that will contain address of CRC table
7838 * @param tmp scratch register
7839 */
7840 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
7841 assert_different_registers(crc, buf, len, table, tmp, rax);
7842
7843 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7844 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7845
7846 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
7847 notl(crc); // ~crc
7848 cmpl(len, 16);
7849 jcc(Assembler::less, L_tail);
7850
7851 // Align buffer to 16 bytes
7852 movl(tmp, buf);
7853 andl(tmp, 0xF);
7854 jccb(Assembler::zero, L_aligned);
7855 subl(tmp, 16);
7856 addl(len, tmp);
7857
7858 align(4);
7859 BIND(L_align_loop);
7860 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7861 update_byte_crc32(crc, rax, table);
7862 increment(buf);
7863 incrementl(tmp);
7864 jccb(Assembler::less, L_align_loop);
7865
7866 BIND(L_aligned);
7867 movl(tmp, len); // save
7868 shrl(len, 4);
7869 jcc(Assembler::zero, L_tail_restore);
7870
7871 // Fold crc into first bytes of vector
7872 movdqa(xmm1, Address(buf, 0));
7873 movdl(rax, xmm1);
7874 xorl(crc, rax);
7875 pinsrd(xmm1, crc, 0);
7876 addptr(buf, 16);
7877 subl(len, 4); // len > 0
7878 jcc(Assembler::less, L_fold_tail);
7879
7880 movdqa(xmm2, Address(buf, 0));
7881 movdqa(xmm3, Address(buf, 16));
7882 movdqa(xmm4, Address(buf, 32));
7883 addptr(buf, 48);
7884 subl(len, 3);
7885 jcc(Assembler::lessEqual, L_fold_512b);
7886
7887 // Fold total 512 bits of polynomial on each iteration,
7888 // 128 bits per each of 4 parallel streams.
7889 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
7890
7891 align(32);
7892 BIND(L_fold_512b_loop);
7893 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7894 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
7895 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
7896 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
7897 addptr(buf, 64);
7898 subl(len, 4);
7899 jcc(Assembler::greater, L_fold_512b_loop);
7900
7901 // Fold 512 bits to 128 bits.
7902 BIND(L_fold_512b);
7903 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7904 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
7905 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
7906 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
7907
7908 // Fold the rest of 128 bits data chunks
7909 BIND(L_fold_tail);
7910 addl(len, 3);
7911 jccb(Assembler::lessEqual, L_fold_128b);
7912 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7913
7914 BIND(L_fold_tail_loop);
7915 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7916 addptr(buf, 16);
7917 decrementl(len);
7918 jccb(Assembler::greater, L_fold_tail_loop);
7919
7920 // Fold 128 bits in xmm1 down into 32 bits in crc register.
7921 BIND(L_fold_128b);
7922 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
7923 if (UseAVX > 0) {
7924 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
7925 vpand(xmm3, xmm0, xmm2, false /* vector256 */);
7926 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
7927 } else {
7928 movdqa(xmm2, xmm0);
7929 pclmulqdq(xmm2, xmm1, 0x1);
7930 movdqa(xmm3, xmm0);
7931 pand(xmm3, xmm2);
7932 pclmulqdq(xmm0, xmm3, 0x1);
7933 }
7934 psrldq(xmm1, 8);
7935 psrldq(xmm2, 4);
7936 pxor(xmm0, xmm1);
7937 pxor(xmm0, xmm2);
7938
7939 // 8 8-bit folds to compute 32-bit CRC.
7940 for (int j = 0; j < 4; j++) {
7941 fold_8bit_crc32(xmm0, table, xmm1, rax);
7942 }
7943 movdl(crc, xmm0); // mov 32 bits to general register
7944 for (int j = 0; j < 4; j++) {
7945 fold_8bit_crc32(crc, table, rax);
7946 }
7947
7948 BIND(L_tail_restore);
7949 movl(len, tmp); // restore
7950 BIND(L_tail);
7951 andl(len, 0xf);
7952 jccb(Assembler::zero, L_exit);
7953
7954 // Fold the rest of bytes
7955 align(4);
7956 BIND(L_tail_loop);
7957 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7958 update_byte_crc32(crc, rax, table);
7959 increment(buf);
7960 decrementl(len);
7961 jccb(Assembler::greater, L_tail_loop);
7962
7963 BIND(L_exit);
7964 notl(crc); // ~c
7965 }
7966
7967 #undef BIND
7968 #undef BLOCK_COMMENT
7969
7970
7971 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
7972 switch (cond) {
7973 // Note some conditions are synonyms for others
7974 case Assembler::zero: return Assembler::notZero;
7975 case Assembler::notZero: return Assembler::zero;
7976 case Assembler::less: return Assembler::greaterEqual;
7977 case Assembler::lessEqual: return Assembler::greater;
7978 case Assembler::greater: return Assembler::lessEqual;
7979 case Assembler::greaterEqual: return Assembler::less;
7980 case Assembler::below: return Assembler::aboveEqual;
7981 case Assembler::belowEqual: return Assembler::above;
7982 case Assembler::above: return Assembler::belowEqual;
7983 case Assembler::aboveEqual: return Assembler::below;
7984 case Assembler::overflow: return Assembler::noOverflow;
7985 case Assembler::noOverflow: return Assembler::overflow;
7986 case Assembler::negative: return Assembler::positive;
7987 case Assembler::positive: return Assembler::negative;
7988 case Assembler::parity: return Assembler::noParity;
7989 case Assembler::noParity: return Assembler::parity;
7990 }
7991 ShouldNotReachHere(); return Assembler::overflow;
7992 }
7993
7994 SkipIfEqual::SkipIfEqual(
7995 MacroAssembler* masm, const bool* flag_addr, bool value) {
7996 _masm = masm;
7997 _masm->cmp8(ExternalAddress((address)flag_addr), value);
7998 _masm->jcc(Assembler::equal, _label);
7999 }
8000
8001 SkipIfEqual::~SkipIfEqual() {
8002 _masm->bind(_label);
8003 }