68
69 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
70 warning("BIS instructions are not available on this CPU");
71 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
72 }
73
74 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
75
76 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
77 if (ArraycopySrcPrefetchDistance >= 4096)
78 ArraycopySrcPrefetchDistance = 4064;
79 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
80 if (ArraycopyDstPrefetchDistance >= 4096)
81 ArraycopyDstPrefetchDistance = 4064;
82
83 UseSSE = 0; // Only on x86 and x64
84
85 _supports_cx8 = has_v9();
86 _supports_atomic_getset4 = true; // swap instruction
87
88 // There are Fujitsu Sparc64 CPUs which support blk_init as well so
89 // we have to take this check out of the 'is_niagara()' block below.
90 if (has_blk_init()) {
91 // When using CMS or G1, we cannot use memset() in BOT updates
92 // because the sun4v/CMT version in libc_psr uses BIS which
93 // exposes "phantom zeros" to concurrent readers. See 6948537.
94 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) {
95 FLAG_SET_DEFAULT(UseMemSetInBOT, false);
96 }
97 // Issue a stern warning if the user has explicitly set
98 // UseMemSetInBOT (it is known to cause issues), but allow
99 // use for experimentation and debugging.
100 if (UseConcMarkSweepGC || UseG1GC) {
101 if (UseMemSetInBOT) {
102 assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error");
103 warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability"
104 " on sun4v; please understand that you are using at your own risk!");
105 }
106 }
107 }
108
109 if (is_niagara()) {
110 // Indirect branch is the same cost as direct
111 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
112 FLAG_SET_DEFAULT(UseInlineCaches, false);
113 }
114 // Align loops on a single instruction boundary.
115 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
116 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
117 }
118 #ifdef _LP64
119 // 32-bit oops don't make sense for the 64-bit VM on sparc
120 // since the 32-bit VM has the same registers and smaller objects.
121 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
122 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
123 #endif // _LP64
124 #ifdef COMPILER2
125 // Indirect branch is the same cost as direct
126 if (FLAG_IS_DEFAULT(UseJumpTables)) {
127 FLAG_SET_DEFAULT(UseJumpTables, true);
128 }
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68
69 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
70 warning("BIS instructions are not available on this CPU");
71 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
72 }
73
74 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
75
76 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
77 if (ArraycopySrcPrefetchDistance >= 4096)
78 ArraycopySrcPrefetchDistance = 4064;
79 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
80 if (ArraycopyDstPrefetchDistance >= 4096)
81 ArraycopyDstPrefetchDistance = 4064;
82
83 UseSSE = 0; // Only on x86 and x64
84
85 _supports_cx8 = has_v9();
86 _supports_atomic_getset4 = true; // swap instruction
87
88 if (is_niagara()) {
89 // Indirect branch is the same cost as direct
90 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
91 FLAG_SET_DEFAULT(UseInlineCaches, false);
92 }
93 // Align loops on a single instruction boundary.
94 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
95 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
96 }
97 #ifdef _LP64
98 // 32-bit oops don't make sense for the 64-bit VM on sparc
99 // since the 32-bit VM has the same registers and smaller objects.
100 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
101 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
102 #endif // _LP64
103 #ifdef COMPILER2
104 // Indirect branch is the same cost as direct
105 if (FLAG_IS_DEFAULT(UseJumpTables)) {
106 FLAG_SET_DEFAULT(UseJumpTables, true);
107 }
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