1 /* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2017, SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "asm/macroAssembler.inline.hpp" 29 #include "compiler/disassembler.hpp" 30 #include "memory/resourceArea.hpp" 31 #include "runtime/java.hpp" 32 #include "runtime/os.hpp" 33 #include "runtime/stubCodeGenerator.hpp" 34 #include "utilities/defaultStream.hpp" 35 #include "utilities/globalDefinitions.hpp" 36 #include "vm_version_ppc.hpp" 37 38 # include <sys/sysinfo.h> 39 40 bool VM_Version::_is_determine_features_test_running = false; 41 uint64_t VM_Version::_dscr_val = 0; 42 43 #define MSG(flag) \ 44 if (flag && !FLAG_IS_DEFAULT(flag)) \ 45 jio_fprintf(defaultStream::error_stream(), \ 46 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \ 47 " -XX:+" #flag " will be disabled!\n"); 48 49 void VM_Version::initialize() { 50 51 // Test which instructions are supported and measure cache line size. 52 determine_features(); 53 54 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features. 55 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) { 56 if (VM_Version::has_lqarx()) { 57 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8); 58 } else if (VM_Version::has_popcntw()) { 59 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7); 60 } else if (VM_Version::has_cmpb()) { 61 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6); 62 } else if (VM_Version::has_popcntb()) { 63 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5); 64 } else { 65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0); 66 } 67 } 68 69 bool PowerArchitecturePPC64_ok = false; 70 switch (PowerArchitecturePPC64) { 71 case 8: if (!VM_Version::has_lqarx() ) break; 72 case 7: if (!VM_Version::has_popcntw()) break; 73 case 6: if (!VM_Version::has_cmpb() ) break; 74 case 5: if (!VM_Version::has_popcntb()) break; 75 case 0: PowerArchitecturePPC64_ok = true; break; 76 default: break; 77 } 78 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to " 79 UINTX_FORMAT " on this machine", PowerArchitecturePPC64); 80 81 // Power 8: Configure Data Stream Control Register. 82 if (has_mfdscr()) { 83 config_dscr(); 84 } 85 86 if (!UseSIGTRAP) { 87 MSG(TrapBasedICMissChecks); 88 MSG(TrapBasedNotEntrantChecks); 89 MSG(TrapBasedNullChecks); 90 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false); 91 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false); 92 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false); 93 } 94 95 #ifdef COMPILER2 96 if (!UseSIGTRAP) { 97 MSG(TrapBasedRangeChecks); 98 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false); 99 } 100 101 // On Power6 test for section size. 102 if (PowerArchitecturePPC64 == 6) { 103 determine_section_size(); 104 // TODO: PPC port } else { 105 // TODO: PPC port PdScheduling::power6SectorSize = 0x20; 106 } 107 108 MaxVectorSize = 8; 109 #endif 110 111 // Create and print feature-string. 112 char buf[(num_features+1) * 16]; // Max 16 chars per feature. 113 jio_snprintf(buf, sizeof(buf), 114 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 115 (has_fsqrt() ? " fsqrt" : ""), 116 (has_isel() ? " isel" : ""), 117 (has_lxarxeh() ? " lxarxeh" : ""), 118 (has_cmpb() ? " cmpb" : ""), 119 //(has_mftgpr()? " mftgpr" : ""), 120 (has_popcntb() ? " popcntb" : ""), 121 (has_popcntw() ? " popcntw" : ""), 122 (has_fcfids() ? " fcfids" : ""), 123 (has_vand() ? " vand" : ""), 124 (has_lqarx() ? " lqarx" : ""), 125 (has_vcipher() ? " aes" : ""), 126 (has_vpmsumb() ? " vpmsumb" : ""), 127 (has_tcheck() ? " tcheck" : ""), 128 (has_mfdscr() ? " mfdscr" : ""), 129 (has_vsx() ? " vsx" : ""), 130 (has_ldbrx() ? " ldbrx" : ""), 131 (has_stdbrx() ? " stdbrx" : "") 132 // Make sure number of %s matches num_features! 133 ); 134 _features_string = os::strdup(buf); 135 if (Verbose) { 136 print_features(); 137 } 138 139 // PPC64 supports 8-byte compare-exchange operations (see 140 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr) 141 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile). 142 _supports_cx8 = true; 143 144 // Used by C1. 145 _supports_atomic_getset4 = true; 146 _supports_atomic_getadd4 = true; 147 _supports_atomic_getset8 = true; 148 _supports_atomic_getadd8 = true; 149 150 UseSSE = 0; // Only on x86 and x64 151 152 intx cache_line_size = L1_data_cache_line_size(); 153 154 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1; 155 156 if (AllocatePrefetchStyle == 4) { 157 AllocatePrefetchStepSize = cache_line_size; // Need exact value. 158 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default. 159 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined? 160 } else { 161 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size; 162 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value. 163 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined? 164 } 165 166 assert(AllocatePrefetchLines > 0, "invalid value"); 167 if (AllocatePrefetchLines < 1) { // Set valid value in product VM. 168 AllocatePrefetchLines = 1; // Conservative value. 169 } 170 171 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) { 172 AllocatePrefetchStyle = 1; // Fall back if inappropriate. 173 } 174 175 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 176 177 // If defined(VM_LITTLE_ENDIAN) and running on Power8 or newer hardware, 178 // the implementation uses the vector instructions available with Power8. 179 // In all other cases, the implementation uses only generally available instructions. 180 if (!UseCRC32Intrinsics) { 181 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 182 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true); 183 } 184 } 185 186 // Implementation does not use any of the vector instructions available with Power8. 187 // Their exploitation is still pending (aka "work in progress"). 188 if (!UseCRC32CIntrinsics) { 189 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 190 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true); 191 } 192 } 193 194 // TODO: Provide implementation. 195 if (UseAdler32Intrinsics) { 196 warning("Adler32Intrinsics not available on this CPU."); 197 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); 198 } 199 200 // The AES intrinsic stubs require AES instruction support. 201 #if defined(VM_LITTLE_ENDIAN) 202 if (has_vcipher()) { 203 if (FLAG_IS_DEFAULT(UseAES)) { 204 UseAES = true; 205 } 206 } else if (UseAES) { 207 if (!FLAG_IS_DEFAULT(UseAES)) 208 warning("AES instructions are not available on this CPU"); 209 FLAG_SET_DEFAULT(UseAES, false); 210 } 211 212 if (UseAES && has_vcipher()) { 213 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { 214 UseAESIntrinsics = true; 215 } 216 } else if (UseAESIntrinsics) { 217 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) 218 warning("AES intrinsics are not available on this CPU"); 219 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 220 } 221 222 #else 223 if (UseAES) { 224 warning("AES instructions are not available on this CPU"); 225 FLAG_SET_DEFAULT(UseAES, false); 226 } 227 if (UseAESIntrinsics) { 228 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) 229 warning("AES intrinsics are not available on this CPU"); 230 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 231 } 232 #endif 233 234 if (UseAESCTRIntrinsics) { 235 warning("AES/CTR intrinsics are not available on this CPU"); 236 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 237 } 238 239 if (UseGHASHIntrinsics) { 240 warning("GHASH intrinsics are not available on this CPU"); 241 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 242 } 243 244 if (FLAG_IS_DEFAULT(UseFMA)) { 245 FLAG_SET_DEFAULT(UseFMA, true); 246 } 247 248 if (UseSHA) { 249 warning("SHA instructions are not available on this CPU"); 250 FLAG_SET_DEFAULT(UseSHA, false); 251 } 252 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) { 253 warning("SHA intrinsics are not available on this CPU"); 254 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 255 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 256 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 257 } 258 259 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 260 UseMultiplyToLenIntrinsic = true; 261 } 262 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 263 UseMontgomeryMultiplyIntrinsic = true; 264 } 265 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { 266 UseMontgomerySquareIntrinsic = true; 267 } 268 269 if (UseVectorizedMismatchIntrinsic) { 270 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU."); 271 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); 272 } 273 274 275 // Adjust RTM (Restricted Transactional Memory) flags. 276 if (UseRTMLocking) { 277 // If CPU or OS are too old: 278 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 279 // setting during arguments processing. See use_biased_locking(). 280 // VM_Version_init() is executed after UseBiasedLocking is used 281 // in Thread::allocate(). 282 if (!has_tcheck()) { 283 vm_exit_during_initialization("RTM instructions are not available on this CPU"); 284 } 285 bool os_too_old = true; 286 #ifdef AIX 287 // Actually, this is supported since AIX 7.1.. Unfortunately, this first 288 // contained bugs, so that it can only be enabled after AIX 7.1.3.30. 289 // The Java property os.version, which is used in RTM tests to decide 290 // whether the feature is available, only knows major and minor versions. 291 // We don't want to change this property, as user code might depend on it. 292 // So the tests can not check on subversion 3.30, and we only enable RTM 293 // with AIX 7.2. 294 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2. 295 os_too_old = false; 296 } 297 #endif 298 #ifdef LINUX 299 // At least Linux kernel 4.2, as the problematic behavior of syscalls 300 // being called in the middle of a transaction has been addressed. 301 // Please, refer to commit b4b56f9ecab40f3b4ef53e130c9f6663be491894 302 // in Linux kernel source tree: https://goo.gl/Kc5i7A 303 if (os::Linux::os_version_is_known()) { 304 if (os::Linux::os_version() >= 0x040200) 305 os_too_old = false; 306 } else { 307 vm_exit_during_initialization("RTM can not be enabled: kernel version is unknown."); 308 } 309 #endif 310 if (os_too_old) { 311 vm_exit_during_initialization("RTM is not supported on this OS version."); 312 } 313 } 314 315 if (UseRTMLocking) { 316 #if INCLUDE_RTM_OPT 317 if (!UnlockExperimentalVMOptions) { 318 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. " 319 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag."); 320 } else { 321 warning("UseRTMLocking is only available as experimental option on this platform."); 322 } 323 if (!FLAG_IS_CMDLINE(UseRTMLocking)) { 324 // RTM locking should be used only for applications with 325 // high lock contention. For now we do not use it by default. 326 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); 327 } 328 if (!is_power_of_2(RTMTotalCountIncrRate)) { 329 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64"); 330 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64); 331 } 332 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) { 333 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50"); 334 FLAG_SET_DEFAULT(RTMAbortRatio, 50); 335 } 336 if (RTMSpinLoopCount < 0) { 337 warning("RTMSpinLoopCount must not be a negative value, resetting it to 0"); 338 FLAG_SET_DEFAULT(RTMSpinLoopCount, 0); 339 } 340 #else 341 // Only C2 does RTM locking optimization. 342 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 343 // setting during arguments processing. See use_biased_locking(). 344 vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); 345 #endif 346 } else { // !UseRTMLocking 347 if (UseRTMForStackLocks) { 348 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) { 349 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off"); 350 } 351 FLAG_SET_DEFAULT(UseRTMForStackLocks, false); 352 } 353 if (UseRTMDeopt) { 354 FLAG_SET_DEFAULT(UseRTMDeopt, false); 355 } 356 if (PrintPreciseRTMLockingStatistics) { 357 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); 358 } 359 } 360 361 // This machine allows unaligned memory accesses 362 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { 363 FLAG_SET_DEFAULT(UseUnalignedAccesses, true); 364 } 365 } 366 367 bool VM_Version::use_biased_locking() { 368 #if INCLUDE_RTM_OPT 369 // RTM locking is most useful when there is high lock contention and 370 // low data contention. With high lock contention the lock is usually 371 // inflated and biased locking is not suitable for that case. 372 // RTM locking code requires that biased locking is off. 373 // Note: we can't switch off UseBiasedLocking in get_processor_features() 374 // because it is used by Thread::allocate() which is called before 375 // VM_Version::initialize(). 376 if (UseRTMLocking && UseBiasedLocking) { 377 if (FLAG_IS_DEFAULT(UseBiasedLocking)) { 378 FLAG_SET_DEFAULT(UseBiasedLocking, false); 379 } else { 380 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." ); 381 UseBiasedLocking = false; 382 } 383 } 384 #endif 385 return UseBiasedLocking; 386 } 387 388 void VM_Version::print_features() { 389 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size()); 390 } 391 392 #ifdef COMPILER2 393 // Determine section size on power6: If section size is 8 instructions, 394 // there should be a difference between the two testloops of ~15 %. If 395 // no difference is detected the section is assumed to be 32 instructions. 396 void VM_Version::determine_section_size() { 397 398 int unroll = 80; 399 400 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord; 401 402 // Allocate space for the code. 403 ResourceMark rm; 404 CodeBuffer cb("detect_section_size", code_size, 0); 405 MacroAssembler* a = new MacroAssembler(&cb); 406 407 uint32_t *code = (uint32_t *)a->pc(); 408 // Emit code. 409 void (*test1)() = (void(*)())(void *)a->function_entry(); 410 411 Label l1; 412 413 a->li(R4, 1); 414 a->sldi(R4, R4, 28); 415 a->b(l1); 416 a->align(CodeEntryAlignment); 417 418 a->bind(l1); 419 420 for (int i = 0; i < unroll; i++) { 421 // Schleife 1 422 // ------- sector 0 ------------ 423 // ;; 0 424 a->nop(); // 1 425 a->fpnop0(); // 2 426 a->fpnop1(); // 3 427 a->addi(R4,R4, -1); // 4 428 429 // ;; 1 430 a->nop(); // 5 431 a->fmr(F6, F6); // 6 432 a->fmr(F7, F7); // 7 433 a->endgroup(); // 8 434 // ------- sector 8 ------------ 435 436 // ;; 2 437 a->nop(); // 9 438 a->nop(); // 10 439 a->fmr(F8, F8); // 11 440 a->fmr(F9, F9); // 12 441 442 // ;; 3 443 a->nop(); // 13 444 a->fmr(F10, F10); // 14 445 a->fmr(F11, F11); // 15 446 a->endgroup(); // 16 447 // -------- sector 16 ------------- 448 449 // ;; 4 450 a->nop(); // 17 451 a->nop(); // 18 452 a->fmr(F15, F15); // 19 453 a->fmr(F16, F16); // 20 454 455 // ;; 5 456 a->nop(); // 21 457 a->fmr(F17, F17); // 22 458 a->fmr(F18, F18); // 23 459 a->endgroup(); // 24 460 // ------- sector 24 ------------ 461 462 // ;; 6 463 a->nop(); // 25 464 a->nop(); // 26 465 a->fmr(F19, F19); // 27 466 a->fmr(F20, F20); // 28 467 468 // ;; 7 469 a->nop(); // 29 470 a->fmr(F21, F21); // 30 471 a->fmr(F22, F22); // 31 472 a->brnop0(); // 32 473 474 // ------- sector 32 ------------ 475 } 476 477 // ;; 8 478 a->cmpdi(CCR0, R4, unroll); // 33 479 a->bge(CCR0, l1); // 34 480 a->blr(); 481 482 // Emit code. 483 void (*test2)() = (void(*)())(void *)a->function_entry(); 484 // uint32_t *code = (uint32_t *)a->pc(); 485 486 Label l2; 487 488 a->li(R4, 1); 489 a->sldi(R4, R4, 28); 490 a->b(l2); 491 a->align(CodeEntryAlignment); 492 493 a->bind(l2); 494 495 for (int i = 0; i < unroll; i++) { 496 // Schleife 2 497 // ------- sector 0 ------------ 498 // ;; 0 499 a->brnop0(); // 1 500 a->nop(); // 2 501 //a->cmpdi(CCR0, R4, unroll); 502 a->fpnop0(); // 3 503 a->fpnop1(); // 4 504 a->addi(R4,R4, -1); // 5 505 506 // ;; 1 507 508 a->nop(); // 6 509 a->fmr(F6, F6); // 7 510 a->fmr(F7, F7); // 8 511 // ------- sector 8 --------------- 512 513 // ;; 2 514 a->endgroup(); // 9 515 516 // ;; 3 517 a->nop(); // 10 518 a->nop(); // 11 519 a->fmr(F8, F8); // 12 520 521 // ;; 4 522 a->fmr(F9, F9); // 13 523 a->nop(); // 14 524 a->fmr(F10, F10); // 15 525 526 // ;; 5 527 a->fmr(F11, F11); // 16 528 // -------- sector 16 ------------- 529 530 // ;; 6 531 a->endgroup(); // 17 532 533 // ;; 7 534 a->nop(); // 18 535 a->nop(); // 19 536 a->fmr(F15, F15); // 20 537 538 // ;; 8 539 a->fmr(F16, F16); // 21 540 a->nop(); // 22 541 a->fmr(F17, F17); // 23 542 543 // ;; 9 544 a->fmr(F18, F18); // 24 545 // -------- sector 24 ------------- 546 547 // ;; 10 548 a->endgroup(); // 25 549 550 // ;; 11 551 a->nop(); // 26 552 a->nop(); // 27 553 a->fmr(F19, F19); // 28 554 555 // ;; 12 556 a->fmr(F20, F20); // 29 557 a->nop(); // 30 558 a->fmr(F21, F21); // 31 559 560 // ;; 13 561 a->fmr(F22, F22); // 32 562 } 563 564 // -------- sector 32 ------------- 565 // ;; 14 566 a->cmpdi(CCR0, R4, unroll); // 33 567 a->bge(CCR0, l2); // 34 568 569 a->blr(); 570 uint32_t *code_end = (uint32_t *)a->pc(); 571 a->flush(); 572 573 double loop1_seconds,loop2_seconds, rel_diff; 574 uint64_t start1, stop1; 575 576 start1 = os::current_thread_cpu_time(false); 577 (*test1)(); 578 stop1 = os::current_thread_cpu_time(false); 579 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0); 580 581 582 start1 = os::current_thread_cpu_time(false); 583 (*test2)(); 584 stop1 = os::current_thread_cpu_time(false); 585 586 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0); 587 588 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100; 589 590 if (PrintAssembly) { 591 ttyLocker ttyl; 592 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 593 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 594 tty->print_cr("Time loop1 :%f", loop1_seconds); 595 tty->print_cr("Time loop2 :%f", loop2_seconds); 596 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff); 597 598 if (rel_diff > 12.0) { 599 tty->print_cr("Section Size 8 Instructions"); 600 } else{ 601 tty->print_cr("Section Size 32 Instructions or Power5"); 602 } 603 } 604 605 #if 0 // TODO: PPC port 606 // Set sector size (if not set explicitly). 607 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) { 608 if (rel_diff > 12.0) { 609 PdScheduling::power6SectorSize = 0x20; 610 } else { 611 PdScheduling::power6SectorSize = 0x80; 612 } 613 } else if (Power6SectorSize128PPC64) { 614 PdScheduling::power6SectorSize = 0x80; 615 } else { 616 PdScheduling::power6SectorSize = 0x20; 617 } 618 #endif 619 if (UsePower6SchedulerPPC64) Unimplemented(); 620 } 621 #endif // COMPILER2 622 623 void VM_Version::determine_features() { 624 #if defined(ABI_ELFv2) 625 // 1 InstWord per call for the blr instruction. 626 const int code_size = (num_features+1+2*1)*BytesPerInstWord; 627 #else 628 // 7 InstWords for each call (function descriptor + blr instruction). 629 const int code_size = (num_features+1+2*7)*BytesPerInstWord; 630 #endif 631 int features = 0; 632 633 // create test area 634 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size). 635 char test_area[BUFFER_SIZE]; 636 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1]; 637 638 // Allocate space for the code. 639 ResourceMark rm; 640 CodeBuffer cb("detect_cpu_features", code_size, 0); 641 MacroAssembler* a = new MacroAssembler(&cb); 642 643 // Must be set to true so we can generate the test code. 644 _features = VM_Version::all_features_m; 645 646 // Emit code. 647 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry(); 648 uint32_t *code = (uint32_t *)a->pc(); 649 // Don't use R0 in ldarx. 650 // Keep R3_ARG1 unmodified, it contains &field (see below). 651 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below). 652 a->fsqrt(F3, F4); // code[0] -> fsqrt_m 653 a->fsqrts(F3, F4); // code[1] -> fsqrts_m 654 a->isel(R7, R5, R6, 0); // code[2] -> isel_m 655 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m 656 a->cmpb(R7, R5, R6); // code[4] -> cmpb 657 a->popcntb(R7, R5); // code[5] -> popcntb 658 a->popcntw(R7, R5); // code[6] -> popcntw 659 a->fcfids(F3, F4); // code[7] -> fcfids 660 a->vand(VR0, VR0, VR0); // code[8] -> vand 661 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16 662 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m 663 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher 664 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb 665 a->tcheck(0); // code[12] -> tcheck 666 a->mfdscr(R0); // code[13] -> mfdscr 667 a->lxvd2x(VSR0, R3_ARG1); // code[14] -> vsx 668 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> ldbrx 669 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[16] -> stdbrx 670 a->blr(); 671 672 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it. 673 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry(); 674 a->dcbz(R3_ARG1); // R3_ARG1 = addr 675 a->blr(); 676 677 uint32_t *code_end = (uint32_t *)a->pc(); 678 a->flush(); 679 _features = VM_Version::unknown_m; 680 681 // Print the detection code. 682 if (PrintAssembly) { 683 ttyLocker ttyl; 684 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 685 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 686 } 687 688 // Measure cache line size. 689 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF. 690 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle. 691 int count = 0; // count zeroed bytes 692 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++; 693 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2"); 694 _L1_data_cache_line_size = count; 695 696 // Execute code. Illegal instructions will be replaced by 0 in the signal handler. 697 VM_Version::_is_determine_features_test_running = true; 698 // We must align the first argument to 16 bytes because of the lqarx check. 699 (*test)((address)align_size_up((intptr_t)mid_of_test_area, 16), (uint64_t)0); 700 VM_Version::_is_determine_features_test_running = false; 701 702 // determine which instructions are legal. 703 int feature_cntr = 0; 704 if (code[feature_cntr++]) features |= fsqrt_m; 705 if (code[feature_cntr++]) features |= fsqrts_m; 706 if (code[feature_cntr++]) features |= isel_m; 707 if (code[feature_cntr++]) features |= lxarxeh_m; 708 if (code[feature_cntr++]) features |= cmpb_m; 709 if (code[feature_cntr++]) features |= popcntb_m; 710 if (code[feature_cntr++]) features |= popcntw_m; 711 if (code[feature_cntr++]) features |= fcfids_m; 712 if (code[feature_cntr++]) features |= vand_m; 713 if (code[feature_cntr++]) features |= lqarx_m; 714 if (code[feature_cntr++]) features |= vcipher_m; 715 if (code[feature_cntr++]) features |= vpmsumb_m; 716 if (code[feature_cntr++]) features |= tcheck_m; 717 if (code[feature_cntr++]) features |= mfdscr_m; 718 if (code[feature_cntr++]) features |= vsx_m; 719 if (code[feature_cntr++]) features |= ldbrx_m; 720 if (code[feature_cntr++]) features |= stdbrx_m; 721 722 // Print the detection code. 723 if (PrintAssembly) { 724 ttyLocker ttyl; 725 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code)); 726 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 727 } 728 729 _features = features; 730 } 731 732 // Power 8: Configure Data Stream Control Register. 733 void VM_Version::config_dscr() { 734 // 7 InstWords for each call (function descriptor + blr instruction). 735 const int code_size = (2+2*7)*BytesPerInstWord; 736 737 // Allocate space for the code. 738 ResourceMark rm; 739 CodeBuffer cb("config_dscr", code_size, 0); 740 MacroAssembler* a = new MacroAssembler(&cb); 741 742 // Emit code. 743 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry(); 744 uint32_t *code = (uint32_t *)a->pc(); 745 a->mfdscr(R3); 746 a->blr(); 747 748 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry(); 749 a->mtdscr(R3); 750 a->blr(); 751 752 uint32_t *code_end = (uint32_t *)a->pc(); 753 a->flush(); 754 755 // Print the detection code. 756 if (PrintAssembly) { 757 ttyLocker ttyl; 758 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code)); 759 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 760 } 761 762 // Apply the configuration if needed. 763 _dscr_val = (*get_dscr)(); 764 if (Verbose) { 765 tty->print_cr("dscr value was 0x%lx" , _dscr_val); 766 } 767 bool change_requested = false; 768 if (DSCR_PPC64 != (uintx)-1) { 769 _dscr_val = DSCR_PPC64; 770 change_requested = true; 771 } 772 if (DSCR_DPFD_PPC64 <= 7) { 773 uint64_t mask = 0x7; 774 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) { 775 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64); 776 change_requested = true; 777 } 778 } 779 if (DSCR_URG_PPC64 <= 7) { 780 uint64_t mask = 0x7 << 6; 781 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) { 782 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6); 783 change_requested = true; 784 } 785 } 786 if (change_requested) { 787 (*set_dscr)(_dscr_val); 788 if (Verbose) { 789 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)()); 790 } 791 } 792 } 793 794 static uint64_t saved_features = 0; 795 796 void VM_Version::allow_all() { 797 saved_features = _features; 798 _features = all_features_m; 799 } 800 801 void VM_Version::revert() { 802 _features = saved_features; 803 }