1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "logging/log.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "prims/jvm.h"
30 #include "runtime/java.hpp"
31 #include "runtime/os.hpp"
32 #include "runtime/stubCodeGenerator.hpp"
33 #include "vm_version_sparc.hpp"
34
35 unsigned int VM_Version::_L2_data_cache_line_size = 0;
36
37 void VM_Version::initialize() {
38 assert(_features != 0, "System pre-initialization is not complete.");
39 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
40
41 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
42 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
43 PrefetchFieldsAhead = prefetch_fields_ahead();
44
45 // Allocation prefetch settings
46 intx cache_line_size = prefetch_data_size();
47 if( cache_line_size > AllocatePrefetchStepSize )
48 AllocatePrefetchStepSize = cache_line_size;
49
50 AllocatePrefetchDistance = allocate_prefetch_distance();
51 AllocatePrefetchStyle = allocate_prefetch_style();
52
53 if (!has_blk_init() || cache_line_size <= 0) {
54 if (AllocatePrefetchInstr == 1) {
55 warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
56 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
57 }
58 }
59
60 UseSSE = 0; // Only on x86 and x64
61
62 _supports_cx8 = has_v9();
63 _supports_atomic_getset4 = true; // swap instruction
64
65 if (is_niagara()) {
66 // Indirect branch is the same cost as direct
67 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
68 FLAG_SET_DEFAULT(UseInlineCaches, false);
69 }
70 // Align loops on a single instruction boundary.
71 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
72 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
73 }
74 // 32-bit oops don't make sense for the 64-bit VM on sparc
75 // since the 32-bit VM has the same registers and smaller objects.
76 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
77 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
78 #ifdef COMPILER2
79 // Indirect branch is the same cost as direct
80 if (FLAG_IS_DEFAULT(UseJumpTables)) {
81 FLAG_SET_DEFAULT(UseJumpTables, true);
82 }
83 // Single-issue, so entry and loop tops are
84 // aligned on a single instruction boundary
85 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
86 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
87 }
88 if (is_niagara_plus()) {
89 if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
90 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
91 if (!has_sparc5_instr()) {
92 // Use BIS instruction for TLAB allocation prefetch
93 // on Niagara plus processors other than those based on CoreS4
94 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
95 } else {
96 // On CoreS4 processors use prefetch instruction
97 // to avoid partial RAW issue, also use prefetch style 3
98 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
99 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
100 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
101 }
102 }
103 }
104 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
105 if (AllocatePrefetchInstr == 0) {
106 // Use different prefetch distance without BIS
107 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
108 } else {
109 // Use smaller prefetch distance with BIS
110 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
111 }
112 }
113 if (is_T4()) {
114 // Double number of prefetched cache lines on T4
115 // since L2 cache line size is smaller (32 bytes).
116 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
117 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
118 }
119 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
120 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
121 }
122 }
123 }
124
125 if (AllocatePrefetchInstr == 1) {
126 // Use allocation prefetch style 3 because BIS instructions
127 // require aligned memory addresses.
128 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
129 }
130 #endif /* COMPILER2 */
131 }
132
133 // Use hardware population count instruction if available.
134 if (has_hardware_popc()) {
135 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
136 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
137 }
138 } else if (UsePopCountInstruction) {
139 warning("POPC instruction is not available on this CPU");
140 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
141 }
142
143 // T4 and newer Sparc cpus have new compare and branch instruction.
144 if (has_cbcond()) {
145 if (FLAG_IS_DEFAULT(UseCBCond)) {
146 FLAG_SET_DEFAULT(UseCBCond, true);
147 }
148 } else if (UseCBCond) {
149 warning("CBCOND instruction is not available on this CPU");
150 FLAG_SET_DEFAULT(UseCBCond, false);
151 }
152
153 assert(BlockZeroingLowLimit > 0, "invalid value");
154 if (has_block_zeroing() && cache_line_size > 0) {
155 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
156 FLAG_SET_DEFAULT(UseBlockZeroing, true);
157 }
158 } else if (UseBlockZeroing) {
159 warning("BIS zeroing instructions are not available on this CPU");
160 FLAG_SET_DEFAULT(UseBlockZeroing, false);
161 }
162
163 assert(BlockCopyLowLimit > 0, "invalid value");
164 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
165 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
166 FLAG_SET_DEFAULT(UseBlockCopy, true);
167 }
168 } else if (UseBlockCopy) {
169 warning("BIS instructions are not available or expensive on this CPU");
170 FLAG_SET_DEFAULT(UseBlockCopy, false);
171 }
172
173 #ifdef COMPILER2
174 // T4 and newer Sparc cpus have fast RDPC.
175 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
176 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
177 }
178
179 // Currently not supported anywhere.
180 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
181
182 MaxVectorSize = 8;
183
184 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
185 #endif
186
187 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
188 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
189
190 char buf[512];
191 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
192 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
193 (has_hardware_popc() ? ", popc" : ""),
194 (has_vis1() ? ", vis1" : ""),
195 (has_vis2() ? ", vis2" : ""),
196 (has_vis3() ? ", vis3" : ""),
197 (has_blk_init() ? ", blk_init" : ""),
198 (has_cbcond() ? ", cbcond" : ""),
199 (has_aes() ? ", aes" : ""),
200 (has_sha1() ? ", sha1" : ""),
201 (has_sha256() ? ", sha256" : ""),
202 (has_sha512() ? ", sha512" : ""),
203 (has_crc32c() ? ", crc32c" : ""),
204 (is_ultra3() ? ", ultra3" : ""),
205 (has_sparc5_instr() ? ", sparc5" : ""),
206 (is_sun4v() ? ", sun4v" : ""),
207 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
208 (is_sparc64() ? ", sparc64" : ""),
209 (!has_hardware_mul32() ? ", no-mul32" : ""),
210 (!has_hardware_div32() ? ", no-div32" : ""),
211 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
212
213 // buf is started with ", " or is empty
214 _features_string = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
215
216 // UseVIS is set to the smallest of what hardware supports and what
217 // the command line requires. I.e., you cannot set UseVIS to 3 on
218 // older UltraSparc which do not support it.
219 if (UseVIS > 3) UseVIS=3;
220 if (UseVIS < 0) UseVIS=0;
221 if (!has_vis3()) // Drop to 2 if no VIS3 support
222 UseVIS = MIN2((intx)2,UseVIS);
223 if (!has_vis2()) // Drop to 1 if no VIS2 support
224 UseVIS = MIN2((intx)1,UseVIS);
225 if (!has_vis1()) // Drop to 0 if no VIS1 support
226 UseVIS = 0;
227
228 // SPARC T4 and above should have support for AES instructions
229 if (has_aes()) {
230 if (FLAG_IS_DEFAULT(UseAES)) {
231 FLAG_SET_DEFAULT(UseAES, true);
232 }
233 if (!UseAES) {
234 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
235 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
236 }
237 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
238 } else {
239 // The AES intrinsic stubs require AES instruction support (of course)
240 // but also require VIS3 mode or higher for instructions it use.
241 if (UseVIS > 2) {
242 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
243 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
244 }
245 } else {
246 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
247 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
248 }
249 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
250 }
251 }
252 } else if (UseAES || UseAESIntrinsics) {
253 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
254 warning("AES instructions are not available on this CPU");
255 FLAG_SET_DEFAULT(UseAES, false);
256 }
257 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
258 warning("AES intrinsics are not available on this CPU");
259 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
260 }
261 }
262
263 if (UseAESCTRIntrinsics) {
264 warning("AES/CTR intrinsics are not available on this CPU");
265 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
266 }
267
268 // GHASH/GCM intrinsics
269 if (has_vis3() && (UseVIS > 2)) {
270 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
271 UseGHASHIntrinsics = true;
272 }
273 } else if (UseGHASHIntrinsics) {
274 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
275 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
276 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
277 }
278
279 if (UseFMA) {
280 warning("FMA instructions are not available on this CPU");
281 FLAG_SET_DEFAULT(UseFMA, false);
282 }
283
284 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
285 if (has_sha1() || has_sha256() || has_sha512()) {
286 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
287 if (FLAG_IS_DEFAULT(UseSHA)) {
288 FLAG_SET_DEFAULT(UseSHA, true);
289 }
290 } else {
291 if (UseSHA) {
292 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
293 FLAG_SET_DEFAULT(UseSHA, false);
294 }
295 }
296 } else if (UseSHA) {
297 warning("SHA instructions are not available on this CPU");
298 FLAG_SET_DEFAULT(UseSHA, false);
299 }
300
301 if (UseSHA && has_sha1()) {
302 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
303 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
304 }
305 } else if (UseSHA1Intrinsics) {
306 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
307 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
308 }
309
310 if (UseSHA && has_sha256()) {
311 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
312 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
313 }
314 } else if (UseSHA256Intrinsics) {
315 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
316 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
317 }
318
319 if (UseSHA && has_sha512()) {
320 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
321 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
322 }
323 } else if (UseSHA512Intrinsics) {
324 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
325 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
326 }
327
328 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
329 FLAG_SET_DEFAULT(UseSHA, false);
330 }
331
332 // SPARC T4 and above should have support for CRC32C instruction
333 if (has_crc32c()) {
334 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
335 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
336 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
337 }
338 } else {
339 if (UseCRC32CIntrinsics) {
340 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
341 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
342 }
343 }
344 } else if (UseCRC32CIntrinsics) {
345 warning("CRC32C instruction is not available on this CPU");
346 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
347 }
348
349 if (UseVIS > 2) {
350 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
351 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
352 }
353 } else if (UseAdler32Intrinsics) {
354 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
355 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
356 }
357
358 if (UseVIS > 2) {
359 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
360 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
361 }
362 } else if (UseCRC32Intrinsics) {
363 warning("SPARC CRC32 intrinsics require VIS3 instructions support. Intrinsics will be disabled");
364 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
365 }
366
367 if (UseVectorizedMismatchIntrinsic) {
368 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
369 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
370 }
371
372 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
373 (cache_line_size > ContendedPaddingWidth))
374 ContendedPaddingWidth = cache_line_size;
375
376 // This machine does not allow unaligned memory accesses
377 if (UseUnalignedAccesses) {
378 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
379 warning("Unaligned memory access is not available on this CPU");
380 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
381 }
382
383 if (log_is_enabled(Info, os, cpu)) {
384 ResourceMark rm;
385 outputStream* log = Log(os, cpu)::info_stream();
386 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
387 log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
388 log->print("Allocation");
389 if (AllocatePrefetchStyle <= 0) {
390 log->print(": no prefetching");
391 } else {
392 log->print(" prefetching: ");
393 if (AllocatePrefetchInstr == 0) {
394 log->print("PREFETCH");
395 } else if (AllocatePrefetchInstr == 1) {
396 log->print("BIS");
397 }
398 if (AllocatePrefetchLines > 1) {
399 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
400 } else {
401 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
402 }
403 }
404 if (PrefetchCopyIntervalInBytes > 0) {
405 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
406 }
407 if (PrefetchScanIntervalInBytes > 0) {
408 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
409 }
410 if (PrefetchFieldsAhead > 0) {
411 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
412 }
413 if (ContendedPaddingWidth > 0) {
414 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
415 }
416 }
417 }
418
419 void VM_Version::print_features() {
420 tty->print_cr("Version:%s", _features);
421 }
422
423 int VM_Version::determine_features() {
424 if (UseV8InstrsOnly) {
425 log_info(os, cpu)("Version is Forced-V8");
426 return generic_v8_m;
427 }
428
429 int features = platform_features(unknown_m); // platform_features() is os_arch specific
430
431 if (features == unknown_m) {
432 features = generic_v9_m;
433 log_info(os)("Cannot recognize SPARC version. Default to V9");
434 }
435
436 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
437 if (UseNiagaraInstrs) { // Force code generation for Niagara
438 if (is_T_family(features)) {
439 // Happy to accomodate...
440 } else {
441 log_info(os, cpu)("Version is Forced-Niagara");
442 features |= T_family_m;
443 }
444 } else {
445 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
446 log_info(os, cpu)("Version is Forced-Not-Niagara");
447 features &= ~(T_family_m | T1_model_m);
448 } else {
449 // Happy to accomodate...
450 }
451 }
452
453 return features;
454 }
455
456 static uint64_t saved_features = 0;
457
458 void VM_Version::allow_all() {
459 saved_features = _features;
460 _features = all_features_m;
461 }
462
463 void VM_Version::revert() {
464 _features = saved_features;
465 }
466
467 unsigned int VM_Version::calc_parallel_worker_threads() {
468 unsigned int result;
469 if (is_M_series() || is_S_series()) {
470 // for now, use same gc thread calculation for M-series and S-series as for
471 // niagara-plus. In future, we may want to tweak parameters for
472 // nof_parallel_worker_thread
473 result = nof_parallel_worker_threads(5, 16, 8);
474 } else if (is_niagara_plus()) {
475 result = nof_parallel_worker_threads(5, 16, 8);
476 } else {
477 result = nof_parallel_worker_threads(5, 8, 8);
478 }
479 return result;
480 }
481
482
483 int VM_Version::parse_features(const char* implementation) {
484 int features = unknown_m;
485 // Convert to UPPER case before compare.
486 char* impl = os::strdup_check_oom(implementation);
487
488 for (int i = 0; impl[i] != 0; i++)
489 impl[i] = (char)toupper((uint)impl[i]);
490
491 if (strstr(impl, "SPARC64") != NULL) {
492 features |= sparc64_family_m;
493 } else if (strstr(impl, "SPARC-M") != NULL) {
494 // M-series SPARC is based on T-series.
495 features |= (M_family_m | T_family_m);
496 } else if (strstr(impl, "SPARC-S") != NULL) {
497 // S-series SPARC is based on T-series.
498 features |= (S_family_m | T_family_m);
499 } else if (strstr(impl, "SPARC-T") != NULL) {
500 features |= T_family_m;
501 if (strstr(impl, "SPARC-T1") != NULL) {
502 features |= T1_model_m;
503 }
504 } else if (strstr(impl, "SUN4V-CPU") != NULL) {
505 // Generic or migration class LDOM
506 features |= T_family_m;
507 } else {
508 log_info(os, cpu)("Failed to parse CPU implementation = '%s'", impl);
509 }
510 os::free((void*)impl);
511 return features;
512 }