1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "logging/log.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "prims/jvm.h"
31 #include "runtime/java.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/stubCodeGenerator.hpp"
34 #include "vm_version_x86.hpp"
35
36
37 int VM_Version::_cpu;
38 int VM_Version::_model;
39 int VM_Version::_stepping;
40 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
41
42 // Address of instruction which causes SEGV
43 address VM_Version::_cpuinfo_segv_addr = 0;
44 // Address of instruction after the one which causes SEGV
45 address VM_Version::_cpuinfo_cont_addr = 0;
46
47 static BufferBlob* stub_blob;
48 static const int stub_size = 1000;
49
50 extern "C" {
51 typedef void (*get_cpu_info_stub_t)(void*);
52 }
53 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
54
55
56 class VM_Version_StubGenerator: public StubCodeGenerator {
57 public:
58
59 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
60
61 address generate_get_cpu_info() {
62 // Flags to test CPU type.
63 const uint32_t HS_EFL_AC = 0x40000;
64 const uint32_t HS_EFL_ID = 0x200000;
65 // Values for when we don't have a CPUID instruction.
66 const int CPU_FAMILY_SHIFT = 8;
67 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
68 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
69 bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2);
70
71 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
72 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done, wrapup;
73 Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
74
75 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
76 # define __ _masm->
77
78 address start = __ pc();
79
80 //
81 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
82 //
83 // LP64: rcx and rdx are first and second argument registers on windows
84
85 __ push(rbp);
86 #ifdef _LP64
87 __ mov(rbp, c_rarg0); // cpuid_info address
88 #else
89 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
90 #endif
91 __ push(rbx);
92 __ push(rsi);
93 __ pushf(); // preserve rbx, and flags
94 __ pop(rax);
95 __ push(rax);
96 __ mov(rcx, rax);
97 //
98 // if we are unable to change the AC flag, we have a 386
99 //
100 __ xorl(rax, HS_EFL_AC);
101 __ push(rax);
102 __ popf();
103 __ pushf();
104 __ pop(rax);
105 __ cmpptr(rax, rcx);
106 __ jccb(Assembler::notEqual, detect_486);
107
108 __ movl(rax, CPU_FAMILY_386);
109 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
110 __ jmp(done);
111
112 //
113 // If we are unable to change the ID flag, we have a 486 which does
114 // not support the "cpuid" instruction.
115 //
116 __ bind(detect_486);
117 __ mov(rax, rcx);
118 __ xorl(rax, HS_EFL_ID);
119 __ push(rax);
120 __ popf();
121 __ pushf();
122 __ pop(rax);
123 __ cmpptr(rcx, rax);
124 __ jccb(Assembler::notEqual, detect_586);
125
126 __ bind(cpu486);
127 __ movl(rax, CPU_FAMILY_486);
128 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
129 __ jmp(done);
130
131 //
132 // At this point, we have a chip which supports the "cpuid" instruction
133 //
134 __ bind(detect_586);
135 __ xorl(rax, rax);
136 __ cpuid();
137 __ orl(rax, rax);
138 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
139 // value of at least 1, we give up and
140 // assume a 486
141 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
142 __ movl(Address(rsi, 0), rax);
143 __ movl(Address(rsi, 4), rbx);
144 __ movl(Address(rsi, 8), rcx);
145 __ movl(Address(rsi,12), rdx);
146
147 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
148 __ jccb(Assembler::belowEqual, std_cpuid4);
149
150 //
151 // cpuid(0xB) Processor Topology
152 //
153 __ movl(rax, 0xb);
154 __ xorl(rcx, rcx); // Threads level
155 __ cpuid();
156
157 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
158 __ movl(Address(rsi, 0), rax);
159 __ movl(Address(rsi, 4), rbx);
160 __ movl(Address(rsi, 8), rcx);
161 __ movl(Address(rsi,12), rdx);
162
163 __ movl(rax, 0xb);
164 __ movl(rcx, 1); // Cores level
165 __ cpuid();
166 __ push(rax);
167 __ andl(rax, 0x1f); // Determine if valid topology level
168 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
169 __ andl(rax, 0xffff);
170 __ pop(rax);
171 __ jccb(Assembler::equal, std_cpuid4);
172
173 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
174 __ movl(Address(rsi, 0), rax);
175 __ movl(Address(rsi, 4), rbx);
176 __ movl(Address(rsi, 8), rcx);
177 __ movl(Address(rsi,12), rdx);
178
179 __ movl(rax, 0xb);
180 __ movl(rcx, 2); // Packages level
181 __ cpuid();
182 __ push(rax);
183 __ andl(rax, 0x1f); // Determine if valid topology level
184 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
185 __ andl(rax, 0xffff);
186 __ pop(rax);
187 __ jccb(Assembler::equal, std_cpuid4);
188
189 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
190 __ movl(Address(rsi, 0), rax);
191 __ movl(Address(rsi, 4), rbx);
192 __ movl(Address(rsi, 8), rcx);
193 __ movl(Address(rsi,12), rdx);
194
195 //
196 // cpuid(0x4) Deterministic cache params
197 //
198 __ bind(std_cpuid4);
199 __ movl(rax, 4);
200 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
201 __ jccb(Assembler::greater, std_cpuid1);
202
203 __ xorl(rcx, rcx); // L1 cache
204 __ cpuid();
205 __ push(rax);
206 __ andl(rax, 0x1f); // Determine if valid cache parameters used
207 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
208 __ pop(rax);
209 __ jccb(Assembler::equal, std_cpuid1);
210
211 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
212 __ movl(Address(rsi, 0), rax);
213 __ movl(Address(rsi, 4), rbx);
214 __ movl(Address(rsi, 8), rcx);
215 __ movl(Address(rsi,12), rdx);
216
217 //
218 // Standard cpuid(0x1)
219 //
220 __ bind(std_cpuid1);
221 __ movl(rax, 1);
222 __ cpuid();
223 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
224 __ movl(Address(rsi, 0), rax);
225 __ movl(Address(rsi, 4), rbx);
226 __ movl(Address(rsi, 8), rcx);
227 __ movl(Address(rsi,12), rdx);
228
229 //
230 // Check if OS has enabled XGETBV instruction to access XCR0
231 // (OSXSAVE feature flag) and CPU supports AVX
232 //
233 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
234 __ cmpl(rcx, 0x18000000);
235 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
236
237 //
238 // XCR0, XFEATURE_ENABLED_MASK register
239 //
240 __ xorl(rcx, rcx); // zero for XCR0 register
241 __ xgetbv();
242 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
243 __ movl(Address(rsi, 0), rax);
244 __ movl(Address(rsi, 4), rdx);
245
246 //
247 // cpuid(0x7) Structured Extended Features
248 //
249 __ bind(sef_cpuid);
250 __ movl(rax, 7);
251 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
252 __ jccb(Assembler::greater, ext_cpuid);
253
254 __ xorl(rcx, rcx);
255 __ cpuid();
256 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
257 __ movl(Address(rsi, 0), rax);
258 __ movl(Address(rsi, 4), rbx);
259
260 //
261 // Extended cpuid(0x80000000)
262 //
263 __ bind(ext_cpuid);
264 __ movl(rax, 0x80000000);
265 __ cpuid();
266 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
267 __ jcc(Assembler::belowEqual, done);
268 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
269 __ jccb(Assembler::belowEqual, ext_cpuid1);
270 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
271 __ jccb(Assembler::belowEqual, ext_cpuid5);
272 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
273 __ jccb(Assembler::belowEqual, ext_cpuid7);
274 //
275 // Extended cpuid(0x80000008)
276 //
277 __ movl(rax, 0x80000008);
278 __ cpuid();
279 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
280 __ movl(Address(rsi, 0), rax);
281 __ movl(Address(rsi, 4), rbx);
282 __ movl(Address(rsi, 8), rcx);
283 __ movl(Address(rsi,12), rdx);
284
285 //
286 // Extended cpuid(0x80000007)
287 //
288 __ bind(ext_cpuid7);
289 __ movl(rax, 0x80000007);
290 __ cpuid();
291 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
292 __ movl(Address(rsi, 0), rax);
293 __ movl(Address(rsi, 4), rbx);
294 __ movl(Address(rsi, 8), rcx);
295 __ movl(Address(rsi,12), rdx);
296
297 //
298 // Extended cpuid(0x80000005)
299 //
300 __ bind(ext_cpuid5);
301 __ movl(rax, 0x80000005);
302 __ cpuid();
303 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
304 __ movl(Address(rsi, 0), rax);
305 __ movl(Address(rsi, 4), rbx);
306 __ movl(Address(rsi, 8), rcx);
307 __ movl(Address(rsi,12), rdx);
308
309 //
310 // Extended cpuid(0x80000001)
311 //
312 __ bind(ext_cpuid1);
313 __ movl(rax, 0x80000001);
314 __ cpuid();
315 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
316 __ movl(Address(rsi, 0), rax);
317 __ movl(Address(rsi, 4), rbx);
318 __ movl(Address(rsi, 8), rcx);
319 __ movl(Address(rsi,12), rdx);
320
321 //
322 // Check if OS has enabled XGETBV instruction to access XCR0
323 // (OSXSAVE feature flag) and CPU supports AVX
324 //
325 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
326 __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
327 __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
328 __ cmpl(rcx, 0x18000000);
329 __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
330
331 __ movl(rax, 0x6);
332 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
333 __ cmpl(rax, 0x6);
334 __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
335
336 // we need to bridge farther than imm8, so we use this island as a thunk
337 __ bind(done);
338 __ jmp(wrapup);
339
340 __ bind(start_simd_check);
341 //
342 // Some OSs have a bug when upper 128/256bits of YMM/ZMM
343 // registers are not restored after a signal processing.
344 // Generate SEGV here (reference through NULL)
345 // and check upper YMM/ZMM bits after it.
346 //
347 intx saved_useavx = UseAVX;
348 intx saved_usesse = UseSSE;
349 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
350 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
351 __ movl(rax, 0x10000);
352 __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
353 __ cmpl(rax, 0x10000);
354 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
355 // check _cpuid_info.xem_xcr0_eax.bits.opmask
356 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
357 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
358 __ movl(rax, 0xE0);
359 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
360 __ cmpl(rax, 0xE0);
361 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
362
363 // If UseAVX is unitialized or is set by the user to include EVEX
364 if (use_evex) {
365 // EVEX setup: run in lowest evex mode
366 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
367 UseAVX = 3;
368 UseSSE = 2;
369 #ifdef _WINDOWS
370 // xmm5-xmm15 are not preserved by caller on windows
371 // https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx
372 __ subptr(rsp, 64);
373 __ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit);
374 #ifdef _LP64
375 __ subptr(rsp, 64);
376 __ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit);
377 __ subptr(rsp, 64);
378 __ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit);
379 #endif // _LP64
380 #endif // _WINDOWS
381
382 // load value into all 64 bytes of zmm7 register
383 __ movl(rcx, VM_Version::ymm_test_value());
384 __ movdl(xmm0, rcx);
385 __ movl(rcx, 0xffff);
386 __ kmovwl(k1, rcx);
387 __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
388 __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
389 #ifdef _LP64
390 __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
391 __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
392 #endif
393 VM_Version::clean_cpuFeatures();
394 __ jmp(save_restore_except);
395 }
396
397 __ bind(legacy_setup);
398 // AVX setup
399 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
400 UseAVX = 1;
401 UseSSE = 2;
402 #ifdef _WINDOWS
403 __ subptr(rsp, 32);
404 __ vmovdqu(Address(rsp, 0), xmm7);
405 #ifdef _LP64
406 __ subptr(rsp, 32);
407 __ vmovdqu(Address(rsp, 0), xmm8);
408 __ subptr(rsp, 32);
409 __ vmovdqu(Address(rsp, 0), xmm15);
410 #endif // _LP64
411 #endif // _WINDOWS
412
413 // load value into all 32 bytes of ymm7 register
414 __ movl(rcx, VM_Version::ymm_test_value());
415
416 __ movdl(xmm0, rcx);
417 __ pshufd(xmm0, xmm0, 0x00);
418 __ vinsertf128_high(xmm0, xmm0);
419 __ vmovdqu(xmm7, xmm0);
420 #ifdef _LP64
421 __ vmovdqu(xmm8, xmm0);
422 __ vmovdqu(xmm15, xmm0);
423 #endif
424 VM_Version::clean_cpuFeatures();
425
426 __ bind(save_restore_except);
427 __ xorl(rsi, rsi);
428 VM_Version::set_cpuinfo_segv_addr(__ pc());
429 // Generate SEGV
430 __ movl(rax, Address(rsi, 0));
431
432 VM_Version::set_cpuinfo_cont_addr(__ pc());
433 // Returns here after signal. Save xmm0 to check it later.
434
435 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
436 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
437 __ movl(rax, 0x10000);
438 __ andl(rax, Address(rsi, 4));
439 __ cmpl(rax, 0x10000);
440 __ jcc(Assembler::notEqual, legacy_save_restore);
441 // check _cpuid_info.xem_xcr0_eax.bits.opmask
442 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
443 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
444 __ movl(rax, 0xE0);
445 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
446 __ cmpl(rax, 0xE0);
447 __ jcc(Assembler::notEqual, legacy_save_restore);
448
449 // If UseAVX is unitialized or is set by the user to include EVEX
450 if (use_evex) {
451 // EVEX check: run in lowest evex mode
452 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
453 UseAVX = 3;
454 UseSSE = 2;
455 __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
456 __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
457 __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
458 #ifdef _LP64
459 __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
460 __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
461 #endif
462
463 #ifdef _WINDOWS
464 #ifdef _LP64
465 __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
466 __ addptr(rsp, 64);
467 __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
468 __ addptr(rsp, 64);
469 #endif // _LP64
470 __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
471 __ addptr(rsp, 64);
472 #endif // _WINDOWS
473 generate_vzeroupper(wrapup);
474 VM_Version::clean_cpuFeatures();
475 UseAVX = saved_useavx;
476 UseSSE = saved_usesse;
477 __ jmp(wrapup);
478 }
479
480 __ bind(legacy_save_restore);
481 // AVX check
482 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
483 UseAVX = 1;
484 UseSSE = 2;
485 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
486 __ vmovdqu(Address(rsi, 0), xmm0);
487 __ vmovdqu(Address(rsi, 32), xmm7);
488 #ifdef _LP64
489 __ vmovdqu(Address(rsi, 64), xmm8);
490 __ vmovdqu(Address(rsi, 96), xmm15);
491 #endif
492
493 #ifdef _WINDOWS
494 #ifdef _LP64
495 __ vmovdqu(xmm15, Address(rsp, 0));
496 __ addptr(rsp, 32);
497 __ vmovdqu(xmm8, Address(rsp, 0));
498 __ addptr(rsp, 32);
499 #endif // _LP64
500 __ vmovdqu(xmm7, Address(rsp, 0));
501 __ addptr(rsp, 32);
502 #endif // _WINDOWS
503 generate_vzeroupper(wrapup);
504 VM_Version::clean_cpuFeatures();
505 UseAVX = saved_useavx;
506 UseSSE = saved_usesse;
507
508 __ bind(wrapup);
509 __ popf();
510 __ pop(rsi);
511 __ pop(rbx);
512 __ pop(rbp);
513 __ ret(0);
514
515 # undef __
516
517 return start;
518 };
519 void generate_vzeroupper(Label& L_wrapup) {
520 # define __ _masm->
521 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
522 __ cmpl(Address(rsi, 4), 0x756e6547); // 'uneG'
523 __ jcc(Assembler::notEqual, L_wrapup);
524 __ movl(rcx, 0x0FFF0FF0);
525 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
526 __ andl(rcx, Address(rsi, 0));
527 __ cmpl(rcx, 0x00050670); // If it is Xeon Phi 3200/5200/7200
528 __ jcc(Assembler::equal, L_wrapup);
529 __ cmpl(rcx, 0x00080650); // If it is Future Xeon Phi
530 __ jcc(Assembler::equal, L_wrapup);
531 __ vzeroupper();
532 # undef __
533 }
534 };
535
536 void VM_Version::get_processor_features() {
537
538 _cpu = 4; // 486 by default
539 _model = 0;
540 _stepping = 0;
541 _features = 0;
542 _logical_processors_per_package = 1;
543 // i486 internal cache is both I&D and has a 16-byte line size
544 _L1_data_cache_line_size = 16;
545
546 // Get raw processor info
547
548 get_cpu_info_stub(&_cpuid_info);
549
550 assert_is_initialized();
551 _cpu = extended_cpu_family();
552 _model = extended_cpu_model();
553 _stepping = cpu_stepping();
554
555 if (cpu_family() > 4) { // it supports CPUID
556 _features = feature_flags();
557 // Logical processors are only available on P4s and above,
558 // and only if hyperthreading is available.
559 _logical_processors_per_package = logical_processor_count();
560 _L1_data_cache_line_size = L1_line_size();
561 }
562
563 _supports_cx8 = supports_cmpxchg8();
564 // xchg and xadd instructions
565 _supports_atomic_getset4 = true;
566 _supports_atomic_getadd4 = true;
567 LP64_ONLY(_supports_atomic_getset8 = true);
568 LP64_ONLY(_supports_atomic_getadd8 = true);
569
570 #ifdef _LP64
571 // OS should support SSE for x64 and hardware should support at least SSE2.
572 if (!VM_Version::supports_sse2()) {
573 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
574 }
575 // in 64 bit the use of SSE2 is the minimum
576 if (UseSSE < 2) UseSSE = 2;
577 #endif
578
579 #ifdef AMD64
580 // flush_icache_stub have to be generated first.
581 // That is why Icache line size is hard coded in ICache class,
582 // see icache_x86.hpp. It is also the reason why we can't use
583 // clflush instruction in 32-bit VM since it could be running
584 // on CPU which does not support it.
585 //
586 // The only thing we can do is to verify that flushed
587 // ICache::line_size has correct value.
588 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
589 // clflush_size is size in quadwords (8 bytes).
590 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
591 #endif
592
593 // If the OS doesn't support SSE, we can't use this feature even if the HW does
594 if (!os::supports_sse())
595 _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
596
597 if (UseSSE < 4) {
598 _features &= ~CPU_SSE4_1;
599 _features &= ~CPU_SSE4_2;
600 }
601
602 if (UseSSE < 3) {
603 _features &= ~CPU_SSE3;
604 _features &= ~CPU_SSSE3;
605 _features &= ~CPU_SSE4A;
606 }
607
608 if (UseSSE < 2)
609 _features &= ~CPU_SSE2;
610
611 if (UseSSE < 1)
612 _features &= ~CPU_SSE;
613
614 // first try initial setting and detect what we can support
615 if (UseAVX > 0) {
616 if (UseAVX > 2 && supports_evex()) {
617 UseAVX = 3;
618 } else if (UseAVX > 1 && supports_avx2()) {
619 UseAVX = 2;
620 } else if (UseAVX > 0 && supports_avx()) {
621 UseAVX = 1;
622 } else {
623 UseAVX = 0;
624 }
625 } else if (UseAVX < 0) {
626 UseAVX = 0;
627 }
628
629 if (UseAVX < 3) {
630 _features &= ~CPU_AVX512F;
631 _features &= ~CPU_AVX512DQ;
632 _features &= ~CPU_AVX512CD;
633 _features &= ~CPU_AVX512BW;
634 _features &= ~CPU_AVX512VL;
635 }
636
637 if (UseAVX < 2)
638 _features &= ~CPU_AVX2;
639
640 if (UseAVX < 1) {
641 _features &= ~CPU_AVX;
642 _features &= ~CPU_VZEROUPPER;
643 }
644
645 if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
646 _features &= ~CPU_AES;
647
648 if (logical_processors_per_package() == 1) {
649 // HT processor could be installed on a system which doesn't support HT.
650 _features &= ~CPU_HT;
651 }
652
653 if( is_intel() ) { // Intel cpus specific settings
654 if ((cpu_family() == 0x06) &&
655 ((extended_cpu_model() == 0x57) || // Xeon Phi 3200/5200/7200
656 (extended_cpu_model() == 0x85))) { // Future Xeon Phi
657 _features &= ~CPU_VZEROUPPER;
658 }
659 }
660
661 char buf[256];
662 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
663 cores_per_cpu(), threads_per_core(),
664 cpu_family(), _model, _stepping,
665 (supports_cmov() ? ", cmov" : ""),
666 (supports_cmpxchg8() ? ", cx8" : ""),
667 (supports_fxsr() ? ", fxsr" : ""),
668 (supports_mmx() ? ", mmx" : ""),
669 (supports_sse() ? ", sse" : ""),
670 (supports_sse2() ? ", sse2" : ""),
671 (supports_sse3() ? ", sse3" : ""),
672 (supports_ssse3()? ", ssse3": ""),
673 (supports_sse4_1() ? ", sse4.1" : ""),
674 (supports_sse4_2() ? ", sse4.2" : ""),
675 (supports_popcnt() ? ", popcnt" : ""),
676 (supports_avx() ? ", avx" : ""),
677 (supports_avx2() ? ", avx2" : ""),
678 (supports_aes() ? ", aes" : ""),
679 (supports_clmul() ? ", clmul" : ""),
680 (supports_erms() ? ", erms" : ""),
681 (supports_rtm() ? ", rtm" : ""),
682 (supports_mmx_ext() ? ", mmxext" : ""),
683 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
684 (supports_lzcnt() ? ", lzcnt": ""),
685 (supports_sse4a() ? ", sse4a": ""),
686 (supports_ht() ? ", ht": ""),
687 (supports_tsc() ? ", tsc": ""),
688 (supports_tscinv_bit() ? ", tscinvbit": ""),
689 (supports_tscinv() ? ", tscinv": ""),
690 (supports_bmi1() ? ", bmi1" : ""),
691 (supports_bmi2() ? ", bmi2" : ""),
692 (supports_adx() ? ", adx" : ""),
693 (supports_evex() ? ", evex" : ""),
694 (supports_sha() ? ", sha" : ""),
695 (supports_fma() ? ", fma" : ""));
696 _features_string = os::strdup(buf);
697
698 // UseSSE is set to the smaller of what hardware supports and what
699 // the command line requires. I.e., you cannot set UseSSE to 2 on
700 // older Pentiums which do not support it.
701 if (UseSSE > 4) UseSSE=4;
702 if (UseSSE < 0) UseSSE=0;
703 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
704 UseSSE = MIN2((intx)3,UseSSE);
705 if (!supports_sse3()) // Drop to 2 if no SSE3 support
706 UseSSE = MIN2((intx)2,UseSSE);
707 if (!supports_sse2()) // Drop to 1 if no SSE2 support
708 UseSSE = MIN2((intx)1,UseSSE);
709 if (!supports_sse ()) // Drop to 0 if no SSE support
710 UseSSE = 0;
711
712 // Use AES instructions if available.
713 if (supports_aes()) {
714 if (FLAG_IS_DEFAULT(UseAES)) {
715 FLAG_SET_DEFAULT(UseAES, true);
716 }
717 if (!UseAES) {
718 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
719 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
720 }
721 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
722 } else {
723 if (UseSSE > 2) {
724 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
725 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
726 }
727 } else {
728 // The AES intrinsic stubs require AES instruction support (of course)
729 // but also require sse3 mode or higher for instructions it use.
730 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
731 warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
732 }
733 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
734 }
735
736 // --AES-CTR begins--
737 if (!UseAESIntrinsics) {
738 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
739 warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
740 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
741 }
742 } else {
743 if(supports_sse4_1()) {
744 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
745 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
746 }
747 } else {
748 // The AES-CTR intrinsic stubs require AES instruction support (of course)
749 // but also require sse4.1 mode or higher for instructions it use.
750 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
751 warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
752 }
753 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
754 }
755 }
756 // --AES-CTR ends--
757 }
758 } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
759 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
760 warning("AES instructions are not available on this CPU");
761 FLAG_SET_DEFAULT(UseAES, false);
762 }
763 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
764 warning("AES intrinsics are not available on this CPU");
765 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
766 }
767 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
768 warning("AES-CTR intrinsics are not available on this CPU");
769 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
770 }
771 }
772
773 // Use CLMUL instructions if available.
774 if (supports_clmul()) {
775 if (FLAG_IS_DEFAULT(UseCLMUL)) {
776 UseCLMUL = true;
777 }
778 } else if (UseCLMUL) {
779 if (!FLAG_IS_DEFAULT(UseCLMUL))
780 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
781 FLAG_SET_DEFAULT(UseCLMUL, false);
782 }
783
784 if (UseCLMUL && (UseSSE > 2)) {
785 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
786 UseCRC32Intrinsics = true;
787 }
788 } else if (UseCRC32Intrinsics) {
789 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
790 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
791 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
792 }
793
794 if (supports_sse4_2() && supports_clmul()) {
795 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
796 UseCRC32CIntrinsics = true;
797 }
798 } else if (UseCRC32CIntrinsics) {
799 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
800 warning("CRC32C intrinsics are not available on this CPU");
801 }
802 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
803 }
804
805 // GHASH/GCM intrinsics
806 if (UseCLMUL && (UseSSE > 2)) {
807 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
808 UseGHASHIntrinsics = true;
809 }
810 } else if (UseGHASHIntrinsics) {
811 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
812 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
813 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
814 }
815
816 if (supports_fma() && UseSSE >= 2) { // Check UseSSE since FMA code uses SSE instructions
817 if (FLAG_IS_DEFAULT(UseFMA)) {
818 UseFMA = true;
819 }
820 } else if (UseFMA) {
821 warning("FMA instructions are not available on this CPU");
822 FLAG_SET_DEFAULT(UseFMA, false);
823 }
824
825 if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) {
826 if (FLAG_IS_DEFAULT(UseSHA)) {
827 UseSHA = true;
828 }
829 } else if (UseSHA) {
830 warning("SHA instructions are not available on this CPU");
831 FLAG_SET_DEFAULT(UseSHA, false);
832 }
833
834 if (supports_sha() && UseSHA) {
835 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
836 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
837 }
838 } else if (UseSHA1Intrinsics) {
839 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
840 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
841 }
842
843 if (UseSHA) {
844 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
845 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
846 }
847 } else if (UseSHA256Intrinsics) {
848 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
849 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
850 }
851
852 if (UseSHA) {
853 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
854 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
855 }
856 } else if (UseSHA512Intrinsics) {
857 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
858 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
859 }
860
861 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
862 FLAG_SET_DEFAULT(UseSHA, false);
863 }
864
865 if (UseAdler32Intrinsics) {
866 warning("Adler32Intrinsics not available on this CPU.");
867 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
868 }
869
870 if (!supports_rtm() && UseRTMLocking) {
871 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
872 // setting during arguments processing. See use_biased_locking().
873 // VM_Version_init() is executed after UseBiasedLocking is used
874 // in Thread::allocate().
875 vm_exit_during_initialization("RTM instructions are not available on this CPU");
876 }
877
878 #if INCLUDE_RTM_OPT
879 if (UseRTMLocking) {
880 if (is_client_compilation_mode_vm()) {
881 // Only C2 does RTM locking optimization.
882 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
883 // setting during arguments processing. See use_biased_locking().
884 vm_exit_during_initialization("RTM locking optimization is not supported in emulated client VM");
885 }
886 if (is_intel_family_core()) {
887 if ((_model == CPU_MODEL_HASWELL_E3) ||
888 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
889 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) {
890 // currently a collision between SKL and HSW_E3
891 if (!UnlockExperimentalVMOptions && UseAVX < 3) {
892 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
893 } else {
894 warning("UseRTMLocking is only available as experimental option on this platform.");
895 }
896 }
897 }
898 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
899 // RTM locking should be used only for applications with
900 // high lock contention. For now we do not use it by default.
901 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
902 }
903 if (!is_power_of_2(RTMTotalCountIncrRate)) {
904 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
905 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
906 }
907 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
908 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
909 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
910 }
911 } else { // !UseRTMLocking
912 if (UseRTMForStackLocks) {
913 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
914 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
915 }
916 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
917 }
918 if (UseRTMDeopt) {
919 FLAG_SET_DEFAULT(UseRTMDeopt, false);
920 }
921 if (PrintPreciseRTMLockingStatistics) {
922 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
923 }
924 }
925 #else
926 if (UseRTMLocking) {
927 // Only C2 does RTM locking optimization.
928 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
929 // setting during arguments processing. See use_biased_locking().
930 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
931 }
932 #endif
933
934 #ifdef COMPILER2
935 if (UseFPUForSpilling) {
936 if (UseSSE < 2) {
937 // Only supported with SSE2+
938 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
939 }
940 }
941 #endif
942 #if defined(COMPILER2) || INCLUDE_JVMCI
943 if (MaxVectorSize > 0) {
944 if (!is_power_of_2(MaxVectorSize)) {
945 warning("MaxVectorSize must be a power of 2");
946 FLAG_SET_DEFAULT(MaxVectorSize, 64);
947 }
948 if (UseSSE < 2) {
949 // Vectors (in XMM) are only supported with SSE2+
950 if (MaxVectorSize > 0) {
951 if (!FLAG_IS_DEFAULT(MaxVectorSize))
952 warning("MaxVectorSize must be 0");
953 FLAG_SET_DEFAULT(MaxVectorSize, 0);
954 }
955 }
956 else if (UseAVX == 0 || !os_supports_avx_vectors()) {
957 // 32 bytes vectors (in YMM) are only supported with AVX+
958 if (MaxVectorSize > 16) {
959 if (!FLAG_IS_DEFAULT(MaxVectorSize))
960 warning("MaxVectorSize must be <= 16");
961 FLAG_SET_DEFAULT(MaxVectorSize, 16);
962 }
963 }
964 else if (UseAVX == 1 || UseAVX == 2) {
965 // 64 bytes vectors (in ZMM) are only supported with AVX 3
966 if (MaxVectorSize > 32) {
967 if (!FLAG_IS_DEFAULT(MaxVectorSize))
968 warning("MaxVectorSize must be <= 32");
969 FLAG_SET_DEFAULT(MaxVectorSize, 32);
970 }
971 }
972 else if (UseAVX > 2 ) {
973 if (MaxVectorSize > 64) {
974 if (!FLAG_IS_DEFAULT(MaxVectorSize))
975 warning("MaxVectorSize must be <= 64");
976 FLAG_SET_DEFAULT(MaxVectorSize, 64);
977 }
978 }
979 #if defined(COMPILER2) && defined(ASSERT)
980 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
981 tty->print_cr("State of YMM registers after signal handle:");
982 int nreg = 2 LP64_ONLY(+2);
983 const char* ymm_name[4] = {"0", "7", "8", "15"};
984 for (int i = 0; i < nreg; i++) {
985 tty->print("YMM%s:", ymm_name[i]);
986 for (int j = 7; j >=0; j--) {
987 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
988 }
989 tty->cr();
990 }
991 }
992 #endif // COMPILER2 && ASSERT
993 }
994 #endif // COMPILER2 || INCLUDE_JVMCI
995
996 #ifdef COMPILER2
997 #ifdef _LP64
998 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
999 UseMultiplyToLenIntrinsic = true;
1000 }
1001 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1002 UseSquareToLenIntrinsic = true;
1003 }
1004 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1005 UseMulAddIntrinsic = true;
1006 }
1007 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1008 UseMontgomeryMultiplyIntrinsic = true;
1009 }
1010 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1011 UseMontgomerySquareIntrinsic = true;
1012 }
1013 #else
1014 if (UseMultiplyToLenIntrinsic) {
1015 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1016 warning("multiplyToLen intrinsic is not available in 32-bit VM");
1017 }
1018 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
1019 }
1020 if (UseMontgomeryMultiplyIntrinsic) {
1021 if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1022 warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
1023 }
1024 FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
1025 }
1026 if (UseMontgomerySquareIntrinsic) {
1027 if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1028 warning("montgomerySquare intrinsic is not available in 32-bit VM");
1029 }
1030 FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
1031 }
1032 if (UseSquareToLenIntrinsic) {
1033 if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1034 warning("squareToLen intrinsic is not available in 32-bit VM");
1035 }
1036 FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
1037 }
1038 if (UseMulAddIntrinsic) {
1039 if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1040 warning("mulAdd intrinsic is not available in 32-bit VM");
1041 }
1042 FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
1043 }
1044 #endif
1045 #endif // COMPILER2
1046
1047 // On new cpus instructions which update whole XMM register should be used
1048 // to prevent partial register stall due to dependencies on high half.
1049 //
1050 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
1051 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1052 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
1053 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
1054
1055 if( is_amd() ) { // AMD cpus specific settings
1056 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
1057 // Use it on new AMD cpus starting from Opteron.
1058 UseAddressNop = true;
1059 }
1060 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
1061 // Use it on new AMD cpus starting from Opteron.
1062 UseNewLongLShift = true;
1063 }
1064 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1065 if (supports_sse4a()) {
1066 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1067 } else {
1068 UseXmmLoadAndClearUpper = false;
1069 }
1070 }
1071 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1072 if( supports_sse4a() ) {
1073 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1074 } else {
1075 UseXmmRegToRegMoveAll = false;
1076 }
1077 }
1078 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
1079 if( supports_sse4a() ) {
1080 UseXmmI2F = true;
1081 } else {
1082 UseXmmI2F = false;
1083 }
1084 }
1085 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
1086 if( supports_sse4a() ) {
1087 UseXmmI2D = true;
1088 } else {
1089 UseXmmI2D = false;
1090 }
1091 }
1092 if (supports_sse4_2()) {
1093 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1094 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1095 }
1096 } else {
1097 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1098 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1099 }
1100 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1101 }
1102
1103 // some defaults for AMD family 15h
1104 if ( cpu_family() == 0x15 ) {
1105 // On family 15h processors default is no sw prefetch
1106 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1107 AllocatePrefetchStyle = 0;
1108 }
1109 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1110 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1111 AllocatePrefetchInstr = 3;
1112 }
1113 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1114 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1115 UseXMMForArrayCopy = true;
1116 }
1117 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1118 UseUnalignedLoadStores = true;
1119 }
1120 }
1121
1122 #ifdef COMPILER2
1123 if (MaxVectorSize > 16) {
1124 // Limit vectors size to 16 bytes on current AMD cpus.
1125 FLAG_SET_DEFAULT(MaxVectorSize, 16);
1126 }
1127 #endif // COMPILER2
1128 }
1129
1130 if( is_intel() ) { // Intel cpus specific settings
1131 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
1132 UseStoreImmI16 = false; // don't use it on Intel cpus
1133 }
1134 if( cpu_family() == 6 || cpu_family() == 15 ) {
1135 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
1136 // Use it on all Intel cpus starting from PentiumPro
1137 UseAddressNop = true;
1138 }
1139 }
1140 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
1141 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1142 }
1143 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
1144 if( supports_sse3() ) {
1145 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1146 } else {
1147 UseXmmRegToRegMoveAll = false;
1148 }
1149 }
1150 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
1151 #ifdef COMPILER2
1152 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
1153 // For new Intel cpus do the next optimization:
1154 // don't align the beginning of a loop if there are enough instructions
1155 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1156 // in current fetch line (OptoLoopAlignment) or the padding
1157 // is big (> MaxLoopPad).
1158 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1159 // generated NOP instructions. 11 is the largest size of one
1160 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1161 MaxLoopPad = 11;
1162 }
1163 #endif // COMPILER2
1164 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1165 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1166 }
1167 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
1168 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1169 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1170 }
1171 }
1172 if (supports_sse4_2()) {
1173 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1174 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1175 }
1176 } else {
1177 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1178 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1179 }
1180 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1181 }
1182 }
1183 if ((cpu_family() == 0x06) &&
1184 ((extended_cpu_model() == 0x36) || // Centerton
1185 (extended_cpu_model() == 0x37) || // Silvermont
1186 (extended_cpu_model() == 0x4D))) {
1187 #ifdef COMPILER2
1188 if (FLAG_IS_DEFAULT(OptoScheduling)) {
1189 OptoScheduling = true;
1190 }
1191 #endif
1192 if (supports_sse4_2()) { // Silvermont
1193 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1194 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1195 }
1196 }
1197 }
1198 if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1199 AllocatePrefetchInstr = 3;
1200 }
1201 }
1202
1203 #ifdef _LP64
1204 if (UseSSE42Intrinsics) {
1205 if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1206 UseVectorizedMismatchIntrinsic = true;
1207 }
1208 } else if (UseVectorizedMismatchIntrinsic) {
1209 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1210 warning("vectorizedMismatch intrinsics are not available on this CPU");
1211 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1212 }
1213 #else
1214 if (UseVectorizedMismatchIntrinsic) {
1215 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1216 warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1217 }
1218 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1219 }
1220 #endif // _LP64
1221
1222 // Use count leading zeros count instruction if available.
1223 if (supports_lzcnt()) {
1224 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1225 UseCountLeadingZerosInstruction = true;
1226 }
1227 } else if (UseCountLeadingZerosInstruction) {
1228 warning("lzcnt instruction is not available on this CPU");
1229 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1230 }
1231
1232 // Use count trailing zeros instruction if available
1233 if (supports_bmi1()) {
1234 // tzcnt does not require VEX prefix
1235 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1236 if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1237 // Don't use tzcnt if BMI1 is switched off on command line.
1238 UseCountTrailingZerosInstruction = false;
1239 } else {
1240 UseCountTrailingZerosInstruction = true;
1241 }
1242 }
1243 } else if (UseCountTrailingZerosInstruction) {
1244 warning("tzcnt instruction is not available on this CPU");
1245 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1246 }
1247
1248 // BMI instructions (except tzcnt) use an encoding with VEX prefix.
1249 // VEX prefix is generated only when AVX > 0.
1250 if (supports_bmi1() && supports_avx()) {
1251 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1252 UseBMI1Instructions = true;
1253 }
1254 } else if (UseBMI1Instructions) {
1255 warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1256 FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1257 }
1258
1259 if (supports_bmi2() && supports_avx()) {
1260 if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1261 UseBMI2Instructions = true;
1262 }
1263 } else if (UseBMI2Instructions) {
1264 warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1265 FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1266 }
1267
1268 // Use population count instruction if available.
1269 if (supports_popcnt()) {
1270 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1271 UsePopCountInstruction = true;
1272 }
1273 } else if (UsePopCountInstruction) {
1274 warning("POPCNT instruction is not available on this CPU");
1275 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1276 }
1277
1278 // Use fast-string operations if available.
1279 if (supports_erms()) {
1280 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1281 UseFastStosb = true;
1282 }
1283 } else if (UseFastStosb) {
1284 warning("fast-string operations are not available on this CPU");
1285 FLAG_SET_DEFAULT(UseFastStosb, false);
1286 }
1287
1288 #ifdef COMPILER2
1289 if (FLAG_IS_DEFAULT(AlignVector)) {
1290 // Modern processors allow misaligned memory operations for vectors.
1291 AlignVector = !UseUnalignedLoadStores;
1292 }
1293 #endif // COMPILER2
1294
1295 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
1296 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
1297
1298 // Allocation prefetch settings
1299 intx cache_line_size = prefetch_data_size();
1300 if( cache_line_size > AllocatePrefetchStepSize )
1301 AllocatePrefetchStepSize = cache_line_size;
1302
1303 AllocatePrefetchDistance = allocate_prefetch_distance();
1304 AllocatePrefetchStyle = allocate_prefetch_style();
1305
1306 if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1307 if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core
1308 #ifdef _LP64
1309 AllocatePrefetchDistance = 384;
1310 #else
1311 AllocatePrefetchDistance = 320;
1312 #endif
1313 }
1314 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1315 AllocatePrefetchDistance = 192;
1316 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
1317 FLAG_SET_DEFAULT(AllocatePrefetchLines, 4);
1318 }
1319 }
1320 #ifdef COMPILER2
1321 if (supports_sse4_2()) {
1322 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1323 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1324 }
1325 }
1326 #endif
1327 }
1328
1329 #ifdef _LP64
1330 // Prefetch settings
1331 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
1332 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
1333 PrefetchFieldsAhead = prefetch_fields_ahead();
1334 #endif
1335
1336 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1337 (cache_line_size > ContendedPaddingWidth))
1338 ContendedPaddingWidth = cache_line_size;
1339
1340 // This machine allows unaligned memory accesses
1341 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1342 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1343 }
1344
1345 #ifndef PRODUCT
1346 if (log_is_enabled(Info, os, cpu)) {
1347 outputStream* log = Log(os, cpu)::info_stream();
1348 log->print_cr("Logical CPUs per core: %u",
1349 logical_processors_per_package());
1350 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1351 log->print("UseSSE=%d", (int) UseSSE);
1352 if (UseAVX > 0) {
1353 log->print(" UseAVX=%d", (int) UseAVX);
1354 }
1355 if (UseAES) {
1356 log->print(" UseAES=1");
1357 }
1358 #ifdef COMPILER2
1359 if (MaxVectorSize > 0) {
1360 log->print(" MaxVectorSize=%d", (int) MaxVectorSize);
1361 }
1362 #endif
1363 log->cr();
1364 log->print("Allocation");
1365 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
1366 log->print_cr(": no prefetching");
1367 } else {
1368 log->print(" prefetching: ");
1369 if (UseSSE == 0 && supports_3dnow_prefetch()) {
1370 log->print("PREFETCHW");
1371 } else if (UseSSE >= 1) {
1372 if (AllocatePrefetchInstr == 0) {
1373 log->print("PREFETCHNTA");
1374 } else if (AllocatePrefetchInstr == 1) {
1375 log->print("PREFETCHT0");
1376 } else if (AllocatePrefetchInstr == 2) {
1377 log->print("PREFETCHT2");
1378 } else if (AllocatePrefetchInstr == 3) {
1379 log->print("PREFETCHW");
1380 }
1381 }
1382 if (AllocatePrefetchLines > 1) {
1383 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1384 } else {
1385 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1386 }
1387 }
1388
1389 if (PrefetchCopyIntervalInBytes > 0) {
1390 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1391 }
1392 if (PrefetchScanIntervalInBytes > 0) {
1393 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1394 }
1395 if (PrefetchFieldsAhead > 0) {
1396 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1397 }
1398 if (ContendedPaddingWidth > 0) {
1399 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1400 }
1401 }
1402 #endif // !PRODUCT
1403 }
1404
1405 bool VM_Version::use_biased_locking() {
1406 #if INCLUDE_RTM_OPT
1407 // RTM locking is most useful when there is high lock contention and
1408 // low data contention. With high lock contention the lock is usually
1409 // inflated and biased locking is not suitable for that case.
1410 // RTM locking code requires that biased locking is off.
1411 // Note: we can't switch off UseBiasedLocking in get_processor_features()
1412 // because it is used by Thread::allocate() which is called before
1413 // VM_Version::initialize().
1414 if (UseRTMLocking && UseBiasedLocking) {
1415 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1416 FLAG_SET_DEFAULT(UseBiasedLocking, false);
1417 } else {
1418 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1419 UseBiasedLocking = false;
1420 }
1421 }
1422 #endif
1423 return UseBiasedLocking;
1424 }
1425
1426 void VM_Version::initialize() {
1427 ResourceMark rm;
1428 // Making this stub must be FIRST use of assembler
1429
1430 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1431 if (stub_blob == NULL) {
1432 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1433 }
1434 CodeBuffer c(stub_blob);
1435 VM_Version_StubGenerator g(&c);
1436 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1437 g.generate_get_cpu_info());
1438
1439 get_processor_features();
1440 }