src/cpu/ppc/vm/ppc.ad

*** 1,7 ****
  //
! // Copyright (c) 2011, 2014, Oracle and/or its affiliates. All rights reserved.
  // Copyright (c) 2012, 2017 SAP SE. All rights reserved.
  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  //
  // This code is free software; you can redistribute it and/or modify it
  // under the terms of the GNU General Public License version 2 only, as
--- 1,7 ----
  //
! // Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved.
  // Copyright (c) 2012, 2017 SAP SE. All rights reserved.
  // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  //
  // This code is free software; you can redistribute it and/or modify it
  // under the terms of the GNU General Public License version 2 only, as
*** 2172,2187 ****
    assert(MaxVectorSize == 8, "");
    return 8;
  }
  
  // Vector ideal reg.
! const int Matcher::vector_ideal_reg(int size) {
    assert(MaxVectorSize == 8 && size == 8, "");
    return Op_RegL;
  }
  
! const int Matcher::vector_shift_count_ideal_reg(int size) {
    fatal("vector shift is not supported");
    return Node::NotAMachineReg;
  }
  
  // Limits on vector size (number of elements) loaded into vector.
--- 2172,2187 ----
    assert(MaxVectorSize == 8, "");
    return 8;
  }
  
  // Vector ideal reg.
! const uint Matcher::vector_ideal_reg(int size) {
    assert(MaxVectorSize == 8 && size == 8, "");
    return Op_RegL;
  }
  
! const uint Matcher::vector_shift_count_ideal_reg(int size) {
    fatal("vector shift is not supported");
    return Node::NotAMachineReg;
  }
  
  // Limits on vector size (number of elements) loaded into vector.