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src/cpu/x86/vm/x86.ad

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*** 1,7 **** // ! // Copyright (c) 2011, 2012, Oracle and/or its affiliates. All rights reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This code is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License version 2 only, as // published by the Free Software Foundation. --- 1,7 ---- // ! // Copyright (c) 2011, 2018, Oracle and/or its affiliates. All rights reserved. // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. // // This code is free software; you can redistribute it and/or modify it // under the terms of the GNU General Public License version 2 only, as // published by the Free Software Foundation.
*** 681,691 **** int size = (type2aelembytes(bt) == 1) ? 4 : 2; return MIN2(size,max_size); } // Vector ideal reg corresponding to specidied size in bytes ! const int Matcher::vector_ideal_reg(int size) { assert(MaxVectorSize >= size, ""); switch(size) { case 4: return Op_VecS; case 8: return Op_VecD; case 16: return Op_VecX; --- 681,691 ---- int size = (type2aelembytes(bt) == 1) ? 4 : 2; return MIN2(size,max_size); } // Vector ideal reg corresponding to specidied size in bytes ! const uint Matcher::vector_ideal_reg(int size) { assert(MaxVectorSize >= size, ""); switch(size) { case 4: return Op_VecS; case 8: return Op_VecD; case 16: return Op_VecX;
*** 694,704 **** ShouldNotReachHere(); return 0; } // Only lowest bits of xmm reg are used for vector shift count. ! const int Matcher::vector_shift_count_ideal_reg(int size) { return Op_VecS; } // x86 supports misaligned vectors store/load. const bool Matcher::misaligned_vectors_ok() { --- 694,704 ---- ShouldNotReachHere(); return 0; } // Only lowest bits of xmm reg are used for vector shift count. ! const uint Matcher::vector_shift_count_ideal_reg(int size) { return Op_VecS; } // x86 supports misaligned vectors store/load. const bool Matcher::misaligned_vectors_ok() {
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