1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "runtime/java.hpp"
30 #include "runtime/os.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_x86.hpp"
33
34
35 int VM_Version::_cpu;
36 int VM_Version::_model;
37 int VM_Version::_stepping;
38 uint64_t VM_Version::_cpuFeatures;
39 const char* VM_Version::_features_str = "";
40 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
41
42 // Address of instruction which causes SEGV
43 address VM_Version::_cpuinfo_segv_addr = 0;
44 // Address of instruction after the one which causes SEGV
45 address VM_Version::_cpuinfo_cont_addr = 0;
46
47 static BufferBlob* stub_blob;
48 static const int stub_size = 1000;
49
50 extern "C" {
51 typedef void (*get_cpu_info_stub_t)(void*);
52 }
53 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
54
55
56 class VM_Version_StubGenerator: public StubCodeGenerator {
57 public:
58
59 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
60
61 address generate_get_cpu_info() {
62 // Flags to test CPU type.
63 const uint32_t HS_EFL_AC = 0x40000;
64 const uint32_t HS_EFL_ID = 0x200000;
65 // Values for when we don't have a CPUID instruction.
66 const int CPU_FAMILY_SHIFT = 8;
67 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
68 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
69
70 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
71 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done, wrapup;
72 Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
73
74 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
75 # define __ _masm->
76
77 address start = __ pc();
78
79 //
80 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
81 //
82 // LP64: rcx and rdx are first and second argument registers on windows
83
84 __ push(rbp);
85 #ifdef _LP64
86 __ mov(rbp, c_rarg0); // cpuid_info address
87 #else
88 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
89 #endif
90 __ push(rbx);
91 __ push(rsi);
92 __ pushf(); // preserve rbx, and flags
93 __ pop(rax);
94 __ push(rax);
95 __ mov(rcx, rax);
96 //
97 // if we are unable to change the AC flag, we have a 386
98 //
99 __ xorl(rax, HS_EFL_AC);
100 __ push(rax);
101 __ popf();
102 __ pushf();
103 __ pop(rax);
104 __ cmpptr(rax, rcx);
105 __ jccb(Assembler::notEqual, detect_486);
106
107 __ movl(rax, CPU_FAMILY_386);
108 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
109 __ jmp(done);
110
111 //
112 // If we are unable to change the ID flag, we have a 486 which does
113 // not support the "cpuid" instruction.
114 //
115 __ bind(detect_486);
116 __ mov(rax, rcx);
117 __ xorl(rax, HS_EFL_ID);
118 __ push(rax);
119 __ popf();
120 __ pushf();
121 __ pop(rax);
122 __ cmpptr(rcx, rax);
123 __ jccb(Assembler::notEqual, detect_586);
124
125 __ bind(cpu486);
126 __ movl(rax, CPU_FAMILY_486);
127 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
128 __ jmp(done);
129
130 //
131 // At this point, we have a chip which supports the "cpuid" instruction
132 //
133 __ bind(detect_586);
134 __ xorl(rax, rax);
135 __ cpuid();
136 __ orl(rax, rax);
137 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
138 // value of at least 1, we give up and
139 // assume a 486
140 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
141 __ movl(Address(rsi, 0), rax);
142 __ movl(Address(rsi, 4), rbx);
143 __ movl(Address(rsi, 8), rcx);
144 __ movl(Address(rsi,12), rdx);
145
146 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
147 __ jccb(Assembler::belowEqual, std_cpuid4);
148
149 //
150 // cpuid(0xB) Processor Topology
151 //
152 __ movl(rax, 0xb);
153 __ xorl(rcx, rcx); // Threads level
154 __ cpuid();
155
156 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
157 __ movl(Address(rsi, 0), rax);
158 __ movl(Address(rsi, 4), rbx);
159 __ movl(Address(rsi, 8), rcx);
160 __ movl(Address(rsi,12), rdx);
161
162 __ movl(rax, 0xb);
163 __ movl(rcx, 1); // Cores level
164 __ cpuid();
165 __ push(rax);
166 __ andl(rax, 0x1f); // Determine if valid topology level
167 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
168 __ andl(rax, 0xffff);
169 __ pop(rax);
170 __ jccb(Assembler::equal, std_cpuid4);
171
172 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
173 __ movl(Address(rsi, 0), rax);
174 __ movl(Address(rsi, 4), rbx);
175 __ movl(Address(rsi, 8), rcx);
176 __ movl(Address(rsi,12), rdx);
177
178 __ movl(rax, 0xb);
179 __ movl(rcx, 2); // Packages level
180 __ cpuid();
181 __ push(rax);
182 __ andl(rax, 0x1f); // Determine if valid topology level
183 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
184 __ andl(rax, 0xffff);
185 __ pop(rax);
186 __ jccb(Assembler::equal, std_cpuid4);
187
188 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
189 __ movl(Address(rsi, 0), rax);
190 __ movl(Address(rsi, 4), rbx);
191 __ movl(Address(rsi, 8), rcx);
192 __ movl(Address(rsi,12), rdx);
193
194 //
195 // cpuid(0x4) Deterministic cache params
196 //
197 __ bind(std_cpuid4);
198 __ movl(rax, 4);
199 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
200 __ jccb(Assembler::greater, std_cpuid1);
201
202 __ xorl(rcx, rcx); // L1 cache
203 __ cpuid();
204 __ push(rax);
205 __ andl(rax, 0x1f); // Determine if valid cache parameters used
206 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
207 __ pop(rax);
208 __ jccb(Assembler::equal, std_cpuid1);
209
210 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
211 __ movl(Address(rsi, 0), rax);
212 __ movl(Address(rsi, 4), rbx);
213 __ movl(Address(rsi, 8), rcx);
214 __ movl(Address(rsi,12), rdx);
215
216 //
217 // Standard cpuid(0x1)
218 //
219 __ bind(std_cpuid1);
220 __ movl(rax, 1);
221 __ cpuid();
222 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
223 __ movl(Address(rsi, 0), rax);
224 __ movl(Address(rsi, 4), rbx);
225 __ movl(Address(rsi, 8), rcx);
226 __ movl(Address(rsi,12), rdx);
227
228 //
229 // Check if OS has enabled XGETBV instruction to access XCR0
230 // (OSXSAVE feature flag) and CPU supports AVX
231 //
232 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
233 __ cmpl(rcx, 0x18000000);
234 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
235
236 //
237 // XCR0, XFEATURE_ENABLED_MASK register
238 //
239 __ xorl(rcx, rcx); // zero for XCR0 register
240 __ xgetbv();
241 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
242 __ movl(Address(rsi, 0), rax);
243 __ movl(Address(rsi, 4), rdx);
244
245 //
246 // cpuid(0x7) Structured Extended Features
247 //
248 __ bind(sef_cpuid);
249 __ movl(rax, 7);
250 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
251 __ jccb(Assembler::greater, ext_cpuid);
252
253 __ xorl(rcx, rcx);
254 __ cpuid();
255 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
256 __ movl(Address(rsi, 0), rax);
257 __ movl(Address(rsi, 4), rbx);
258
259 //
260 // Extended cpuid(0x80000000)
261 //
262 __ bind(ext_cpuid);
263 __ movl(rax, 0x80000000);
264 __ cpuid();
265 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
266 __ jcc(Assembler::belowEqual, done);
267 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
268 __ jccb(Assembler::belowEqual, ext_cpuid1);
269 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
270 __ jccb(Assembler::belowEqual, ext_cpuid5);
271 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
272 __ jccb(Assembler::belowEqual, ext_cpuid7);
273 //
274 // Extended cpuid(0x80000008)
275 //
276 __ movl(rax, 0x80000008);
277 __ cpuid();
278 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
279 __ movl(Address(rsi, 0), rax);
280 __ movl(Address(rsi, 4), rbx);
281 __ movl(Address(rsi, 8), rcx);
282 __ movl(Address(rsi,12), rdx);
283
284 //
285 // Extended cpuid(0x80000007)
286 //
287 __ bind(ext_cpuid7);
288 __ movl(rax, 0x80000007);
289 __ cpuid();
290 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
291 __ movl(Address(rsi, 0), rax);
292 __ movl(Address(rsi, 4), rbx);
293 __ movl(Address(rsi, 8), rcx);
294 __ movl(Address(rsi,12), rdx);
295
296 //
297 // Extended cpuid(0x80000005)
298 //
299 __ bind(ext_cpuid5);
300 __ movl(rax, 0x80000005);
301 __ cpuid();
302 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
303 __ movl(Address(rsi, 0), rax);
304 __ movl(Address(rsi, 4), rbx);
305 __ movl(Address(rsi, 8), rcx);
306 __ movl(Address(rsi,12), rdx);
307
308 //
309 // Extended cpuid(0x80000001)
310 //
311 __ bind(ext_cpuid1);
312 __ movl(rax, 0x80000001);
313 __ cpuid();
314 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
315 __ movl(Address(rsi, 0), rax);
316 __ movl(Address(rsi, 4), rbx);
317 __ movl(Address(rsi, 8), rcx);
318 __ movl(Address(rsi,12), rdx);
319
320 //
321 // Check if OS has enabled XGETBV instruction to access XCR0
322 // (OSXSAVE feature flag) and CPU supports AVX
323 //
324 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
325 __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
326 __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
327 __ cmpl(rcx, 0x18000000);
328 __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
329
330 __ movl(rax, 0x6);
331 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
332 __ cmpl(rax, 0x6);
333 __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
334
335 // we need to bridge farther than imm8, so we use this island as a thunk
336 __ bind(done);
337 __ jmp(wrapup);
338
339 __ bind(start_simd_check);
340 //
341 // Some OSs have a bug when upper 128/256bits of YMM/ZMM
342 // registers are not restored after a signal processing.
343 // Generate SEGV here (reference through NULL)
344 // and check upper YMM/ZMM bits after it.
345 //
346 intx saved_useavx = UseAVX;
347 intx saved_usesse = UseSSE;
348 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
349 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
350 __ movl(rax, 0x10000);
351 __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
352 __ cmpl(rax, 0x10000);
353 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
354 // check _cpuid_info.xem_xcr0_eax.bits.opmask
355 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
356 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
357 __ movl(rax, 0xE0);
358 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
359 __ cmpl(rax, 0xE0);
360 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
361
362 // EVEX setup: run in lowest evex mode
363 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
364 UseAVX = 3;
365 UseSSE = 2;
366 // load value into all 64 bytes of zmm7 register
367 __ movl(rcx, VM_Version::ymm_test_value());
368 __ movdl(xmm0, rcx);
369 __ movl(rcx, 0xffff);
370 __ kmovwl(k1, rcx);
371 __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
372 __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
373 #ifdef _LP64
374 __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
375 __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
376 #endif
377 VM_Version::clean_cpuFeatures();
378 __ jmp(save_restore_except);
379
380 __ bind(legacy_setup);
381 // AVX setup
382 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
383 UseAVX = 1;
384 UseSSE = 2;
385 // load value into all 32 bytes of ymm7 register
386 __ movl(rcx, VM_Version::ymm_test_value());
387
388 __ movdl(xmm0, rcx);
389 __ pshufd(xmm0, xmm0, 0x00);
390 __ vinsertf128h(xmm0, xmm0, xmm0);
391 __ vmovdqu(xmm7, xmm0);
392 #ifdef _LP64
393 __ vmovdqu(xmm8, xmm0);
394 __ vmovdqu(xmm15, xmm0);
395 #endif
396 VM_Version::clean_cpuFeatures();
397
398 __ bind(save_restore_except);
399 __ xorl(rsi, rsi);
400 VM_Version::set_cpuinfo_segv_addr(__ pc());
401 // Generate SEGV
402 __ movl(rax, Address(rsi, 0));
403
404 VM_Version::set_cpuinfo_cont_addr(__ pc());
405 // Returns here after signal. Save xmm0 to check it later.
406
407 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
408 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
409 __ movl(rax, 0x10000);
410 __ andl(rax, Address(rsi, 4));
411 __ cmpl(rax, 0x10000);
412 __ jccb(Assembler::notEqual, legacy_save_restore);
413 // check _cpuid_info.xem_xcr0_eax.bits.opmask
414 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
415 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
416 __ movl(rax, 0xE0);
417 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
418 __ cmpl(rax, 0xE0);
419 __ jccb(Assembler::notEqual, legacy_save_restore);
420
421 // EVEX check: run in lowest evex mode
422 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
423 UseAVX = 3;
424 UseSSE = 2;
425 __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
426 __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
427 __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
428 #ifdef _LP64
429 __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
430 __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
431 #endif
432 VM_Version::clean_cpuFeatures();
433 UseAVX = saved_useavx;
434 UseSSE = saved_usesse;
435 __ jmp(wrapup);
436
437 __ bind(legacy_save_restore);
438 // AVX check
439 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
440 UseAVX = 1;
441 UseSSE = 2;
442 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
443 __ vmovdqu(Address(rsi, 0), xmm0);
444 __ vmovdqu(Address(rsi, 32), xmm7);
445 #ifdef _LP64
446 __ vmovdqu(Address(rsi, 64), xmm8);
447 __ vmovdqu(Address(rsi, 96), xmm15);
448 #endif
449 VM_Version::clean_cpuFeatures();
450 UseAVX = saved_useavx;
451 UseSSE = saved_usesse;
452
453 __ bind(wrapup);
454 __ popf();
455 __ pop(rsi);
456 __ pop(rbx);
457 __ pop(rbp);
458 __ ret(0);
459
460 # undef __
461
462 return start;
463 };
464 };
465
466 void VM_Version::get_processor_features() {
467
468 _cpu = 4; // 486 by default
469 _model = 0;
470 _stepping = 0;
471 _cpuFeatures = 0;
472 _logical_processors_per_package = 1;
473 // i486 internal cache is both I&D and has a 16-byte line size
474 _L1_data_cache_line_size = 16;
475
476 if (!Use486InstrsOnly) {
477 // Get raw processor info
478
479 get_cpu_info_stub(&_cpuid_info);
480
481 assert_is_initialized();
482 _cpu = extended_cpu_family();
483 _model = extended_cpu_model();
484 _stepping = cpu_stepping();
485
486 if (cpu_family() > 4) { // it supports CPUID
487 _cpuFeatures = feature_flags();
488 // Logical processors are only available on P4s and above,
489 // and only if hyperthreading is available.
490 _logical_processors_per_package = logical_processor_count();
491 _L1_data_cache_line_size = L1_line_size();
492 }
493 }
494
495 _supports_cx8 = supports_cmpxchg8();
496 // xchg and xadd instructions
497 _supports_atomic_getset4 = true;
498 _supports_atomic_getadd4 = true;
499 LP64_ONLY(_supports_atomic_getset8 = true);
500 LP64_ONLY(_supports_atomic_getadd8 = true);
501
502 #ifdef _LP64
503 // OS should support SSE for x64 and hardware should support at least SSE2.
504 if (!VM_Version::supports_sse2()) {
505 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
506 }
507 // in 64 bit the use of SSE2 is the minimum
508 if (UseSSE < 2) UseSSE = 2;
509 #endif
510
511 #ifdef AMD64
512 // flush_icache_stub have to be generated first.
513 // That is why Icache line size is hard coded in ICache class,
514 // see icache_x86.hpp. It is also the reason why we can't use
515 // clflush instruction in 32-bit VM since it could be running
516 // on CPU which does not support it.
517 //
518 // The only thing we can do is to verify that flushed
519 // ICache::line_size has correct value.
520 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
521 // clflush_size is size in quadwords (8 bytes).
522 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
523 #endif
524
525 // If the OS doesn't support SSE, we can't use this feature even if the HW does
526 if (!os::supports_sse())
527 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
528
529 if (UseSSE < 4) {
530 _cpuFeatures &= ~CPU_SSE4_1;
531 _cpuFeatures &= ~CPU_SSE4_2;
532 }
533
534 if (UseSSE < 3) {
535 _cpuFeatures &= ~CPU_SSE3;
536 _cpuFeatures &= ~CPU_SSSE3;
537 _cpuFeatures &= ~CPU_SSE4A;
538 }
539
540 if (UseSSE < 2)
541 _cpuFeatures &= ~CPU_SSE2;
542
543 if (UseSSE < 1)
544 _cpuFeatures &= ~CPU_SSE;
545
546 // first try initial setting and detect what we can support
547 if (UseAVX > 0) {
548 if (UseAVX > 2 && supports_evex()) {
549 UseAVX = 3;
550 } else if (UseAVX > 1 && supports_avx2()) {
551 UseAVX = 2;
552 } else if (UseAVX > 0 && supports_avx()) {
553 UseAVX = 1;
554 } else {
555 UseAVX = 0;
556 }
557 } else if (UseAVX < 0) {
558 UseAVX = 0;
559 }
560
561 if (UseAVX < 3) {
562 _cpuFeatures &= ~CPU_AVX512F;
563 _cpuFeatures &= ~CPU_AVX512DQ;
564 _cpuFeatures &= ~CPU_AVX512CD;
565 _cpuFeatures &= ~CPU_AVX512BW;
566 _cpuFeatures &= ~CPU_AVX512VL;
567 }
568
569 if (UseAVX < 2)
570 _cpuFeatures &= ~CPU_AVX2;
571
572 if (UseAVX < 1)
573 _cpuFeatures &= ~CPU_AVX;
574
575 if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
576 _cpuFeatures &= ~CPU_AES;
577
578 if (logical_processors_per_package() == 1) {
579 // HT processor could be installed on a system which doesn't support HT.
580 _cpuFeatures &= ~CPU_HT;
581 }
582
583 char buf[256];
584 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
585 cores_per_cpu(), threads_per_core(),
586 cpu_family(), _model, _stepping,
587 (supports_cmov() ? ", cmov" : ""),
588 (supports_cmpxchg8() ? ", cx8" : ""),
589 (supports_fxsr() ? ", fxsr" : ""),
590 (supports_mmx() ? ", mmx" : ""),
591 (supports_sse() ? ", sse" : ""),
592 (supports_sse2() ? ", sse2" : ""),
593 (supports_sse3() ? ", sse3" : ""),
594 (supports_ssse3()? ", ssse3": ""),
595 (supports_sse4_1() ? ", sse4.1" : ""),
596 (supports_sse4_2() ? ", sse4.2" : ""),
597 (supports_popcnt() ? ", popcnt" : ""),
598 (supports_avx() ? ", avx" : ""),
599 (supports_avx2() ? ", avx2" : ""),
600 (supports_aes() ? ", aes" : ""),
601 (supports_clmul() ? ", clmul" : ""),
602 (supports_erms() ? ", erms" : ""),
603 (supports_rtm() ? ", rtm" : ""),
604 (supports_mmx_ext() ? ", mmxext" : ""),
605 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
606 (supports_lzcnt() ? ", lzcnt": ""),
607 (supports_sse4a() ? ", sse4a": ""),
608 (supports_ht() ? ", ht": ""),
609 (supports_tsc() ? ", tsc": ""),
610 (supports_tscinv_bit() ? ", tscinvbit": ""),
611 (supports_tscinv() ? ", tscinv": ""),
612 (supports_bmi1() ? ", bmi1" : ""),
613 (supports_bmi2() ? ", bmi2" : ""),
614 (supports_adx() ? ", adx" : ""),
615 (supports_evex() ? ", evex" : ""));
616 _features_str = os::strdup(buf);
617
618 // UseSSE is set to the smaller of what hardware supports and what
619 // the command line requires. I.e., you cannot set UseSSE to 2 on
620 // older Pentiums which do not support it.
621 if (UseSSE > 4) UseSSE=4;
622 if (UseSSE < 0) UseSSE=0;
623 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
624 UseSSE = MIN2((intx)3,UseSSE);
625 if (!supports_sse3()) // Drop to 2 if no SSE3 support
626 UseSSE = MIN2((intx)2,UseSSE);
627 if (!supports_sse2()) // Drop to 1 if no SSE2 support
628 UseSSE = MIN2((intx)1,UseSSE);
629 if (!supports_sse ()) // Drop to 0 if no SSE support
630 UseSSE = 0;
631
632 // Use AES instructions if available.
633 if (supports_aes()) {
634 if (FLAG_IS_DEFAULT(UseAES)) {
635 FLAG_SET_DEFAULT(UseAES, true);
636 }
637 if (!UseAES) {
638 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
639 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
640 }
641 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
642 } else {
643 if (UseSSE > 2) {
644 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
645 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
646 }
647 } else {
648 // The AES intrinsic stubs require AES instruction support (of course)
649 // but also require sse3 mode or higher for instructions it use.
650 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
651 warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
652 }
653 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
654 }
655 }
656 } else if (UseAES || UseAESIntrinsics) {
657 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
658 warning("AES instructions are not available on this CPU");
659 }
660 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
661 warning("AES intrinsics are not available on this CPU");
662 }
663 }
664
665 // Use CLMUL instructions if available.
666 if (supports_clmul()) {
667 if (FLAG_IS_DEFAULT(UseCLMUL)) {
668 UseCLMUL = true;
669 }
670 } else if (UseCLMUL) {
671 if (!FLAG_IS_DEFAULT(UseCLMUL))
672 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
673 FLAG_SET_DEFAULT(UseCLMUL, false);
674 }
675
676 if (UseCLMUL && (UseSSE > 2)) {
677 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
678 UseCRC32Intrinsics = true;
679 }
680 } else if (UseCRC32Intrinsics) {
681 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
682 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
683 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
684 }
685
686 if (supports_sse4_2()) {
687 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
688 UseCRC32CIntrinsics = true;
689 }
690 }
691 else if (UseCRC32CIntrinsics) {
692 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
693 warning("CRC32C intrinsics are not available on this CPU");
694 }
695 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
696 }
697
698 // GHASH/GCM intrinsics
699 if (UseCLMUL && (UseSSE > 2)) {
700 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
701 UseGHASHIntrinsics = true;
702 }
703 } else if (UseGHASHIntrinsics) {
704 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
705 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
706 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
707 }
708
709 if (UseSHA) {
710 warning("SHA instructions are not available on this CPU");
711 FLAG_SET_DEFAULT(UseSHA, false);
712 }
713
714 if (UseSHA1Intrinsics) {
715 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
716 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
717 }
718
719 if (UseSHA256Intrinsics) {
720 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
721 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
722 }
723
724 if (UseSHA512Intrinsics) {
725 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
726 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
727 }
728
729 if (UseAdler32Intrinsics) {
730 warning("Adler32Intrinsics not available on this CPU.");
731 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
732 }
733
734 // Adjust RTM (Restricted Transactional Memory) flags
735 if (!supports_rtm() && UseRTMLocking) {
736 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
737 // setting during arguments processing. See use_biased_locking().
738 // VM_Version_init() is executed after UseBiasedLocking is used
739 // in Thread::allocate().
740 vm_exit_during_initialization("RTM instructions are not available on this CPU");
741 }
742
743 #if INCLUDE_RTM_OPT
744 if (UseRTMLocking) {
745 if (is_intel_family_core()) {
746 if ((_model == CPU_MODEL_HASWELL_E3) ||
747 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
748 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) {
749 // currently a collision between SKL and HSW_E3
750 if (!UnlockExperimentalVMOptions && UseAVX < 3) {
751 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
752 } else {
753 warning("UseRTMLocking is only available as experimental option on this platform.");
754 }
755 }
756 }
757 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
758 // RTM locking should be used only for applications with
759 // high lock contention. For now we do not use it by default.
760 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
761 }
762 if (!is_power_of_2(RTMTotalCountIncrRate)) {
763 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
764 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
765 }
766 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
767 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
768 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
769 }
770 } else { // !UseRTMLocking
771 if (UseRTMForStackLocks) {
772 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
773 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
774 }
775 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
776 }
777 if (UseRTMDeopt) {
778 FLAG_SET_DEFAULT(UseRTMDeopt, false);
779 }
780 if (PrintPreciseRTMLockingStatistics) {
781 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
782 }
783 }
784 #else
785 if (UseRTMLocking) {
786 // Only C2 does RTM locking optimization.
787 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
788 // setting during arguments processing. See use_biased_locking().
789 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
790 }
791 #endif
792
793 #ifdef COMPILER2
794 if (UseFPUForSpilling) {
795 if (UseSSE < 2) {
796 // Only supported with SSE2+
797 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
798 }
799 }
800 #endif
801 #if defined(COMPILER2) || INCLUDE_JVMCI
802 if (MaxVectorSize > 0) {
803 if (!is_power_of_2(MaxVectorSize)) {
804 warning("MaxVectorSize must be a power of 2");
805 FLAG_SET_DEFAULT(MaxVectorSize, 64);
806 }
807 if (MaxVectorSize > 64) {
808 FLAG_SET_DEFAULT(MaxVectorSize, 64);
809 }
810 if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) {
811 // 32 bytes vectors (in YMM) are only supported with AVX+
812 FLAG_SET_DEFAULT(MaxVectorSize, 16);
813 }
814 if (UseSSE < 2) {
815 // Vectors (in XMM) are only supported with SSE2+
816 FLAG_SET_DEFAULT(MaxVectorSize, 0);
817 }
818 #if defined(COMPILER2) && defined(ASSERT)
819 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
820 tty->print_cr("State of YMM registers after signal handle:");
821 int nreg = 2 LP64_ONLY(+2);
822 const char* ymm_name[4] = {"0", "7", "8", "15"};
823 for (int i = 0; i < nreg; i++) {
824 tty->print("YMM%s:", ymm_name[i]);
825 for (int j = 7; j >=0; j--) {
826 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
827 }
828 tty->cr();
829 }
830 }
831 #endif // COMPILER2 && ASSERT
832 }
833 #endif // COMPILER2 || INCLUDE_JVMCI
834
835 #ifdef COMPILER2
836 #ifdef _LP64
837 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
838 UseMultiplyToLenIntrinsic = true;
839 }
840 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
841 UseSquareToLenIntrinsic = true;
842 }
843 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
844 UseMulAddIntrinsic = true;
845 }
846 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
847 UseMontgomeryMultiplyIntrinsic = true;
848 }
849 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
850 UseMontgomerySquareIntrinsic = true;
851 }
852 #else
853 if (UseMultiplyToLenIntrinsic) {
854 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
855 warning("multiplyToLen intrinsic is not available in 32-bit VM");
856 }
857 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
858 }
859 if (UseMontgomeryMultiplyIntrinsic) {
860 if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
861 warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
862 }
863 FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
864 }
865 if (UseMontgomerySquareIntrinsic) {
866 if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
867 warning("montgomerySquare intrinsic is not available in 32-bit VM");
868 }
869 FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
870 }
871 if (UseSquareToLenIntrinsic) {
872 if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
873 warning("squareToLen intrinsic is not available in 32-bit VM");
874 }
875 FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
876 }
877 if (UseMulAddIntrinsic) {
878 if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
879 warning("mulAdd intrinsic is not available in 32-bit VM");
880 }
881 FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
882 }
883 #endif
884 #endif // COMPILER2
885
886 // On new cpus instructions which update whole XMM register should be used
887 // to prevent partial register stall due to dependencies on high half.
888 //
889 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
890 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
891 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
892 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
893
894 if( is_amd() ) { // AMD cpus specific settings
895 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
896 // Use it on new AMD cpus starting from Opteron.
897 UseAddressNop = true;
898 }
899 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
900 // Use it on new AMD cpus starting from Opteron.
901 UseNewLongLShift = true;
902 }
903 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
904 if( supports_sse4a() ) {
905 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
906 } else {
907 UseXmmLoadAndClearUpper = false;
908 }
909 }
910 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
911 if( supports_sse4a() ) {
912 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
913 } else {
914 UseXmmRegToRegMoveAll = false;
915 }
916 }
917 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
918 if( supports_sse4a() ) {
919 UseXmmI2F = true;
920 } else {
921 UseXmmI2F = false;
922 }
923 }
924 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
925 if( supports_sse4a() ) {
926 UseXmmI2D = true;
927 } else {
928 UseXmmI2D = false;
929 }
930 }
931 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) {
932 if( supports_sse4_2() && UseSSE >= 4 ) {
933 UseSSE42Intrinsics = true;
934 }
935 }
936
937 // some defaults for AMD family 15h
938 if ( cpu_family() == 0x15 ) {
939 // On family 15h processors default is no sw prefetch
940 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
941 AllocatePrefetchStyle = 0;
942 }
943 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
944 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
945 AllocatePrefetchInstr = 3;
946 }
947 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
948 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
949 UseXMMForArrayCopy = true;
950 }
951 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
952 UseUnalignedLoadStores = true;
953 }
954 }
955
956 #ifdef COMPILER2
957 if (MaxVectorSize > 16) {
958 // Limit vectors size to 16 bytes on current AMD cpus.
959 FLAG_SET_DEFAULT(MaxVectorSize, 16);
960 }
961 #endif // COMPILER2
962 }
963
964 if( is_intel() ) { // Intel cpus specific settings
965 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
966 UseStoreImmI16 = false; // don't use it on Intel cpus
967 }
968 if( cpu_family() == 6 || cpu_family() == 15 ) {
969 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
970 // Use it on all Intel cpus starting from PentiumPro
971 UseAddressNop = true;
972 }
973 }
974 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
975 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
976 }
977 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
978 if( supports_sse3() ) {
979 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
980 } else {
981 UseXmmRegToRegMoveAll = false;
982 }
983 }
984 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
985 #ifdef COMPILER2
986 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
987 // For new Intel cpus do the next optimization:
988 // don't align the beginning of a loop if there are enough instructions
989 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
990 // in current fetch line (OptoLoopAlignment) or the padding
991 // is big (> MaxLoopPad).
992 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
993 // generated NOP instructions. 11 is the largest size of one
994 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
995 MaxLoopPad = 11;
996 }
997 #endif // COMPILER2
998 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
999 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1000 }
1001 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
1002 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1003 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1004 }
1005 }
1006 if (supports_sse4_2() && UseSSE >= 4) {
1007 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1008 UseSSE42Intrinsics = true;
1009 }
1010 }
1011 }
1012 if ((cpu_family() == 0x06) &&
1013 ((extended_cpu_model() == 0x36) || // Centerton
1014 (extended_cpu_model() == 0x37) || // Silvermont
1015 (extended_cpu_model() == 0x4D))) {
1016 #ifdef COMPILER2
1017 if (FLAG_IS_DEFAULT(OptoScheduling)) {
1018 OptoScheduling = true;
1019 }
1020 #endif
1021 if (supports_sse4_2()) { // Silvermont
1022 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1023 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1024 }
1025 }
1026 }
1027 if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1028 AllocatePrefetchInstr = 3;
1029 }
1030 }
1031
1032 // Use count leading zeros count instruction if available.
1033 if (supports_lzcnt()) {
1034 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1035 UseCountLeadingZerosInstruction = true;
1036 }
1037 } else if (UseCountLeadingZerosInstruction) {
1038 warning("lzcnt instruction is not available on this CPU");
1039 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1040 }
1041
1042 // Use count trailing zeros instruction if available
1043 if (supports_bmi1()) {
1044 // tzcnt does not require VEX prefix
1045 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1046 if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1047 // Don't use tzcnt if BMI1 is switched off on command line.
1048 UseCountTrailingZerosInstruction = false;
1049 } else {
1050 UseCountTrailingZerosInstruction = true;
1051 }
1052 }
1053 } else if (UseCountTrailingZerosInstruction) {
1054 warning("tzcnt instruction is not available on this CPU");
1055 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1056 }
1057
1058 // BMI instructions (except tzcnt) use an encoding with VEX prefix.
1059 // VEX prefix is generated only when AVX > 0.
1060 if (supports_bmi1() && supports_avx()) {
1061 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1062 UseBMI1Instructions = true;
1063 }
1064 } else if (UseBMI1Instructions) {
1065 warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1066 FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1067 }
1068
1069 if (supports_bmi2() && supports_avx()) {
1070 if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1071 UseBMI2Instructions = true;
1072 }
1073 } else if (UseBMI2Instructions) {
1074 warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1075 FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1076 }
1077
1078 // Use population count instruction if available.
1079 if (supports_popcnt()) {
1080 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1081 UsePopCountInstruction = true;
1082 }
1083 } else if (UsePopCountInstruction) {
1084 warning("POPCNT instruction is not available on this CPU");
1085 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1086 }
1087
1088 // Use fast-string operations if available.
1089 if (supports_erms()) {
1090 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1091 UseFastStosb = true;
1092 }
1093 } else if (UseFastStosb) {
1094 warning("fast-string operations are not available on this CPU");
1095 FLAG_SET_DEFAULT(UseFastStosb, false);
1096 }
1097
1098 #ifdef COMPILER2
1099 if (FLAG_IS_DEFAULT(AlignVector)) {
1100 // Modern processors allow misaligned memory operations for vectors.
1101 AlignVector = !UseUnalignedLoadStores;
1102 }
1103 #endif // COMPILER2
1104
1105 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
1106 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
1107
1108 // Allocation prefetch settings
1109 intx cache_line_size = prefetch_data_size();
1110 if( cache_line_size > AllocatePrefetchStepSize )
1111 AllocatePrefetchStepSize = cache_line_size;
1112
1113 assert(AllocatePrefetchLines > 0, "invalid value");
1114 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
1115 AllocatePrefetchLines = 3;
1116 assert(AllocateInstancePrefetchLines > 0, "invalid value");
1117 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
1118 AllocateInstancePrefetchLines = 1;
1119
1120 AllocatePrefetchDistance = allocate_prefetch_distance();
1121 AllocatePrefetchStyle = allocate_prefetch_style();
1122
1123 if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1124 if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core
1125 #ifdef _LP64
1126 AllocatePrefetchDistance = 384;
1127 #else
1128 AllocatePrefetchDistance = 320;
1129 #endif
1130 }
1131 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1132 AllocatePrefetchDistance = 192;
1133 AllocatePrefetchLines = 4;
1134 }
1135 #ifdef COMPILER2
1136 if (supports_sse4_2()) {
1137 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1138 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1139 }
1140 }
1141 #endif
1142 }
1143
1144 #ifdef _LP64
1145 // Prefetch settings
1146 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
1147 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
1148 PrefetchFieldsAhead = prefetch_fields_ahead();
1149 #endif
1150
1151 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1152 (cache_line_size > ContendedPaddingWidth))
1153 ContendedPaddingWidth = cache_line_size;
1154
1155 // This machine allows unaligned memory accesses
1156 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1157 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1158 }
1159
1160 #ifndef PRODUCT
1161 if (PrintMiscellaneous && Verbose) {
1162 tty->print_cr("Logical CPUs per core: %u",
1163 logical_processors_per_package());
1164 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1165 tty->print("UseSSE=%d", (int) UseSSE);
1166 if (UseAVX > 0) {
1167 tty->print(" UseAVX=%d", (int) UseAVX);
1168 }
1169 if (UseAES) {
1170 tty->print(" UseAES=1");
1171 }
1172 #ifdef COMPILER2
1173 if (MaxVectorSize > 0) {
1174 tty->print(" MaxVectorSize=%d", (int) MaxVectorSize);
1175 }
1176 #endif
1177 tty->cr();
1178 tty->print("Allocation");
1179 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
1180 tty->print_cr(": no prefetching");
1181 } else {
1182 tty->print(" prefetching: ");
1183 if (UseSSE == 0 && supports_3dnow_prefetch()) {
1184 tty->print("PREFETCHW");
1185 } else if (UseSSE >= 1) {
1186 if (AllocatePrefetchInstr == 0) {
1187 tty->print("PREFETCHNTA");
1188 } else if (AllocatePrefetchInstr == 1) {
1189 tty->print("PREFETCHT0");
1190 } else if (AllocatePrefetchInstr == 2) {
1191 tty->print("PREFETCHT2");
1192 } else if (AllocatePrefetchInstr == 3) {
1193 tty->print("PREFETCHW");
1194 }
1195 }
1196 if (AllocatePrefetchLines > 1) {
1197 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1198 } else {
1199 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1200 }
1201 }
1202
1203 if (PrefetchCopyIntervalInBytes > 0) {
1204 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1205 }
1206 if (PrefetchScanIntervalInBytes > 0) {
1207 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1208 }
1209 if (PrefetchFieldsAhead > 0) {
1210 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1211 }
1212 if (ContendedPaddingWidth > 0) {
1213 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1214 }
1215 }
1216 #endif // !PRODUCT
1217 }
1218
1219 bool VM_Version::use_biased_locking() {
1220 #if INCLUDE_RTM_OPT
1221 // RTM locking is most useful when there is high lock contention and
1222 // low data contention. With high lock contention the lock is usually
1223 // inflated and biased locking is not suitable for that case.
1224 // RTM locking code requires that biased locking is off.
1225 // Note: we can't switch off UseBiasedLocking in get_processor_features()
1226 // because it is used by Thread::allocate() which is called before
1227 // VM_Version::initialize().
1228 if (UseRTMLocking && UseBiasedLocking) {
1229 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1230 FLAG_SET_DEFAULT(UseBiasedLocking, false);
1231 } else {
1232 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1233 UseBiasedLocking = false;
1234 }
1235 }
1236 #endif
1237 return UseBiasedLocking;
1238 }
1239
1240 void VM_Version::initialize() {
1241 ResourceMark rm;
1242 // Making this stub must be FIRST use of assembler
1243
1244 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1245 if (stub_blob == NULL) {
1246 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1247 }
1248 CodeBuffer c(stub_blob);
1249 VM_Version_StubGenerator g(&c);
1250 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1251 g.generate_get_cpu_info());
1252
1253 get_processor_features();
1254 }