212 (!has_hardware_div32() ? ", no-div32" : ""),
213 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
214
215 // buf is started with ", " or is empty
216 _features_str = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
217
218 // UseVIS is set to the smallest of what hardware supports and what
219 // the command line requires. I.e., you cannot set UseVIS to 3 on
220 // older UltraSparc which do not support it.
221 if (UseVIS > 3) UseVIS=3;
222 if (UseVIS < 0) UseVIS=0;
223 if (!has_vis3()) // Drop to 2 if no VIS3 support
224 UseVIS = MIN2((intx)2,UseVIS);
225 if (!has_vis2()) // Drop to 1 if no VIS2 support
226 UseVIS = MIN2((intx)1,UseVIS);
227 if (!has_vis1()) // Drop to 0 if no VIS1 support
228 UseVIS = 0;
229
230 // SPARC T4 and above should have support for AES instructions
231 if (has_aes()) {
232 if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3
233 if (FLAG_IS_DEFAULT(UseAES)) {
234 FLAG_SET_DEFAULT(UseAES, true);
235 }
236 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
237 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
238 }
239 // we disable both the AES flags if either of them is disabled on the command line
240 if (!UseAES || !UseAESIntrinsics) {
241 FLAG_SET_DEFAULT(UseAES, false);
242 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
243 }
244 } else {
245 if (UseAES || UseAESIntrinsics) {
246 warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
247 if (UseAES) {
248 FLAG_SET_DEFAULT(UseAES, false);
249 }
250 if (UseAESIntrinsics) {
251 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
252 }
253 }
254 }
255 } else if (UseAES || UseAESIntrinsics) {
256 warning("AES instructions are not available on this CPU");
257 if (UseAES) {
258 FLAG_SET_DEFAULT(UseAES, false);
259 }
260 if (UseAESIntrinsics) {
261 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
262 }
263 }
264
265 // GHASH/GCM intrinsics
266 if (has_vis3() && (UseVIS > 2)) {
267 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
268 UseGHASHIntrinsics = true;
269 }
270 } else if (UseGHASHIntrinsics) {
271 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
272 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
273 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
274 }
275
276 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
277 if (has_sha1() || has_sha256() || has_sha512()) {
278 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
279 if (FLAG_IS_DEFAULT(UseSHA)) {
280 FLAG_SET_DEFAULT(UseSHA, true);
|
212 (!has_hardware_div32() ? ", no-div32" : ""),
213 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
214
215 // buf is started with ", " or is empty
216 _features_str = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
217
218 // UseVIS is set to the smallest of what hardware supports and what
219 // the command line requires. I.e., you cannot set UseVIS to 3 on
220 // older UltraSparc which do not support it.
221 if (UseVIS > 3) UseVIS=3;
222 if (UseVIS < 0) UseVIS=0;
223 if (!has_vis3()) // Drop to 2 if no VIS3 support
224 UseVIS = MIN2((intx)2,UseVIS);
225 if (!has_vis2()) // Drop to 1 if no VIS2 support
226 UseVIS = MIN2((intx)1,UseVIS);
227 if (!has_vis1()) // Drop to 0 if no VIS1 support
228 UseVIS = 0;
229
230 // SPARC T4 and above should have support for AES instructions
231 if (has_aes()) {
232 if (FLAG_IS_DEFAULT(UseAES)) {
233 FLAG_SET_DEFAULT(UseAES, true);
234 }
235 if (!UseAES) {
236 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
237 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
238 }
239 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
240 } else {
241 // The AES intrinsic stubs require AES instruction support (of course)
242 // but also require VIS3 mode or higher for instructions it use.
243 if (UseVIS > 2) {
244 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
245 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
246 }
247 } else {
248 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
249 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
250 }
251 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
252 }
253 }
254 } else if (UseAES || UseAESIntrinsics) {
255 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
256 warning("AES instructions are not available on this CPU");
257 FLAG_SET_DEFAULT(UseAES, false);
258 }
259 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
260 warning("AES intrinsics are not available on this CPU");
261 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
262 }
263 }
264
265 // GHASH/GCM intrinsics
266 if (has_vis3() && (UseVIS > 2)) {
267 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
268 UseGHASHIntrinsics = true;
269 }
270 } else if (UseGHASHIntrinsics) {
271 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
272 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
273 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
274 }
275
276 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
277 if (has_sha1() || has_sha256() || has_sha512()) {
278 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
279 if (FLAG_IS_DEFAULT(UseSHA)) {
280 FLAG_SET_DEFAULT(UseSHA, true);
|