615 (supports_evex() ? ", evex" : ""));
616 _features_str = os::strdup(buf);
617
618 // UseSSE is set to the smaller of what hardware supports and what
619 // the command line requires. I.e., you cannot set UseSSE to 2 on
620 // older Pentiums which do not support it.
621 if (UseSSE > 4) UseSSE=4;
622 if (UseSSE < 0) UseSSE=0;
623 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
624 UseSSE = MIN2((intx)3,UseSSE);
625 if (!supports_sse3()) // Drop to 2 if no SSE3 support
626 UseSSE = MIN2((intx)2,UseSSE);
627 if (!supports_sse2()) // Drop to 1 if no SSE2 support
628 UseSSE = MIN2((intx)1,UseSSE);
629 if (!supports_sse ()) // Drop to 0 if no SSE support
630 UseSSE = 0;
631
632 // Use AES instructions if available.
633 if (supports_aes()) {
634 if (FLAG_IS_DEFAULT(UseAES)) {
635 UseAES = true;
636 }
637 } else if (UseAES) {
638 if (!FLAG_IS_DEFAULT(UseAES))
639 warning("AES instructions are not available on this CPU");
640 FLAG_SET_DEFAULT(UseAES, false);
641 }
642
643 // Use CLMUL instructions if available.
644 if (supports_clmul()) {
645 if (FLAG_IS_DEFAULT(UseCLMUL)) {
646 UseCLMUL = true;
647 }
648 } else if (UseCLMUL) {
649 if (!FLAG_IS_DEFAULT(UseCLMUL))
650 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
651 FLAG_SET_DEFAULT(UseCLMUL, false);
652 }
653
654 if (UseCLMUL && (UseSSE > 2)) {
655 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
656 UseCRC32Intrinsics = true;
657 }
658 } else if (UseCRC32Intrinsics) {
659 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
660 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
661 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
662 }
663
664 if (supports_sse4_2()) {
665 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
666 UseCRC32CIntrinsics = true;
667 }
668 }
669 else if (UseCRC32CIntrinsics) {
670 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
671 warning("CRC32C intrinsics are not available on this CPU");
672 }
673 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
674 }
675
676 // The AES intrinsic stubs require AES instruction support (of course)
677 // but also require sse3 mode for instructions it use.
678 if (UseAES && (UseSSE > 2)) {
679 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
680 UseAESIntrinsics = true;
681 }
682 } else if (UseAESIntrinsics) {
683 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
684 warning("AES intrinsics are not available on this CPU");
685 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
686 }
687
688 // GHASH/GCM intrinsics
689 if (UseCLMUL && (UseSSE > 2)) {
690 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
691 UseGHASHIntrinsics = true;
692 }
693 } else if (UseGHASHIntrinsics) {
694 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
695 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
696 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
697 }
698
699 if (UseSHA) {
700 warning("SHA instructions are not available on this CPU");
701 FLAG_SET_DEFAULT(UseSHA, false);
702 }
703
704 if (UseSHA1Intrinsics) {
705 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
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615 (supports_evex() ? ", evex" : ""));
616 _features_str = os::strdup(buf);
617
618 // UseSSE is set to the smaller of what hardware supports and what
619 // the command line requires. I.e., you cannot set UseSSE to 2 on
620 // older Pentiums which do not support it.
621 if (UseSSE > 4) UseSSE=4;
622 if (UseSSE < 0) UseSSE=0;
623 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
624 UseSSE = MIN2((intx)3,UseSSE);
625 if (!supports_sse3()) // Drop to 2 if no SSE3 support
626 UseSSE = MIN2((intx)2,UseSSE);
627 if (!supports_sse2()) // Drop to 1 if no SSE2 support
628 UseSSE = MIN2((intx)1,UseSSE);
629 if (!supports_sse ()) // Drop to 0 if no SSE support
630 UseSSE = 0;
631
632 // Use AES instructions if available.
633 if (supports_aes()) {
634 if (FLAG_IS_DEFAULT(UseAES)) {
635 FLAG_SET_DEFAULT(UseAES, true);
636 }
637 if (!UseAES) {
638 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
639 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
640 }
641 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
642 } else {
643 if (UseSSE > 2) {
644 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
645 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
646 }
647 } else {
648 // The AES intrinsic stubs require AES instruction support (of course)
649 // but also require sse3 mode or higher for instructions it use.
650 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
651 warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
652 }
653 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
654 }
655 }
656 } else if (UseAES || UseAESIntrinsics) {
657 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
658 warning("AES instructions are not available on this CPU");
659 FLAG_SET_DEFAULT(UseAES, false);
660 }
661 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
662 warning("AES intrinsics are not available on this CPU");
663 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
664 }
665 }
666
667 // Use CLMUL instructions if available.
668 if (supports_clmul()) {
669 if (FLAG_IS_DEFAULT(UseCLMUL)) {
670 UseCLMUL = true;
671 }
672 } else if (UseCLMUL) {
673 if (!FLAG_IS_DEFAULT(UseCLMUL))
674 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
675 FLAG_SET_DEFAULT(UseCLMUL, false);
676 }
677
678 if (UseCLMUL && (UseSSE > 2)) {
679 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
680 UseCRC32Intrinsics = true;
681 }
682 } else if (UseCRC32Intrinsics) {
683 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
684 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
685 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
686 }
687
688 if (supports_sse4_2()) {
689 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
690 UseCRC32CIntrinsics = true;
691 }
692 }
693 else if (UseCRC32CIntrinsics) {
694 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
695 warning("CRC32C intrinsics are not available on this CPU");
696 }
697 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
698 }
699
700 // GHASH/GCM intrinsics
701 if (UseCLMUL && (UseSSE > 2)) {
702 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
703 UseGHASHIntrinsics = true;
704 }
705 } else if (UseGHASHIntrinsics) {
706 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
707 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
708 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
709 }
710
711 if (UseSHA) {
712 warning("SHA instructions are not available on this CPU");
713 FLAG_SET_DEFAULT(UseSHA, false);
714 }
715
716 if (UseSHA1Intrinsics) {
717 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
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