973 assert(UseAddressNop, "no CPU support");
974 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
975 emit_byte(0x0F);
976 emit_byte(0x1F);
977 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
978 emit_long(0); // 32-bits offset (4 bytes)
979 }
980
981 void Assembler::addr_nop_8() {
982 assert(UseAddressNop, "no CPU support");
983 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
984 emit_byte(0x0F);
985 emit_byte(0x1F);
986 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
987 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
988 emit_long(0); // 32-bits offset (4 bytes)
989 }
990
991 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
992 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
993 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
994 emit_byte(0x58);
995 emit_byte(0xC0 | encode);
996 }
997
998 void Assembler::addsd(XMMRegister dst, Address src) {
999 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1000 InstructionMark im(this);
1001 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1002 emit_byte(0x58);
1003 emit_operand(dst, src);
1004 }
1005
1006 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1007 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1008 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1009 emit_byte(0x58);
1010 emit_byte(0xC0 | encode);
1011 }
1012
1013 void Assembler::addss(XMMRegister dst, Address src) {
1014 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1015 InstructionMark im(this);
1016 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1017 emit_byte(0x58);
1018 emit_operand(dst, src);
1019 }
1020
1021 void Assembler::andl(Address dst, int32_t imm32) {
1022 InstructionMark im(this);
1023 prefix(dst);
1024 emit_byte(0x81);
1025 emit_operand(rsp, dst, 4);
1026 emit_long(imm32);
1027 }
1028
1029 void Assembler::andl(Register dst, int32_t imm32) {
1030 prefix(dst);
1031 emit_arith(0x81, 0xE0, dst, imm32);
1032 }
1033
1034 void Assembler::andl(Register dst, Address src) {
1035 InstructionMark im(this);
1036 prefix(src, dst);
1037 emit_byte(0x23);
1038 emit_operand(dst, src);
1039 }
1040
1041 void Assembler::andl(Register dst, Register src) {
1042 (void) prefix_and_encode(dst->encoding(), src->encoding());
1043 emit_arith(0x23, 0xC0, dst, src);
1044 }
1045
1046 void Assembler::andpd(XMMRegister dst, Address src) {
1047 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1048 InstructionMark im(this);
1049 simd_prefix(dst, dst, src, VEX_SIMD_66);
1050 emit_byte(0x54);
1051 emit_operand(dst, src);
1052 }
1053
1054 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
1055 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1056 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
1057 emit_byte(0x54);
1058 emit_byte(0xC0 | encode);
1059 }
1060
1061 void Assembler::andps(XMMRegister dst, Address src) {
1062 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1063 InstructionMark im(this);
1064 simd_prefix(dst, dst, src, VEX_SIMD_NONE);
1065 emit_byte(0x54);
1066 emit_operand(dst, src);
1067 }
1068
1069 void Assembler::andps(XMMRegister dst, XMMRegister src) {
1070 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1071 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE);
1072 emit_byte(0x54);
1073 emit_byte(0xC0 | encode);
1074 }
1075
1076 void Assembler::bsfl(Register dst, Register src) {
1077 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1078 emit_byte(0x0F);
1079 emit_byte(0xBC);
1080 emit_byte(0xC0 | encode);
1081 }
1082
1083 void Assembler::bsrl(Register dst, Register src) {
1084 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
1085 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1086 emit_byte(0x0F);
1087 emit_byte(0xBD);
1088 emit_byte(0xC0 | encode);
1089 }
1090
1091 void Assembler::bswapl(Register reg) { // bswap
1092 int encode = prefix_and_encode(reg->encoding());
1093 emit_byte(0x0F);
1094 emit_byte(0xC8 | encode);
1095 }
1220 movl(rax, adr);
1221 if (reg != rax) {
1222 Label L ;
1223 jcc(Assembler::notEqual, L);
1224 movl(adr, reg);
1225 bind(L);
1226 }
1227 } else {
1228 InstructionMark im(this);
1229 prefix(adr, reg);
1230 emit_byte(0x0F);
1231 emit_byte(0xB1);
1232 emit_operand(reg, adr);
1233 }
1234 }
1235
1236 void Assembler::comisd(XMMRegister dst, Address src) {
1237 // NOTE: dbx seems to decode this as comiss even though the
1238 // 0x66 is there. Strangly ucomisd comes out correct
1239 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1240 InstructionMark im(this);
1241 simd_prefix(dst, src, VEX_SIMD_66);
1242 emit_byte(0x2F);
1243 emit_operand(dst, src);
1244 }
1245
1246 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1247 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1248 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1249 emit_byte(0x2F);
1250 emit_byte(0xC0 | encode);
1251 }
1252
1253 void Assembler::comiss(XMMRegister dst, Address src) {
1254 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1255 InstructionMark im(this);
1256 simd_prefix(dst, src, VEX_SIMD_NONE);
1257 emit_byte(0x2F);
1258 emit_operand(dst, src);
1259 }
1260
1261 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1262 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1263 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1264 emit_byte(0x2F);
1265 emit_byte(0xC0 | encode);
1266 }
1267
1268 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1269 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1270 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1271 emit_byte(0xE6);
1272 emit_byte(0xC0 | encode);
1273 }
1274
1275 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1277 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1278 emit_byte(0x5B);
1279 emit_byte(0xC0 | encode);
1280 }
1281
1282 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1283 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1284 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1285 emit_byte(0x5A);
1286 emit_byte(0xC0 | encode);
1287 }
1288
1289 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1290 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1291 InstructionMark im(this);
1292 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1293 emit_byte(0x5A);
1294 emit_operand(dst, src);
1295 }
1296
1297 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1298 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1299 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1300 emit_byte(0x2A);
1301 emit_byte(0xC0 | encode);
1302 }
1303
1304 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1305 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1306 InstructionMark im(this);
1307 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1308 emit_byte(0x2A);
1309 emit_operand(dst, src);
1310 }
1311
1312 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1313 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1314 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1315 emit_byte(0x2A);
1316 emit_byte(0xC0 | encode);
1317 }
1318
1319 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1320 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1321 InstructionMark im(this);
1322 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1323 emit_byte(0x2A);
1324 emit_operand(dst, src);
1325 }
1326
1327 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1328 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1329 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1330 emit_byte(0x5A);
1331 emit_byte(0xC0 | encode);
1332 }
1333
1334 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1335 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1336 InstructionMark im(this);
1337 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1338 emit_byte(0x5A);
1339 emit_operand(dst, src);
1340 }
1341
1342
1343 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1344 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1345 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1346 emit_byte(0x2C);
1347 emit_byte(0xC0 | encode);
1348 }
1349
1350 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1351 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1352 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1353 emit_byte(0x2C);
1354 emit_byte(0xC0 | encode);
1355 }
1356
1357 void Assembler::decl(Address dst) {
1358 // Don't use it directly. Use MacroAssembler::decrement() instead.
1359 InstructionMark im(this);
1360 prefix(dst);
1361 emit_byte(0xFF);
1362 emit_operand(rcx, dst);
1363 }
1364
1365 void Assembler::divsd(XMMRegister dst, Address src) {
1366 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1367 InstructionMark im(this);
1368 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1369 emit_byte(0x5E);
1370 emit_operand(dst, src);
1371 }
1372
1373 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1374 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1375 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1376 emit_byte(0x5E);
1377 emit_byte(0xC0 | encode);
1378 }
1379
1380 void Assembler::divss(XMMRegister dst, Address src) {
1381 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1382 InstructionMark im(this);
1383 simd_prefix(dst, dst, src, VEX_SIMD_F3);
1384 emit_byte(0x5E);
1385 emit_operand(dst, src);
1386 }
1387
1388 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1389 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1390 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1391 emit_byte(0x5E);
1392 emit_byte(0xC0 | encode);
1393 }
1394
1395 void Assembler::emms() {
1396 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1397 emit_byte(0x0F);
1398 emit_byte(0x77);
1399 }
1400
1401 void Assembler::hlt() {
1402 emit_byte(0xF4);
1403 }
1404
1405 void Assembler::idivl(Register src) {
1406 int encode = prefix_and_encode(src->encoding());
1407 emit_byte(0xF7);
1408 emit_byte(0xF8 | encode);
1409 }
1410
1411 void Assembler::divl(Register src) { // Unsigned
1412 int encode = prefix_and_encode(src->encoding());
1608 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1609 emit_byte(0x0F);
1610 emit_byte(0xBD);
1611 emit_byte(0xC0 | encode);
1612 }
1613
1614 // Emit mfence instruction
1615 void Assembler::mfence() {
1616 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1617 emit_byte( 0x0F );
1618 emit_byte( 0xAE );
1619 emit_byte( 0xF0 );
1620 }
1621
1622 void Assembler::mov(Register dst, Register src) {
1623 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1624 }
1625
1626 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1627 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1628 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1629 emit_byte(0x28);
1630 emit_byte(0xC0 | encode);
1631 }
1632
1633 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1634 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1635 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
1636 emit_byte(0x28);
1637 emit_byte(0xC0 | encode);
1638 }
1639
1640 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
1641 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1642 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE);
1643 emit_byte(0x16);
1644 emit_byte(0xC0 | encode);
1645 }
1646
1647 void Assembler::movb(Register dst, Address src) {
1648 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1649 InstructionMark im(this);
1650 prefix(src, dst, true);
1651 emit_byte(0x8A);
1652 emit_operand(dst, src);
1653 }
1654
1655
1656 void Assembler::movb(Address dst, int imm8) {
1657 InstructionMark im(this);
1686 }
1687
1688 void Assembler::movdl(XMMRegister dst, Address src) {
1689 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1690 InstructionMark im(this);
1691 simd_prefix(dst, src, VEX_SIMD_66);
1692 emit_byte(0x6E);
1693 emit_operand(dst, src);
1694 }
1695
1696 void Assembler::movdl(Address dst, XMMRegister src) {
1697 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1698 InstructionMark im(this);
1699 simd_prefix(dst, src, VEX_SIMD_66);
1700 emit_byte(0x7E);
1701 emit_operand(src, dst);
1702 }
1703
1704 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1705 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1706 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1707 emit_byte(0x6F);
1708 emit_byte(0xC0 | encode);
1709 }
1710
1711 void Assembler::movdqu(XMMRegister dst, Address src) {
1712 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1713 InstructionMark im(this);
1714 simd_prefix(dst, src, VEX_SIMD_F3);
1715 emit_byte(0x6F);
1716 emit_operand(dst, src);
1717 }
1718
1719 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1720 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1721 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1722 emit_byte(0x6F);
1723 emit_byte(0xC0 | encode);
1724 }
1725
1726 void Assembler::movdqu(Address dst, XMMRegister src) {
1727 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1728 InstructionMark im(this);
1729 simd_prefix(dst, src, VEX_SIMD_F3);
1730 emit_byte(0x7F);
1731 emit_operand(src, dst);
1732 }
1733
1734 // Move Unaligned 256bit Vector
1735 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
1736 assert(UseAVX, "");
1737 bool vector256 = true;
1738 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1739 emit_byte(0x6F);
1740 emit_byte(0xC0 | encode);
1741 }
1742
1743 void Assembler::vmovdqu(XMMRegister dst, Address src) {
1784 void Assembler::movl(Address dst, int32_t imm32) {
1785 InstructionMark im(this);
1786 prefix(dst);
1787 emit_byte(0xC7);
1788 emit_operand(rax, dst, 4);
1789 emit_long(imm32);
1790 }
1791
1792 void Assembler::movl(Address dst, Register src) {
1793 InstructionMark im(this);
1794 prefix(dst, src);
1795 emit_byte(0x89);
1796 emit_operand(src, dst);
1797 }
1798
1799 // New cpus require to use movsd and movss to avoid partial register stall
1800 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1801 // The selection is done in MacroAssembler::movdbl() and movflt().
1802 void Assembler::movlpd(XMMRegister dst, Address src) {
1803 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1804 InstructionMark im(this);
1805 simd_prefix(dst, dst, src, VEX_SIMD_66);
1806 emit_byte(0x12);
1807 emit_operand(dst, src);
1808 }
1809
1810 void Assembler::movq( MMXRegister dst, Address src ) {
1811 assert( VM_Version::supports_mmx(), "" );
1812 emit_byte(0x0F);
1813 emit_byte(0x6F);
1814 emit_operand(dst, src);
1815 }
1816
1817 void Assembler::movq( Address dst, MMXRegister src ) {
1818 assert( VM_Version::supports_mmx(), "" );
1819 emit_byte(0x0F);
1820 emit_byte(0x7F);
1821 // workaround gcc (3.2.1-7a) bug
1822 // In that version of gcc with only an emit_operand(MMX, Address)
1823 // gcc will tail jump and try and reverse the parameters completely
1824 // obliterating dst in the process. By having a version available
1825 // that doesn't need to swap the args at the tail jump the bug is
1826 // avoided.
1827 emit_operand(dst, src);
1844 }
1845
1846 void Assembler::movsbl(Register dst, Address src) { // movsxb
1847 InstructionMark im(this);
1848 prefix(src, dst);
1849 emit_byte(0x0F);
1850 emit_byte(0xBE);
1851 emit_operand(dst, src);
1852 }
1853
1854 void Assembler::movsbl(Register dst, Register src) { // movsxb
1855 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1856 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1857 emit_byte(0x0F);
1858 emit_byte(0xBE);
1859 emit_byte(0xC0 | encode);
1860 }
1861
1862 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1863 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1864 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1865 emit_byte(0x10);
1866 emit_byte(0xC0 | encode);
1867 }
1868
1869 void Assembler::movsd(XMMRegister dst, Address src) {
1870 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1871 InstructionMark im(this);
1872 simd_prefix(dst, src, VEX_SIMD_F2);
1873 emit_byte(0x10);
1874 emit_operand(dst, src);
1875 }
1876
1877 void Assembler::movsd(Address dst, XMMRegister src) {
1878 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1879 InstructionMark im(this);
1880 simd_prefix(dst, src, VEX_SIMD_F2);
1881 emit_byte(0x11);
1882 emit_operand(src, dst);
1883 }
1884
1885 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1886 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1887 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1888 emit_byte(0x10);
1889 emit_byte(0xC0 | encode);
1890 }
1891
1892 void Assembler::movss(XMMRegister dst, Address src) {
1893 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1894 InstructionMark im(this);
1895 simd_prefix(dst, src, VEX_SIMD_F3);
1896 emit_byte(0x10);
1897 emit_operand(dst, src);
1898 }
1899
1900 void Assembler::movss(Address dst, XMMRegister src) {
1901 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1902 InstructionMark im(this);
1903 simd_prefix(dst, src, VEX_SIMD_F3);
1904 emit_byte(0x11);
1905 emit_operand(src, dst);
1906 }
1907
1908 void Assembler::movswl(Register dst, Address src) { // movsxw
1909 InstructionMark im(this);
1910 prefix(src, dst);
1911 emit_byte(0x0F);
1912 emit_byte(0xBF);
1913 emit_operand(dst, src);
1914 }
1915
1916 void Assembler::movswl(Register dst, Register src) { // movsxw
1917 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1975 emit_byte(0x0F);
1976 emit_byte(0xB7);
1977 emit_byte(0xC0 | encode);
1978 }
1979
1980 void Assembler::mull(Address src) {
1981 InstructionMark im(this);
1982 prefix(src);
1983 emit_byte(0xF7);
1984 emit_operand(rsp, src);
1985 }
1986
1987 void Assembler::mull(Register src) {
1988 int encode = prefix_and_encode(src->encoding());
1989 emit_byte(0xF7);
1990 emit_byte(0xE0 | encode);
1991 }
1992
1993 void Assembler::mulsd(XMMRegister dst, Address src) {
1994 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1995 InstructionMark im(this);
1996 simd_prefix(dst, dst, src, VEX_SIMD_F2);
1997 emit_byte(0x59);
1998 emit_operand(dst, src);
1999 }
2000
2001 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2002 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2003 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
2004 emit_byte(0x59);
2005 emit_byte(0xC0 | encode);
2006 }
2007
2008 void Assembler::mulss(XMMRegister dst, Address src) {
2009 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2010 InstructionMark im(this);
2011 simd_prefix(dst, dst, src, VEX_SIMD_F3);
2012 emit_byte(0x59);
2013 emit_operand(dst, src);
2014 }
2015
2016 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2017 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2018 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
2019 emit_byte(0x59);
2020 emit_byte(0xC0 | encode);
2021 }
2022
2023 void Assembler::negl(Register dst) {
2024 int encode = prefix_and_encode(dst->encoding());
2025 emit_byte(0xF7);
2026 emit_byte(0xD8 | encode);
2027 }
2028
2029 void Assembler::nop(int i) {
2030 #ifdef ASSERT
2031 assert(i > 0, " ");
2032 // The fancy nops aren't currently recognized by debuggers making it a
2033 // pain to disassemble code while debugging. If asserts are on clearly
2034 // speed is not an issue so simply use the single byte traditional nop
2035 // to do alignment.
2036
2037 for (; i > 0 ; i--) emit_byte(0x90);
2038 return;
2039
2040 #endif // ASSERT
2289 void Assembler::orl(Register dst, int32_t imm32) {
2290 prefix(dst);
2291 emit_arith(0x81, 0xC8, dst, imm32);
2292 }
2293
2294 void Assembler::orl(Register dst, Address src) {
2295 InstructionMark im(this);
2296 prefix(src, dst);
2297 emit_byte(0x0B);
2298 emit_operand(dst, src);
2299 }
2300
2301 void Assembler::orl(Register dst, Register src) {
2302 (void) prefix_and_encode(dst->encoding(), src->encoding());
2303 emit_arith(0x0B, 0xC0, dst, src);
2304 }
2305
2306 void Assembler::packuswb(XMMRegister dst, Address src) {
2307 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2308 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2309 InstructionMark im(this);
2310 simd_prefix(dst, dst, src, VEX_SIMD_66);
2311 emit_byte(0x67);
2312 emit_operand(dst, src);
2313 }
2314
2315 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2316 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2317 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2318 emit_byte(0x67);
2319 emit_byte(0xC0 | encode);
2320 }
2321
2322 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2323 assert(VM_Version::supports_sse4_2(), "");
2324 InstructionMark im(this);
2325 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2326 emit_byte(0x61);
2327 emit_operand(dst, src);
2328 emit_byte(imm8);
2329 }
2330
2331 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2332 assert(VM_Version::supports_sse4_2(), "");
2333 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2334 emit_byte(0x61);
2335 emit_byte(0xC0 | encode);
2336 emit_byte(imm8);
2337 }
2338
2339 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2340 assert(VM_Version::supports_sse4_1(), "");
2341 InstructionMark im(this);
2342 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2343 emit_byte(0x30);
2344 emit_operand(dst, src);
2345 }
2346
2347 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2348 assert(VM_Version::supports_sse4_1(), "");
2349 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2350 emit_byte(0x30);
2351 emit_byte(0xC0 | encode);
2352 }
2353
2354 // generic
2355 void Assembler::pop(Register dst) {
2356 int encode = prefix_and_encode(dst->encoding());
2357 emit_byte(0x58 | encode);
2358 }
2359
2360 void Assembler::popcntl(Register dst, Address src) {
2361 assert(VM_Version::supports_popcnt(), "must support");
2362 InstructionMark im(this);
2363 emit_byte(0xF3);
2364 prefix(src, dst);
2365 emit_byte(0x0F);
2366 emit_byte(0xB8);
2367 emit_operand(dst, src);
2368 }
2369
2430 void Assembler::prefetcht2(Address src) {
2431 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2432 InstructionMark im(this);
2433 prefetch_prefix(src);
2434 emit_byte(0x18);
2435 emit_operand(rbx, src); // 3, src
2436 }
2437
2438 void Assembler::prefetchw(Address src) {
2439 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2440 InstructionMark im(this);
2441 prefetch_prefix(src);
2442 emit_byte(0x0D);
2443 emit_operand(rcx, src); // 1, src
2444 }
2445
2446 void Assembler::prefix(Prefix p) {
2447 a_byte(p);
2448 }
2449
2450 void Assembler::por(XMMRegister dst, XMMRegister src) {
2451 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2452 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2453 emit_byte(0xEB);
2454 emit_byte(0xC0 | encode);
2455 }
2456
2457 void Assembler::por(XMMRegister dst, Address src) {
2458 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2459 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2460 InstructionMark im(this);
2461 simd_prefix(dst, dst, src, VEX_SIMD_66);
2462 emit_byte(0xEB);
2463 emit_operand(dst, src);
2464 }
2465
2466 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2467 assert(isByte(mode), "invalid value");
2468 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2469 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
2470 emit_byte(0x70);
2471 emit_byte(0xC0 | encode);
2472 emit_byte(mode & 0xFF);
2473
2474 }
2475
2476 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2477 assert(isByte(mode), "invalid value");
2478 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2479 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2480 InstructionMark im(this);
2481 simd_prefix(dst, src, VEX_SIMD_66);
2482 emit_byte(0x70);
2483 emit_operand(dst, src);
2484 emit_byte(mode & 0xFF);
2485 }
2486
2487 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2488 assert(isByte(mode), "invalid value");
2489 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2490 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
2491 emit_byte(0x70);
2492 emit_byte(0xC0 | encode);
2493 emit_byte(mode & 0xFF);
2494 }
2495
2496 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2497 assert(isByte(mode), "invalid value");
2498 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2499 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2500 InstructionMark im(this);
2501 simd_prefix(dst, src, VEX_SIMD_F2);
2502 emit_byte(0x70);
2503 emit_operand(dst, src);
2504 emit_byte(mode & 0xFF);
2505 }
2506
2507 void Assembler::psrlq(XMMRegister dst, int shift) {
2508 // Shift 64 bit value logically right by specified number of bits.
2509 // HMM Table D-1 says sse2 or mmx.
2510 // Do not confuse it with psrldq SSE2 instruction which
2511 // shifts 128 bit value in xmm register by number of bytes.
2512 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2513 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
2514 emit_byte(0x73);
2515 emit_byte(0xC0 | encode);
2516 emit_byte(shift);
2517 }
2518
2519 void Assembler::psrldq(XMMRegister dst, int shift) {
2520 // Shift 128 bit value in xmm register by number of bytes.
2521 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2522 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
2523 emit_byte(0x73);
2524 emit_byte(0xC0 | encode);
2525 emit_byte(shift);
2526 }
2527
2528 void Assembler::ptest(XMMRegister dst, Address src) {
2529 assert(VM_Version::supports_sse4_1(), "");
2530 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2531 InstructionMark im(this);
2532 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2533 emit_byte(0x17);
2534 emit_operand(dst, src);
2535 }
2536
2537 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2538 assert(VM_Version::supports_sse4_1(), "");
2539 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2540 emit_byte(0x17);
2541 emit_byte(0xC0 | encode);
2542 }
2543
2544 void Assembler::punpcklbw(XMMRegister dst, Address src) {
2545 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2546 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2547 InstructionMark im(this);
2548 simd_prefix(dst, dst, src, VEX_SIMD_66);
2549 emit_byte(0x60);
2550 emit_operand(dst, src);
2551 }
2552
2553 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2554 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2555 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2556 emit_byte(0x60);
2557 emit_byte(0xC0 | encode);
2558 }
2559
2560 void Assembler::punpckldq(XMMRegister dst, Address src) {
2561 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2562 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2563 InstructionMark im(this);
2564 simd_prefix(dst, dst, src, VEX_SIMD_66);
2565 emit_byte(0x62);
2566 emit_operand(dst, src);
2567 }
2568
2569 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2570 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2571 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2572 emit_byte(0x62);
2573 emit_byte(0xC0 | encode);
2574 }
2575
2576 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
2577 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2578 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2579 emit_byte(0x6C);
2580 emit_byte(0xC0 | encode);
2581 }
2582
2583 void Assembler::push(int32_t imm32) {
2584 // in 64bits we push 64bits onto the stack but only
2585 // take a 32bit immediate
2586 emit_byte(0x68);
2587 emit_long(imm32);
2588 }
2589
2590 void Assembler::push(Register src) {
2591 int encode = prefix_and_encode(src->encoding());
2592
2593 emit_byte(0x50 | encode);
2594 }
2595
2596 void Assembler::pushf() {
2597 emit_byte(0x9C);
2598 }
2599
2600 #ifndef _LP64 // no 32bit push/pop on amd64
2601 void Assembler::pushl(Address src) {
2602 // Note this will push 64bit on 64bit
2603 InstructionMark im(this);
2604 prefix(src);
2605 emit_byte(0xFF);
2606 emit_operand(rsi, src);
2607 }
2608 #endif
2609
2610 void Assembler::pxor(XMMRegister dst, Address src) {
2611 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2612 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2613 InstructionMark im(this);
2614 simd_prefix(dst, dst, src, VEX_SIMD_66);
2615 emit_byte(0xEF);
2616 emit_operand(dst, src);
2617 }
2618
2619 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2620 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2621 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2622 emit_byte(0xEF);
2623 emit_byte(0xC0 | encode);
2624 }
2625
2626 void Assembler::rcll(Register dst, int imm8) {
2627 assert(isShiftCount(imm8), "illegal shift count");
2628 int encode = prefix_and_encode(dst->encoding());
2629 if (imm8 == 1) {
2630 emit_byte(0xD1);
2631 emit_byte(0xD0 | encode);
2632 } else {
2633 emit_byte(0xC1);
2634 emit_byte(0xD0 | encode);
2635 emit_byte(imm8);
2636 }
2637 }
2638
2639 // copies data from [esi] to [edi] using rcx pointer sized words
2640 // generic
2641 void Assembler::rep_mov() {
2642 emit_byte(0xF3);
2643 // MOVSQ
2644 LP64_ONLY(prefix(REX_W));
2645 emit_byte(0xA5);
2764 assert(isShiftCount(imm8), "illegal shift count");
2765 int encode = prefix_and_encode(dst->encoding());
2766 emit_byte(0xC1);
2767 emit_byte(0xE8 | encode);
2768 emit_byte(imm8);
2769 }
2770
2771 void Assembler::shrl(Register dst) {
2772 int encode = prefix_and_encode(dst->encoding());
2773 emit_byte(0xD3);
2774 emit_byte(0xE8 | encode);
2775 }
2776
2777 // copies a single word from [esi] to [edi]
2778 void Assembler::smovl() {
2779 emit_byte(0xA5);
2780 }
2781
2782 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2783 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2784 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
2785 emit_byte(0x51);
2786 emit_byte(0xC0 | encode);
2787 }
2788
2789 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2790 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2791 InstructionMark im(this);
2792 simd_prefix(dst, dst, src, VEX_SIMD_F2);
2793 emit_byte(0x51);
2794 emit_operand(dst, src);
2795 }
2796
2797 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2798 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2799 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
2800 emit_byte(0x51);
2801 emit_byte(0xC0 | encode);
2802 }
2803
2804 void Assembler::sqrtss(XMMRegister dst, Address src) {
2805 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2806 InstructionMark im(this);
2807 simd_prefix(dst, dst, src, VEX_SIMD_F3);
2808 emit_byte(0x51);
2809 emit_operand(dst, src);
2810 }
2811
2812 void Assembler::stmxcsr( Address dst) {
2813 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2814 InstructionMark im(this);
2815 prefix(dst);
2816 emit_byte(0x0F);
2817 emit_byte(0xAE);
2818 emit_operand(as_Register(3), dst);
2819 }
2820
2821 void Assembler::subl(Address dst, int32_t imm32) {
2822 InstructionMark im(this);
2823 prefix(dst);
2824 emit_arith_operand(0x81, rbp, dst, imm32);
2825 }
2826
2827 void Assembler::subl(Address dst, Register src) {
2828 InstructionMark im(this);
2829 prefix(dst, src);
2839 // Force generation of a 4 byte immediate value even if it fits into 8bit
2840 void Assembler::subl_imm32(Register dst, int32_t imm32) {
2841 prefix(dst);
2842 emit_arith_imm32(0x81, 0xE8, dst, imm32);
2843 }
2844
2845 void Assembler::subl(Register dst, Address src) {
2846 InstructionMark im(this);
2847 prefix(src, dst);
2848 emit_byte(0x2B);
2849 emit_operand(dst, src);
2850 }
2851
2852 void Assembler::subl(Register dst, Register src) {
2853 (void) prefix_and_encode(dst->encoding(), src->encoding());
2854 emit_arith(0x2B, 0xC0, dst, src);
2855 }
2856
2857 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2858 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2859 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
2860 emit_byte(0x5C);
2861 emit_byte(0xC0 | encode);
2862 }
2863
2864 void Assembler::subsd(XMMRegister dst, Address src) {
2865 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2866 InstructionMark im(this);
2867 simd_prefix(dst, dst, src, VEX_SIMD_F2);
2868 emit_byte(0x5C);
2869 emit_operand(dst, src);
2870 }
2871
2872 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2873 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2874 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
2875 emit_byte(0x5C);
2876 emit_byte(0xC0 | encode);
2877 }
2878
2879 void Assembler::subss(XMMRegister dst, Address src) {
2880 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2881 InstructionMark im(this);
2882 simd_prefix(dst, dst, src, VEX_SIMD_F3);
2883 emit_byte(0x5C);
2884 emit_operand(dst, src);
2885 }
2886
2887 void Assembler::testb(Register dst, int imm8) {
2888 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2889 (void) prefix_and_encode(dst->encoding(), true);
2890 emit_arith_b(0xF6, 0xC0, dst, imm8);
2891 }
2892
2893 void Assembler::testl(Register dst, int32_t imm32) {
2894 // not using emit_arith because test
2895 // doesn't support sign-extension of
2896 // 8bit operands
2897 int encode = dst->encoding();
2898 if (encode == 0) {
2899 emit_byte(0xA9);
2900 } else {
2901 encode = prefix_and_encode(encode);
2902 emit_byte(0xF7);
2903 emit_byte(0xC0 | encode);
2904 }
2905 emit_long(imm32);
2906 }
2907
2908 void Assembler::testl(Register dst, Register src) {
2909 (void) prefix_and_encode(dst->encoding(), src->encoding());
2910 emit_arith(0x85, 0xC0, dst, src);
2911 }
2912
2913 void Assembler::testl(Register dst, Address src) {
2914 InstructionMark im(this);
2915 prefix(src, dst);
2916 emit_byte(0x85);
2917 emit_operand(dst, src);
2918 }
2919
2920 void Assembler::ucomisd(XMMRegister dst, Address src) {
2921 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2922 InstructionMark im(this);
2923 simd_prefix(dst, src, VEX_SIMD_66);
2924 emit_byte(0x2E);
2925 emit_operand(dst, src);
2926 }
2927
2928 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2929 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2930 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
2931 emit_byte(0x2E);
2932 emit_byte(0xC0 | encode);
2933 }
2934
2935 void Assembler::ucomiss(XMMRegister dst, Address src) {
2936 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2937 InstructionMark im(this);
2938 simd_prefix(dst, src, VEX_SIMD_NONE);
2939 emit_byte(0x2E);
2940 emit_operand(dst, src);
2941 }
2942
2943 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2944 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2945 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_NONE);
2946 emit_byte(0x2E);
2947 emit_byte(0xC0 | encode);
2948 }
2949
2950
2951 void Assembler::xaddl(Address dst, Register src) {
2952 InstructionMark im(this);
2953 prefix(dst, src);
2954 emit_byte(0x0F);
2955 emit_byte(0xC1);
2956 emit_operand(src, dst);
2957 }
2958
2959 void Assembler::xchgl(Register dst, Address src) { // xchg
2960 InstructionMark im(this);
2961 prefix(src, dst);
2962 emit_byte(0x87);
2963 emit_operand(dst, src);
2964 }
2965
2966 void Assembler::xchgl(Register dst, Register src) {
2967 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2969 emit_byte(0xc0 | encode);
2970 }
2971
2972 void Assembler::xorl(Register dst, int32_t imm32) {
2973 prefix(dst);
2974 emit_arith(0x81, 0xF0, dst, imm32);
2975 }
2976
2977 void Assembler::xorl(Register dst, Address src) {
2978 InstructionMark im(this);
2979 prefix(src, dst);
2980 emit_byte(0x33);
2981 emit_operand(dst, src);
2982 }
2983
2984 void Assembler::xorl(Register dst, Register src) {
2985 (void) prefix_and_encode(dst->encoding(), src->encoding());
2986 emit_arith(0x33, 0xC0, dst, src);
2987 }
2988
2989 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2990 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2991 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66);
2992 emit_byte(0x57);
2993 emit_byte(0xC0 | encode);
2994 }
2995
2996 void Assembler::xorpd(XMMRegister dst, Address src) {
2997 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2998 InstructionMark im(this);
2999 simd_prefix(dst, dst, src, VEX_SIMD_66);
3000 emit_byte(0x57);
3001 emit_operand(dst, src);
3002 }
3003
3004
3005 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
3006 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3007 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE);
3008 emit_byte(0x57);
3009 emit_byte(0xC0 | encode);
3010 }
3011
3012 void Assembler::xorps(XMMRegister dst, Address src) {
3013 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3014 InstructionMark im(this);
3015 simd_prefix(dst, dst, src, VEX_SIMD_NONE);
3016 emit_byte(0x57);
3017 emit_operand(dst, src);
3018 }
3019
3020 // AVX 3-operands non destructive source instructions (encoded with VEX prefix)
3021
3022 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3023 assert(VM_Version::supports_avx(), "");
3024 InstructionMark im(this);
3025 vex_prefix(dst, nds, src, VEX_SIMD_F2);
3026 emit_byte(0x58);
3027 emit_operand(dst, src);
3028 }
3029
3030 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3031 assert(VM_Version::supports_avx(), "");
3032 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
3033 emit_byte(0x58);
3034 emit_byte(0xC0 | encode);
3035 }
3036
3037 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3038 assert(VM_Version::supports_avx(), "");
3039 InstructionMark im(this);
3040 vex_prefix(dst, nds, src, VEX_SIMD_F3);
3041 emit_byte(0x58);
3042 emit_operand(dst, src);
3043 }
3044
3045 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3046 assert(VM_Version::supports_avx(), "");
3047 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
3048 emit_byte(0x58);
3049 emit_byte(0xC0 | encode);
3050 }
3051
3052 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src) {
3053 assert(VM_Version::supports_avx(), "");
3054 InstructionMark im(this);
3055 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector
3056 emit_byte(0x54);
3057 emit_operand(dst, src);
3058 }
3059
3060 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src) {
3061 assert(VM_Version::supports_avx(), "");
3062 InstructionMark im(this);
3063 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector
3064 emit_byte(0x54);
3065 emit_operand(dst, src);
3066 }
3067
3068 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3069 assert(VM_Version::supports_avx(), "");
3070 InstructionMark im(this);
3071 vex_prefix(dst, nds, src, VEX_SIMD_F2);
3072 emit_byte(0x5E);
3073 emit_operand(dst, src);
3074 }
3075
3076 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3077 assert(VM_Version::supports_avx(), "");
3078 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
3079 emit_byte(0x5E);
3080 emit_byte(0xC0 | encode);
3081 }
3082
3083 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3084 assert(VM_Version::supports_avx(), "");
3085 InstructionMark im(this);
3086 vex_prefix(dst, nds, src, VEX_SIMD_F3);
3087 emit_byte(0x5E);
3088 emit_operand(dst, src);
3089 }
3090
3091 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3092 assert(VM_Version::supports_avx(), "");
3093 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
3094 emit_byte(0x5E);
3095 emit_byte(0xC0 | encode);
3096 }
3097
3098 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3099 assert(VM_Version::supports_avx(), "");
3100 InstructionMark im(this);
3101 vex_prefix(dst, nds, src, VEX_SIMD_F2);
3102 emit_byte(0x59);
3103 emit_operand(dst, src);
3104 }
3105
3106 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3107 assert(VM_Version::supports_avx(), "");
3108 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
3109 emit_byte(0x59);
3110 emit_byte(0xC0 | encode);
3111 }
3112
3113 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3114 InstructionMark im(this);
3115 vex_prefix(dst, nds, src, VEX_SIMD_F3);
3116 emit_byte(0x59);
3117 emit_operand(dst, src);
3118 }
3119
3120 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3121 assert(VM_Version::supports_avx(), "");
3122 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
3123 emit_byte(0x59);
3124 emit_byte(0xC0 | encode);
3125 }
3126
3127
3128 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3129 assert(VM_Version::supports_avx(), "");
3130 InstructionMark im(this);
3131 vex_prefix(dst, nds, src, VEX_SIMD_F2);
3132 emit_byte(0x5C);
3133 emit_operand(dst, src);
3134 }
3135
3136 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3137 assert(VM_Version::supports_avx(), "");
3138 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F2);
3139 emit_byte(0x5C);
3140 emit_byte(0xC0 | encode);
3141 }
3142
3143 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3144 assert(VM_Version::supports_avx(), "");
3145 InstructionMark im(this);
3146 vex_prefix(dst, nds, src, VEX_SIMD_F3);
3147 emit_byte(0x5C);
3148 emit_operand(dst, src);
3149 }
3150
3151 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3152 assert(VM_Version::supports_avx(), "");
3153 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_F3);
3154 emit_byte(0x5C);
3155 emit_byte(0xC0 | encode);
3156 }
3157
3158 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src) {
3159 assert(VM_Version::supports_avx(), "");
3160 InstructionMark im(this);
3161 vex_prefix(dst, nds, src, VEX_SIMD_66); // 128-bit vector
3162 emit_byte(0x57);
3163 emit_operand(dst, src);
3164 }
3165
3166 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3167 assert(VM_Version::supports_avx(), "");
3168 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256);
3169 emit_byte(0x57);
3170 emit_byte(0xC0 | encode);
3171 }
3172
3173 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src) {
3174 assert(VM_Version::supports_avx(), "");
3175 InstructionMark im(this);
3176 vex_prefix(dst, nds, src, VEX_SIMD_NONE); // 128-bit vector
3177 emit_byte(0x57);
3178 emit_operand(dst, src);
3179 }
3180
3181 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3182 assert(VM_Version::supports_avx(), "");
3183 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, vector256);
3184 emit_byte(0x57);
3185 emit_byte(0xC0 | encode);
3186 }
3187
3188 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3189 assert(VM_Version::supports_avx2() || (!vector256) && VM_Version::supports_avx(), "");
3190 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256);
3191 emit_byte(0xEF);
3192 emit_byte(0xC0 | encode);
3193 }
3194
3195 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3196 assert(VM_Version::supports_avx(), "");
3197 bool vector256 = true;
3198 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3199 emit_byte(0x18);
3200 emit_byte(0xC0 | encode);
3201 // 0x00 - insert into lower 128 bits
3202 // 0x01 - insert into upper 128 bits
3203 emit_byte(0x01);
3204 }
3205
3206 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3207 assert(VM_Version::supports_avx2(), "");
3208 bool vector256 = true;
3209 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3210 emit_byte(0x38);
3211 emit_byte(0xC0 | encode);
3212 // 0x00 - insert into lower 128 bits
3213 // 0x01 - insert into upper 128 bits
3214 emit_byte(0x01);
3779 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3780 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
3781 } else {
3782 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
3783 rex_prefix(adr, xreg, pre, opc, rex_w);
3784 }
3785 }
3786
3787 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
3788 int dst_enc = dst->encoding();
3789 int src_enc = src->encoding();
3790 if (UseAVX > 0) {
3791 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3792 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
3793 } else {
3794 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
3795 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
3796 }
3797 }
3798
3799 #ifndef _LP64
3800
3801 void Assembler::incl(Register dst) {
3802 // Don't use it directly. Use MacroAssembler::incrementl() instead.
3803 emit_byte(0x40 | dst->encoding());
3804 }
3805
3806 void Assembler::lea(Register dst, Address src) {
3807 leal(dst, src);
3808 }
3809
3810 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
3811 InstructionMark im(this);
3812 emit_byte(0xC7);
3813 emit_operand(rax, dst);
3814 emit_data((int)imm32, rspec, 0);
3815 }
3816
3817 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
3818 InstructionMark im(this);
7859 // AVX 3-operands instructions
7860
7861 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7862 if (reachable(src)) {
7863 vaddsd(dst, nds, as_Address(src));
7864 } else {
7865 lea(rscratch1, src);
7866 vaddsd(dst, nds, Address(rscratch1, 0));
7867 }
7868 }
7869
7870 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7871 if (reachable(src)) {
7872 vaddss(dst, nds, as_Address(src));
7873 } else {
7874 lea(rscratch1, src);
7875 vaddss(dst, nds, Address(rscratch1, 0));
7876 }
7877 }
7878
7879 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7880 if (reachable(src)) {
7881 vandpd(dst, nds, as_Address(src));
7882 } else {
7883 lea(rscratch1, src);
7884 vandpd(dst, nds, Address(rscratch1, 0));
7885 }
7886 }
7887
7888 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7889 if (reachable(src)) {
7890 vandps(dst, nds, as_Address(src));
7891 } else {
7892 lea(rscratch1, src);
7893 vandps(dst, nds, Address(rscratch1, 0));
7894 }
7895 }
7896
7897 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7898 if (reachable(src)) {
7899 vdivsd(dst, nds, as_Address(src));
7900 } else {
7901 lea(rscratch1, src);
7902 vdivsd(dst, nds, Address(rscratch1, 0));
7903 }
7904 }
7905
7906 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7907 if (reachable(src)) {
7908 vdivss(dst, nds, as_Address(src));
7909 } else {
7910 lea(rscratch1, src);
7911 vdivss(dst, nds, Address(rscratch1, 0));
7912 }
7913 }
7931 }
7932
7933 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7934 if (reachable(src)) {
7935 vsubsd(dst, nds, as_Address(src));
7936 } else {
7937 lea(rscratch1, src);
7938 vsubsd(dst, nds, Address(rscratch1, 0));
7939 }
7940 }
7941
7942 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7943 if (reachable(src)) {
7944 vsubss(dst, nds, as_Address(src));
7945 } else {
7946 lea(rscratch1, src);
7947 vsubss(dst, nds, Address(rscratch1, 0));
7948 }
7949 }
7950
7951 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7952 if (reachable(src)) {
7953 vxorpd(dst, nds, as_Address(src));
7954 } else {
7955 lea(rscratch1, src);
7956 vxorpd(dst, nds, Address(rscratch1, 0));
7957 }
7958 }
7959
7960 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
7961 if (reachable(src)) {
7962 vxorps(dst, nds, as_Address(src));
7963 } else {
7964 lea(rscratch1, src);
7965 vxorps(dst, nds, Address(rscratch1, 0));
7966 }
7967 }
7968
7969
7970 //////////////////////////////////////////////////////////////////////////////////
7971 #ifndef SERIALGC
7972
7973 void MacroAssembler::g1_write_barrier_pre(Register obj,
7974 Register pre_val,
7975 Register thread,
7976 Register tmp,
7977 bool tosca_live,
7978 bool expand_call) {
7979
7980 // If expand_call is true then we expand the call_VM_leaf macro
7981 // directly to skip generating the check by
7982 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
7983
7984 #ifdef _LP64
7985 assert(thread == r15_thread, "must be");
|
973 assert(UseAddressNop, "no CPU support");
974 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
975 emit_byte(0x0F);
976 emit_byte(0x1F);
977 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
978 emit_long(0); // 32-bits offset (4 bytes)
979 }
980
981 void Assembler::addr_nop_8() {
982 assert(UseAddressNop, "no CPU support");
983 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
984 emit_byte(0x0F);
985 emit_byte(0x1F);
986 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
987 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
988 emit_long(0); // 32-bits offset (4 bytes)
989 }
990
991 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
992 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
993 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
994 }
995
996 void Assembler::addsd(XMMRegister dst, Address src) {
997 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
998 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
999 }
1000
1001 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1002 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1003 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1004 }
1005
1006 void Assembler::addss(XMMRegister dst, Address src) {
1007 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1008 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1009 }
1010
1011 void Assembler::andl(Address dst, int32_t imm32) {
1012 InstructionMark im(this);
1013 prefix(dst);
1014 emit_byte(0x81);
1015 emit_operand(rsp, dst, 4);
1016 emit_long(imm32);
1017 }
1018
1019 void Assembler::andl(Register dst, int32_t imm32) {
1020 prefix(dst);
1021 emit_arith(0x81, 0xE0, dst, imm32);
1022 }
1023
1024 void Assembler::andl(Register dst, Address src) {
1025 InstructionMark im(this);
1026 prefix(src, dst);
1027 emit_byte(0x23);
1028 emit_operand(dst, src);
1029 }
1030
1031 void Assembler::andl(Register dst, Register src) {
1032 (void) prefix_and_encode(dst->encoding(), src->encoding());
1033 emit_arith(0x23, 0xC0, dst, src);
1034 }
1035
1036 void Assembler::bsfl(Register dst, Register src) {
1037 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1038 emit_byte(0x0F);
1039 emit_byte(0xBC);
1040 emit_byte(0xC0 | encode);
1041 }
1042
1043 void Assembler::bsrl(Register dst, Register src) {
1044 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT");
1045 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1046 emit_byte(0x0F);
1047 emit_byte(0xBD);
1048 emit_byte(0xC0 | encode);
1049 }
1050
1051 void Assembler::bswapl(Register reg) { // bswap
1052 int encode = prefix_and_encode(reg->encoding());
1053 emit_byte(0x0F);
1054 emit_byte(0xC8 | encode);
1055 }
1180 movl(rax, adr);
1181 if (reg != rax) {
1182 Label L ;
1183 jcc(Assembler::notEqual, L);
1184 movl(adr, reg);
1185 bind(L);
1186 }
1187 } else {
1188 InstructionMark im(this);
1189 prefix(adr, reg);
1190 emit_byte(0x0F);
1191 emit_byte(0xB1);
1192 emit_operand(reg, adr);
1193 }
1194 }
1195
1196 void Assembler::comisd(XMMRegister dst, Address src) {
1197 // NOTE: dbx seems to decode this as comiss even though the
1198 // 0x66 is there. Strangly ucomisd comes out correct
1199 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1200 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1201 }
1202
1203 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1204 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1205 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1206 }
1207
1208 void Assembler::comiss(XMMRegister dst, Address src) {
1209 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1210 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1211 }
1212
1213 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1214 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1215 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1216 }
1217
1218 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1219 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1220 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1221 }
1222
1223 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1224 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1225 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1226 }
1227
1228 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1229 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1230 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1231 }
1232
1233 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1234 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1235 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1236 }
1237
1238 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1239 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1240 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1241 emit_byte(0x2A);
1242 emit_byte(0xC0 | encode);
1243 }
1244
1245 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1246 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1247 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1248 }
1249
1250 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1251 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1252 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1253 emit_byte(0x2A);
1254 emit_byte(0xC0 | encode);
1255 }
1256
1257 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1258 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1259 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3);
1260 }
1261
1262 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1263 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1264 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1265 }
1266
1267 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1268 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1269 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1270 }
1271
1272
1273 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1274 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1275 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1276 emit_byte(0x2C);
1277 emit_byte(0xC0 | encode);
1278 }
1279
1280 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1281 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1282 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1283 emit_byte(0x2C);
1284 emit_byte(0xC0 | encode);
1285 }
1286
1287 void Assembler::decl(Address dst) {
1288 // Don't use it directly. Use MacroAssembler::decrement() instead.
1289 InstructionMark im(this);
1290 prefix(dst);
1291 emit_byte(0xFF);
1292 emit_operand(rcx, dst);
1293 }
1294
1295 void Assembler::divsd(XMMRegister dst, Address src) {
1296 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1297 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1298 }
1299
1300 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1301 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1302 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1303 }
1304
1305 void Assembler::divss(XMMRegister dst, Address src) {
1306 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1307 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1308 }
1309
1310 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1311 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1312 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1313 }
1314
1315 void Assembler::emms() {
1316 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1317 emit_byte(0x0F);
1318 emit_byte(0x77);
1319 }
1320
1321 void Assembler::hlt() {
1322 emit_byte(0xF4);
1323 }
1324
1325 void Assembler::idivl(Register src) {
1326 int encode = prefix_and_encode(src->encoding());
1327 emit_byte(0xF7);
1328 emit_byte(0xF8 | encode);
1329 }
1330
1331 void Assembler::divl(Register src) { // Unsigned
1332 int encode = prefix_and_encode(src->encoding());
1528 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1529 emit_byte(0x0F);
1530 emit_byte(0xBD);
1531 emit_byte(0xC0 | encode);
1532 }
1533
1534 // Emit mfence instruction
1535 void Assembler::mfence() {
1536 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1537 emit_byte( 0x0F );
1538 emit_byte( 0xAE );
1539 emit_byte( 0xF0 );
1540 }
1541
1542 void Assembler::mov(Register dst, Register src) {
1543 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1544 }
1545
1546 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1547 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1548 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
1549 }
1550
1551 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1552 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1553 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
1554 }
1555
1556 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
1557 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1558 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE);
1559 emit_byte(0x16);
1560 emit_byte(0xC0 | encode);
1561 }
1562
1563 void Assembler::movb(Register dst, Address src) {
1564 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1565 InstructionMark im(this);
1566 prefix(src, dst, true);
1567 emit_byte(0x8A);
1568 emit_operand(dst, src);
1569 }
1570
1571
1572 void Assembler::movb(Address dst, int imm8) {
1573 InstructionMark im(this);
1602 }
1603
1604 void Assembler::movdl(XMMRegister dst, Address src) {
1605 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1606 InstructionMark im(this);
1607 simd_prefix(dst, src, VEX_SIMD_66);
1608 emit_byte(0x6E);
1609 emit_operand(dst, src);
1610 }
1611
1612 void Assembler::movdl(Address dst, XMMRegister src) {
1613 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1614 InstructionMark im(this);
1615 simd_prefix(dst, src, VEX_SIMD_66);
1616 emit_byte(0x7E);
1617 emit_operand(src, dst);
1618 }
1619
1620 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1621 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1622 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1623 }
1624
1625 void Assembler::movdqu(XMMRegister dst, Address src) {
1626 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1627 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1628 }
1629
1630 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1631 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1632 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1633 }
1634
1635 void Assembler::movdqu(Address dst, XMMRegister src) {
1636 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1637 InstructionMark im(this);
1638 simd_prefix(dst, src, VEX_SIMD_F3);
1639 emit_byte(0x7F);
1640 emit_operand(src, dst);
1641 }
1642
1643 // Move Unaligned 256bit Vector
1644 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
1645 assert(UseAVX, "");
1646 bool vector256 = true;
1647 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1648 emit_byte(0x6F);
1649 emit_byte(0xC0 | encode);
1650 }
1651
1652 void Assembler::vmovdqu(XMMRegister dst, Address src) {
1693 void Assembler::movl(Address dst, int32_t imm32) {
1694 InstructionMark im(this);
1695 prefix(dst);
1696 emit_byte(0xC7);
1697 emit_operand(rax, dst, 4);
1698 emit_long(imm32);
1699 }
1700
1701 void Assembler::movl(Address dst, Register src) {
1702 InstructionMark im(this);
1703 prefix(dst, src);
1704 emit_byte(0x89);
1705 emit_operand(src, dst);
1706 }
1707
1708 // New cpus require to use movsd and movss to avoid partial register stall
1709 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1710 // The selection is done in MacroAssembler::movdbl() and movflt().
1711 void Assembler::movlpd(XMMRegister dst, Address src) {
1712 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1713 emit_simd_arith(0x12, dst, src, VEX_SIMD_66);
1714 }
1715
1716 void Assembler::movq( MMXRegister dst, Address src ) {
1717 assert( VM_Version::supports_mmx(), "" );
1718 emit_byte(0x0F);
1719 emit_byte(0x6F);
1720 emit_operand(dst, src);
1721 }
1722
1723 void Assembler::movq( Address dst, MMXRegister src ) {
1724 assert( VM_Version::supports_mmx(), "" );
1725 emit_byte(0x0F);
1726 emit_byte(0x7F);
1727 // workaround gcc (3.2.1-7a) bug
1728 // In that version of gcc with only an emit_operand(MMX, Address)
1729 // gcc will tail jump and try and reverse the parameters completely
1730 // obliterating dst in the process. By having a version available
1731 // that doesn't need to swap the args at the tail jump the bug is
1732 // avoided.
1733 emit_operand(dst, src);
1750 }
1751
1752 void Assembler::movsbl(Register dst, Address src) { // movsxb
1753 InstructionMark im(this);
1754 prefix(src, dst);
1755 emit_byte(0x0F);
1756 emit_byte(0xBE);
1757 emit_operand(dst, src);
1758 }
1759
1760 void Assembler::movsbl(Register dst, Register src) { // movsxb
1761 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1762 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1763 emit_byte(0x0F);
1764 emit_byte(0xBE);
1765 emit_byte(0xC0 | encode);
1766 }
1767
1768 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1769 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1770 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
1771 }
1772
1773 void Assembler::movsd(XMMRegister dst, Address src) {
1774 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1775 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
1776 }
1777
1778 void Assembler::movsd(Address dst, XMMRegister src) {
1779 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1780 InstructionMark im(this);
1781 simd_prefix(dst, src, VEX_SIMD_F2);
1782 emit_byte(0x11);
1783 emit_operand(src, dst);
1784 }
1785
1786 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1787 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1788 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3);
1789 }
1790
1791 void Assembler::movss(XMMRegister dst, Address src) {
1792 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1793 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3);
1794 }
1795
1796 void Assembler::movss(Address dst, XMMRegister src) {
1797 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1798 InstructionMark im(this);
1799 simd_prefix(dst, src, VEX_SIMD_F3);
1800 emit_byte(0x11);
1801 emit_operand(src, dst);
1802 }
1803
1804 void Assembler::movswl(Register dst, Address src) { // movsxw
1805 InstructionMark im(this);
1806 prefix(src, dst);
1807 emit_byte(0x0F);
1808 emit_byte(0xBF);
1809 emit_operand(dst, src);
1810 }
1811
1812 void Assembler::movswl(Register dst, Register src) { // movsxw
1813 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1871 emit_byte(0x0F);
1872 emit_byte(0xB7);
1873 emit_byte(0xC0 | encode);
1874 }
1875
1876 void Assembler::mull(Address src) {
1877 InstructionMark im(this);
1878 prefix(src);
1879 emit_byte(0xF7);
1880 emit_operand(rsp, src);
1881 }
1882
1883 void Assembler::mull(Register src) {
1884 int encode = prefix_and_encode(src->encoding());
1885 emit_byte(0xF7);
1886 emit_byte(0xE0 | encode);
1887 }
1888
1889 void Assembler::mulsd(XMMRegister dst, Address src) {
1890 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1891 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
1892 }
1893
1894 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
1895 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1896 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
1897 }
1898
1899 void Assembler::mulss(XMMRegister dst, Address src) {
1900 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1901 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
1902 }
1903
1904 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
1905 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1906 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
1907 }
1908
1909 void Assembler::negl(Register dst) {
1910 int encode = prefix_and_encode(dst->encoding());
1911 emit_byte(0xF7);
1912 emit_byte(0xD8 | encode);
1913 }
1914
1915 void Assembler::nop(int i) {
1916 #ifdef ASSERT
1917 assert(i > 0, " ");
1918 // The fancy nops aren't currently recognized by debuggers making it a
1919 // pain to disassemble code while debugging. If asserts are on clearly
1920 // speed is not an issue so simply use the single byte traditional nop
1921 // to do alignment.
1922
1923 for (; i > 0 ; i--) emit_byte(0x90);
1924 return;
1925
1926 #endif // ASSERT
2175 void Assembler::orl(Register dst, int32_t imm32) {
2176 prefix(dst);
2177 emit_arith(0x81, 0xC8, dst, imm32);
2178 }
2179
2180 void Assembler::orl(Register dst, Address src) {
2181 InstructionMark im(this);
2182 prefix(src, dst);
2183 emit_byte(0x0B);
2184 emit_operand(dst, src);
2185 }
2186
2187 void Assembler::orl(Register dst, Register src) {
2188 (void) prefix_and_encode(dst->encoding(), src->encoding());
2189 emit_arith(0x0B, 0xC0, dst, src);
2190 }
2191
2192 void Assembler::packuswb(XMMRegister dst, Address src) {
2193 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2194 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2195 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2196 }
2197
2198 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2199 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2200 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2201 }
2202
2203 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2204 assert(VM_Version::supports_sse4_2(), "");
2205 InstructionMark im(this);
2206 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2207 emit_byte(0x61);
2208 emit_operand(dst, src);
2209 emit_byte(imm8);
2210 }
2211
2212 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2213 assert(VM_Version::supports_sse4_2(), "");
2214 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2215 emit_byte(0x61);
2216 emit_byte(0xC0 | encode);
2217 emit_byte(imm8);
2218 }
2219
2220 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2221 assert(VM_Version::supports_sse4_1(), "");
2222 InstructionMark im(this);
2223 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2224 emit_byte(0x30);
2225 emit_operand(dst, src);
2226 }
2227
2228 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2229 assert(VM_Version::supports_sse4_1(), "");
2230 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2231 emit_byte(0x30);
2232 emit_byte(0xC0 | encode);
2233 }
2234
2235 // generic
2236 void Assembler::pop(Register dst) {
2237 int encode = prefix_and_encode(dst->encoding());
2238 emit_byte(0x58 | encode);
2239 }
2240
2241 void Assembler::popcntl(Register dst, Address src) {
2242 assert(VM_Version::supports_popcnt(), "must support");
2243 InstructionMark im(this);
2244 emit_byte(0xF3);
2245 prefix(src, dst);
2246 emit_byte(0x0F);
2247 emit_byte(0xB8);
2248 emit_operand(dst, src);
2249 }
2250
2311 void Assembler::prefetcht2(Address src) {
2312 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2313 InstructionMark im(this);
2314 prefetch_prefix(src);
2315 emit_byte(0x18);
2316 emit_operand(rbx, src); // 3, src
2317 }
2318
2319 void Assembler::prefetchw(Address src) {
2320 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2321 InstructionMark im(this);
2322 prefetch_prefix(src);
2323 emit_byte(0x0D);
2324 emit_operand(rcx, src); // 1, src
2325 }
2326
2327 void Assembler::prefix(Prefix p) {
2328 a_byte(p);
2329 }
2330
2331 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2332 assert(isByte(mode), "invalid value");
2333 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2334 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
2335 emit_byte(mode & 0xFF);
2336
2337 }
2338
2339 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2340 assert(isByte(mode), "invalid value");
2341 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2342 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2343 InstructionMark im(this);
2344 simd_prefix(dst, src, VEX_SIMD_66);
2345 emit_byte(0x70);
2346 emit_operand(dst, src);
2347 emit_byte(mode & 0xFF);
2348 }
2349
2350 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2351 assert(isByte(mode), "invalid value");
2352 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2353 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2);
2354 emit_byte(mode & 0xFF);
2355 }
2356
2357 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2358 assert(isByte(mode), "invalid value");
2359 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2360 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2361 InstructionMark im(this);
2362 simd_prefix(dst, src, VEX_SIMD_F2);
2363 emit_byte(0x70);
2364 emit_operand(dst, src);
2365 emit_byte(mode & 0xFF);
2366 }
2367
2368 void Assembler::psrldq(XMMRegister dst, int shift) {
2369 // Shift 128 bit value in xmm register by number of bytes.
2370 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2371 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
2372 emit_byte(0x73);
2373 emit_byte(0xC0 | encode);
2374 emit_byte(shift);
2375 }
2376
2377 void Assembler::ptest(XMMRegister dst, Address src) {
2378 assert(VM_Version::supports_sse4_1(), "");
2379 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2380 InstructionMark im(this);
2381 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2382 emit_byte(0x17);
2383 emit_operand(dst, src);
2384 }
2385
2386 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2387 assert(VM_Version::supports_sse4_1(), "");
2388 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2389 emit_byte(0x17);
2390 emit_byte(0xC0 | encode);
2391 }
2392
2393 void Assembler::punpcklbw(XMMRegister dst, Address src) {
2394 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2395 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2396 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2397 }
2398
2399 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2400 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2401 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2402 }
2403
2404 void Assembler::punpckldq(XMMRegister dst, Address src) {
2405 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2406 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2407 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2408 }
2409
2410 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2411 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2412 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2413 }
2414
2415 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
2416 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2417 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
2418 }
2419
2420 void Assembler::push(int32_t imm32) {
2421 // in 64bits we push 64bits onto the stack but only
2422 // take a 32bit immediate
2423 emit_byte(0x68);
2424 emit_long(imm32);
2425 }
2426
2427 void Assembler::push(Register src) {
2428 int encode = prefix_and_encode(src->encoding());
2429
2430 emit_byte(0x50 | encode);
2431 }
2432
2433 void Assembler::pushf() {
2434 emit_byte(0x9C);
2435 }
2436
2437 #ifndef _LP64 // no 32bit push/pop on amd64
2438 void Assembler::pushl(Address src) {
2439 // Note this will push 64bit on 64bit
2440 InstructionMark im(this);
2441 prefix(src);
2442 emit_byte(0xFF);
2443 emit_operand(rsi, src);
2444 }
2445 #endif
2446
2447 void Assembler::rcll(Register dst, int imm8) {
2448 assert(isShiftCount(imm8), "illegal shift count");
2449 int encode = prefix_and_encode(dst->encoding());
2450 if (imm8 == 1) {
2451 emit_byte(0xD1);
2452 emit_byte(0xD0 | encode);
2453 } else {
2454 emit_byte(0xC1);
2455 emit_byte(0xD0 | encode);
2456 emit_byte(imm8);
2457 }
2458 }
2459
2460 // copies data from [esi] to [edi] using rcx pointer sized words
2461 // generic
2462 void Assembler::rep_mov() {
2463 emit_byte(0xF3);
2464 // MOVSQ
2465 LP64_ONLY(prefix(REX_W));
2466 emit_byte(0xA5);
2585 assert(isShiftCount(imm8), "illegal shift count");
2586 int encode = prefix_and_encode(dst->encoding());
2587 emit_byte(0xC1);
2588 emit_byte(0xE8 | encode);
2589 emit_byte(imm8);
2590 }
2591
2592 void Assembler::shrl(Register dst) {
2593 int encode = prefix_and_encode(dst->encoding());
2594 emit_byte(0xD3);
2595 emit_byte(0xE8 | encode);
2596 }
2597
2598 // copies a single word from [esi] to [edi]
2599 void Assembler::smovl() {
2600 emit_byte(0xA5);
2601 }
2602
2603 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2604 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2605 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2606 }
2607
2608 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2609 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2610 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2611 }
2612
2613 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2614 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2615 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2616 }
2617
2618 void Assembler::sqrtss(XMMRegister dst, Address src) {
2619 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2620 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2621 }
2622
2623 void Assembler::stmxcsr( Address dst) {
2624 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2625 InstructionMark im(this);
2626 prefix(dst);
2627 emit_byte(0x0F);
2628 emit_byte(0xAE);
2629 emit_operand(as_Register(3), dst);
2630 }
2631
2632 void Assembler::subl(Address dst, int32_t imm32) {
2633 InstructionMark im(this);
2634 prefix(dst);
2635 emit_arith_operand(0x81, rbp, dst, imm32);
2636 }
2637
2638 void Assembler::subl(Address dst, Register src) {
2639 InstructionMark im(this);
2640 prefix(dst, src);
2650 // Force generation of a 4 byte immediate value even if it fits into 8bit
2651 void Assembler::subl_imm32(Register dst, int32_t imm32) {
2652 prefix(dst);
2653 emit_arith_imm32(0x81, 0xE8, dst, imm32);
2654 }
2655
2656 void Assembler::subl(Register dst, Address src) {
2657 InstructionMark im(this);
2658 prefix(src, dst);
2659 emit_byte(0x2B);
2660 emit_operand(dst, src);
2661 }
2662
2663 void Assembler::subl(Register dst, Register src) {
2664 (void) prefix_and_encode(dst->encoding(), src->encoding());
2665 emit_arith(0x2B, 0xC0, dst, src);
2666 }
2667
2668 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2669 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2670 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2671 }
2672
2673 void Assembler::subsd(XMMRegister dst, Address src) {
2674 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2675 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2676 }
2677
2678 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2679 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2680 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2681 }
2682
2683 void Assembler::subss(XMMRegister dst, Address src) {
2684 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2685 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2686 }
2687
2688 void Assembler::testb(Register dst, int imm8) {
2689 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2690 (void) prefix_and_encode(dst->encoding(), true);
2691 emit_arith_b(0xF6, 0xC0, dst, imm8);
2692 }
2693
2694 void Assembler::testl(Register dst, int32_t imm32) {
2695 // not using emit_arith because test
2696 // doesn't support sign-extension of
2697 // 8bit operands
2698 int encode = dst->encoding();
2699 if (encode == 0) {
2700 emit_byte(0xA9);
2701 } else {
2702 encode = prefix_and_encode(encode);
2703 emit_byte(0xF7);
2704 emit_byte(0xC0 | encode);
2705 }
2706 emit_long(imm32);
2707 }
2708
2709 void Assembler::testl(Register dst, Register src) {
2710 (void) prefix_and_encode(dst->encoding(), src->encoding());
2711 emit_arith(0x85, 0xC0, dst, src);
2712 }
2713
2714 void Assembler::testl(Register dst, Address src) {
2715 InstructionMark im(this);
2716 prefix(src, dst);
2717 emit_byte(0x85);
2718 emit_operand(dst, src);
2719 }
2720
2721 void Assembler::ucomisd(XMMRegister dst, Address src) {
2722 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2723 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2724 }
2725
2726 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2727 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2728 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2729 }
2730
2731 void Assembler::ucomiss(XMMRegister dst, Address src) {
2732 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2733 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2734 }
2735
2736 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2737 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2738 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2739 }
2740
2741
2742 void Assembler::xaddl(Address dst, Register src) {
2743 InstructionMark im(this);
2744 prefix(dst, src);
2745 emit_byte(0x0F);
2746 emit_byte(0xC1);
2747 emit_operand(src, dst);
2748 }
2749
2750 void Assembler::xchgl(Register dst, Address src) { // xchg
2751 InstructionMark im(this);
2752 prefix(src, dst);
2753 emit_byte(0x87);
2754 emit_operand(dst, src);
2755 }
2756
2757 void Assembler::xchgl(Register dst, Register src) {
2758 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2760 emit_byte(0xc0 | encode);
2761 }
2762
2763 void Assembler::xorl(Register dst, int32_t imm32) {
2764 prefix(dst);
2765 emit_arith(0x81, 0xF0, dst, imm32);
2766 }
2767
2768 void Assembler::xorl(Register dst, Address src) {
2769 InstructionMark im(this);
2770 prefix(src, dst);
2771 emit_byte(0x33);
2772 emit_operand(dst, src);
2773 }
2774
2775 void Assembler::xorl(Register dst, Register src) {
2776 (void) prefix_and_encode(dst->encoding(), src->encoding());
2777 emit_arith(0x33, 0xC0, dst, src);
2778 }
2779
2780
2781 // AVX 3-operands scalar float-point arithmetic instructions
2782
2783 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
2784 assert(VM_Version::supports_avx(), "");
2785 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2786 }
2787
2788 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2789 assert(VM_Version::supports_avx(), "");
2790 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2791 }
2792
2793 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
2794 assert(VM_Version::supports_avx(), "");
2795 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2796 }
2797
2798 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2799 assert(VM_Version::supports_avx(), "");
2800 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2801 }
2802
2803 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
2804 assert(VM_Version::supports_avx(), "");
2805 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2806 }
2807
2808 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2809 assert(VM_Version::supports_avx(), "");
2810 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2811 }
2812
2813 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
2814 assert(VM_Version::supports_avx(), "");
2815 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2816 }
2817
2818 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2819 assert(VM_Version::supports_avx(), "");
2820 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2821 }
2822
2823 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
2824 assert(VM_Version::supports_avx(), "");
2825 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2826 }
2827
2828 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2829 assert(VM_Version::supports_avx(), "");
2830 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2831 }
2832
2833 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
2834 assert(VM_Version::supports_avx(), "");
2835 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2836 }
2837
2838 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2839 assert(VM_Version::supports_avx(), "");
2840 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2841 }
2842
2843 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
2844 assert(VM_Version::supports_avx(), "");
2845 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2846 }
2847
2848 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2849 assert(VM_Version::supports_avx(), "");
2850 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
2851 }
2852
2853 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
2854 assert(VM_Version::supports_avx(), "");
2855 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2856 }
2857
2858 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2859 assert(VM_Version::supports_avx(), "");
2860 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
2861 }
2862
2863 //====================VECTOR ARITHMETIC=====================================
2864
2865 // Float-point vector arithmetic
2866
2867 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
2868 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2869 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
2870 }
2871
2872 void Assembler::addps(XMMRegister dst, XMMRegister src) {
2873 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2874 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
2875 }
2876
2877 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2878 assert(VM_Version::supports_avx(), "");
2879 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
2880 }
2881
2882 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2883 assert(VM_Version::supports_avx(), "");
2884 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
2885 }
2886
2887 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
2888 assert(VM_Version::supports_avx(), "");
2889 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
2890 }
2891
2892 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
2893 assert(VM_Version::supports_avx(), "");
2894 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
2895 }
2896
2897 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
2898 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2899 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
2900 }
2901
2902 void Assembler::subps(XMMRegister dst, XMMRegister src) {
2903 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2904 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
2905 }
2906
2907 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2908 assert(VM_Version::supports_avx(), "");
2909 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
2910 }
2911
2912 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2913 assert(VM_Version::supports_avx(), "");
2914 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
2915 }
2916
2917 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
2918 assert(VM_Version::supports_avx(), "");
2919 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
2920 }
2921
2922 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
2923 assert(VM_Version::supports_avx(), "");
2924 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
2925 }
2926
2927 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
2928 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2929 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
2930 }
2931
2932 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
2933 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2934 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
2935 }
2936
2937 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2938 assert(VM_Version::supports_avx(), "");
2939 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
2940 }
2941
2942 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2943 assert(VM_Version::supports_avx(), "");
2944 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
2945 }
2946
2947 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
2948 assert(VM_Version::supports_avx(), "");
2949 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
2950 }
2951
2952 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
2953 assert(VM_Version::supports_avx(), "");
2954 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
2955 }
2956
2957 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
2958 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2959 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
2960 }
2961
2962 void Assembler::divps(XMMRegister dst, XMMRegister src) {
2963 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2964 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
2965 }
2966
2967 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2968 assert(VM_Version::supports_avx(), "");
2969 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
2970 }
2971
2972 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2973 assert(VM_Version::supports_avx(), "");
2974 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
2975 }
2976
2977 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
2978 assert(VM_Version::supports_avx(), "");
2979 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
2980 }
2981
2982 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
2983 assert(VM_Version::supports_avx(), "");
2984 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
2985 }
2986
2987 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
2988 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2989 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
2990 }
2991
2992 void Assembler::andps(XMMRegister dst, XMMRegister src) {
2993 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2994 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
2995 }
2996
2997 void Assembler::andps(XMMRegister dst, Address src) {
2998 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2999 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3000 }
3001
3002 void Assembler::andpd(XMMRegister dst, Address src) {
3003 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3004 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3005 }
3006
3007 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3008 assert(VM_Version::supports_avx(), "");
3009 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3010 }
3011
3012 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3013 assert(VM_Version::supports_avx(), "");
3014 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3015 }
3016
3017 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3018 assert(VM_Version::supports_avx(), "");
3019 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3020 }
3021
3022 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3023 assert(VM_Version::supports_avx(), "");
3024 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3025 }
3026
3027 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
3028 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3029 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3030 }
3031
3032 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
3033 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3034 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3035 }
3036
3037 void Assembler::xorpd(XMMRegister dst, Address src) {
3038 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3039 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3040 }
3041
3042 void Assembler::xorps(XMMRegister dst, Address src) {
3043 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3044 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3045 }
3046
3047 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3048 assert(VM_Version::supports_avx(), "");
3049 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3050 }
3051
3052 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3053 assert(VM_Version::supports_avx(), "");
3054 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3055 }
3056
3057 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3058 assert(VM_Version::supports_avx(), "");
3059 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3060 }
3061
3062 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3063 assert(VM_Version::supports_avx(), "");
3064 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3065 }
3066
3067
3068 // Integer vector arithmetic
3069 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
3070 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3071 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
3072 }
3073
3074 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
3075 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3076 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
3077 }
3078
3079 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
3080 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3081 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
3082 }
3083
3084 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
3085 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3086 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
3087 }
3088
3089 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3090 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3091 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3092 }
3093
3094 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3095 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3096 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3097 }
3098
3099 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3100 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3101 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3102 }
3103
3104 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3105 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3106 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3107 }
3108
3109 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3110 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3111 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3112 }
3113
3114 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3115 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3116 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3117 }
3118
3119 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3120 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3121 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3122 }
3123
3124 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3125 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3126 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3127 }
3128
3129 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
3130 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3131 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
3132 }
3133
3134 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
3135 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3136 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
3137 }
3138
3139 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
3140 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3141 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
3142 }
3143
3144 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
3145 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3146 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
3147 }
3148
3149 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3150 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3151 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3152 }
3153
3154 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3155 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3156 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3157 }
3158
3159 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3160 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3161 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3162 }
3163
3164 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3165 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3166 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3167 }
3168
3169 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3170 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3171 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3172 }
3173
3174 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3175 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3176 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3177 }
3178
3179 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3180 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3181 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3182 }
3183
3184 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3185 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3186 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3187 }
3188
3189 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
3190 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3191 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66);
3192 }
3193
3194 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
3195 assert(VM_Version::supports_sse4_1(), "");
3196 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
3197 emit_byte(0x40);
3198 emit_byte(0xC0 | encode);
3199 }
3200
3201 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3202 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3203 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3204 }
3205
3206 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3207 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3208 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3209 emit_byte(0x40);
3210 emit_byte(0xC0 | encode);
3211 }
3212
3213 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3214 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3215 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3216 }
3217
3218 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3219 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3220 InstructionMark im(this);
3221 int dst_enc = dst->encoding();
3222 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3223 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
3224 emit_byte(0x40);
3225 emit_operand(dst, src);
3226 }
3227
3228 // Shift packed integers left by specified number of bits.
3229 void Assembler::psllw(XMMRegister dst, int shift) {
3230 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3231 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3232 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3233 emit_byte(0x71);
3234 emit_byte(0xC0 | encode);
3235 emit_byte(shift & 0xFF);
3236 }
3237
3238 void Assembler::pslld(XMMRegister dst, int shift) {
3239 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3240 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3241 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3242 emit_byte(0x72);
3243 emit_byte(0xC0 | encode);
3244 emit_byte(shift & 0xFF);
3245 }
3246
3247 void Assembler::psllq(XMMRegister dst, int shift) {
3248 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3249 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3250 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3251 emit_byte(0x73);
3252 emit_byte(0xC0 | encode);
3253 emit_byte(shift & 0xFF);
3254 }
3255
3256 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
3257 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3258 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66);
3259 }
3260
3261 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
3262 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3263 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
3264 }
3265
3266 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
3267 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3268 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
3269 }
3270
3271 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3272 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3273 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3274 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256);
3275 emit_byte(shift & 0xFF);
3276 }
3277
3278 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3279 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3280 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3281 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256);
3282 emit_byte(shift & 0xFF);
3283 }
3284
3285 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3286 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3287 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3288 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256);
3289 emit_byte(shift & 0xFF);
3290 }
3291
3292 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3293 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3294 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256);
3295 }
3296
3297 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3298 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3299 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256);
3300 }
3301
3302 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3303 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3304 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256);
3305 }
3306
3307 // Shift packed integers logically right by specified number of bits.
3308 void Assembler::psrlw(XMMRegister dst, int shift) {
3309 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3310 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
3311 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3312 emit_byte(0x71);
3313 emit_byte(0xC0 | encode);
3314 emit_byte(shift & 0xFF);
3315 }
3316
3317 void Assembler::psrld(XMMRegister dst, int shift) {
3318 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3319 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
3320 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3321 emit_byte(0x72);
3322 emit_byte(0xC0 | encode);
3323 emit_byte(shift & 0xFF);
3324 }
3325
3326 void Assembler::psrlq(XMMRegister dst, int shift) {
3327 // Do not confuse it with psrldq SSE2 instruction which
3328 // shifts 128 bit value in xmm register by number of bytes.
3329 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3330 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3331 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3332 emit_byte(0x73);
3333 emit_byte(0xC0 | encode);
3334 emit_byte(shift & 0xFF);
3335 }
3336
3337 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
3338 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3339 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66);
3340 }
3341
3342 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
3343 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3344 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
3345 }
3346
3347 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
3348 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3349 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
3350 }
3351
3352 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3353 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3354 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3355 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256);
3356 emit_byte(shift & 0xFF);
3357 }
3358
3359 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3360 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3361 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3362 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256);
3363 emit_byte(shift & 0xFF);
3364 }
3365
3366 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3367 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3368 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3369 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256);
3370 emit_byte(shift & 0xFF);
3371 }
3372
3373 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3374 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3375 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256);
3376 }
3377
3378 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3379 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3380 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256);
3381 }
3382
3383 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3384 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3385 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256);
3386 }
3387
3388 // Shift packed integers arithmetically right by specified number of bits.
3389 void Assembler::psraw(XMMRegister dst, int shift) {
3390 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3391 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3392 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3393 emit_byte(0x71);
3394 emit_byte(0xC0 | encode);
3395 emit_byte(shift & 0xFF);
3396 }
3397
3398 void Assembler::psrad(XMMRegister dst, int shift) {
3399 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3400 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
3401 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3402 emit_byte(0x72);
3403 emit_byte(0xC0 | encode);
3404 emit_byte(shift & 0xFF);
3405 }
3406
3407 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
3408 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3409 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66);
3410 }
3411
3412 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
3413 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3414 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
3415 }
3416
3417 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3418 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3419 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3420 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256);
3421 emit_byte(shift & 0xFF);
3422 }
3423
3424 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3425 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3426 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3427 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256);
3428 emit_byte(shift & 0xFF);
3429 }
3430
3431 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3432 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3433 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256);
3434 }
3435
3436 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3437 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3438 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256);
3439 }
3440
3441
3442 // AND packed integers
3443 void Assembler::pand(XMMRegister dst, XMMRegister src) {
3444 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3445 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
3446 }
3447
3448 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3449 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3450 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3451 }
3452
3453 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3454 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3455 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3456 }
3457
3458 void Assembler::por(XMMRegister dst, XMMRegister src) {
3459 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3460 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
3461 }
3462
3463 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3464 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3465 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3466 }
3467
3468 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3469 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3470 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3471 }
3472
3473 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
3474 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3475 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
3476 }
3477
3478 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3479 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3480 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3481 }
3482
3483 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3484 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3485 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3486 }
3487
3488
3489 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3490 assert(VM_Version::supports_avx(), "");
3491 bool vector256 = true;
3492 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3493 emit_byte(0x18);
3494 emit_byte(0xC0 | encode);
3495 // 0x00 - insert into lower 128 bits
3496 // 0x01 - insert into upper 128 bits
3497 emit_byte(0x01);
3498 }
3499
3500 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3501 assert(VM_Version::supports_avx2(), "");
3502 bool vector256 = true;
3503 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3504 emit_byte(0x38);
3505 emit_byte(0xC0 | encode);
3506 // 0x00 - insert into lower 128 bits
3507 // 0x01 - insert into upper 128 bits
3508 emit_byte(0x01);
4073 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4074 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
4075 } else {
4076 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
4077 rex_prefix(adr, xreg, pre, opc, rex_w);
4078 }
4079 }
4080
4081 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4082 int dst_enc = dst->encoding();
4083 int src_enc = src->encoding();
4084 if (UseAVX > 0) {
4085 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4086 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
4087 } else {
4088 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
4089 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
4090 }
4091 }
4092
4093 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4094 InstructionMark im(this);
4095 simd_prefix(dst, dst, src, pre);
4096 emit_byte(opcode);
4097 emit_operand(dst, src);
4098 }
4099
4100 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4101 int encode = simd_prefix_and_encode(dst, dst, src, pre);
4102 emit_byte(opcode);
4103 emit_byte(0xC0 | encode);
4104 }
4105
4106 // Versions with no second source register (non-destructive source).
4107 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4108 InstructionMark im(this);
4109 simd_prefix(dst, xnoreg, src, pre);
4110 emit_byte(opcode);
4111 emit_operand(dst, src);
4112 }
4113
4114 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4115 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre);
4116 emit_byte(opcode);
4117 emit_byte(0xC0 | encode);
4118 }
4119
4120 // 3-operands AVX instructions
4121 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4122 Address src, VexSimdPrefix pre, bool vector256) {
4123 InstructionMark im(this);
4124 vex_prefix(dst, nds, src, pre, vector256);
4125 emit_byte(opcode);
4126 emit_operand(dst, src);
4127 }
4128
4129 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4130 XMMRegister src, VexSimdPrefix pre, bool vector256) {
4131 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256);
4132 emit_byte(opcode);
4133 emit_byte(0xC0 | encode);
4134 }
4135
4136 #ifndef _LP64
4137
4138 void Assembler::incl(Register dst) {
4139 // Don't use it directly. Use MacroAssembler::incrementl() instead.
4140 emit_byte(0x40 | dst->encoding());
4141 }
4142
4143 void Assembler::lea(Register dst, Address src) {
4144 leal(dst, src);
4145 }
4146
4147 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
4148 InstructionMark im(this);
4149 emit_byte(0xC7);
4150 emit_operand(rax, dst);
4151 emit_data((int)imm32, rspec, 0);
4152 }
4153
4154 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
4155 InstructionMark im(this);
8196 // AVX 3-operands instructions
8197
8198 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
8199 if (reachable(src)) {
8200 vaddsd(dst, nds, as_Address(src));
8201 } else {
8202 lea(rscratch1, src);
8203 vaddsd(dst, nds, Address(rscratch1, 0));
8204 }
8205 }
8206
8207 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
8208 if (reachable(src)) {
8209 vaddss(dst, nds, as_Address(src));
8210 } else {
8211 lea(rscratch1, src);
8212 vaddss(dst, nds, Address(rscratch1, 0));
8213 }
8214 }
8215
8216 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
8217 if (reachable(src)) {
8218 vandpd(dst, nds, as_Address(src), vector256);
8219 } else {
8220 lea(rscratch1, src);
8221 vandpd(dst, nds, Address(rscratch1, 0), vector256);
8222 }
8223 }
8224
8225 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
8226 if (reachable(src)) {
8227 vandps(dst, nds, as_Address(src), vector256);
8228 } else {
8229 lea(rscratch1, src);
8230 vandps(dst, nds, Address(rscratch1, 0), vector256);
8231 }
8232 }
8233
8234 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
8235 if (reachable(src)) {
8236 vdivsd(dst, nds, as_Address(src));
8237 } else {
8238 lea(rscratch1, src);
8239 vdivsd(dst, nds, Address(rscratch1, 0));
8240 }
8241 }
8242
8243 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
8244 if (reachable(src)) {
8245 vdivss(dst, nds, as_Address(src));
8246 } else {
8247 lea(rscratch1, src);
8248 vdivss(dst, nds, Address(rscratch1, 0));
8249 }
8250 }
8268 }
8269
8270 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
8271 if (reachable(src)) {
8272 vsubsd(dst, nds, as_Address(src));
8273 } else {
8274 lea(rscratch1, src);
8275 vsubsd(dst, nds, Address(rscratch1, 0));
8276 }
8277 }
8278
8279 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
8280 if (reachable(src)) {
8281 vsubss(dst, nds, as_Address(src));
8282 } else {
8283 lea(rscratch1, src);
8284 vsubss(dst, nds, Address(rscratch1, 0));
8285 }
8286 }
8287
8288 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
8289 if (reachable(src)) {
8290 vxorpd(dst, nds, as_Address(src), vector256);
8291 } else {
8292 lea(rscratch1, src);
8293 vxorpd(dst, nds, Address(rscratch1, 0), vector256);
8294 }
8295 }
8296
8297 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256) {
8298 if (reachable(src)) {
8299 vxorps(dst, nds, as_Address(src), vector256);
8300 } else {
8301 lea(rscratch1, src);
8302 vxorps(dst, nds, Address(rscratch1, 0), vector256);
8303 }
8304 }
8305
8306
8307 //////////////////////////////////////////////////////////////////////////////////
8308 #ifndef SERIALGC
8309
8310 void MacroAssembler::g1_write_barrier_pre(Register obj,
8311 Register pre_val,
8312 Register thread,
8313 Register tmp,
8314 bool tosca_live,
8315 bool expand_call) {
8316
8317 // If expand_call is true then we expand the call_VM_leaf macro
8318 // directly to skip generating the check by
8319 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
8320
8321 #ifdef _LP64
8322 assert(thread == r15_thread, "must be");
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