1 /* 2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP 26 #define CPU_X86_VM_ASSEMBLER_X86_HPP 27 28 class BiasedLockingCounters; 29 30 // Contains all the definitions needed for x86 assembly code generation. 31 32 // Calling convention 33 class Argument VALUE_OBJ_CLASS_SPEC { 34 public: 35 enum { 36 #ifdef _LP64 37 #ifdef _WIN64 38 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) 39 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) 40 #else 41 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) 42 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) 43 #endif // _WIN64 44 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... 45 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... 46 #else 47 n_register_parameters = 0 // 0 registers used to pass arguments 48 #endif // _LP64 49 }; 50 }; 51 52 53 #ifdef _LP64 54 // Symbolically name the register arguments used by the c calling convention. 55 // Windows is different from linux/solaris. So much for standards... 56 57 #ifdef _WIN64 58 59 REGISTER_DECLARATION(Register, c_rarg0, rcx); 60 REGISTER_DECLARATION(Register, c_rarg1, rdx); 61 REGISTER_DECLARATION(Register, c_rarg2, r8); 62 REGISTER_DECLARATION(Register, c_rarg3, r9); 63 64 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); 65 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); 66 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); 67 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); 68 69 #else 70 71 REGISTER_DECLARATION(Register, c_rarg0, rdi); 72 REGISTER_DECLARATION(Register, c_rarg1, rsi); 73 REGISTER_DECLARATION(Register, c_rarg2, rdx); 74 REGISTER_DECLARATION(Register, c_rarg3, rcx); 75 REGISTER_DECLARATION(Register, c_rarg4, r8); 76 REGISTER_DECLARATION(Register, c_rarg5, r9); 77 78 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); 79 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); 80 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); 81 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); 82 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); 83 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); 84 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); 85 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); 86 87 #endif // _WIN64 88 89 // Symbolically name the register arguments used by the Java calling convention. 90 // We have control over the convention for java so we can do what we please. 91 // What pleases us is to offset the java calling convention so that when 92 // we call a suitable jni method the arguments are lined up and we don't 93 // have to do little shuffling. A suitable jni method is non-static and a 94 // small number of arguments (two fewer args on windows) 95 // 96 // |-------------------------------------------------------| 97 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | 98 // |-------------------------------------------------------| 99 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) 100 // | rdi rsi rdx rcx r8 r9 | solaris/linux 101 // |-------------------------------------------------------| 102 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | 103 // |-------------------------------------------------------| 104 105 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); 106 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); 107 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); 108 // Windows runs out of register args here 109 #ifdef _WIN64 110 REGISTER_DECLARATION(Register, j_rarg3, rdi); 111 REGISTER_DECLARATION(Register, j_rarg4, rsi); 112 #else 113 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); 114 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); 115 #endif /* _WIN64 */ 116 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); 117 118 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); 119 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); 120 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); 121 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); 122 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); 123 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); 124 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); 125 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); 126 127 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile 128 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile 129 130 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved 131 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved 132 133 #else 134 // rscratch1 will apear in 32bit code that is dead but of course must compile 135 // Using noreg ensures if the dead code is incorrectly live and executed it 136 // will cause an assertion failure 137 #define rscratch1 noreg 138 #define rscratch2 noreg 139 140 #endif // _LP64 141 142 // JSR 292 fixed register usages: 143 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); 144 145 // Address is an abstraction used to represent a memory location 146 // using any of the amd64 addressing modes with one object. 147 // 148 // Note: A register location is represented via a Register, not 149 // via an address for efficiency & simplicity reasons. 150 151 class ArrayAddress; 152 153 class Address VALUE_OBJ_CLASS_SPEC { 154 public: 155 enum ScaleFactor { 156 no_scale = -1, 157 times_1 = 0, 158 times_2 = 1, 159 times_4 = 2, 160 times_8 = 3, 161 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) 162 }; 163 static ScaleFactor times(int size) { 164 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); 165 if (size == 8) return times_8; 166 if (size == 4) return times_4; 167 if (size == 2) return times_2; 168 return times_1; 169 } 170 static int scale_size(ScaleFactor scale) { 171 assert(scale != no_scale, ""); 172 assert(((1 << (int)times_1) == 1 && 173 (1 << (int)times_2) == 2 && 174 (1 << (int)times_4) == 4 && 175 (1 << (int)times_8) == 8), ""); 176 return (1 << (int)scale); 177 } 178 179 private: 180 Register _base; 181 Register _index; 182 ScaleFactor _scale; 183 int _disp; 184 RelocationHolder _rspec; 185 186 // Easily misused constructors make them private 187 // %%% can we make these go away? 188 NOT_LP64(Address(address loc, RelocationHolder spec);) 189 Address(int disp, address loc, relocInfo::relocType rtype); 190 Address(int disp, address loc, RelocationHolder spec); 191 192 public: 193 194 int disp() { return _disp; } 195 // creation 196 Address() 197 : _base(noreg), 198 _index(noreg), 199 _scale(no_scale), 200 _disp(0) { 201 } 202 203 // No default displacement otherwise Register can be implicitly 204 // converted to 0(Register) which is quite a different animal. 205 206 Address(Register base, int disp) 207 : _base(base), 208 _index(noreg), 209 _scale(no_scale), 210 _disp(disp) { 211 } 212 213 Address(Register base, Register index, ScaleFactor scale, int disp = 0) 214 : _base (base), 215 _index(index), 216 _scale(scale), 217 _disp (disp) { 218 assert(!index->is_valid() == (scale == Address::no_scale), 219 "inconsistent address"); 220 } 221 222 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) 223 : _base (base), 224 _index(index.register_or_noreg()), 225 _scale(scale), 226 _disp (disp + (index.constant_or_zero() * scale_size(scale))) { 227 if (!index.is_register()) scale = Address::no_scale; 228 assert(!_index->is_valid() == (scale == Address::no_scale), 229 "inconsistent address"); 230 } 231 232 Address plus_disp(int disp) const { 233 Address a = (*this); 234 a._disp += disp; 235 return a; 236 } 237 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { 238 Address a = (*this); 239 a._disp += disp.constant_or_zero() * scale_size(scale); 240 if (disp.is_register()) { 241 assert(!a.index()->is_valid(), "competing indexes"); 242 a._index = disp.as_register(); 243 a._scale = scale; 244 } 245 return a; 246 } 247 bool is_same_address(Address a) const { 248 // disregard _rspec 249 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; 250 } 251 252 // The following two overloads are used in connection with the 253 // ByteSize type (see sizes.hpp). They simplify the use of 254 // ByteSize'd arguments in assembly code. Note that their equivalent 255 // for the optimized build are the member functions with int disp 256 // argument since ByteSize is mapped to an int type in that case. 257 // 258 // Note: DO NOT introduce similar overloaded functions for WordSize 259 // arguments as in the optimized mode, both ByteSize and WordSize 260 // are mapped to the same type and thus the compiler cannot make a 261 // distinction anymore (=> compiler errors). 262 263 #ifdef ASSERT 264 Address(Register base, ByteSize disp) 265 : _base(base), 266 _index(noreg), 267 _scale(no_scale), 268 _disp(in_bytes(disp)) { 269 } 270 271 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) 272 : _base(base), 273 _index(index), 274 _scale(scale), 275 _disp(in_bytes(disp)) { 276 assert(!index->is_valid() == (scale == Address::no_scale), 277 "inconsistent address"); 278 } 279 280 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) 281 : _base (base), 282 _index(index.register_or_noreg()), 283 _scale(scale), 284 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { 285 if (!index.is_register()) scale = Address::no_scale; 286 assert(!_index->is_valid() == (scale == Address::no_scale), 287 "inconsistent address"); 288 } 289 290 #endif // ASSERT 291 292 // accessors 293 bool uses(Register reg) const { return _base == reg || _index == reg; } 294 Register base() const { return _base; } 295 Register index() const { return _index; } 296 ScaleFactor scale() const { return _scale; } 297 int disp() const { return _disp; } 298 299 // Convert the raw encoding form into the form expected by the constructor for 300 // Address. An index of 4 (rsp) corresponds to having no index, so convert 301 // that to noreg for the Address constructor. 302 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop); 303 304 static Address make_array(ArrayAddress); 305 306 private: 307 bool base_needs_rex() const { 308 return _base != noreg && _base->encoding() >= 8; 309 } 310 311 bool index_needs_rex() const { 312 return _index != noreg &&_index->encoding() >= 8; 313 } 314 315 relocInfo::relocType reloc() const { return _rspec.type(); } 316 317 friend class Assembler; 318 friend class MacroAssembler; 319 friend class LIR_Assembler; // base/index/scale/disp 320 }; 321 322 // 323 // AddressLiteral has been split out from Address because operands of this type 324 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out 325 // the few instructions that need to deal with address literals are unique and the 326 // MacroAssembler does not have to implement every instruction in the Assembler 327 // in order to search for address literals that may need special handling depending 328 // on the instruction and the platform. As small step on the way to merging i486/amd64 329 // directories. 330 // 331 class AddressLiteral VALUE_OBJ_CLASS_SPEC { 332 friend class ArrayAddress; 333 RelocationHolder _rspec; 334 // Typically we use AddressLiterals we want to use their rval 335 // However in some situations we want the lval (effect address) of the item. 336 // We provide a special factory for making those lvals. 337 bool _is_lval; 338 339 // If the target is far we'll need to load the ea of this to 340 // a register to reach it. Otherwise if near we can do rip 341 // relative addressing. 342 343 address _target; 344 345 protected: 346 // creation 347 AddressLiteral() 348 : _is_lval(false), 349 _target(NULL) 350 {} 351 352 public: 353 354 355 AddressLiteral(address target, relocInfo::relocType rtype); 356 357 AddressLiteral(address target, RelocationHolder const& rspec) 358 : _rspec(rspec), 359 _is_lval(false), 360 _target(target) 361 {} 362 363 AddressLiteral addr() { 364 AddressLiteral ret = *this; 365 ret._is_lval = true; 366 return ret; 367 } 368 369 370 private: 371 372 address target() { return _target; } 373 bool is_lval() { return _is_lval; } 374 375 relocInfo::relocType reloc() const { return _rspec.type(); } 376 const RelocationHolder& rspec() const { return _rspec; } 377 378 friend class Assembler; 379 friend class MacroAssembler; 380 friend class Address; 381 friend class LIR_Assembler; 382 }; 383 384 // Convience classes 385 class RuntimeAddress: public AddressLiteral { 386 387 public: 388 389 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} 390 391 }; 392 393 class OopAddress: public AddressLiteral { 394 395 public: 396 397 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} 398 399 }; 400 401 class ExternalAddress: public AddressLiteral { 402 private: 403 static relocInfo::relocType reloc_for_target(address target) { 404 // Sometimes ExternalAddress is used for values which aren't 405 // exactly addresses, like the card table base. 406 // external_word_type can't be used for values in the first page 407 // so just skip the reloc in that case. 408 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; 409 } 410 411 public: 412 413 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} 414 415 }; 416 417 class InternalAddress: public AddressLiteral { 418 419 public: 420 421 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} 422 423 }; 424 425 // x86 can do array addressing as a single operation since disp can be an absolute 426 // address amd64 can't. We create a class that expresses the concept but does extra 427 // magic on amd64 to get the final result 428 429 class ArrayAddress VALUE_OBJ_CLASS_SPEC { 430 private: 431 432 AddressLiteral _base; 433 Address _index; 434 435 public: 436 437 ArrayAddress() {}; 438 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; 439 AddressLiteral base() { return _base; } 440 Address index() { return _index; } 441 442 }; 443 444 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); 445 446 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction 447 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write 448 // is what you get. The Assembler is generating code into a CodeBuffer. 449 450 class Assembler : public AbstractAssembler { 451 friend class AbstractAssembler; // for the non-virtual hack 452 friend class LIR_Assembler; // as_Address() 453 friend class StubGenerator; 454 455 public: 456 enum Condition { // The x86 condition codes used for conditional jumps/moves. 457 zero = 0x4, 458 notZero = 0x5, 459 equal = 0x4, 460 notEqual = 0x5, 461 less = 0xc, 462 lessEqual = 0xe, 463 greater = 0xf, 464 greaterEqual = 0xd, 465 below = 0x2, 466 belowEqual = 0x6, 467 above = 0x7, 468 aboveEqual = 0x3, 469 overflow = 0x0, 470 noOverflow = 0x1, 471 carrySet = 0x2, 472 carryClear = 0x3, 473 negative = 0x8, 474 positive = 0x9, 475 parity = 0xa, 476 noParity = 0xb 477 }; 478 479 enum Prefix { 480 // segment overrides 481 CS_segment = 0x2e, 482 SS_segment = 0x36, 483 DS_segment = 0x3e, 484 ES_segment = 0x26, 485 FS_segment = 0x64, 486 GS_segment = 0x65, 487 488 REX = 0x40, 489 490 REX_B = 0x41, 491 REX_X = 0x42, 492 REX_XB = 0x43, 493 REX_R = 0x44, 494 REX_RB = 0x45, 495 REX_RX = 0x46, 496 REX_RXB = 0x47, 497 498 REX_W = 0x48, 499 500 REX_WB = 0x49, 501 REX_WX = 0x4A, 502 REX_WXB = 0x4B, 503 REX_WR = 0x4C, 504 REX_WRB = 0x4D, 505 REX_WRX = 0x4E, 506 REX_WRXB = 0x4F, 507 508 VEX_3bytes = 0xC4, 509 VEX_2bytes = 0xC5 510 }; 511 512 enum VexPrefix { 513 VEX_B = 0x20, 514 VEX_X = 0x40, 515 VEX_R = 0x80, 516 VEX_W = 0x80 517 }; 518 519 enum VexSimdPrefix { 520 VEX_SIMD_NONE = 0x0, 521 VEX_SIMD_66 = 0x1, 522 VEX_SIMD_F3 = 0x2, 523 VEX_SIMD_F2 = 0x3 524 }; 525 526 enum VexOpcode { 527 VEX_OPCODE_NONE = 0x0, 528 VEX_OPCODE_0F = 0x1, 529 VEX_OPCODE_0F_38 = 0x2, 530 VEX_OPCODE_0F_3A = 0x3 531 }; 532 533 enum WhichOperand { 534 // input to locate_operand, and format code for relocations 535 imm_operand = 0, // embedded 32-bit|64-bit immediate operand 536 disp32_operand = 1, // embedded 32-bit displacement or address 537 call32_operand = 2, // embedded 32-bit self-relative displacement 538 #ifndef _LP64 539 _WhichOperand_limit = 3 540 #else 541 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop 542 _WhichOperand_limit = 4 543 #endif 544 }; 545 546 547 548 // NOTE: The general philopsophy of the declarations here is that 64bit versions 549 // of instructions are freely declared without the need for wrapping them an ifdef. 550 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) 551 // In the .cpp file the implementations are wrapped so that they are dropped out 552 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL 553 // to the size it was prior to merging up the 32bit and 64bit assemblers. 554 // 555 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction 556 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. 557 558 private: 559 560 561 // 64bit prefixes 562 int prefix_and_encode(int reg_enc, bool byteinst = false); 563 int prefixq_and_encode(int reg_enc); 564 565 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); 566 int prefixq_and_encode(int dst_enc, int src_enc); 567 568 void prefix(Register reg); 569 void prefix(Address adr); 570 void prefixq(Address adr); 571 572 void prefix(Address adr, Register reg, bool byteinst = false); 573 void prefix(Address adr, XMMRegister reg); 574 void prefixq(Address adr, Register reg); 575 void prefixq(Address adr, XMMRegister reg); 576 577 void prefetch_prefix(Address src); 578 579 void rex_prefix(Address adr, XMMRegister xreg, 580 VexSimdPrefix pre, VexOpcode opc, bool rex_w); 581 int rex_prefix_and_encode(int dst_enc, int src_enc, 582 VexSimdPrefix pre, VexOpcode opc, bool rex_w); 583 584 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, 585 int nds_enc, VexSimdPrefix pre, VexOpcode opc, 586 bool vector256); 587 588 void vex_prefix(Address adr, int nds_enc, int xreg_enc, 589 VexSimdPrefix pre, VexOpcode opc, 590 bool vex_w, bool vector256); 591 592 void vex_prefix(XMMRegister dst, XMMRegister nds, Address src, 593 VexSimdPrefix pre, bool vector256 = false) { 594 int dst_enc = dst->encoding(); 595 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 596 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256); 597 } 598 599 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, 600 VexSimdPrefix pre, VexOpcode opc, 601 bool vex_w, bool vector256); 602 603 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, 604 VexSimdPrefix pre, bool vector256 = false, 605 VexOpcode opc = VEX_OPCODE_0F) { 606 int src_enc = src->encoding(); 607 int dst_enc = dst->encoding(); 608 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 609 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, false, vector256); 610 } 611 612 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, 613 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, 614 bool rex_w = false, bool vector256 = false); 615 616 void simd_prefix(XMMRegister dst, Address src, 617 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { 618 simd_prefix(dst, xnoreg, src, pre, opc); 619 } 620 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) { 621 simd_prefix(src, dst, pre); 622 } 623 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src, 624 VexSimdPrefix pre) { 625 bool rex_w = true; 626 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w); 627 } 628 629 630 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, 631 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, 632 bool rex_w = false, bool vector256 = false); 633 634 int simd_prefix_and_encode(XMMRegister dst, XMMRegister src, 635 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { 636 return simd_prefix_and_encode(dst, xnoreg, src, pre, opc); 637 } 638 639 // Move/convert 32-bit integer value. 640 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src, 641 VexSimdPrefix pre) { 642 // It is OK to cast from Register to XMMRegister to pass argument here 643 // since only encoding is used in simd_prefix_and_encode() and number of 644 // Gen and Xmm registers are the same. 645 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre); 646 } 647 int simd_prefix_and_encode(XMMRegister dst, Register src, VexSimdPrefix pre) { 648 return simd_prefix_and_encode(dst, xnoreg, src, pre); 649 } 650 int simd_prefix_and_encode(Register dst, XMMRegister src, 651 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { 652 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc); 653 } 654 655 // Move/convert 64-bit integer value. 656 int simd_prefix_and_encode_q(XMMRegister dst, XMMRegister nds, Register src, 657 VexSimdPrefix pre) { 658 bool rex_w = true; 659 return simd_prefix_and_encode(dst, nds, as_XMMRegister(src->encoding()), pre, VEX_OPCODE_0F, rex_w); 660 } 661 int simd_prefix_and_encode_q(XMMRegister dst, Register src, VexSimdPrefix pre) { 662 return simd_prefix_and_encode_q(dst, xnoreg, src, pre); 663 } 664 int simd_prefix_and_encode_q(Register dst, XMMRegister src, 665 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { 666 bool rex_w = true; 667 return simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, pre, opc, rex_w); 668 } 669 670 // Helper functions for groups of instructions 671 void emit_arith_b(int op1, int op2, Register dst, int imm8); 672 673 void emit_arith(int op1, int op2, Register dst, int32_t imm32); 674 // Force generation of a 4 byte immediate value even if it fits into 8bit 675 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); 676 // only 32bit?? 677 void emit_arith(int op1, int op2, Register dst, jobject obj); 678 void emit_arith(int op1, int op2, Register dst, Register src); 679 680 void emit_operand(Register reg, 681 Register base, Register index, Address::ScaleFactor scale, 682 int disp, 683 RelocationHolder const& rspec, 684 int rip_relative_correction = 0); 685 686 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); 687 688 // operands that only take the original 32bit registers 689 void emit_operand32(Register reg, Address adr); 690 691 void emit_operand(XMMRegister reg, 692 Register base, Register index, Address::ScaleFactor scale, 693 int disp, 694 RelocationHolder const& rspec); 695 696 void emit_operand(XMMRegister reg, Address adr); 697 698 void emit_operand(MMXRegister reg, Address adr); 699 700 // workaround gcc (3.2.1-7) bug 701 void emit_operand(Address adr, MMXRegister reg); 702 703 704 // Immediate-to-memory forms 705 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); 706 707 void emit_farith(int b1, int b2, int i); 708 709 710 protected: 711 #ifdef ASSERT 712 void check_relocation(RelocationHolder const& rspec, int format); 713 #endif 714 715 inline void emit_long64(jlong x); 716 717 void emit_data(jint data, relocInfo::relocType rtype, int format); 718 void emit_data(jint data, RelocationHolder const& rspec, int format); 719 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); 720 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); 721 722 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); 723 724 // These are all easily abused and hence protected 725 726 // 32BIT ONLY SECTION 727 #ifndef _LP64 728 // Make these disappear in 64bit mode since they would never be correct 729 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 730 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 731 732 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 733 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 734 735 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 736 #else 737 // 64BIT ONLY SECTION 738 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY 739 740 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); 741 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); 742 743 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); 744 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); 745 #endif // _LP64 746 747 // These are unique in that we are ensured by the caller that the 32bit 748 // relative in these instructions will always be able to reach the potentially 749 // 64bit address described by entry. Since they can take a 64bit address they 750 // don't have the 32 suffix like the other instructions in this class. 751 752 void call_literal(address entry, RelocationHolder const& rspec); 753 void jmp_literal(address entry, RelocationHolder const& rspec); 754 755 // Avoid using directly section 756 // Instructions in this section are actually usable by anyone without danger 757 // of failure but have performance issues that are addressed my enhanced 758 // instructions which will do the proper thing base on the particular cpu. 759 // We protect them because we don't trust you... 760 761 // Don't use next inc() and dec() methods directly. INC & DEC instructions 762 // could cause a partial flag stall since they don't set CF flag. 763 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods 764 // which call inc() & dec() or add() & sub() in accordance with 765 // the product flag UseIncDec value. 766 767 void decl(Register dst); 768 void decl(Address dst); 769 void decq(Register dst); 770 void decq(Address dst); 771 772 void incl(Register dst); 773 void incl(Address dst); 774 void incq(Register dst); 775 void incq(Address dst); 776 777 // New cpus require use of movsd and movss to avoid partial register stall 778 // when loading from memory. But for old Opteron use movlpd instead of movsd. 779 // The selection is done in MacroAssembler::movdbl() and movflt(). 780 781 // Move Scalar Single-Precision Floating-Point Values 782 void movss(XMMRegister dst, Address src); 783 void movss(XMMRegister dst, XMMRegister src); 784 void movss(Address dst, XMMRegister src); 785 786 // Move Scalar Double-Precision Floating-Point Values 787 void movsd(XMMRegister dst, Address src); 788 void movsd(XMMRegister dst, XMMRegister src); 789 void movsd(Address dst, XMMRegister src); 790 void movlpd(XMMRegister dst, Address src); 791 792 // New cpus require use of movaps and movapd to avoid partial register stall 793 // when moving between registers. 794 void movaps(XMMRegister dst, XMMRegister src); 795 void movapd(XMMRegister dst, XMMRegister src); 796 797 // End avoid using directly 798 799 800 // Instruction prefixes 801 void prefix(Prefix p); 802 803 public: 804 805 // Creation 806 Assembler(CodeBuffer* code) : AbstractAssembler(code) {} 807 808 // Decoding 809 static address locate_operand(address inst, WhichOperand which); 810 static address locate_next_instruction(address inst); 811 812 // Utilities 813 static bool is_polling_page_far() NOT_LP64({ return false;}); 814 815 // Generic instructions 816 // Does 32bit or 64bit as needed for the platform. In some sense these 817 // belong in macro assembler but there is no need for both varieties to exist 818 819 void lea(Register dst, Address src); 820 821 void mov(Register dst, Register src); 822 823 void pusha(); 824 void popa(); 825 826 void pushf(); 827 void popf(); 828 829 void push(int32_t imm32); 830 831 void push(Register src); 832 833 void pop(Register dst); 834 835 // These are dummies to prevent surprise implicit conversions to Register 836 void push(void* v); 837 void pop(void* v); 838 839 // These do register sized moves/scans 840 void rep_mov(); 841 void rep_set(); 842 void repne_scan(); 843 #ifdef _LP64 844 void repne_scanl(); 845 #endif 846 847 // Vanilla instructions in lexical order 848 849 void adcl(Address dst, int32_t imm32); 850 void adcl(Address dst, Register src); 851 void adcl(Register dst, int32_t imm32); 852 void adcl(Register dst, Address src); 853 void adcl(Register dst, Register src); 854 855 void adcq(Register dst, int32_t imm32); 856 void adcq(Register dst, Address src); 857 void adcq(Register dst, Register src); 858 859 void addl(Address dst, int32_t imm32); 860 void addl(Address dst, Register src); 861 void addl(Register dst, int32_t imm32); 862 void addl(Register dst, Address src); 863 void addl(Register dst, Register src); 864 865 void addq(Address dst, int32_t imm32); 866 void addq(Address dst, Register src); 867 void addq(Register dst, int32_t imm32); 868 void addq(Register dst, Address src); 869 void addq(Register dst, Register src); 870 871 void addr_nop_4(); 872 void addr_nop_5(); 873 void addr_nop_7(); 874 void addr_nop_8(); 875 876 // Add Scalar Double-Precision Floating-Point Values 877 void addsd(XMMRegister dst, Address src); 878 void addsd(XMMRegister dst, XMMRegister src); 879 880 // Add Scalar Single-Precision Floating-Point Values 881 void addss(XMMRegister dst, Address src); 882 void addss(XMMRegister dst, XMMRegister src); 883 884 void andl(Address dst, int32_t imm32); 885 void andl(Register dst, int32_t imm32); 886 void andl(Register dst, Address src); 887 void andl(Register dst, Register src); 888 889 void andq(Address dst, int32_t imm32); 890 void andq(Register dst, int32_t imm32); 891 void andq(Register dst, Address src); 892 void andq(Register dst, Register src); 893 894 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values 895 void andpd(XMMRegister dst, XMMRegister src); 896 897 // Bitwise Logical AND of Packed Single-Precision Floating-Point Values 898 void andps(XMMRegister dst, XMMRegister src); 899 900 void bsfl(Register dst, Register src); 901 void bsrl(Register dst, Register src); 902 903 #ifdef _LP64 904 void bsfq(Register dst, Register src); 905 void bsrq(Register dst, Register src); 906 #endif 907 908 void bswapl(Register reg); 909 910 void bswapq(Register reg); 911 912 void call(Label& L, relocInfo::relocType rtype); 913 void call(Register reg); // push pc; pc <- reg 914 void call(Address adr); // push pc; pc <- adr 915 916 void cdql(); 917 918 void cdqq(); 919 920 void cld() { emit_byte(0xfc); } 921 922 void clflush(Address adr); 923 924 void cmovl(Condition cc, Register dst, Register src); 925 void cmovl(Condition cc, Register dst, Address src); 926 927 void cmovq(Condition cc, Register dst, Register src); 928 void cmovq(Condition cc, Register dst, Address src); 929 930 931 void cmpb(Address dst, int imm8); 932 933 void cmpl(Address dst, int32_t imm32); 934 935 void cmpl(Register dst, int32_t imm32); 936 void cmpl(Register dst, Register src); 937 void cmpl(Register dst, Address src); 938 939 void cmpq(Address dst, int32_t imm32); 940 void cmpq(Address dst, Register src); 941 942 void cmpq(Register dst, int32_t imm32); 943 void cmpq(Register dst, Register src); 944 void cmpq(Register dst, Address src); 945 946 // these are dummies used to catch attempting to convert NULL to Register 947 void cmpl(Register dst, void* junk); // dummy 948 void cmpq(Register dst, void* junk); // dummy 949 950 void cmpw(Address dst, int imm16); 951 952 void cmpxchg8 (Address adr); 953 954 void cmpxchgl(Register reg, Address adr); 955 956 void cmpxchgq(Register reg, Address adr); 957 958 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS 959 void comisd(XMMRegister dst, Address src); 960 void comisd(XMMRegister dst, XMMRegister src); 961 962 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 963 void comiss(XMMRegister dst, Address src); 964 void comiss(XMMRegister dst, XMMRegister src); 965 966 // Identify processor type and features 967 void cpuid() { 968 emit_byte(0x0F); 969 emit_byte(0xA2); 970 } 971 972 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value 973 void cvtsd2ss(XMMRegister dst, XMMRegister src); 974 void cvtsd2ss(XMMRegister dst, Address src); 975 976 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value 977 void cvtsi2sdl(XMMRegister dst, Register src); 978 void cvtsi2sdl(XMMRegister dst, Address src); 979 void cvtsi2sdq(XMMRegister dst, Register src); 980 void cvtsi2sdq(XMMRegister dst, Address src); 981 982 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value 983 void cvtsi2ssl(XMMRegister dst, Register src); 984 void cvtsi2ssl(XMMRegister dst, Address src); 985 void cvtsi2ssq(XMMRegister dst, Register src); 986 void cvtsi2ssq(XMMRegister dst, Address src); 987 988 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value 989 void cvtdq2pd(XMMRegister dst, XMMRegister src); 990 991 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value 992 void cvtdq2ps(XMMRegister dst, XMMRegister src); 993 994 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value 995 void cvtss2sd(XMMRegister dst, XMMRegister src); 996 void cvtss2sd(XMMRegister dst, Address src); 997 998 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer 999 void cvttsd2sil(Register dst, Address src); 1000 void cvttsd2sil(Register dst, XMMRegister src); 1001 void cvttsd2siq(Register dst, XMMRegister src); 1002 1003 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer 1004 void cvttss2sil(Register dst, XMMRegister src); 1005 void cvttss2siq(Register dst, XMMRegister src); 1006 1007 // Divide Scalar Double-Precision Floating-Point Values 1008 void divsd(XMMRegister dst, Address src); 1009 void divsd(XMMRegister dst, XMMRegister src); 1010 1011 // Divide Scalar Single-Precision Floating-Point Values 1012 void divss(XMMRegister dst, Address src); 1013 void divss(XMMRegister dst, XMMRegister src); 1014 1015 void emms(); 1016 1017 void fabs(); 1018 1019 void fadd(int i); 1020 1021 void fadd_d(Address src); 1022 void fadd_s(Address src); 1023 1024 // "Alternate" versions of x87 instructions place result down in FPU 1025 // stack instead of on TOS 1026 1027 void fadda(int i); // "alternate" fadd 1028 void faddp(int i = 1); 1029 1030 void fchs(); 1031 1032 void fcom(int i); 1033 1034 void fcomp(int i = 1); 1035 void fcomp_d(Address src); 1036 void fcomp_s(Address src); 1037 1038 void fcompp(); 1039 1040 void fcos(); 1041 1042 void fdecstp(); 1043 1044 void fdiv(int i); 1045 void fdiv_d(Address src); 1046 void fdivr_s(Address src); 1047 void fdiva(int i); // "alternate" fdiv 1048 void fdivp(int i = 1); 1049 1050 void fdivr(int i); 1051 void fdivr_d(Address src); 1052 void fdiv_s(Address src); 1053 1054 void fdivra(int i); // "alternate" reversed fdiv 1055 1056 void fdivrp(int i = 1); 1057 1058 void ffree(int i = 0); 1059 1060 void fild_d(Address adr); 1061 void fild_s(Address adr); 1062 1063 void fincstp(); 1064 1065 void finit(); 1066 1067 void fist_s (Address adr); 1068 void fistp_d(Address adr); 1069 void fistp_s(Address adr); 1070 1071 void fld1(); 1072 1073 void fld_d(Address adr); 1074 void fld_s(Address adr); 1075 void fld_s(int index); 1076 void fld_x(Address adr); // extended-precision (80-bit) format 1077 1078 void fldcw(Address src); 1079 1080 void fldenv(Address src); 1081 1082 void fldlg2(); 1083 1084 void fldln2(); 1085 1086 void fldz(); 1087 1088 void flog(); 1089 void flog10(); 1090 1091 void fmul(int i); 1092 1093 void fmul_d(Address src); 1094 void fmul_s(Address src); 1095 1096 void fmula(int i); // "alternate" fmul 1097 1098 void fmulp(int i = 1); 1099 1100 void fnsave(Address dst); 1101 1102 void fnstcw(Address src); 1103 1104 void fnstsw_ax(); 1105 1106 void fprem(); 1107 void fprem1(); 1108 1109 void frstor(Address src); 1110 1111 void fsin(); 1112 1113 void fsqrt(); 1114 1115 void fst_d(Address adr); 1116 void fst_s(Address adr); 1117 1118 void fstp_d(Address adr); 1119 void fstp_d(int index); 1120 void fstp_s(Address adr); 1121 void fstp_x(Address adr); // extended-precision (80-bit) format 1122 1123 void fsub(int i); 1124 void fsub_d(Address src); 1125 void fsub_s(Address src); 1126 1127 void fsuba(int i); // "alternate" fsub 1128 1129 void fsubp(int i = 1); 1130 1131 void fsubr(int i); 1132 void fsubr_d(Address src); 1133 void fsubr_s(Address src); 1134 1135 void fsubra(int i); // "alternate" reversed fsub 1136 1137 void fsubrp(int i = 1); 1138 1139 void ftan(); 1140 1141 void ftst(); 1142 1143 void fucomi(int i = 1); 1144 void fucomip(int i = 1); 1145 1146 void fwait(); 1147 1148 void fxch(int i = 1); 1149 1150 void fxrstor(Address src); 1151 1152 void fxsave(Address dst); 1153 1154 void fyl2x(); 1155 void frndint(); 1156 void f2xm1(); 1157 void fldl2e(); 1158 1159 void hlt(); 1160 1161 void idivl(Register src); 1162 void divl(Register src); // Unsigned division 1163 1164 void idivq(Register src); 1165 1166 void imull(Register dst, Register src); 1167 void imull(Register dst, Register src, int value); 1168 1169 void imulq(Register dst, Register src); 1170 void imulq(Register dst, Register src, int value); 1171 1172 1173 // jcc is the generic conditional branch generator to run- 1174 // time routines, jcc is used for branches to labels. jcc 1175 // takes a branch opcode (cc) and a label (L) and generates 1176 // either a backward branch or a forward branch and links it 1177 // to the label fixup chain. Usage: 1178 // 1179 // Label L; // unbound label 1180 // jcc(cc, L); // forward branch to unbound label 1181 // bind(L); // bind label to the current pc 1182 // jcc(cc, L); // backward branch to bound label 1183 // bind(L); // illegal: a label may be bound only once 1184 // 1185 // Note: The same Label can be used for forward and backward branches 1186 // but it may be bound only once. 1187 1188 void jcc(Condition cc, Label& L, bool maybe_short = true); 1189 1190 // Conditional jump to a 8-bit offset to L. 1191 // WARNING: be very careful using this for forward jumps. If the label is 1192 // not bound within an 8-bit offset of this instruction, a run-time error 1193 // will occur. 1194 void jccb(Condition cc, Label& L); 1195 1196 void jmp(Address entry); // pc <- entry 1197 1198 // Label operations & relative jumps (PPUM Appendix D) 1199 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L 1200 1201 void jmp(Register entry); // pc <- entry 1202 1203 // Unconditional 8-bit offset jump to L. 1204 // WARNING: be very careful using this for forward jumps. If the label is 1205 // not bound within an 8-bit offset of this instruction, a run-time error 1206 // will occur. 1207 void jmpb(Label& L); 1208 1209 void ldmxcsr( Address src ); 1210 1211 void leal(Register dst, Address src); 1212 1213 void leaq(Register dst, Address src); 1214 1215 void lfence() { 1216 emit_byte(0x0F); 1217 emit_byte(0xAE); 1218 emit_byte(0xE8); 1219 } 1220 1221 void lock(); 1222 1223 void lzcntl(Register dst, Register src); 1224 1225 #ifdef _LP64 1226 void lzcntq(Register dst, Register src); 1227 #endif 1228 1229 enum Membar_mask_bits { 1230 StoreStore = 1 << 3, 1231 LoadStore = 1 << 2, 1232 StoreLoad = 1 << 1, 1233 LoadLoad = 1 << 0 1234 }; 1235 1236 // Serializes memory and blows flags 1237 void membar(Membar_mask_bits order_constraint) { 1238 if (os::is_MP()) { 1239 // We only have to handle StoreLoad 1240 if (order_constraint & StoreLoad) { 1241 // All usable chips support "locked" instructions which suffice 1242 // as barriers, and are much faster than the alternative of 1243 // using cpuid instruction. We use here a locked add [esp],0. 1244 // This is conveniently otherwise a no-op except for blowing 1245 // flags. 1246 // Any change to this code may need to revisit other places in 1247 // the code where this idiom is used, in particular the 1248 // orderAccess code. 1249 lock(); 1250 addl(Address(rsp, 0), 0);// Assert the lock# signal here 1251 } 1252 } 1253 } 1254 1255 void mfence(); 1256 1257 // Moves 1258 1259 void mov64(Register dst, int64_t imm64); 1260 1261 void movb(Address dst, Register src); 1262 void movb(Address dst, int imm8); 1263 void movb(Register dst, Address src); 1264 1265 void movdl(XMMRegister dst, Register src); 1266 void movdl(Register dst, XMMRegister src); 1267 void movdl(XMMRegister dst, Address src); 1268 void movdl(Address dst, XMMRegister src); 1269 1270 // Move Double Quadword 1271 void movdq(XMMRegister dst, Register src); 1272 void movdq(Register dst, XMMRegister src); 1273 1274 // Move Aligned Double Quadword 1275 void movdqa(XMMRegister dst, XMMRegister src); 1276 1277 // Move Unaligned Double Quadword 1278 void movdqu(Address dst, XMMRegister src); 1279 void movdqu(XMMRegister dst, Address src); 1280 void movdqu(XMMRegister dst, XMMRegister src); 1281 1282 // Move Unaligned 256bit Vector 1283 void vmovdqu(Address dst, XMMRegister src); 1284 void vmovdqu(XMMRegister dst, Address src); 1285 void vmovdqu(XMMRegister dst, XMMRegister src); 1286 1287 // Move lower 64bit to high 64bit in 128bit register 1288 void movlhps(XMMRegister dst, XMMRegister src); 1289 1290 void movl(Register dst, int32_t imm32); 1291 void movl(Address dst, int32_t imm32); 1292 void movl(Register dst, Register src); 1293 void movl(Register dst, Address src); 1294 void movl(Address dst, Register src); 1295 1296 // These dummies prevent using movl from converting a zero (like NULL) into Register 1297 // by giving the compiler two choices it can't resolve 1298 1299 void movl(Address dst, void* junk); 1300 void movl(Register dst, void* junk); 1301 1302 #ifdef _LP64 1303 void movq(Register dst, Register src); 1304 void movq(Register dst, Address src); 1305 void movq(Address dst, Register src); 1306 #endif 1307 1308 void movq(Address dst, MMXRegister src ); 1309 void movq(MMXRegister dst, Address src ); 1310 1311 #ifdef _LP64 1312 // These dummies prevent using movq from converting a zero (like NULL) into Register 1313 // by giving the compiler two choices it can't resolve 1314 1315 void movq(Address dst, void* dummy); 1316 void movq(Register dst, void* dummy); 1317 #endif 1318 1319 // Move Quadword 1320 void movq(Address dst, XMMRegister src); 1321 void movq(XMMRegister dst, Address src); 1322 1323 void movsbl(Register dst, Address src); 1324 void movsbl(Register dst, Register src); 1325 1326 #ifdef _LP64 1327 void movsbq(Register dst, Address src); 1328 void movsbq(Register dst, Register src); 1329 1330 // Move signed 32bit immediate to 64bit extending sign 1331 void movslq(Address dst, int32_t imm64); 1332 void movslq(Register dst, int32_t imm64); 1333 1334 void movslq(Register dst, Address src); 1335 void movslq(Register dst, Register src); 1336 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous 1337 #endif 1338 1339 void movswl(Register dst, Address src); 1340 void movswl(Register dst, Register src); 1341 1342 #ifdef _LP64 1343 void movswq(Register dst, Address src); 1344 void movswq(Register dst, Register src); 1345 #endif 1346 1347 void movw(Address dst, int imm16); 1348 void movw(Register dst, Address src); 1349 void movw(Address dst, Register src); 1350 1351 void movzbl(Register dst, Address src); 1352 void movzbl(Register dst, Register src); 1353 1354 #ifdef _LP64 1355 void movzbq(Register dst, Address src); 1356 void movzbq(Register dst, Register src); 1357 #endif 1358 1359 void movzwl(Register dst, Address src); 1360 void movzwl(Register dst, Register src); 1361 1362 #ifdef _LP64 1363 void movzwq(Register dst, Address src); 1364 void movzwq(Register dst, Register src); 1365 #endif 1366 1367 void mull(Address src); 1368 void mull(Register src); 1369 1370 // Multiply Scalar Double-Precision Floating-Point Values 1371 void mulsd(XMMRegister dst, Address src); 1372 void mulsd(XMMRegister dst, XMMRegister src); 1373 1374 // Multiply Scalar Single-Precision Floating-Point Values 1375 void mulss(XMMRegister dst, Address src); 1376 void mulss(XMMRegister dst, XMMRegister src); 1377 1378 void negl(Register dst); 1379 1380 #ifdef _LP64 1381 void negq(Register dst); 1382 #endif 1383 1384 void nop(int i = 1); 1385 1386 void notl(Register dst); 1387 1388 #ifdef _LP64 1389 void notq(Register dst); 1390 #endif 1391 1392 void orl(Address dst, int32_t imm32); 1393 void orl(Register dst, int32_t imm32); 1394 void orl(Register dst, Address src); 1395 void orl(Register dst, Register src); 1396 1397 void orq(Address dst, int32_t imm32); 1398 void orq(Register dst, int32_t imm32); 1399 void orq(Register dst, Address src); 1400 void orq(Register dst, Register src); 1401 1402 // Pack with unsigned saturation 1403 void packuswb(XMMRegister dst, XMMRegister src); 1404 void packuswb(XMMRegister dst, Address src); 1405 1406 // SSE4.2 string instructions 1407 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); 1408 void pcmpestri(XMMRegister xmm1, Address src, int imm8); 1409 1410 // SSE4.1 packed move 1411 void pmovzxbw(XMMRegister dst, XMMRegister src); 1412 void pmovzxbw(XMMRegister dst, Address src); 1413 1414 #ifndef _LP64 // no 32bit push/pop on amd64 1415 void popl(Address dst); 1416 #endif 1417 1418 #ifdef _LP64 1419 void popq(Address dst); 1420 #endif 1421 1422 void popcntl(Register dst, Address src); 1423 void popcntl(Register dst, Register src); 1424 1425 #ifdef _LP64 1426 void popcntq(Register dst, Address src); 1427 void popcntq(Register dst, Register src); 1428 #endif 1429 1430 // Prefetches (SSE, SSE2, 3DNOW only) 1431 1432 void prefetchnta(Address src); 1433 void prefetchr(Address src); 1434 void prefetcht0(Address src); 1435 void prefetcht1(Address src); 1436 void prefetcht2(Address src); 1437 void prefetchw(Address src); 1438 1439 // POR - Bitwise logical OR 1440 void por(XMMRegister dst, XMMRegister src); 1441 void por(XMMRegister dst, Address src); 1442 1443 // Shuffle Packed Doublewords 1444 void pshufd(XMMRegister dst, XMMRegister src, int mode); 1445 void pshufd(XMMRegister dst, Address src, int mode); 1446 1447 // Shuffle Packed Low Words 1448 void pshuflw(XMMRegister dst, XMMRegister src, int mode); 1449 void pshuflw(XMMRegister dst, Address src, int mode); 1450 1451 // Shift Right by bits Logical Quadword Immediate 1452 void psrlq(XMMRegister dst, int shift); 1453 1454 // Shift Right by bytes Logical DoubleQuadword Immediate 1455 void psrldq(XMMRegister dst, int shift); 1456 1457 // Logical Compare Double Quadword 1458 void ptest(XMMRegister dst, XMMRegister src); 1459 void ptest(XMMRegister dst, Address src); 1460 1461 // Interleave Low Bytes 1462 void punpcklbw(XMMRegister dst, XMMRegister src); 1463 void punpcklbw(XMMRegister dst, Address src); 1464 1465 // Interleave Low Doublewords 1466 void punpckldq(XMMRegister dst, XMMRegister src); 1467 void punpckldq(XMMRegister dst, Address src); 1468 1469 // Interleave Low Quadwords 1470 void punpcklqdq(XMMRegister dst, XMMRegister src); 1471 1472 #ifndef _LP64 // no 32bit push/pop on amd64 1473 void pushl(Address src); 1474 #endif 1475 1476 void pushq(Address src); 1477 1478 // Xor Packed Byte Integer Values 1479 void pxor(XMMRegister dst, Address src); 1480 void pxor(XMMRegister dst, XMMRegister src); 1481 1482 void rcll(Register dst, int imm8); 1483 1484 void rclq(Register dst, int imm8); 1485 1486 void ret(int imm16); 1487 1488 void sahf(); 1489 1490 void sarl(Register dst, int imm8); 1491 void sarl(Register dst); 1492 1493 void sarq(Register dst, int imm8); 1494 void sarq(Register dst); 1495 1496 void sbbl(Address dst, int32_t imm32); 1497 void sbbl(Register dst, int32_t imm32); 1498 void sbbl(Register dst, Address src); 1499 void sbbl(Register dst, Register src); 1500 1501 void sbbq(Address dst, int32_t imm32); 1502 void sbbq(Register dst, int32_t imm32); 1503 void sbbq(Register dst, Address src); 1504 void sbbq(Register dst, Register src); 1505 1506 void setb(Condition cc, Register dst); 1507 1508 void shldl(Register dst, Register src); 1509 1510 void shll(Register dst, int imm8); 1511 void shll(Register dst); 1512 1513 void shlq(Register dst, int imm8); 1514 void shlq(Register dst); 1515 1516 void shrdl(Register dst, Register src); 1517 1518 void shrl(Register dst, int imm8); 1519 void shrl(Register dst); 1520 1521 void shrq(Register dst, int imm8); 1522 void shrq(Register dst); 1523 1524 void smovl(); // QQQ generic? 1525 1526 // Compute Square Root of Scalar Double-Precision Floating-Point Value 1527 void sqrtsd(XMMRegister dst, Address src); 1528 void sqrtsd(XMMRegister dst, XMMRegister src); 1529 1530 // Compute Square Root of Scalar Single-Precision Floating-Point Value 1531 void sqrtss(XMMRegister dst, Address src); 1532 void sqrtss(XMMRegister dst, XMMRegister src); 1533 1534 void std() { emit_byte(0xfd); } 1535 1536 void stmxcsr( Address dst ); 1537 1538 void subl(Address dst, int32_t imm32); 1539 void subl(Address dst, Register src); 1540 void subl(Register dst, int32_t imm32); 1541 void subl(Register dst, Address src); 1542 void subl(Register dst, Register src); 1543 1544 void subq(Address dst, int32_t imm32); 1545 void subq(Address dst, Register src); 1546 void subq(Register dst, int32_t imm32); 1547 void subq(Register dst, Address src); 1548 void subq(Register dst, Register src); 1549 1550 // Force generation of a 4 byte immediate value even if it fits into 8bit 1551 void subl_imm32(Register dst, int32_t imm32); 1552 void subq_imm32(Register dst, int32_t imm32); 1553 1554 // Subtract Scalar Double-Precision Floating-Point Values 1555 void subsd(XMMRegister dst, Address src); 1556 void subsd(XMMRegister dst, XMMRegister src); 1557 1558 // Subtract Scalar Single-Precision Floating-Point Values 1559 void subss(XMMRegister dst, Address src); 1560 void subss(XMMRegister dst, XMMRegister src); 1561 1562 void testb(Register dst, int imm8); 1563 1564 void testl(Register dst, int32_t imm32); 1565 void testl(Register dst, Register src); 1566 void testl(Register dst, Address src); 1567 1568 void testq(Register dst, int32_t imm32); 1569 void testq(Register dst, Register src); 1570 1571 1572 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS 1573 void ucomisd(XMMRegister dst, Address src); 1574 void ucomisd(XMMRegister dst, XMMRegister src); 1575 1576 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 1577 void ucomiss(XMMRegister dst, Address src); 1578 void ucomiss(XMMRegister dst, XMMRegister src); 1579 1580 void xaddl(Address dst, Register src); 1581 1582 void xaddq(Address dst, Register src); 1583 1584 void xchgl(Register reg, Address adr); 1585 void xchgl(Register dst, Register src); 1586 1587 void xchgq(Register reg, Address adr); 1588 void xchgq(Register dst, Register src); 1589 1590 // Get Value of Extended Control Register 1591 void xgetbv() { 1592 emit_byte(0x0F); 1593 emit_byte(0x01); 1594 emit_byte(0xD0); 1595 } 1596 1597 void xorl(Register dst, int32_t imm32); 1598 void xorl(Register dst, Address src); 1599 void xorl(Register dst, Register src); 1600 1601 void xorq(Register dst, Address src); 1602 void xorq(Register dst, Register src); 1603 1604 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values 1605 void xorpd(XMMRegister dst, XMMRegister src); 1606 1607 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values 1608 void xorps(XMMRegister dst, XMMRegister src); 1609 1610 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 1611 1612 // AVX 3-operands scalar instructions (encoded with VEX prefix) 1613 void vaddsd(XMMRegister dst, XMMRegister nds, Address src); 1614 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 1615 void vaddss(XMMRegister dst, XMMRegister nds, Address src); 1616 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src); 1617 void vdivsd(XMMRegister dst, XMMRegister nds, Address src); 1618 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 1619 void vdivss(XMMRegister dst, XMMRegister nds, Address src); 1620 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src); 1621 void vmulsd(XMMRegister dst, XMMRegister nds, Address src); 1622 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 1623 void vmulss(XMMRegister dst, XMMRegister nds, Address src); 1624 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src); 1625 void vsubsd(XMMRegister dst, XMMRegister nds, Address src); 1626 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 1627 void vsubss(XMMRegister dst, XMMRegister nds, Address src); 1628 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); 1629 1630 // AVX Vector instrucitons. 1631 void vandpd(XMMRegister dst, XMMRegister nds, Address src); 1632 void vandps(XMMRegister dst, XMMRegister nds, Address src); 1633 void vxorpd(XMMRegister dst, XMMRegister nds, Address src); 1634 void vxorps(XMMRegister dst, XMMRegister nds, Address src); 1635 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1636 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1637 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1638 void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src); 1639 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src); 1640 1641 // AVX instruction which is used to clear upper 128 bits of YMM registers and 1642 // to avoid transaction penalty between AVX and SSE states. There is no 1643 // penalty if legacy SSE instructions are encoded using VEX prefix because 1644 // they always clear upper 128 bits. It should be used before calling 1645 // runtime code and native libraries. 1646 void vzeroupper(); 1647 1648 protected: 1649 // Next instructions require address alignment 16 bytes SSE mode. 1650 // They should be called only from corresponding MacroAssembler instructions. 1651 void andpd(XMMRegister dst, Address src); 1652 void andps(XMMRegister dst, Address src); 1653 void xorpd(XMMRegister dst, Address src); 1654 void xorps(XMMRegister dst, Address src); 1655 1656 }; 1657 1658 1659 // MacroAssembler extends Assembler by frequently used macros. 1660 // 1661 // Instructions for which a 'better' code sequence exists depending 1662 // on arguments should also go in here. 1663 1664 class MacroAssembler: public Assembler { 1665 friend class LIR_Assembler; 1666 friend class Runtime1; // as_Address() 1667 1668 protected: 1669 1670 Address as_Address(AddressLiteral adr); 1671 Address as_Address(ArrayAddress adr); 1672 1673 // Support for VM calls 1674 // 1675 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 1676 // may customize this version by overriding it for its purposes (e.g., to save/restore 1677 // additional registers when doing a VM call). 1678 #ifdef CC_INTERP 1679 // c++ interpreter never wants to use interp_masm version of call_VM 1680 #define VIRTUAL 1681 #else 1682 #define VIRTUAL virtual 1683 #endif 1684 1685 VIRTUAL void call_VM_leaf_base( 1686 address entry_point, // the entry point 1687 int number_of_arguments // the number of arguments to pop after the call 1688 ); 1689 1690 // This is the base routine called by the different versions of call_VM. The interpreter 1691 // may customize this version by overriding it for its purposes (e.g., to save/restore 1692 // additional registers when doing a VM call). 1693 // 1694 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base 1695 // returns the register which contains the thread upon return. If a thread register has been 1696 // specified, the return value will correspond to that register. If no last_java_sp is specified 1697 // (noreg) than rsp will be used instead. 1698 VIRTUAL void call_VM_base( // returns the register containing the thread upon return 1699 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 1700 Register java_thread, // the thread if computed before ; use noreg otherwise 1701 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 1702 address entry_point, // the entry point 1703 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 1704 bool check_exceptions // whether to check for pending exceptions after return 1705 ); 1706 1707 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 1708 // The implementation is only non-empty for the InterpreterMacroAssembler, 1709 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 1710 virtual void check_and_handle_popframe(Register java_thread); 1711 virtual void check_and_handle_earlyret(Register java_thread); 1712 1713 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 1714 1715 // helpers for FPU flag access 1716 // tmp is a temporary register, if none is available use noreg 1717 void save_rax (Register tmp); 1718 void restore_rax(Register tmp); 1719 1720 public: 1721 MacroAssembler(CodeBuffer* code) : Assembler(code) {} 1722 1723 // Support for NULL-checks 1724 // 1725 // Generates code that causes a NULL OS exception if the content of reg is NULL. 1726 // If the accessed location is M[reg + offset] and the offset is known, provide the 1727 // offset. No explicit code generation is needed if the offset is within a certain 1728 // range (0 <= offset <= page_size). 1729 1730 void null_check(Register reg, int offset = -1); 1731 static bool needs_explicit_null_check(intptr_t offset); 1732 1733 // Required platform-specific helpers for Label::patch_instructions. 1734 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 1735 void pd_patch_instruction(address branch, address target); 1736 #ifndef PRODUCT 1737 static void pd_print_patched_instruction(address branch); 1738 #endif 1739 1740 // The following 4 methods return the offset of the appropriate move instruction 1741 1742 // Support for fast byte/short loading with zero extension (depending on particular CPU) 1743 int load_unsigned_byte(Register dst, Address src); 1744 int load_unsigned_short(Register dst, Address src); 1745 1746 // Support for fast byte/short loading with sign extension (depending on particular CPU) 1747 int load_signed_byte(Register dst, Address src); 1748 int load_signed_short(Register dst, Address src); 1749 1750 // Support for sign-extension (hi:lo = extend_sign(lo)) 1751 void extend_sign(Register hi, Register lo); 1752 1753 // Load and store values by size and signed-ness 1754 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); 1755 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); 1756 1757 // Support for inc/dec with optimal instruction selection depending on value 1758 1759 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } 1760 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } 1761 1762 void decrementl(Address dst, int value = 1); 1763 void decrementl(Register reg, int value = 1); 1764 1765 void decrementq(Register reg, int value = 1); 1766 void decrementq(Address dst, int value = 1); 1767 1768 void incrementl(Address dst, int value = 1); 1769 void incrementl(Register reg, int value = 1); 1770 1771 void incrementq(Register reg, int value = 1); 1772 void incrementq(Address dst, int value = 1); 1773 1774 1775 // Support optimal SSE move instructions. 1776 void movflt(XMMRegister dst, XMMRegister src) { 1777 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } 1778 else { movss (dst, src); return; } 1779 } 1780 void movflt(XMMRegister dst, Address src) { movss(dst, src); } 1781 void movflt(XMMRegister dst, AddressLiteral src); 1782 void movflt(Address dst, XMMRegister src) { movss(dst, src); } 1783 1784 void movdbl(XMMRegister dst, XMMRegister src) { 1785 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } 1786 else { movsd (dst, src); return; } 1787 } 1788 1789 void movdbl(XMMRegister dst, AddressLiteral src); 1790 1791 void movdbl(XMMRegister dst, Address src) { 1792 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } 1793 else { movlpd(dst, src); return; } 1794 } 1795 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } 1796 1797 void incrementl(AddressLiteral dst); 1798 void incrementl(ArrayAddress dst); 1799 1800 // Alignment 1801 void align(int modulus); 1802 1803 // A 5 byte nop that is safe for patching (see patch_verified_entry) 1804 void fat_nop(); 1805 1806 // Stack frame creation/removal 1807 void enter(); 1808 void leave(); 1809 1810 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 1811 // The pointer will be loaded into the thread register. 1812 void get_thread(Register thread); 1813 1814 1815 // Support for VM calls 1816 // 1817 // It is imperative that all calls into the VM are handled via the call_VM macros. 1818 // They make sure that the stack linkage is setup correctly. call_VM's correspond 1819 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 1820 1821 1822 void call_VM(Register oop_result, 1823 address entry_point, 1824 bool check_exceptions = true); 1825 void call_VM(Register oop_result, 1826 address entry_point, 1827 Register arg_1, 1828 bool check_exceptions = true); 1829 void call_VM(Register oop_result, 1830 address entry_point, 1831 Register arg_1, Register arg_2, 1832 bool check_exceptions = true); 1833 void call_VM(Register oop_result, 1834 address entry_point, 1835 Register arg_1, Register arg_2, Register arg_3, 1836 bool check_exceptions = true); 1837 1838 // Overloadings with last_Java_sp 1839 void call_VM(Register oop_result, 1840 Register last_java_sp, 1841 address entry_point, 1842 int number_of_arguments = 0, 1843 bool check_exceptions = true); 1844 void call_VM(Register oop_result, 1845 Register last_java_sp, 1846 address entry_point, 1847 Register arg_1, bool 1848 check_exceptions = true); 1849 void call_VM(Register oop_result, 1850 Register last_java_sp, 1851 address entry_point, 1852 Register arg_1, Register arg_2, 1853 bool check_exceptions = true); 1854 void call_VM(Register oop_result, 1855 Register last_java_sp, 1856 address entry_point, 1857 Register arg_1, Register arg_2, Register arg_3, 1858 bool check_exceptions = true); 1859 1860 // These always tightly bind to MacroAssembler::call_VM_base 1861 // bypassing the virtual implementation 1862 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 1863 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 1864 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 1865 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 1866 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); 1867 1868 void call_VM_leaf(address entry_point, 1869 int number_of_arguments = 0); 1870 void call_VM_leaf(address entry_point, 1871 Register arg_1); 1872 void call_VM_leaf(address entry_point, 1873 Register arg_1, Register arg_2); 1874 void call_VM_leaf(address entry_point, 1875 Register arg_1, Register arg_2, Register arg_3); 1876 1877 // These always tightly bind to MacroAssembler::call_VM_leaf_base 1878 // bypassing the virtual implementation 1879 void super_call_VM_leaf(address entry_point); 1880 void super_call_VM_leaf(address entry_point, Register arg_1); 1881 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 1882 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 1883 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); 1884 1885 // last Java Frame (fills frame anchor) 1886 void set_last_Java_frame(Register thread, 1887 Register last_java_sp, 1888 Register last_java_fp, 1889 address last_java_pc); 1890 1891 // thread in the default location (r15_thread on 64bit) 1892 void set_last_Java_frame(Register last_java_sp, 1893 Register last_java_fp, 1894 address last_java_pc); 1895 1896 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); 1897 1898 // thread in the default location (r15_thread on 64bit) 1899 void reset_last_Java_frame(bool clear_fp, bool clear_pc); 1900 1901 // Stores 1902 void store_check(Register obj); // store check for obj - register is destroyed afterwards 1903 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 1904 1905 #ifndef SERIALGC 1906 1907 void g1_write_barrier_pre(Register obj, 1908 Register pre_val, 1909 Register thread, 1910 Register tmp, 1911 bool tosca_live, 1912 bool expand_call); 1913 1914 void g1_write_barrier_post(Register store_addr, 1915 Register new_val, 1916 Register thread, 1917 Register tmp, 1918 Register tmp2); 1919 1920 #endif // SERIALGC 1921 1922 // split store_check(Register obj) to enhance instruction interleaving 1923 void store_check_part_1(Register obj); 1924 void store_check_part_2(Register obj); 1925 1926 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 1927 void c2bool(Register x); 1928 1929 // C++ bool manipulation 1930 1931 void movbool(Register dst, Address src); 1932 void movbool(Address dst, bool boolconst); 1933 void movbool(Address dst, Register src); 1934 void testbool(Register dst); 1935 1936 // oop manipulations 1937 void load_klass(Register dst, Register src); 1938 void store_klass(Register dst, Register src); 1939 1940 void load_heap_oop(Register dst, Address src); 1941 void load_heap_oop_not_null(Register dst, Address src); 1942 void store_heap_oop(Address dst, Register src); 1943 1944 // Used for storing NULL. All other oop constants should be 1945 // stored using routines that take a jobject. 1946 void store_heap_oop_null(Address dst); 1947 1948 void load_prototype_header(Register dst, Register src); 1949 1950 #ifdef _LP64 1951 void store_klass_gap(Register dst, Register src); 1952 1953 // This dummy is to prevent a call to store_heap_oop from 1954 // converting a zero (like NULL) into a Register by giving 1955 // the compiler two choices it can't resolve 1956 1957 void store_heap_oop(Address dst, void* dummy); 1958 1959 void encode_heap_oop(Register r); 1960 void decode_heap_oop(Register r); 1961 void encode_heap_oop_not_null(Register r); 1962 void decode_heap_oop_not_null(Register r); 1963 void encode_heap_oop_not_null(Register dst, Register src); 1964 void decode_heap_oop_not_null(Register dst, Register src); 1965 1966 void set_narrow_oop(Register dst, jobject obj); 1967 void set_narrow_oop(Address dst, jobject obj); 1968 void cmp_narrow_oop(Register dst, jobject obj); 1969 void cmp_narrow_oop(Address dst, jobject obj); 1970 1971 // if heap base register is used - reinit it with the correct value 1972 void reinit_heapbase(); 1973 1974 DEBUG_ONLY(void verify_heapbase(const char* msg);) 1975 1976 #endif // _LP64 1977 1978 // Int division/remainder for Java 1979 // (as idivl, but checks for special case as described in JVM spec.) 1980 // returns idivl instruction offset for implicit exception handling 1981 int corrected_idivl(Register reg); 1982 1983 // Long division/remainder for Java 1984 // (as idivq, but checks for special case as described in JVM spec.) 1985 // returns idivq instruction offset for implicit exception handling 1986 int corrected_idivq(Register reg); 1987 1988 void int3(); 1989 1990 // Long operation macros for a 32bit cpu 1991 // Long negation for Java 1992 void lneg(Register hi, Register lo); 1993 1994 // Long multiplication for Java 1995 // (destroys contents of eax, ebx, ecx and edx) 1996 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y 1997 1998 // Long shifts for Java 1999 // (semantics as described in JVM spec.) 2000 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) 2001 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) 2002 2003 // Long compare for Java 2004 // (semantics as described in JVM spec.) 2005 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) 2006 2007 2008 // misc 2009 2010 // Sign extension 2011 void sign_extend_short(Register reg); 2012 void sign_extend_byte(Register reg); 2013 2014 // Division by power of 2, rounding towards 0 2015 void division_with_shift(Register reg, int shift_value); 2016 2017 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: 2018 // 2019 // CF (corresponds to C0) if x < y 2020 // PF (corresponds to C2) if unordered 2021 // ZF (corresponds to C3) if x = y 2022 // 2023 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 2024 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) 2025 void fcmp(Register tmp); 2026 // Variant of the above which allows y to be further down the stack 2027 // and which only pops x and y if specified. If pop_right is 2028 // specified then pop_left must also be specified. 2029 void fcmp(Register tmp, int index, bool pop_left, bool pop_right); 2030 2031 // Floating-point comparison for Java 2032 // Compares the top-most stack entries on the FPU stack and stores the result in dst. 2033 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 2034 // (semantics as described in JVM spec.) 2035 void fcmp2int(Register dst, bool unordered_is_less); 2036 // Variant of the above which allows y to be further down the stack 2037 // and which only pops x and y if specified. If pop_right is 2038 // specified then pop_left must also be specified. 2039 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); 2040 2041 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) 2042 // tmp is a temporary register, if none is available use noreg 2043 void fremr(Register tmp); 2044 2045 2046 // same as fcmp2int, but using SSE2 2047 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 2048 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 2049 2050 // Inlined sin/cos generator for Java; must not use CPU instruction 2051 // directly on Intel as it does not have high enough precision 2052 // outside of the range [-pi/4, pi/4]. Extra argument indicate the 2053 // number of FPU stack slots in use; all but the topmost will 2054 // require saving if a slow case is necessary. Assumes argument is 2055 // on FP TOS; result is on FP TOS. No cpu registers are changed by 2056 // this code. 2057 void trigfunc(char trig, int num_fpu_regs_in_use = 1); 2058 2059 // branch to L if FPU flag C2 is set/not set 2060 // tmp is a temporary register, if none is available use noreg 2061 void jC2 (Register tmp, Label& L); 2062 void jnC2(Register tmp, Label& L); 2063 2064 // Pop ST (ffree & fincstp combined) 2065 void fpop(); 2066 2067 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack 2068 void push_fTOS(); 2069 2070 // pops double TOS element from CPU stack and pushes on FPU stack 2071 void pop_fTOS(); 2072 2073 void empty_FPU_stack(); 2074 2075 void push_IU_state(); 2076 void pop_IU_state(); 2077 2078 void push_FPU_state(); 2079 void pop_FPU_state(); 2080 2081 void push_CPU_state(); 2082 void pop_CPU_state(); 2083 2084 // Round up to a power of two 2085 void round_to(Register reg, int modulus); 2086 2087 // Callee saved registers handling 2088 void push_callee_saved_registers(); 2089 void pop_callee_saved_registers(); 2090 2091 // allocation 2092 void eden_allocate( 2093 Register obj, // result: pointer to object after successful allocation 2094 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 2095 int con_size_in_bytes, // object size in bytes if known at compile time 2096 Register t1, // temp register 2097 Label& slow_case // continuation point if fast allocation fails 2098 ); 2099 void tlab_allocate( 2100 Register obj, // result: pointer to object after successful allocation 2101 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 2102 int con_size_in_bytes, // object size in bytes if known at compile time 2103 Register t1, // temp register 2104 Register t2, // temp register 2105 Label& slow_case // continuation point if fast allocation fails 2106 ); 2107 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address 2108 void incr_allocated_bytes(Register thread, 2109 Register var_size_in_bytes, int con_size_in_bytes, 2110 Register t1 = noreg); 2111 2112 // interface method calling 2113 void lookup_interface_method(Register recv_klass, 2114 Register intf_klass, 2115 RegisterOrConstant itable_index, 2116 Register method_result, 2117 Register scan_temp, 2118 Label& no_such_interface); 2119 2120 // Test sub_klass against super_klass, with fast and slow paths. 2121 2122 // The fast path produces a tri-state answer: yes / no / maybe-slow. 2123 // One of the three labels can be NULL, meaning take the fall-through. 2124 // If super_check_offset is -1, the value is loaded up from super_klass. 2125 // No registers are killed, except temp_reg. 2126 void check_klass_subtype_fast_path(Register sub_klass, 2127 Register super_klass, 2128 Register temp_reg, 2129 Label* L_success, 2130 Label* L_failure, 2131 Label* L_slow_path, 2132 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 2133 2134 // The rest of the type check; must be wired to a corresponding fast path. 2135 // It does not repeat the fast path logic, so don't use it standalone. 2136 // The temp_reg and temp2_reg can be noreg, if no temps are available. 2137 // Updates the sub's secondary super cache as necessary. 2138 // If set_cond_codes, condition codes will be Z on success, NZ on failure. 2139 void check_klass_subtype_slow_path(Register sub_klass, 2140 Register super_klass, 2141 Register temp_reg, 2142 Register temp2_reg, 2143 Label* L_success, 2144 Label* L_failure, 2145 bool set_cond_codes = false); 2146 2147 // Simplified, combined version, good for typical uses. 2148 // Falls through on failure. 2149 void check_klass_subtype(Register sub_klass, 2150 Register super_klass, 2151 Register temp_reg, 2152 Label& L_success); 2153 2154 // method handles (JSR 292) 2155 void check_method_handle_type(Register mtype_reg, Register mh_reg, 2156 Register temp_reg, 2157 Label& wrong_method_type); 2158 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, 2159 Register temp_reg); 2160 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg); 2161 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); 2162 2163 2164 //---- 2165 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 2166 2167 // Debugging 2168 2169 // only if +VerifyOops 2170 void verify_oop(Register reg, const char* s = "broken oop"); 2171 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); 2172 2173 // only if +VerifyFPU 2174 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); 2175 2176 // prints msg, dumps registers and stops execution 2177 void stop(const char* msg); 2178 2179 // prints msg and continues 2180 void warn(const char* msg); 2181 2182 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); 2183 static void debug64(char* msg, int64_t pc, int64_t regs[]); 2184 2185 void os_breakpoint(); 2186 2187 void untested() { stop("untested"); } 2188 2189 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } 2190 2191 void should_not_reach_here() { stop("should not reach here"); } 2192 2193 void print_CPU_state(); 2194 2195 // Stack overflow checking 2196 void bang_stack_with_offset(int offset) { 2197 // stack grows down, caller passes positive offset 2198 assert(offset > 0, "must bang with negative offset"); 2199 movl(Address(rsp, (-offset)), rax); 2200 } 2201 2202 // Writes to stack successive pages until offset reached to check for 2203 // stack overflow + shadow pages. Also, clobbers tmp 2204 void bang_stack_size(Register size, Register tmp); 2205 2206 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 2207 Register tmp, 2208 int offset); 2209 2210 // Support for serializing memory accesses between threads 2211 void serialize_memory(Register thread, Register tmp); 2212 2213 void verify_tlab(); 2214 2215 // Biased locking support 2216 // lock_reg and obj_reg must be loaded up with the appropriate values. 2217 // swap_reg must be rax, and is killed. 2218 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will 2219 // be killed; if not supplied, push/pop will be used internally to 2220 // allocate a temporary (inefficient, avoid if possible). 2221 // Optional slow case is for implementations (interpreter and C1) which branch to 2222 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. 2223 // Returns offset of first potentially-faulting instruction for null 2224 // check info (currently consumed only by C1). If 2225 // swap_reg_contains_mark is true then returns -1 as it is assumed 2226 // the calling code has already passed any potential faults. 2227 int biased_locking_enter(Register lock_reg, Register obj_reg, 2228 Register swap_reg, Register tmp_reg, 2229 bool swap_reg_contains_mark, 2230 Label& done, Label* slow_case = NULL, 2231 BiasedLockingCounters* counters = NULL); 2232 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); 2233 2234 2235 Condition negate_condition(Condition cond); 2236 2237 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit 2238 // operands. In general the names are modified to avoid hiding the instruction in Assembler 2239 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers 2240 // here in MacroAssembler. The major exception to this rule is call 2241 2242 // Arithmetics 2243 2244 2245 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } 2246 void addptr(Address dst, Register src); 2247 2248 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } 2249 void addptr(Register dst, int32_t src); 2250 void addptr(Register dst, Register src); 2251 void addptr(Register dst, RegisterOrConstant src) { 2252 if (src.is_constant()) addptr(dst, (int) src.as_constant()); 2253 else addptr(dst, src.as_register()); 2254 } 2255 2256 void andptr(Register dst, int32_t src); 2257 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } 2258 2259 void cmp8(AddressLiteral src1, int imm); 2260 2261 // renamed to drag out the casting of address to int32_t/intptr_t 2262 void cmp32(Register src1, int32_t imm); 2263 2264 void cmp32(AddressLiteral src1, int32_t imm); 2265 // compare reg - mem, or reg - &mem 2266 void cmp32(Register src1, AddressLiteral src2); 2267 2268 void cmp32(Register src1, Address src2); 2269 2270 #ifndef _LP64 2271 void cmpoop(Address dst, jobject obj); 2272 void cmpoop(Register dst, jobject obj); 2273 #endif // _LP64 2274 2275 // NOTE src2 must be the lval. This is NOT an mem-mem compare 2276 void cmpptr(Address src1, AddressLiteral src2); 2277 2278 void cmpptr(Register src1, AddressLiteral src2); 2279 2280 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 2281 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 2282 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 2283 2284 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 2285 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 2286 2287 // cmp64 to avoild hiding cmpq 2288 void cmp64(Register src1, AddressLiteral src); 2289 2290 void cmpxchgptr(Register reg, Address adr); 2291 2292 void locked_cmpxchgptr(Register reg, AddressLiteral adr); 2293 2294 2295 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } 2296 2297 2298 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } 2299 2300 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } 2301 2302 void shlptr(Register dst, int32_t shift); 2303 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } 2304 2305 void shrptr(Register dst, int32_t shift); 2306 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } 2307 2308 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } 2309 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } 2310 2311 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 2312 2313 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 2314 void subptr(Register dst, int32_t src); 2315 // Force generation of a 4 byte immediate value even if it fits into 8bit 2316 void subptr_imm32(Register dst, int32_t src); 2317 void subptr(Register dst, Register src); 2318 void subptr(Register dst, RegisterOrConstant src) { 2319 if (src.is_constant()) subptr(dst, (int) src.as_constant()); 2320 else subptr(dst, src.as_register()); 2321 } 2322 2323 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } 2324 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } 2325 2326 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } 2327 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } 2328 2329 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } 2330 2331 2332 2333 // Helper functions for statistics gathering. 2334 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. 2335 void cond_inc32(Condition cond, AddressLiteral counter_addr); 2336 // Unconditional atomic increment. 2337 void atomic_incl(AddressLiteral counter_addr); 2338 2339 void lea(Register dst, AddressLiteral adr); 2340 void lea(Address dst, AddressLiteral adr); 2341 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } 2342 2343 void leal32(Register dst, Address src) { leal(dst, src); } 2344 2345 // Import other testl() methods from the parent class or else 2346 // they will be hidden by the following overriding declaration. 2347 using Assembler::testl; 2348 void testl(Register dst, AddressLiteral src); 2349 2350 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 2351 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 2352 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 2353 2354 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } 2355 void testptr(Register src1, Register src2); 2356 2357 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } 2358 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } 2359 2360 // Calls 2361 2362 void call(Label& L, relocInfo::relocType rtype); 2363 void call(Register entry); 2364 2365 // NOTE: this call tranfers to the effective address of entry NOT 2366 // the address contained by entry. This is because this is more natural 2367 // for jumps/calls. 2368 void call(AddressLiteral entry); 2369 2370 // Jumps 2371 2372 // NOTE: these jumps tranfer to the effective address of dst NOT 2373 // the address contained by dst. This is because this is more natural 2374 // for jumps/calls. 2375 void jump(AddressLiteral dst); 2376 void jump_cc(Condition cc, AddressLiteral dst); 2377 2378 // 32bit can do a case table jump in one instruction but we no longer allow the base 2379 // to be installed in the Address class. This jump will tranfers to the address 2380 // contained in the location described by entry (not the address of entry) 2381 void jump(ArrayAddress entry); 2382 2383 // Floating 2384 2385 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } 2386 void andpd(XMMRegister dst, AddressLiteral src); 2387 2388 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); } 2389 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); } 2390 void andps(XMMRegister dst, AddressLiteral src); 2391 2392 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); } 2393 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } 2394 void comiss(XMMRegister dst, AddressLiteral src); 2395 2396 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); } 2397 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } 2398 void comisd(XMMRegister dst, AddressLiteral src); 2399 2400 void fadd_s(Address src) { Assembler::fadd_s(src); } 2401 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); } 2402 2403 void fldcw(Address src) { Assembler::fldcw(src); } 2404 void fldcw(AddressLiteral src); 2405 2406 void fld_s(int index) { Assembler::fld_s(index); } 2407 void fld_s(Address src) { Assembler::fld_s(src); } 2408 void fld_s(AddressLiteral src); 2409 2410 void fld_d(Address src) { Assembler::fld_d(src); } 2411 void fld_d(AddressLiteral src); 2412 2413 void fld_x(Address src) { Assembler::fld_x(src); } 2414 void fld_x(AddressLiteral src); 2415 2416 void fmul_s(Address src) { Assembler::fmul_s(src); } 2417 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); } 2418 2419 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } 2420 void ldmxcsr(AddressLiteral src); 2421 2422 // compute pow(x,y) and exp(x) with x86 instructions. Don't cover 2423 // all corner cases and may result in NaN and require fallback to a 2424 // runtime call. 2425 void fast_pow(); 2426 void fast_exp(); 2427 void increase_precision(); 2428 void restore_precision(); 2429 2430 // computes exp(x). Fallback to runtime call included. 2431 void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); } 2432 // computes pow(x,y). Fallback to runtime call included. 2433 void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); } 2434 2435 private: 2436 2437 // call runtime as a fallback for trig functions and pow/exp. 2438 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use); 2439 2440 // computes 2^(Ylog2X); Ylog2X in ST(0) 2441 void pow_exp_core_encoding(); 2442 2443 // computes pow(x,y) or exp(x). Fallback to runtime call included. 2444 void pow_or_exp(bool is_exp, int num_fpu_regs_in_use); 2445 2446 // these are private because users should be doing movflt/movdbl 2447 2448 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } 2449 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } 2450 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } 2451 void movss(XMMRegister dst, AddressLiteral src); 2452 2453 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } 2454 void movlpd(XMMRegister dst, AddressLiteral src); 2455 2456 public: 2457 2458 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); } 2459 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); } 2460 void addsd(XMMRegister dst, AddressLiteral src); 2461 2462 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); } 2463 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); } 2464 void addss(XMMRegister dst, AddressLiteral src); 2465 2466 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); } 2467 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); } 2468 void divsd(XMMRegister dst, AddressLiteral src); 2469 2470 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); } 2471 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); } 2472 void divss(XMMRegister dst, AddressLiteral src); 2473 2474 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } 2475 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } 2476 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } 2477 void movsd(XMMRegister dst, AddressLiteral src); 2478 2479 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); } 2480 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); } 2481 void mulsd(XMMRegister dst, AddressLiteral src); 2482 2483 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); } 2484 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); } 2485 void mulss(XMMRegister dst, AddressLiteral src); 2486 2487 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); } 2488 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); } 2489 void sqrtsd(XMMRegister dst, AddressLiteral src); 2490 2491 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); } 2492 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); } 2493 void sqrtss(XMMRegister dst, AddressLiteral src); 2494 2495 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); } 2496 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); } 2497 void subsd(XMMRegister dst, AddressLiteral src); 2498 2499 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); } 2500 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); } 2501 void subss(XMMRegister dst, AddressLiteral src); 2502 2503 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } 2504 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } 2505 void ucomiss(XMMRegister dst, AddressLiteral src); 2506 2507 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } 2508 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } 2509 void ucomisd(XMMRegister dst, AddressLiteral src); 2510 2511 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values 2512 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } 2513 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } 2514 void xorpd(XMMRegister dst, AddressLiteral src); 2515 2516 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values 2517 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } 2518 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } 2519 void xorps(XMMRegister dst, AddressLiteral src); 2520 2521 // AVX 3-operands instructions 2522 2523 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); } 2524 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); } 2525 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2526 2527 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); } 2528 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); } 2529 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2530 2531 void vandpd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vandpd(dst, nds, src); } 2532 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2533 2534 void vandps(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vandps(dst, nds, src); } 2535 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2536 2537 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); } 2538 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); } 2539 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2540 2541 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); } 2542 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); } 2543 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2544 2545 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); } 2546 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); } 2547 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2548 2549 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); } 2550 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); } 2551 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2552 2553 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); } 2554 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); } 2555 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2556 2557 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); } 2558 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); } 2559 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2560 2561 // AVX Vector instructions 2562 2563 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); } 2564 void vxorpd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vxorpd(dst, nds, src); } 2565 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2566 2567 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); } 2568 void vxorps(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vxorps(dst, nds, src); } 2569 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2570 2571 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { 2572 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2 2573 Assembler::vpxor(dst, nds, src, vector256); 2574 else 2575 Assembler::vxorpd(dst, nds, src, vector256); 2576 } 2577 2578 // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector. 2579 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { 2580 if (UseAVX > 1) // vinserti128h is available only in AVX2 2581 Assembler::vinserti128h(dst, nds, src); 2582 else 2583 Assembler::vinsertf128h(dst, nds, src); 2584 } 2585 2586 // Data 2587 2588 void cmov32( Condition cc, Register dst, Address src); 2589 void cmov32( Condition cc, Register dst, Register src); 2590 2591 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); } 2592 2593 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } 2594 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } 2595 2596 void movoop(Register dst, jobject obj); 2597 void movoop(Address dst, jobject obj); 2598 2599 void movptr(ArrayAddress dst, Register src); 2600 // can this do an lea? 2601 void movptr(Register dst, ArrayAddress src); 2602 2603 void movptr(Register dst, Address src); 2604 2605 void movptr(Register dst, AddressLiteral src); 2606 2607 void movptr(Register dst, intptr_t src); 2608 void movptr(Register dst, Register src); 2609 void movptr(Address dst, intptr_t src); 2610 2611 void movptr(Address dst, Register src); 2612 2613 void movptr(Register dst, RegisterOrConstant src) { 2614 if (src.is_constant()) movptr(dst, src.as_constant()); 2615 else movptr(dst, src.as_register()); 2616 } 2617 2618 #ifdef _LP64 2619 // Generally the next two are only used for moving NULL 2620 // Although there are situations in initializing the mark word where 2621 // they could be used. They are dangerous. 2622 2623 // They only exist on LP64 so that int32_t and intptr_t are not the same 2624 // and we have ambiguous declarations. 2625 2626 void movptr(Address dst, int32_t imm32); 2627 void movptr(Register dst, int32_t imm32); 2628 #endif // _LP64 2629 2630 // to avoid hiding movl 2631 void mov32(AddressLiteral dst, Register src); 2632 void mov32(Register dst, AddressLiteral src); 2633 2634 // to avoid hiding movb 2635 void movbyte(ArrayAddress dst, int src); 2636 2637 // Import other mov() methods from the parent class or else 2638 // they will be hidden by the following overriding declaration. 2639 using Assembler::movdl; 2640 using Assembler::movq; 2641 void movdl(XMMRegister dst, AddressLiteral src); 2642 void movq(XMMRegister dst, AddressLiteral src); 2643 2644 // Can push value or effective address 2645 void pushptr(AddressLiteral src); 2646 2647 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } 2648 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } 2649 2650 void pushoop(jobject obj); 2651 2652 // sign extend as need a l to ptr sized element 2653 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } 2654 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } 2655 2656 // C2 compiled method's prolog code. 2657 void verified_entry(int framesize, bool stack_bang, bool fp_mode_24b); 2658 2659 // IndexOf strings. 2660 // Small strings are loaded through stack if they cross page boundary. 2661 void string_indexof(Register str1, Register str2, 2662 Register cnt1, Register cnt2, 2663 int int_cnt2, Register result, 2664 XMMRegister vec, Register tmp); 2665 2666 // IndexOf for constant substrings with size >= 8 elements 2667 // which don't need to be loaded through stack. 2668 void string_indexofC8(Register str1, Register str2, 2669 Register cnt1, Register cnt2, 2670 int int_cnt2, Register result, 2671 XMMRegister vec, Register tmp); 2672 2673 // Smallest code: we don't need to load through stack, 2674 // check string tail. 2675 2676 // Compare strings. 2677 void string_compare(Register str1, Register str2, 2678 Register cnt1, Register cnt2, Register result, 2679 XMMRegister vec1); 2680 2681 // Compare char[] arrays. 2682 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, 2683 Register limit, Register result, Register chr, 2684 XMMRegister vec1, XMMRegister vec2); 2685 2686 // Fill primitive arrays 2687 void generate_fill(BasicType t, bool aligned, 2688 Register to, Register value, Register count, 2689 Register rtmp, XMMRegister xtmp); 2690 2691 #undef VIRTUAL 2692 2693 }; 2694 2695 /** 2696 * class SkipIfEqual: 2697 * 2698 * Instantiating this class will result in assembly code being output that will 2699 * jump around any code emitted between the creation of the instance and it's 2700 * automatic destruction at the end of a scope block, depending on the value of 2701 * the flag passed to the constructor, which will be checked at run-time. 2702 */ 2703 class SkipIfEqual { 2704 private: 2705 MacroAssembler* _masm; 2706 Label _label; 2707 2708 public: 2709 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); 2710 ~SkipIfEqual(); 2711 }; 2712 2713 #ifdef ASSERT 2714 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } 2715 #endif 2716 2717 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP