1 //
2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_FPU_size() {
232 if (Compile::current()->in_24_bit_fp_mode())
233 return 6; // fldcw
234 return 0;
235 }
236
237 static int preserve_SP_size() {
238 return 2; // op, rm(reg/reg)
239 }
240
241 // !!!!! Special hack to get all type of calls to specify the byte offset
242 // from the start of the call to the point where the return address
243 // will point.
244 int MachCallStaticJavaNode::ret_addr_offset() {
245 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
246 if (_method_handle_invoke)
247 offset += preserve_SP_size();
248 return offset;
249 }
250
251 int MachCallDynamicJavaNode::ret_addr_offset() {
252 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
253 }
254
255 static int sizeof_FFree_Float_Stack_All = -1;
256
257 int MachCallRuntimeNode::ret_addr_offset() {
258 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
259 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
260 }
261
262 // Indicate if the safepoint node needs the polling page as an input.
263 // Since x86 does have absolute addressing, it doesn't.
264 bool SafePointNode::needs_polling_address_input() {
265 return false;
266 }
267
268 //
269 // Compute padding required for nodes which need alignment
270 //
271
272 // The address of the call instruction needs to be 4-byte aligned to
273 // ensure that it does not span a cache line so that it can be patched.
274 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
275 current_offset += pre_call_FPU_size(); // skip fldcw, if any
276 current_offset += 1; // skip call opcode byte
277 return round_to(current_offset, alignment_required()) - current_offset;
278 }
279
280 // The address of the call instruction needs to be 4-byte aligned to
281 // ensure that it does not span a cache line so that it can be patched.
282 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
283 current_offset += pre_call_FPU_size(); // skip fldcw, if any
284 current_offset += preserve_SP_size(); // skip mov rbp, rsp
285 current_offset += 1; // skip call opcode byte
286 return round_to(current_offset, alignment_required()) - current_offset;
287 }
288
289 // The address of the call instruction needs to be 4-byte aligned to
290 // ensure that it does not span a cache line so that it can be patched.
291 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
292 current_offset += pre_call_FPU_size(); // skip fldcw, if any
293 current_offset += 5; // skip MOV instruction
294 current_offset += 1; // skip call opcode byte
295 return round_to(current_offset, alignment_required()) - current_offset;
296 }
297
298 // EMIT_RM()
299 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
300 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
301 cbuf.insts()->emit_int8(c);
302 }
303
304 // EMIT_CC()
305 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
306 unsigned char c = (unsigned char)( f1 | f2 );
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_OPCODE()
311 void emit_opcode(CodeBuffer &cbuf, int code) {
312 cbuf.insts()->emit_int8((unsigned char) code);
313 }
314
315 // EMIT_OPCODE() w/ relocation information
316 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
317 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
318 emit_opcode(cbuf, code);
319 }
320
321 // EMIT_D8()
322 void emit_d8(CodeBuffer &cbuf, int d8) {
323 cbuf.insts()->emit_int8((unsigned char) d8);
324 }
325
326 // EMIT_D16()
327 void emit_d16(CodeBuffer &cbuf, int d16) {
328 cbuf.insts()->emit_int16(d16);
329 }
330
331 // EMIT_D32()
332 void emit_d32(CodeBuffer &cbuf, int d32) {
333 cbuf.insts()->emit_int32(d32);
334 }
335
336 // emit 32 bit value and construct relocation entry from relocInfo::relocType
337 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
338 int format) {
339 cbuf.relocate(cbuf.insts_mark(), reloc, format);
340 cbuf.insts()->emit_int32(d32);
341 }
342
343 // emit 32 bit value and construct relocation entry from RelocationHolder
344 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
345 int format) {
346 #ifdef ASSERT
347 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
348 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
349 }
350 #endif
351 cbuf.relocate(cbuf.insts_mark(), rspec, format);
352 cbuf.insts()->emit_int32(d32);
353 }
354
355 // Access stack slot for load or store
356 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
357 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
358 if( -128 <= disp && disp <= 127 ) {
359 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
360 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
361 emit_d8 (cbuf, disp); // Displacement // R/M byte
362 } else {
363 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
364 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
365 emit_d32(cbuf, disp); // Displacement // R/M byte
366 }
367 }
368
369 // rRegI ereg, memory mem) %{ // emit_reg_mem
370 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
371 // There is no index & no scale, use form without SIB byte
372 if ((index == 0x4) &&
373 (scale == 0) && (base != ESP_enc)) {
374 // If no displacement, mode is 0x0; unless base is [EBP]
375 if ( (displace == 0) && (base != EBP_enc) ) {
376 emit_rm(cbuf, 0x0, reg_encoding, base);
377 }
378 else { // If 8-bit displacement, mode 0x1
379 if ((displace >= -128) && (displace <= 127)
380 && !(displace_is_oop) ) {
381 emit_rm(cbuf, 0x1, reg_encoding, base);
382 emit_d8(cbuf, displace);
383 }
384 else { // If 32-bit displacement
385 if (base == -1) { // Special flag for absolute address
386 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
387 // (manual lies; no SIB needed here)
388 if ( displace_is_oop ) {
389 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
390 } else {
391 emit_d32 (cbuf, displace);
392 }
393 }
394 else { // Normal base + offset
395 emit_rm(cbuf, 0x2, reg_encoding, base);
396 if ( displace_is_oop ) {
397 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
398 } else {
399 emit_d32 (cbuf, displace);
400 }
401 }
402 }
403 }
404 }
405 else { // Else, encode with the SIB byte
406 // If no displacement, mode is 0x0; unless base is [EBP]
407 if (displace == 0 && (base != EBP_enc)) { // If no displacement
408 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
409 emit_rm(cbuf, scale, index, base);
410 }
411 else { // If 8-bit displacement, mode 0x1
412 if ((displace >= -128) && (displace <= 127)
413 && !(displace_is_oop) ) {
414 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 emit_d8(cbuf, displace);
417 }
418 else { // If 32-bit displacement
419 if (base == 0x04 ) {
420 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, 0x04);
422 } else {
423 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
424 emit_rm(cbuf, scale, index, base);
425 }
426 if ( displace_is_oop ) {
427 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
428 } else {
429 emit_d32 (cbuf, displace);
430 }
431 }
432 }
433 }
434 }
435
436
437 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
438 if( dst_encoding == src_encoding ) {
439 // reg-reg copy, use an empty encoding
440 } else {
441 emit_opcode( cbuf, 0x8B );
442 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
443 }
444 }
445
446 void emit_cmpfp_fixup(MacroAssembler& _masm) {
447 Label exit;
448 __ jccb(Assembler::noParity, exit);
449 __ pushf();
450 //
451 // comiss/ucomiss instructions set ZF,PF,CF flags and
452 // zero OF,AF,SF for NaN values.
453 // Fixup flags by zeroing ZF,PF so that compare of NaN
454 // values returns 'less than' result (CF is set).
455 // Leave the rest of flags unchanged.
456 //
457 // 7 6 5 4 3 2 1 0
458 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
459 // 0 0 1 0 1 0 1 1 (0x2B)
460 //
461 __ andl(Address(rsp, 0), 0xffffff2b);
462 __ popf();
463 __ bind(exit);
464 }
465
466 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
467 Label done;
468 __ movl(dst, -1);
469 __ jcc(Assembler::parity, done);
470 __ jcc(Assembler::below, done);
471 __ setb(Assembler::notEqual, dst);
472 __ movzbl(dst, dst);
473 __ bind(done);
474 }
475
476
477 //=============================================================================
478 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
479
480 int Compile::ConstantTable::calculate_table_base_offset() const {
481 return 0; // absolute addressing, no offset
482 }
483
484 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
485 // Empty encoding
486 }
487
488 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
489 return 0;
490 }
491
492 #ifndef PRODUCT
493 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
494 st->print("# MachConstantBaseNode (empty encoding)");
495 }
496 #endif
497
498
499 //=============================================================================
500 #ifndef PRODUCT
501 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
502 Compile* C = ra_->C;
503
504 int framesize = C->frame_slots() << LogBytesPerInt;
505 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
506 // Remove wordSize for return addr which is already pushed.
507 framesize -= wordSize;
508
509 if (C->need_stack_bang(framesize)) {
510 framesize -= wordSize;
511 st->print("# stack bang");
512 st->print("\n\t");
513 st->print("PUSH EBP\t# Save EBP");
514 if (framesize) {
515 st->print("\n\t");
516 st->print("SUB ESP, #%d\t# Create frame",framesize);
517 }
518 } else {
519 st->print("SUB ESP, #%d\t# Create frame",framesize);
520 st->print("\n\t");
521 framesize -= wordSize;
522 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
523 }
524
525 if (VerifyStackAtCalls) {
526 st->print("\n\t");
527 framesize -= wordSize;
528 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
529 }
530
531 if( C->in_24_bit_fp_mode() ) {
532 st->print("\n\t");
533 st->print("FLDCW \t# load 24 bit fpu control word");
534 }
535 if (UseSSE >= 2 && VerifyFPU) {
536 st->print("\n\t");
537 st->print("# verify FPU stack (must be clean on entry)");
538 }
539
540 #ifdef ASSERT
541 if (VerifyStackAtCalls) {
542 st->print("\n\t");
543 st->print("# stack alignment check");
544 }
545 #endif
546 st->cr();
547 }
548 #endif
549
550
551 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
552 Compile* C = ra_->C;
553 MacroAssembler _masm(&cbuf);
554
555 int framesize = C->frame_slots() << LogBytesPerInt;
556
557 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
558
559 C->set_frame_complete(cbuf.insts_size());
560
561 if (C->has_mach_constant_base_node()) {
562 // NOTE: We set the table base offset here because users might be
563 // emitted before MachConstantBaseNode.
564 Compile::ConstantTable& constant_table = C->constant_table();
565 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
566 }
567 }
568
569 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
570 return MachNode::size(ra_); // too many variables; just compute it the hard way
571 }
572
573 int MachPrologNode::reloc() const {
574 return 0; // a large enough number
575 }
576
577 //=============================================================================
578 #ifndef PRODUCT
579 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
580 Compile *C = ra_->C;
581 int framesize = C->frame_slots() << LogBytesPerInt;
582 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
583 // Remove two words for return addr and rbp,
584 framesize -= 2*wordSize;
585
586 if( C->in_24_bit_fp_mode() ) {
587 st->print("FLDCW standard control word");
588 st->cr(); st->print("\t");
589 }
590 if( framesize ) {
591 st->print("ADD ESP,%d\t# Destroy frame",framesize);
592 st->cr(); st->print("\t");
593 }
594 st->print_cr("POPL EBP"); st->print("\t");
595 if( do_polling() && C->is_method_compilation() ) {
596 st->print("TEST PollPage,EAX\t! Poll Safepoint");
597 st->cr(); st->print("\t");
598 }
599 }
600 #endif
601
602 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
603 Compile *C = ra_->C;
604
605 // If method set FPU control word, restore to standard control word
606 if( C->in_24_bit_fp_mode() ) {
607 MacroAssembler masm(&cbuf);
608 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
609 }
610
611 int framesize = C->frame_slots() << LogBytesPerInt;
612 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
613 // Remove two words for return addr and rbp,
614 framesize -= 2*wordSize;
615
616 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
617
618 if( framesize >= 128 ) {
619 emit_opcode(cbuf, 0x81); // add SP, #framesize
620 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
621 emit_d32(cbuf, framesize);
622 }
623 else if( framesize ) {
624 emit_opcode(cbuf, 0x83); // add SP, #framesize
625 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
626 emit_d8(cbuf, framesize);
627 }
628
629 emit_opcode(cbuf, 0x58 | EBP_enc);
630
631 if( do_polling() && C->is_method_compilation() ) {
632 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
633 emit_opcode(cbuf,0x85);
634 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
635 emit_d32(cbuf, (intptr_t)os::get_polling_page());
636 }
637 }
638
639 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
640 Compile *C = ra_->C;
641 // If method set FPU control word, restore to standard control word
642 int size = C->in_24_bit_fp_mode() ? 6 : 0;
643 if( do_polling() && C->is_method_compilation() ) size += 6;
644
645 int framesize = C->frame_slots() << LogBytesPerInt;
646 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
647 // Remove two words for return addr and rbp,
648 framesize -= 2*wordSize;
649
650 size++; // popl rbp,
651
652 if( framesize >= 128 ) {
653 size += 6;
654 } else {
655 size += framesize ? 3 : 0;
656 }
657 return size;
658 }
659
660 int MachEpilogNode::reloc() const {
661 return 0; // a large enough number
662 }
663
664 const Pipeline * MachEpilogNode::pipeline() const {
665 return MachNode::pipeline_class();
666 }
667
668 int MachEpilogNode::safepoint_offset() const { return 0; }
669
670 //=============================================================================
671
672 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
673 static enum RC rc_class( OptoReg::Name reg ) {
674
675 if( !OptoReg::is_valid(reg) ) return rc_bad;
676 if (OptoReg::is_stack(reg)) return rc_stack;
677
678 VMReg r = OptoReg::as_VMReg(reg);
679 if (r->is_Register()) return rc_int;
680 if (r->is_FloatRegister()) {
681 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
682 return rc_float;
683 }
684 assert(r->is_XMMRegister(), "must be");
685 return rc_xmm;
686 }
687
688 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
689 int opcode, const char *op_str, int size, outputStream* st ) {
690 if( cbuf ) {
691 emit_opcode (*cbuf, opcode );
692 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
693 #ifndef PRODUCT
694 } else if( !do_size ) {
695 if( size != 0 ) st->print("\n\t");
696 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
697 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
698 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
699 } else { // FLD, FST, PUSH, POP
700 st->print("%s [ESP + #%d]",op_str,offset);
701 }
702 #endif
703 }
704 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
705 return size+3+offset_size;
706 }
707
708 // Helper for XMM registers. Extra opcode bits, limited syntax.
709 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
710 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
711 if (cbuf) {
712 MacroAssembler _masm(cbuf);
713 if (reg_lo+1 == reg_hi) { // double move?
714 if (is_load) {
715 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
716 } else {
717 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
718 }
719 } else {
720 if (is_load) {
721 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
722 } else {
723 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
724 }
725 }
726 #ifndef PRODUCT
727 } else if (!do_size) {
728 if (size != 0) st->print("\n\t");
729 if (reg_lo+1 == reg_hi) { // double move?
730 if (is_load) st->print("%s %s,[ESP + #%d]",
731 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
732 Matcher::regName[reg_lo], offset);
733 else st->print("MOVSD [ESP + #%d],%s",
734 offset, Matcher::regName[reg_lo]);
735 } else {
736 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
737 Matcher::regName[reg_lo], offset);
738 else st->print("MOVSS [ESP + #%d],%s",
739 offset, Matcher::regName[reg_lo]);
740 }
741 #endif
742 }
743 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
744 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
745 return size+5+offset_size;
746 }
747
748
749 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
750 int src_hi, int dst_hi, int size, outputStream* st ) {
751 if (cbuf) {
752 MacroAssembler _masm(cbuf);
753 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
754 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
755 as_XMMRegister(Matcher::_regEncode[src_lo]));
756 } else {
757 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
758 as_XMMRegister(Matcher::_regEncode[src_lo]));
759 }
760 #ifndef PRODUCT
761 } else if (!do_size) {
762 if (size != 0) st->print("\n\t");
763 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
764 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
765 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
766 } else {
767 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
768 }
769 } else {
770 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
771 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
772 } else {
773 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
774 }
775 }
776 #endif
777 }
778 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
779 // Only MOVAPS SSE prefix uses 1 byte.
780 int sz = 4;
781 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
782 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
783 return size + sz;
784 }
785
786 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
787 int src_hi, int dst_hi, int size, outputStream* st ) {
788 // 32-bit
789 if (cbuf) {
790 MacroAssembler _masm(cbuf);
791 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
792 as_Register(Matcher::_regEncode[src_lo]));
793 #ifndef PRODUCT
794 } else if (!do_size) {
795 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
796 #endif
797 }
798 return 4;
799 }
800
801
802 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
803 int src_hi, int dst_hi, int size, outputStream* st ) {
804 // 32-bit
805 if (cbuf) {
806 MacroAssembler _masm(cbuf);
807 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
808 as_XMMRegister(Matcher::_regEncode[src_lo]));
809 #ifndef PRODUCT
810 } else if (!do_size) {
811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
812 #endif
813 }
814 return 4;
815 }
816
817 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
818 if( cbuf ) {
819 emit_opcode(*cbuf, 0x8B );
820 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
821 #ifndef PRODUCT
822 } else if( !do_size ) {
823 if( size != 0 ) st->print("\n\t");
824 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
825 #endif
826 }
827 return size+2;
828 }
829
830 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
831 int offset, int size, outputStream* st ) {
832 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
833 if( cbuf ) {
834 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
835 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
836 #ifndef PRODUCT
837 } else if( !do_size ) {
838 if( size != 0 ) st->print("\n\t");
839 st->print("FLD %s",Matcher::regName[src_lo]);
840 #endif
841 }
842 size += 2;
843 }
844
845 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
846 const char *op_str;
847 int op;
848 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
849 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
850 op = 0xDD;
851 } else { // 32-bit store
852 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
853 op = 0xD9;
854 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
855 }
856
857 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
858 }
859
860 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
861 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
862 int src_hi, int dst_hi, uint ireg, outputStream* st);
863
864 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
865 int stack_offset, int reg, uint ireg, outputStream* st);
866
867 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
868 int dst_offset, uint ireg, outputStream* st) {
869 int calc_size = 0;
870 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
871 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
872 switch (ireg) {
873 case Op_VecS:
874 calc_size = 3+src_offset_size + 3+dst_offset_size;
875 break;
876 case Op_VecD:
877 calc_size = 3+src_offset_size + 3+dst_offset_size;
878 src_offset += 4;
879 dst_offset += 4;
880 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
881 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
882 calc_size += 3+src_offset_size + 3+dst_offset_size;
883 break;
884 case Op_VecX:
885 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
886 break;
887 case Op_VecY:
888 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
889 break;
890 default:
891 ShouldNotReachHere();
892 }
893 if (cbuf) {
894 MacroAssembler _masm(cbuf);
895 int offset = __ offset();
896 switch (ireg) {
897 case Op_VecS:
898 __ pushl(Address(rsp, src_offset));
899 __ popl (Address(rsp, dst_offset));
900 break;
901 case Op_VecD:
902 __ pushl(Address(rsp, src_offset));
903 __ popl (Address(rsp, dst_offset));
904 __ pushl(Address(rsp, src_offset+4));
905 __ popl (Address(rsp, dst_offset+4));
906 break;
907 case Op_VecX:
908 __ movdqu(Address(rsp, -16), xmm0);
909 __ movdqu(xmm0, Address(rsp, src_offset));
910 __ movdqu(Address(rsp, dst_offset), xmm0);
911 __ movdqu(xmm0, Address(rsp, -16));
912 break;
913 case Op_VecY:
914 __ vmovdqu(Address(rsp, -32), xmm0);
915 __ vmovdqu(xmm0, Address(rsp, src_offset));
916 __ vmovdqu(Address(rsp, dst_offset), xmm0);
917 __ vmovdqu(xmm0, Address(rsp, -32));
918 break;
919 default:
920 ShouldNotReachHere();
921 }
922 int size = __ offset() - offset;
923 assert(size == calc_size, "incorrect size calculattion");
924 return size;
925 #ifndef PRODUCT
926 } else if (!do_size) {
927 switch (ireg) {
928 case Op_VecS:
929 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
930 "popl [rsp + #%d]",
931 src_offset, dst_offset);
932 break;
933 case Op_VecD:
934 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
935 "popq [rsp + #%d]\n\t"
936 "pushl [rsp + #%d]\n\t"
937 "popq [rsp + #%d]",
938 src_offset, dst_offset, src_offset+4, dst_offset+4);
939 break;
940 case Op_VecX:
941 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
942 "movdqu xmm0, [rsp + #%d]\n\t"
943 "movdqu [rsp + #%d], xmm0\n\t"
944 "movdqu xmm0, [rsp - #16]",
945 src_offset, dst_offset);
946 break;
947 case Op_VecY:
948 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
949 "vmovdqu xmm0, [rsp + #%d]\n\t"
950 "vmovdqu [rsp + #%d], xmm0\n\t"
951 "vmovdqu xmm0, [rsp - #32]",
952 src_offset, dst_offset);
953 break;
954 default:
955 ShouldNotReachHere();
956 }
957 #endif
958 }
959 return calc_size;
960 }
961
962 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
963 // Get registers to move
964 OptoReg::Name src_second = ra_->get_reg_second(in(1));
965 OptoReg::Name src_first = ra_->get_reg_first(in(1));
966 OptoReg::Name dst_second = ra_->get_reg_second(this );
967 OptoReg::Name dst_first = ra_->get_reg_first(this );
968
969 enum RC src_second_rc = rc_class(src_second);
970 enum RC src_first_rc = rc_class(src_first);
971 enum RC dst_second_rc = rc_class(dst_second);
972 enum RC dst_first_rc = rc_class(dst_first);
973
974 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
975
976 // Generate spill code!
977 int size = 0;
978
979 if( src_first == dst_first && src_second == dst_second )
980 return size; // Self copy, no move
981
982 if (bottom_type()->isa_vect() != NULL) {
983 uint ireg = ideal_reg();
984 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
985 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
986 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
987 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
988 // mem -> mem
989 int src_offset = ra_->reg2offset(src_first);
990 int dst_offset = ra_->reg2offset(dst_first);
991 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
992 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
993 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
994 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
995 int stack_offset = ra_->reg2offset(dst_first);
996 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
997 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
998 int stack_offset = ra_->reg2offset(src_first);
999 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1000 } else {
1001 ShouldNotReachHere();
1002 }
1003 }
1004
1005 // --------------------------------------
1006 // Check for mem-mem move. push/pop to move.
1007 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1008 if( src_second == dst_first ) { // overlapping stack copy ranges
1009 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1010 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1011 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1012 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1013 }
1014 // move low bits
1015 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1016 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1017 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1018 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1019 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1020 }
1021 return size;
1022 }
1023
1024 // --------------------------------------
1025 // Check for integer reg-reg copy
1026 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1027 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1028
1029 // Check for integer store
1030 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1031 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1032
1033 // Check for integer load
1034 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1035 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1036
1037 // Check for integer reg-xmm reg copy
1038 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1039 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1040 "no 64 bit integer-float reg moves" );
1041 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1042 }
1043 // --------------------------------------
1044 // Check for float reg-reg copy
1045 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1046 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1047 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1048 if( cbuf ) {
1049
1050 // Note the mucking with the register encode to compensate for the 0/1
1051 // indexing issue mentioned in a comment in the reg_def sections
1052 // for FPR registers many lines above here.
1053
1054 if( src_first != FPR1L_num ) {
1055 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1056 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1057 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1058 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1059 } else {
1060 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1061 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1062 }
1063 #ifndef PRODUCT
1064 } else if( !do_size ) {
1065 if( size != 0 ) st->print("\n\t");
1066 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1067 else st->print( "FST %s", Matcher::regName[dst_first]);
1068 #endif
1069 }
1070 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1071 }
1072
1073 // Check for float store
1074 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1075 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1076 }
1077
1078 // Check for float load
1079 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1080 int offset = ra_->reg2offset(src_first);
1081 const char *op_str;
1082 int op;
1083 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1084 op_str = "FLD_D";
1085 op = 0xDD;
1086 } else { // 32-bit load
1087 op_str = "FLD_S";
1088 op = 0xD9;
1089 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1090 }
1091 if( cbuf ) {
1092 emit_opcode (*cbuf, op );
1093 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
1094 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1095 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1096 #ifndef PRODUCT
1097 } else if( !do_size ) {
1098 if( size != 0 ) st->print("\n\t");
1099 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1100 #endif
1101 }
1102 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1103 return size + 3+offset_size+2;
1104 }
1105
1106 // Check for xmm reg-reg copy
1107 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1108 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1109 (src_first+1 == src_second && dst_first+1 == dst_second),
1110 "no non-adjacent float-moves" );
1111 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1112 }
1113
1114 // Check for xmm reg-integer reg copy
1115 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1116 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1117 "no 64 bit float-integer reg moves" );
1118 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1119 }
1120
1121 // Check for xmm store
1122 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1123 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1124 }
1125
1126 // Check for float xmm load
1127 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1128 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1129 }
1130
1131 // Copy from float reg to xmm reg
1132 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1133 // copy to the top of stack from floating point reg
1134 // and use LEA to preserve flags
1135 if( cbuf ) {
1136 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1137 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1138 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1139 emit_d8(*cbuf,0xF8);
1140 #ifndef PRODUCT
1141 } else if( !do_size ) {
1142 if( size != 0 ) st->print("\n\t");
1143 st->print("LEA ESP,[ESP-8]");
1144 #endif
1145 }
1146 size += 4;
1147
1148 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1149
1150 // Copy from the temp memory to the xmm reg.
1151 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1152
1153 if( cbuf ) {
1154 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1155 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1156 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1157 emit_d8(*cbuf,0x08);
1158 #ifndef PRODUCT
1159 } else if( !do_size ) {
1160 if( size != 0 ) st->print("\n\t");
1161 st->print("LEA ESP,[ESP+8]");
1162 #endif
1163 }
1164 size += 4;
1165 return size;
1166 }
1167
1168 assert( size > 0, "missed a case" );
1169
1170 // --------------------------------------------------------------------
1171 // Check for second bits still needing moving.
1172 if( src_second == dst_second )
1173 return size; // Self copy; no move
1174 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1175
1176 // Check for second word int-int move
1177 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1178 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1179
1180 // Check for second word integer store
1181 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1182 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1183
1184 // Check for second word integer load
1185 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1186 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1187
1188
1189 Unimplemented();
1190 }
1191
1192 #ifndef PRODUCT
1193 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1194 implementation( NULL, ra_, false, st );
1195 }
1196 #endif
1197
1198 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1199 implementation( &cbuf, ra_, false, NULL );
1200 }
1201
1202 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1203 return implementation( NULL, ra_, true, NULL );
1204 }
1205
1206
1207 //=============================================================================
1208 #ifndef PRODUCT
1209 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1210 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1211 int reg = ra_->get_reg_first(this);
1212 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1213 }
1214 #endif
1215
1216 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1217 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1218 int reg = ra_->get_encode(this);
1219 if( offset >= 128 ) {
1220 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1221 emit_rm(cbuf, 0x2, reg, 0x04);
1222 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1223 emit_d32(cbuf, offset);
1224 }
1225 else {
1226 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1227 emit_rm(cbuf, 0x1, reg, 0x04);
1228 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1229 emit_d8(cbuf, offset);
1230 }
1231 }
1232
1233 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1234 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1235 if( offset >= 128 ) {
1236 return 7;
1237 }
1238 else {
1239 return 4;
1240 }
1241 }
1242
1243 //=============================================================================
1244
1245 // emit call stub, compiled java to interpreter
1246 void emit_java_to_interp(CodeBuffer &cbuf ) {
1247 // Stub is fixed up when the corresponding call is converted from calling
1248 // compiled code to calling interpreted code.
1249 // mov rbx,0
1250 // jmp -1
1251
1252 address mark = cbuf.insts_mark(); // get mark within main instrs section
1253
1254 // Note that the code buffer's insts_mark is always relative to insts.
1255 // That's why we must use the macroassembler to generate a stub.
1256 MacroAssembler _masm(&cbuf);
1257
1258 address base =
1259 __ start_a_stub(Compile::MAX_stubs_size);
1260 if (base == NULL) return; // CodeBuffer::expand failed
1261 // static stub relocation stores the instruction address of the call
1262 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1263 // static stub relocation also tags the methodOop in the code-stream.
1264 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1265 // This is recognized as unresolved by relocs/nativeInst/ic code
1266 __ jump(RuntimeAddress(__ pc()));
1267
1268 __ end_a_stub();
1269 // Update current stubs pointer and restore insts_end.
1270 }
1271 // size of call stub, compiled java to interpretor
1272 uint size_java_to_interp() {
1273 return 10; // movl; jmp
1274 }
1275 // relocation entries for call stub, compiled java to interpretor
1276 uint reloc_java_to_interp() {
1277 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1278 }
1279
1280 //=============================================================================
1281 #ifndef PRODUCT
1282 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1283 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1284 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1285 st->print_cr("\tNOP");
1286 st->print_cr("\tNOP");
1287 if( !OptoBreakpoint )
1288 st->print_cr("\tNOP");
1289 }
1290 #endif
1291
1292 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1293 MacroAssembler masm(&cbuf);
1294 #ifdef ASSERT
1295 uint insts_size = cbuf.insts_size();
1296 #endif
1297 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1298 masm.jump_cc(Assembler::notEqual,
1299 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1300 /* WARNING these NOPs are critical so that verified entry point is properly
1301 aligned for patching by NativeJump::patch_verified_entry() */
1302 int nops_cnt = 2;
1303 if( !OptoBreakpoint ) // Leave space for int3
1304 nops_cnt += 1;
1305 masm.nop(nops_cnt);
1306
1307 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1308 }
1309
1310 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1311 return OptoBreakpoint ? 11 : 12;
1312 }
1313
1314
1315 //=============================================================================
1316 uint size_exception_handler() {
1317 // NativeCall instruction size is the same as NativeJump.
1318 // exception handler starts out as jump and can be patched to
1319 // a call be deoptimization. (4932387)
1320 // Note that this value is also credited (in output.cpp) to
1321 // the size of the code section.
1322 return NativeJump::instruction_size;
1323 }
1324
1325 // Emit exception handler code. Stuff framesize into a register
1326 // and call a VM stub routine.
1327 int emit_exception_handler(CodeBuffer& cbuf) {
1328
1329 // Note that the code buffer's insts_mark is always relative to insts.
1330 // That's why we must use the macroassembler to generate a handler.
1331 MacroAssembler _masm(&cbuf);
1332 address base =
1333 __ start_a_stub(size_exception_handler());
1334 if (base == NULL) return 0; // CodeBuffer::expand failed
1335 int offset = __ offset();
1336 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1337 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1338 __ end_a_stub();
1339 return offset;
1340 }
1341
1342 uint size_deopt_handler() {
1343 // NativeCall instruction size is the same as NativeJump.
1344 // exception handler starts out as jump and can be patched to
1345 // a call be deoptimization. (4932387)
1346 // Note that this value is also credited (in output.cpp) to
1347 // the size of the code section.
1348 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1349 }
1350
1351 // Emit deopt handler code.
1352 int emit_deopt_handler(CodeBuffer& cbuf) {
1353
1354 // Note that the code buffer's insts_mark is always relative to insts.
1355 // That's why we must use the macroassembler to generate a handler.
1356 MacroAssembler _masm(&cbuf);
1357 address base =
1358 __ start_a_stub(size_exception_handler());
1359 if (base == NULL) return 0; // CodeBuffer::expand failed
1360 int offset = __ offset();
1361 InternalAddress here(__ pc());
1362 __ pushptr(here.addr());
1363
1364 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1365 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1366 __ end_a_stub();
1367 return offset;
1368 }
1369
1370
1371 const bool Matcher::match_rule_supported(int opcode) {
1372 if (!has_match_rule(opcode))
1373 return false;
1374
1375 switch (opcode) {
1376 case Op_PopCountI:
1377 case Op_PopCountL:
1378 if (!UsePopCountInstruction)
1379 return false;
1380 break;
1381 }
1382
1383 return true; // Per default match rules are supported.
1384 }
1385
1386 int Matcher::regnum_to_fpu_offset(int regnum) {
1387 return regnum - 32; // The FP registers are in the second chunk
1388 }
1389
1390 // This is UltraSparc specific, true just means we have fast l2f conversion
1391 const bool Matcher::convL2FSupported(void) {
1392 return true;
1393 }
1394
1395 // Is this branch offset short enough that a short branch can be used?
1396 //
1397 // NOTE: If the platform does not provide any short branch variants, then
1398 // this method should return false for offset 0.
1399 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1400 // The passed offset is relative to address of the branch.
1401 // On 86 a branch displacement is calculated relative to address
1402 // of a next instruction.
1403 offset -= br_size;
1404
1405 // the short version of jmpConUCF2 contains multiple branches,
1406 // making the reach slightly less
1407 if (rule == jmpConUCF2_rule)
1408 return (-126 <= offset && offset <= 125);
1409 return (-128 <= offset && offset <= 127);
1410 }
1411
1412 const bool Matcher::isSimpleConstant64(jlong value) {
1413 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1414 return false;
1415 }
1416
1417 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1418 const bool Matcher::init_array_count_is_in_bytes = false;
1419
1420 // Threshold size for cleararray.
1421 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1422
1423 // Needs 2 CMOV's for longs.
1424 const int Matcher::long_cmove_cost() { return 1; }
1425
1426 // No CMOVF/CMOVD with SSE/SSE2
1427 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1428
1429 // Should the Matcher clone shifts on addressing modes, expecting them to
1430 // be subsumed into complex addressing expressions or compute them into
1431 // registers? True for Intel but false for most RISCs
1432 const bool Matcher::clone_shift_expressions = true;
1433
1434 // Do we need to mask the count passed to shift instructions or does
1435 // the cpu only look at the lower 5/6 bits anyway?
1436 const bool Matcher::need_masked_shift_count = false;
1437
1438 bool Matcher::narrow_oop_use_complex_address() {
1439 ShouldNotCallThis();
1440 return true;
1441 }
1442
1443
1444 // Is it better to copy float constants, or load them directly from memory?
1445 // Intel can load a float constant from a direct address, requiring no
1446 // extra registers. Most RISCs will have to materialize an address into a
1447 // register first, so they would do better to copy the constant from stack.
1448 const bool Matcher::rematerialize_float_constants = true;
1449
1450 // If CPU can load and store mis-aligned doubles directly then no fixup is
1451 // needed. Else we split the double into 2 integer pieces and move it
1452 // piece-by-piece. Only happens when passing doubles into C code as the
1453 // Java calling convention forces doubles to be aligned.
1454 const bool Matcher::misaligned_doubles_ok = true;
1455
1456
1457 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1458 // Get the memory operand from the node
1459 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1460 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1461 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1462 uint opcnt = 1; // First operand
1463 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1464 while( idx >= skipped+num_edges ) {
1465 skipped += num_edges;
1466 opcnt++; // Bump operand count
1467 assert( opcnt < numopnds, "Accessing non-existent operand" );
1468 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1469 }
1470
1471 MachOper *memory = node->_opnds[opcnt];
1472 MachOper *new_memory = NULL;
1473 switch (memory->opcode()) {
1474 case DIRECT:
1475 case INDOFFSET32X:
1476 // No transformation necessary.
1477 return;
1478 case INDIRECT:
1479 new_memory = new (C) indirect_win95_safeOper( );
1480 break;
1481 case INDOFFSET8:
1482 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1483 break;
1484 case INDOFFSET32:
1485 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1486 break;
1487 case INDINDEXOFFSET:
1488 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1489 break;
1490 case INDINDEXSCALE:
1491 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1492 break;
1493 case INDINDEXSCALEOFFSET:
1494 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1495 break;
1496 case LOAD_LONG_INDIRECT:
1497 case LOAD_LONG_INDOFFSET32:
1498 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1499 return;
1500 default:
1501 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1502 return;
1503 }
1504 node->_opnds[opcnt] = new_memory;
1505 }
1506
1507 // Advertise here if the CPU requires explicit rounding operations
1508 // to implement the UseStrictFP mode.
1509 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1510
1511 // Are floats conerted to double when stored to stack during deoptimization?
1512 // On x32 it is stored with convertion only when FPU is used for floats.
1513 bool Matcher::float_in_double() { return (UseSSE == 0); }
1514
1515 // Do ints take an entire long register or just half?
1516 const bool Matcher::int_in_long = false;
1517
1518 // Return whether or not this register is ever used as an argument. This
1519 // function is used on startup to build the trampoline stubs in generateOptoStub.
1520 // Registers not mentioned will be killed by the VM call in the trampoline, and
1521 // arguments in those registers not be available to the callee.
1522 bool Matcher::can_be_java_arg( int reg ) {
1523 if( reg == ECX_num || reg == EDX_num ) return true;
1524 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1525 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1526 return false;
1527 }
1528
1529 bool Matcher::is_spillable_arg( int reg ) {
1530 return can_be_java_arg(reg);
1531 }
1532
1533 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1534 // Use hardware integer DIV instruction when
1535 // it is faster than a code which use multiply.
1536 // Only when constant divisor fits into 32 bit
1537 // (min_jint is excluded to get only correct
1538 // positive 32 bit values from negative).
1539 return VM_Version::has_fast_idiv() &&
1540 (divisor == (int)divisor && divisor != min_jint);
1541 }
1542
1543 // Register for DIVI projection of divmodI
1544 RegMask Matcher::divI_proj_mask() {
1545 return EAX_REG_mask();
1546 }
1547
1548 // Register for MODI projection of divmodI
1549 RegMask Matcher::modI_proj_mask() {
1550 return EDX_REG_mask();
1551 }
1552
1553 // Register for DIVL projection of divmodL
1554 RegMask Matcher::divL_proj_mask() {
1555 ShouldNotReachHere();
1556 return RegMask();
1557 }
1558
1559 // Register for MODL projection of divmodL
1560 RegMask Matcher::modL_proj_mask() {
1561 ShouldNotReachHere();
1562 return RegMask();
1563 }
1564
1565 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1566 return EBP_REG_mask();
1567 }
1568
1569 // Returns true if the high 32 bits of the value is known to be zero.
1570 bool is_operand_hi32_zero(Node* n) {
1571 int opc = n->Opcode();
1572 if (opc == Op_LoadUI2L) {
1573 return true;
1574 }
1575 if (opc == Op_AndL) {
1576 Node* o2 = n->in(2);
1577 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1578 return true;
1579 }
1580 }
1581 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1582 return true;
1583 }
1584 return false;
1585 }
1586
1587 %}
1588
1589 //----------ENCODING BLOCK-----------------------------------------------------
1590 // This block specifies the encoding classes used by the compiler to output
1591 // byte streams. Encoding classes generate functions which are called by
1592 // Machine Instruction Nodes in order to generate the bit encoding of the
1593 // instruction. Operands specify their base encoding interface with the
1594 // interface keyword. There are currently supported four interfaces,
1595 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1596 // operand to generate a function which returns its register number when
1597 // queried. CONST_INTER causes an operand to generate a function which
1598 // returns the value of the constant when queried. MEMORY_INTER causes an
1599 // operand to generate four functions which return the Base Register, the
1600 // Index Register, the Scale Value, and the Offset Value of the operand when
1601 // queried. COND_INTER causes an operand to generate six functions which
1602 // return the encoding code (ie - encoding bits for the instruction)
1603 // associated with each basic boolean condition for a conditional instruction.
1604 // Instructions specify two basic values for encoding. They use the
1605 // ins_encode keyword to specify their encoding class (which must be one of
1606 // the class names specified in the encoding block), and they use the
1607 // opcode keyword to specify, in order, their primary, secondary, and
1608 // tertiary opcode. Only the opcode sections which a particular instruction
1609 // needs for encoding need to be specified.
1610 encode %{
1611 // Build emit functions for each basic byte or larger field in the intel
1612 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1613 // code in the enc_class source block. Emit functions will live in the
1614 // main source block for now. In future, we can generalize this by
1615 // adding a syntax that specifies the sizes of fields in an order,
1616 // so that the adlc can build the emit functions automagically
1617
1618 // Emit primary opcode
1619 enc_class OpcP %{
1620 emit_opcode(cbuf, $primary);
1621 %}
1622
1623 // Emit secondary opcode
1624 enc_class OpcS %{
1625 emit_opcode(cbuf, $secondary);
1626 %}
1627
1628 // Emit opcode directly
1629 enc_class Opcode(immI d8) %{
1630 emit_opcode(cbuf, $d8$$constant);
1631 %}
1632
1633 enc_class SizePrefix %{
1634 emit_opcode(cbuf,0x66);
1635 %}
1636
1637 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1638 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1639 %}
1640
1641 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1642 emit_opcode(cbuf,$opcode$$constant);
1643 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1644 %}
1645
1646 enc_class mov_r32_imm0( rRegI dst ) %{
1647 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1648 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1649 %}
1650
1651 enc_class cdq_enc %{
1652 // Full implementation of Java idiv and irem; checks for
1653 // special case as described in JVM spec., p.243 & p.271.
1654 //
1655 // normal case special case
1656 //
1657 // input : rax,: dividend min_int
1658 // reg: divisor -1
1659 //
1660 // output: rax,: quotient (= rax, idiv reg) min_int
1661 // rdx: remainder (= rax, irem reg) 0
1662 //
1663 // Code sequnce:
1664 //
1665 // 81 F8 00 00 00 80 cmp rax,80000000h
1666 // 0F 85 0B 00 00 00 jne normal_case
1667 // 33 D2 xor rdx,edx
1668 // 83 F9 FF cmp rcx,0FFh
1669 // 0F 84 03 00 00 00 je done
1670 // normal_case:
1671 // 99 cdq
1672 // F7 F9 idiv rax,ecx
1673 // done:
1674 //
1675 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1676 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1677 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1678 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1679 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1680 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1681 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1682 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1683 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1684 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1685 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1686 // normal_case:
1687 emit_opcode(cbuf,0x99); // cdq
1688 // idiv (note: must be emitted by the user of this rule)
1689 // normal:
1690 %}
1691
1692 // Dense encoding for older common ops
1693 enc_class Opc_plus(immI opcode, rRegI reg) %{
1694 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1695 %}
1696
1697
1698 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1699 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1700 // Check for 8-bit immediate, and set sign extend bit in opcode
1701 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1702 emit_opcode(cbuf, $primary | 0x02);
1703 }
1704 else { // If 32-bit immediate
1705 emit_opcode(cbuf, $primary);
1706 }
1707 %}
1708
1709 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1710 // Emit primary opcode and set sign-extend bit
1711 // Check for 8-bit immediate, and set sign extend bit in opcode
1712 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1713 emit_opcode(cbuf, $primary | 0x02); }
1714 else { // If 32-bit immediate
1715 emit_opcode(cbuf, $primary);
1716 }
1717 // Emit r/m byte with secondary opcode, after primary opcode.
1718 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1719 %}
1720
1721 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1722 // Check for 8-bit immediate, and set sign extend bit in opcode
1723 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1724 $$$emit8$imm$$constant;
1725 }
1726 else { // If 32-bit immediate
1727 // Output immediate
1728 $$$emit32$imm$$constant;
1729 }
1730 %}
1731
1732 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1733 // Emit primary opcode and set sign-extend bit
1734 // Check for 8-bit immediate, and set sign extend bit in opcode
1735 int con = (int)$imm$$constant; // Throw away top bits
1736 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1737 // Emit r/m byte with secondary opcode, after primary opcode.
1738 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1739 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1740 else emit_d32(cbuf,con);
1741 %}
1742
1743 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1744 // Emit primary opcode and set sign-extend bit
1745 // Check for 8-bit immediate, and set sign extend bit in opcode
1746 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1747 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1748 // Emit r/m byte with tertiary opcode, after primary opcode.
1749 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1750 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1751 else emit_d32(cbuf,con);
1752 %}
1753
1754 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1755 emit_cc(cbuf, $secondary, $dst$$reg );
1756 %}
1757
1758 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1759 int destlo = $dst$$reg;
1760 int desthi = HIGH_FROM_LOW(destlo);
1761 // bswap lo
1762 emit_opcode(cbuf, 0x0F);
1763 emit_cc(cbuf, 0xC8, destlo);
1764 // bswap hi
1765 emit_opcode(cbuf, 0x0F);
1766 emit_cc(cbuf, 0xC8, desthi);
1767 // xchg lo and hi
1768 emit_opcode(cbuf, 0x87);
1769 emit_rm(cbuf, 0x3, destlo, desthi);
1770 %}
1771
1772 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1773 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1774 %}
1775
1776 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1777 $$$emit8$primary;
1778 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1779 %}
1780
1781 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1782 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1783 emit_d8(cbuf, op >> 8 );
1784 emit_d8(cbuf, op & 255);
1785 %}
1786
1787 // emulate a CMOV with a conditional branch around a MOV
1788 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1789 // Invert sense of branch from sense of CMOV
1790 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1791 emit_d8( cbuf, $brOffs$$constant );
1792 %}
1793
1794 enc_class enc_PartialSubtypeCheck( ) %{
1795 Register Redi = as_Register(EDI_enc); // result register
1796 Register Reax = as_Register(EAX_enc); // super class
1797 Register Recx = as_Register(ECX_enc); // killed
1798 Register Resi = as_Register(ESI_enc); // sub class
1799 Label miss;
1800
1801 MacroAssembler _masm(&cbuf);
1802 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1803 NULL, &miss,
1804 /*set_cond_codes:*/ true);
1805 if ($primary) {
1806 __ xorptr(Redi, Redi);
1807 }
1808 __ bind(miss);
1809 %}
1810
1811 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1812 MacroAssembler masm(&cbuf);
1813 int start = masm.offset();
1814 if (UseSSE >= 2) {
1815 if (VerifyFPU) {
1816 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1817 }
1818 } else {
1819 // External c_calling_convention expects the FPU stack to be 'clean'.
1820 // Compiled code leaves it dirty. Do cleanup now.
1821 masm.empty_FPU_stack();
1822 }
1823 if (sizeof_FFree_Float_Stack_All == -1) {
1824 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1825 } else {
1826 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1827 }
1828 %}
1829
1830 enc_class Verify_FPU_For_Leaf %{
1831 if( VerifyFPU ) {
1832 MacroAssembler masm(&cbuf);
1833 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1834 }
1835 %}
1836
1837 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1838 // This is the instruction starting address for relocation info.
1839 cbuf.set_insts_mark();
1840 $$$emit8$primary;
1841 // CALL directly to the runtime
1842 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1843 runtime_call_Relocation::spec(), RELOC_IMM32 );
1844
1845 if (UseSSE >= 2) {
1846 MacroAssembler _masm(&cbuf);
1847 BasicType rt = tf()->return_type();
1848
1849 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1850 // A C runtime call where the return value is unused. In SSE2+
1851 // mode the result needs to be removed from the FPU stack. It's
1852 // likely that this function call could be removed by the
1853 // optimizer if the C function is a pure function.
1854 __ ffree(0);
1855 } else if (rt == T_FLOAT) {
1856 __ lea(rsp, Address(rsp, -4));
1857 __ fstp_s(Address(rsp, 0));
1858 __ movflt(xmm0, Address(rsp, 0));
1859 __ lea(rsp, Address(rsp, 4));
1860 } else if (rt == T_DOUBLE) {
1861 __ lea(rsp, Address(rsp, -8));
1862 __ fstp_d(Address(rsp, 0));
1863 __ movdbl(xmm0, Address(rsp, 0));
1864 __ lea(rsp, Address(rsp, 8));
1865 }
1866 }
1867 %}
1868
1869
1870 enc_class pre_call_FPU %{
1871 // If method sets FPU control word restore it here
1872 debug_only(int off0 = cbuf.insts_size());
1873 if( Compile::current()->in_24_bit_fp_mode() ) {
1874 MacroAssembler masm(&cbuf);
1875 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1876 }
1877 debug_only(int off1 = cbuf.insts_size());
1878 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1879 %}
1880
1881 enc_class post_call_FPU %{
1882 // If method sets FPU control word do it here also
1883 if( Compile::current()->in_24_bit_fp_mode() ) {
1884 MacroAssembler masm(&cbuf);
1885 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1886 }
1887 %}
1888
1889 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1890 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1891 // who we intended to call.
1892 cbuf.set_insts_mark();
1893 $$$emit8$primary;
1894 if ( !_method ) {
1895 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1896 runtime_call_Relocation::spec(), RELOC_IMM32 );
1897 } else if(_optimized_virtual) {
1898 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1899 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1900 } else {
1901 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1902 static_call_Relocation::spec(), RELOC_IMM32 );
1903 }
1904 if( _method ) { // Emit stub for static call
1905 emit_java_to_interp(cbuf);
1906 }
1907 %}
1908
1909 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1910 // !!!!!
1911 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1912 // emit_call_dynamic_prologue( cbuf );
1913 cbuf.set_insts_mark();
1914 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1915 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1916 address virtual_call_oop_addr = cbuf.insts_mark();
1917 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1918 // who we intended to call.
1919 cbuf.set_insts_mark();
1920 $$$emit8$primary;
1921 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1922 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1923 %}
1924
1925 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1926 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1927 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1928
1929 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1930 cbuf.set_insts_mark();
1931 $$$emit8$primary;
1932 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1933 emit_d8(cbuf, disp); // Displacement
1934
1935 %}
1936
1937 // Following encoding is no longer used, but may be restored if calling
1938 // convention changes significantly.
1939 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1940 //
1941 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1942 // // int ic_reg = Matcher::inline_cache_reg();
1943 // // int ic_encode = Matcher::_regEncode[ic_reg];
1944 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1945 // // int imo_encode = Matcher::_regEncode[imo_reg];
1946 //
1947 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1948 // // // so we load it immediately before the call
1949 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1950 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1951 //
1952 // // xor rbp,ebp
1953 // emit_opcode(cbuf, 0x33);
1954 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1955 //
1956 // // CALL to interpreter.
1957 // cbuf.set_insts_mark();
1958 // $$$emit8$primary;
1959 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1960 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1961 // %}
1962
1963 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1964 $$$emit8$primary;
1965 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1966 $$$emit8$shift$$constant;
1967 %}
1968
1969 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1970 // Load immediate does not have a zero or sign extended version
1971 // for 8-bit immediates
1972 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1973 $$$emit32$src$$constant;
1974 %}
1975
1976 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1977 // Load immediate does not have a zero or sign extended version
1978 // for 8-bit immediates
1979 emit_opcode(cbuf, $primary + $dst$$reg);
1980 $$$emit32$src$$constant;
1981 %}
1982
1983 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1984 // Load immediate does not have a zero or sign extended version
1985 // for 8-bit immediates
1986 int dst_enc = $dst$$reg;
1987 int src_con = $src$$constant & 0x0FFFFFFFFL;
1988 if (src_con == 0) {
1989 // xor dst, dst
1990 emit_opcode(cbuf, 0x33);
1991 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1992 } else {
1993 emit_opcode(cbuf, $primary + dst_enc);
1994 emit_d32(cbuf, src_con);
1995 }
1996 %}
1997
1998 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1999 // Load immediate does not have a zero or sign extended version
2000 // for 8-bit immediates
2001 int dst_enc = $dst$$reg + 2;
2002 int src_con = ((julong)($src$$constant)) >> 32;
2003 if (src_con == 0) {
2004 // xor dst, dst
2005 emit_opcode(cbuf, 0x33);
2006 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
2007 } else {
2008 emit_opcode(cbuf, $primary + dst_enc);
2009 emit_d32(cbuf, src_con);
2010 }
2011 %}
2012
2013
2014 // Encode a reg-reg copy. If it is useless, then empty encoding.
2015 enc_class enc_Copy( rRegI dst, rRegI src ) %{
2016 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2017 %}
2018
2019 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
2020 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2021 %}
2022
2023 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
2024 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2025 %}
2026
2027 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2028 $$$emit8$primary;
2029 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2030 %}
2031
2032 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2033 $$$emit8$secondary;
2034 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2035 %}
2036
2037 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2038 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2039 %}
2040
2041 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2042 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2043 %}
2044
2045 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2046 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2047 %}
2048
2049 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2050 // Output immediate
2051 $$$emit32$src$$constant;
2052 %}
2053
2054 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2055 // Output Float immediate bits
2056 jfloat jf = $src$$constant;
2057 int jf_as_bits = jint_cast( jf );
2058 emit_d32(cbuf, jf_as_bits);
2059 %}
2060
2061 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2062 // Output Float immediate bits
2063 jfloat jf = $src$$constant;
2064 int jf_as_bits = jint_cast( jf );
2065 emit_d32(cbuf, jf_as_bits);
2066 %}
2067
2068 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2069 // Output immediate
2070 $$$emit16$src$$constant;
2071 %}
2072
2073 enc_class Con_d32(immI src) %{
2074 emit_d32(cbuf,$src$$constant);
2075 %}
2076
2077 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2078 // Output immediate memory reference
2079 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2080 emit_d32(cbuf, 0x00);
2081 %}
2082
2083 enc_class lock_prefix( ) %{
2084 if( os::is_MP() )
2085 emit_opcode(cbuf,0xF0); // [Lock]
2086 %}
2087
2088 // Cmp-xchg long value.
2089 // Note: we need to swap rbx, and rcx before and after the
2090 // cmpxchg8 instruction because the instruction uses
2091 // rcx as the high order word of the new value to store but
2092 // our register encoding uses rbx,.
2093 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2094
2095 // XCHG rbx,ecx
2096 emit_opcode(cbuf,0x87);
2097 emit_opcode(cbuf,0xD9);
2098 // [Lock]
2099 if( os::is_MP() )
2100 emit_opcode(cbuf,0xF0);
2101 // CMPXCHG8 [Eptr]
2102 emit_opcode(cbuf,0x0F);
2103 emit_opcode(cbuf,0xC7);
2104 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2105 // XCHG rbx,ecx
2106 emit_opcode(cbuf,0x87);
2107 emit_opcode(cbuf,0xD9);
2108 %}
2109
2110 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2111 // [Lock]
2112 if( os::is_MP() )
2113 emit_opcode(cbuf,0xF0);
2114
2115 // CMPXCHG [Eptr]
2116 emit_opcode(cbuf,0x0F);
2117 emit_opcode(cbuf,0xB1);
2118 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2119 %}
2120
2121 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2122 int res_encoding = $res$$reg;
2123
2124 // MOV res,0
2125 emit_opcode( cbuf, 0xB8 + res_encoding);
2126 emit_d32( cbuf, 0 );
2127 // JNE,s fail
2128 emit_opcode(cbuf,0x75);
2129 emit_d8(cbuf, 5 );
2130 // MOV res,1
2131 emit_opcode( cbuf, 0xB8 + res_encoding);
2132 emit_d32( cbuf, 1 );
2133 // fail:
2134 %}
2135
2136 enc_class set_instruction_start( ) %{
2137 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2138 %}
2139
2140 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2141 int reg_encoding = $ereg$$reg;
2142 int base = $mem$$base;
2143 int index = $mem$$index;
2144 int scale = $mem$$scale;
2145 int displace = $mem$$disp;
2146 bool disp_is_oop = $mem->disp_is_oop();
2147 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2148 %}
2149
2150 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2151 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2152 int base = $mem$$base;
2153 int index = $mem$$index;
2154 int scale = $mem$$scale;
2155 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2156 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2157 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2158 %}
2159
2160 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2161 int r1, r2;
2162 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2163 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2164 emit_opcode(cbuf,0x0F);
2165 emit_opcode(cbuf,$tertiary);
2166 emit_rm(cbuf, 0x3, r1, r2);
2167 emit_d8(cbuf,$cnt$$constant);
2168 emit_d8(cbuf,$primary);
2169 emit_rm(cbuf, 0x3, $secondary, r1);
2170 emit_d8(cbuf,$cnt$$constant);
2171 %}
2172
2173 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2174 emit_opcode( cbuf, 0x8B ); // Move
2175 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2176 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2177 emit_d8(cbuf,$primary);
2178 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2179 emit_d8(cbuf,$cnt$$constant-32);
2180 }
2181 emit_d8(cbuf,$primary);
2182 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2183 emit_d8(cbuf,31);
2184 %}
2185
2186 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2187 int r1, r2;
2188 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2189 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2190
2191 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2192 emit_rm(cbuf, 0x3, r1, r2);
2193 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2194 emit_opcode(cbuf,$primary);
2195 emit_rm(cbuf, 0x3, $secondary, r1);
2196 emit_d8(cbuf,$cnt$$constant-32);
2197 }
2198 emit_opcode(cbuf,0x33); // XOR r2,r2
2199 emit_rm(cbuf, 0x3, r2, r2);
2200 %}
2201
2202 // Clone of RegMem but accepts an extra parameter to access each
2203 // half of a double in memory; it never needs relocation info.
2204 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2205 emit_opcode(cbuf,$opcode$$constant);
2206 int reg_encoding = $rm_reg$$reg;
2207 int base = $mem$$base;
2208 int index = $mem$$index;
2209 int scale = $mem$$scale;
2210 int displace = $mem$$disp + $disp_for_half$$constant;
2211 bool disp_is_oop = false;
2212 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2213 %}
2214
2215 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2216 //
2217 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2218 // and it never needs relocation information.
2219 // Frequently used to move data between FPU's Stack Top and memory.
2220 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2221 int rm_byte_opcode = $rm_opcode$$constant;
2222 int base = $mem$$base;
2223 int index = $mem$$index;
2224 int scale = $mem$$scale;
2225 int displace = $mem$$disp;
2226 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2227 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2228 %}
2229
2230 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2231 int rm_byte_opcode = $rm_opcode$$constant;
2232 int base = $mem$$base;
2233 int index = $mem$$index;
2234 int scale = $mem$$scale;
2235 int displace = $mem$$disp;
2236 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2237 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2238 %}
2239
2240 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2241 int reg_encoding = $dst$$reg;
2242 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2243 int index = 0x04; // 0x04 indicates no index
2244 int scale = 0x00; // 0x00 indicates no scale
2245 int displace = $src1$$constant; // 0x00 indicates no displacement
2246 bool disp_is_oop = false;
2247 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2248 %}
2249
2250 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2251 // Compare dst,src
2252 emit_opcode(cbuf,0x3B);
2253 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2254 // jmp dst < src around move
2255 emit_opcode(cbuf,0x7C);
2256 emit_d8(cbuf,2);
2257 // move dst,src
2258 emit_opcode(cbuf,0x8B);
2259 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2260 %}
2261
2262 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2263 // Compare dst,src
2264 emit_opcode(cbuf,0x3B);
2265 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2266 // jmp dst > src around move
2267 emit_opcode(cbuf,0x7F);
2268 emit_d8(cbuf,2);
2269 // move dst,src
2270 emit_opcode(cbuf,0x8B);
2271 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2272 %}
2273
2274 enc_class enc_FPR_store(memory mem, regDPR src) %{
2275 // If src is FPR1, we can just FST to store it.
2276 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2277 int reg_encoding = 0x2; // Just store
2278 int base = $mem$$base;
2279 int index = $mem$$index;
2280 int scale = $mem$$scale;
2281 int displace = $mem$$disp;
2282 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2283 if( $src$$reg != FPR1L_enc ) {
2284 reg_encoding = 0x3; // Store & pop
2285 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2286 emit_d8( cbuf, 0xC0-1+$src$$reg );
2287 }
2288 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2289 emit_opcode(cbuf,$primary);
2290 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2291 %}
2292
2293 enc_class neg_reg(rRegI dst) %{
2294 // NEG $dst
2295 emit_opcode(cbuf,0xF7);
2296 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2297 %}
2298
2299 enc_class setLT_reg(eCXRegI dst) %{
2300 // SETLT $dst
2301 emit_opcode(cbuf,0x0F);
2302 emit_opcode(cbuf,0x9C);
2303 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2304 %}
2305
2306 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2307 int tmpReg = $tmp$$reg;
2308
2309 // SUB $p,$q
2310 emit_opcode(cbuf,0x2B);
2311 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2312 // SBB $tmp,$tmp
2313 emit_opcode(cbuf,0x1B);
2314 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2315 // AND $tmp,$y
2316 emit_opcode(cbuf,0x23);
2317 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2318 // ADD $p,$tmp
2319 emit_opcode(cbuf,0x03);
2320 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2321 %}
2322
2323 enc_class enc_cmpLTP_mem(rRegI p, rRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2324 int tmpReg = $tmp$$reg;
2325
2326 // SUB $p,$q
2327 emit_opcode(cbuf,0x2B);
2328 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2329 // SBB $tmp,$tmp
2330 emit_opcode(cbuf,0x1B);
2331 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2332 // AND $tmp,$y
2333 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2334 emit_opcode(cbuf,0x23);
2335 int reg_encoding = tmpReg;
2336 int base = $mem$$base;
2337 int index = $mem$$index;
2338 int scale = $mem$$scale;
2339 int displace = $mem$$disp;
2340 bool disp_is_oop = $mem->disp_is_oop();
2341 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2342 // ADD $p,$tmp
2343 emit_opcode(cbuf,0x03);
2344 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2345 %}
2346
2347 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2348 // TEST shift,32
2349 emit_opcode(cbuf,0xF7);
2350 emit_rm(cbuf, 0x3, 0, ECX_enc);
2351 emit_d32(cbuf,0x20);
2352 // JEQ,s small
2353 emit_opcode(cbuf, 0x74);
2354 emit_d8(cbuf, 0x04);
2355 // MOV $dst.hi,$dst.lo
2356 emit_opcode( cbuf, 0x8B );
2357 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2358 // CLR $dst.lo
2359 emit_opcode(cbuf, 0x33);
2360 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2361 // small:
2362 // SHLD $dst.hi,$dst.lo,$shift
2363 emit_opcode(cbuf,0x0F);
2364 emit_opcode(cbuf,0xA5);
2365 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2366 // SHL $dst.lo,$shift"
2367 emit_opcode(cbuf,0xD3);
2368 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2369 %}
2370
2371 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2372 // TEST shift,32
2373 emit_opcode(cbuf,0xF7);
2374 emit_rm(cbuf, 0x3, 0, ECX_enc);
2375 emit_d32(cbuf,0x20);
2376 // JEQ,s small
2377 emit_opcode(cbuf, 0x74);
2378 emit_d8(cbuf, 0x04);
2379 // MOV $dst.lo,$dst.hi
2380 emit_opcode( cbuf, 0x8B );
2381 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2382 // CLR $dst.hi
2383 emit_opcode(cbuf, 0x33);
2384 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2385 // small:
2386 // SHRD $dst.lo,$dst.hi,$shift
2387 emit_opcode(cbuf,0x0F);
2388 emit_opcode(cbuf,0xAD);
2389 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2390 // SHR $dst.hi,$shift"
2391 emit_opcode(cbuf,0xD3);
2392 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2393 %}
2394
2395 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2396 // TEST shift,32
2397 emit_opcode(cbuf,0xF7);
2398 emit_rm(cbuf, 0x3, 0, ECX_enc);
2399 emit_d32(cbuf,0x20);
2400 // JEQ,s small
2401 emit_opcode(cbuf, 0x74);
2402 emit_d8(cbuf, 0x05);
2403 // MOV $dst.lo,$dst.hi
2404 emit_opcode( cbuf, 0x8B );
2405 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2406 // SAR $dst.hi,31
2407 emit_opcode(cbuf, 0xC1);
2408 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2409 emit_d8(cbuf, 0x1F );
2410 // small:
2411 // SHRD $dst.lo,$dst.hi,$shift
2412 emit_opcode(cbuf,0x0F);
2413 emit_opcode(cbuf,0xAD);
2414 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2415 // SAR $dst.hi,$shift"
2416 emit_opcode(cbuf,0xD3);
2417 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2418 %}
2419
2420
2421 // ----------------- Encodings for floating point unit -----------------
2422 // May leave result in FPU-TOS or FPU reg depending on opcodes
2423 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2424 $$$emit8$primary;
2425 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2426 %}
2427
2428 // Pop argument in FPR0 with FSTP ST(0)
2429 enc_class PopFPU() %{
2430 emit_opcode( cbuf, 0xDD );
2431 emit_d8( cbuf, 0xD8 );
2432 %}
2433
2434 // !!!!! equivalent to Pop_Reg_F
2435 enc_class Pop_Reg_DPR( regDPR dst ) %{
2436 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2437 emit_d8( cbuf, 0xD8+$dst$$reg );
2438 %}
2439
2440 enc_class Push_Reg_DPR( regDPR dst ) %{
2441 emit_opcode( cbuf, 0xD9 );
2442 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2443 %}
2444
2445 enc_class strictfp_bias1( regDPR dst ) %{
2446 emit_opcode( cbuf, 0xDB ); // FLD m80real
2447 emit_opcode( cbuf, 0x2D );
2448 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2449 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2450 emit_opcode( cbuf, 0xC8+$dst$$reg );
2451 %}
2452
2453 enc_class strictfp_bias2( regDPR dst ) %{
2454 emit_opcode( cbuf, 0xDB ); // FLD m80real
2455 emit_opcode( cbuf, 0x2D );
2456 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2457 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2458 emit_opcode( cbuf, 0xC8+$dst$$reg );
2459 %}
2460
2461 // Special case for moving an integer register to a stack slot.
2462 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2463 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2464 %}
2465
2466 // Special case for moving a register to a stack slot.
2467 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2468 // Opcode already emitted
2469 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2470 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2471 emit_d32(cbuf, $dst$$disp); // Displacement
2472 %}
2473
2474 // Push the integer in stackSlot 'src' onto FP-stack
2475 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2476 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2477 %}
2478
2479 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2480 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2481 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2482 %}
2483
2484 // Same as Pop_Mem_F except for opcode
2485 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2486 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2487 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2488 %}
2489
2490 enc_class Pop_Reg_FPR( regFPR dst ) %{
2491 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2492 emit_d8( cbuf, 0xD8+$dst$$reg );
2493 %}
2494
2495 enc_class Push_Reg_FPR( regFPR dst ) %{
2496 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2497 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2498 %}
2499
2500 // Push FPU's float to a stack-slot, and pop FPU-stack
2501 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2502 int pop = 0x02;
2503 if ($src$$reg != FPR1L_enc) {
2504 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2505 emit_d8( cbuf, 0xC0-1+$src$$reg );
2506 pop = 0x03;
2507 }
2508 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2509 %}
2510
2511 // Push FPU's double to a stack-slot, and pop FPU-stack
2512 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2513 int pop = 0x02;
2514 if ($src$$reg != FPR1L_enc) {
2515 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2516 emit_d8( cbuf, 0xC0-1+$src$$reg );
2517 pop = 0x03;
2518 }
2519 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2520 %}
2521
2522 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2523 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2524 int pop = 0xD0 - 1; // -1 since we skip FLD
2525 if ($src$$reg != FPR1L_enc) {
2526 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2527 emit_d8( cbuf, 0xC0-1+$src$$reg );
2528 pop = 0xD8;
2529 }
2530 emit_opcode( cbuf, 0xDD );
2531 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2532 %}
2533
2534
2535 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2536 // load dst in FPR0
2537 emit_opcode( cbuf, 0xD9 );
2538 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2539 if ($src$$reg != FPR1L_enc) {
2540 // fincstp
2541 emit_opcode (cbuf, 0xD9);
2542 emit_opcode (cbuf, 0xF7);
2543 // swap src with FPR1:
2544 // FXCH FPR1 with src
2545 emit_opcode(cbuf, 0xD9);
2546 emit_d8(cbuf, 0xC8-1+$src$$reg );
2547 // fdecstp
2548 emit_opcode (cbuf, 0xD9);
2549 emit_opcode (cbuf, 0xF6);
2550 }
2551 %}
2552
2553 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2554 MacroAssembler _masm(&cbuf);
2555 __ subptr(rsp, 8);
2556 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2557 __ fld_d(Address(rsp, 0));
2558 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2559 __ fld_d(Address(rsp, 0));
2560 %}
2561
2562 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2563 MacroAssembler _masm(&cbuf);
2564 __ subptr(rsp, 4);
2565 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2566 __ fld_s(Address(rsp, 0));
2567 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2568 __ fld_s(Address(rsp, 0));
2569 %}
2570
2571 enc_class Push_ResultD(regD dst) %{
2572 MacroAssembler _masm(&cbuf);
2573 __ fstp_d(Address(rsp, 0));
2574 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2575 __ addptr(rsp, 8);
2576 %}
2577
2578 enc_class Push_ResultF(regF dst, immI d8) %{
2579 MacroAssembler _masm(&cbuf);
2580 __ fstp_s(Address(rsp, 0));
2581 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2582 __ addptr(rsp, $d8$$constant);
2583 %}
2584
2585 enc_class Push_SrcD(regD src) %{
2586 MacroAssembler _masm(&cbuf);
2587 __ subptr(rsp, 8);
2588 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2589 __ fld_d(Address(rsp, 0));
2590 %}
2591
2592 enc_class push_stack_temp_qword() %{
2593 MacroAssembler _masm(&cbuf);
2594 __ subptr(rsp, 8);
2595 %}
2596
2597 enc_class pop_stack_temp_qword() %{
2598 MacroAssembler _masm(&cbuf);
2599 __ addptr(rsp, 8);
2600 %}
2601
2602 enc_class push_xmm_to_fpr1(regD src) %{
2603 MacroAssembler _masm(&cbuf);
2604 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2605 __ fld_d(Address(rsp, 0));
2606 %}
2607
2608 enc_class Push_Result_Mod_DPR( regDPR src) %{
2609 if ($src$$reg != FPR1L_enc) {
2610 // fincstp
2611 emit_opcode (cbuf, 0xD9);
2612 emit_opcode (cbuf, 0xF7);
2613 // FXCH FPR1 with src
2614 emit_opcode(cbuf, 0xD9);
2615 emit_d8(cbuf, 0xC8-1+$src$$reg );
2616 // fdecstp
2617 emit_opcode (cbuf, 0xD9);
2618 emit_opcode (cbuf, 0xF6);
2619 }
2620 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2621 // // FSTP FPR$dst$$reg
2622 // emit_opcode( cbuf, 0xDD );
2623 // emit_d8( cbuf, 0xD8+$dst$$reg );
2624 %}
2625
2626 enc_class fnstsw_sahf_skip_parity() %{
2627 // fnstsw ax
2628 emit_opcode( cbuf, 0xDF );
2629 emit_opcode( cbuf, 0xE0 );
2630 // sahf
2631 emit_opcode( cbuf, 0x9E );
2632 // jnp ::skip
2633 emit_opcode( cbuf, 0x7B );
2634 emit_opcode( cbuf, 0x05 );
2635 %}
2636
2637 enc_class emitModDPR() %{
2638 // fprem must be iterative
2639 // :: loop
2640 // fprem
2641 emit_opcode( cbuf, 0xD9 );
2642 emit_opcode( cbuf, 0xF8 );
2643 // wait
2644 emit_opcode( cbuf, 0x9b );
2645 // fnstsw ax
2646 emit_opcode( cbuf, 0xDF );
2647 emit_opcode( cbuf, 0xE0 );
2648 // sahf
2649 emit_opcode( cbuf, 0x9E );
2650 // jp ::loop
2651 emit_opcode( cbuf, 0x0F );
2652 emit_opcode( cbuf, 0x8A );
2653 emit_opcode( cbuf, 0xF4 );
2654 emit_opcode( cbuf, 0xFF );
2655 emit_opcode( cbuf, 0xFF );
2656 emit_opcode( cbuf, 0xFF );
2657 %}
2658
2659 enc_class fpu_flags() %{
2660 // fnstsw_ax
2661 emit_opcode( cbuf, 0xDF);
2662 emit_opcode( cbuf, 0xE0);
2663 // test ax,0x0400
2664 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2665 emit_opcode( cbuf, 0xA9 );
2666 emit_d16 ( cbuf, 0x0400 );
2667 // // // This sequence works, but stalls for 12-16 cycles on PPro
2668 // // test rax,0x0400
2669 // emit_opcode( cbuf, 0xA9 );
2670 // emit_d32 ( cbuf, 0x00000400 );
2671 //
2672 // jz exit (no unordered comparison)
2673 emit_opcode( cbuf, 0x74 );
2674 emit_d8 ( cbuf, 0x02 );
2675 // mov ah,1 - treat as LT case (set carry flag)
2676 emit_opcode( cbuf, 0xB4 );
2677 emit_d8 ( cbuf, 0x01 );
2678 // sahf
2679 emit_opcode( cbuf, 0x9E);
2680 %}
2681
2682 enc_class cmpF_P6_fixup() %{
2683 // Fixup the integer flags in case comparison involved a NaN
2684 //
2685 // JNP exit (no unordered comparison, P-flag is set by NaN)
2686 emit_opcode( cbuf, 0x7B );
2687 emit_d8 ( cbuf, 0x03 );
2688 // MOV AH,1 - treat as LT case (set carry flag)
2689 emit_opcode( cbuf, 0xB4 );
2690 emit_d8 ( cbuf, 0x01 );
2691 // SAHF
2692 emit_opcode( cbuf, 0x9E);
2693 // NOP // target for branch to avoid branch to branch
2694 emit_opcode( cbuf, 0x90);
2695 %}
2696
2697 // fnstsw_ax();
2698 // sahf();
2699 // movl(dst, nan_result);
2700 // jcc(Assembler::parity, exit);
2701 // movl(dst, less_result);
2702 // jcc(Assembler::below, exit);
2703 // movl(dst, equal_result);
2704 // jcc(Assembler::equal, exit);
2705 // movl(dst, greater_result);
2706
2707 // less_result = 1;
2708 // greater_result = -1;
2709 // equal_result = 0;
2710 // nan_result = -1;
2711
2712 enc_class CmpF_Result(rRegI dst) %{
2713 // fnstsw_ax();
2714 emit_opcode( cbuf, 0xDF);
2715 emit_opcode( cbuf, 0xE0);
2716 // sahf
2717 emit_opcode( cbuf, 0x9E);
2718 // movl(dst, nan_result);
2719 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2720 emit_d32( cbuf, -1 );
2721 // jcc(Assembler::parity, exit);
2722 emit_opcode( cbuf, 0x7A );
2723 emit_d8 ( cbuf, 0x13 );
2724 // movl(dst, less_result);
2725 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2726 emit_d32( cbuf, -1 );
2727 // jcc(Assembler::below, exit);
2728 emit_opcode( cbuf, 0x72 );
2729 emit_d8 ( cbuf, 0x0C );
2730 // movl(dst, equal_result);
2731 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2732 emit_d32( cbuf, 0 );
2733 // jcc(Assembler::equal, exit);
2734 emit_opcode( cbuf, 0x74 );
2735 emit_d8 ( cbuf, 0x05 );
2736 // movl(dst, greater_result);
2737 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2738 emit_d32( cbuf, 1 );
2739 %}
2740
2741
2742 // Compare the longs and set flags
2743 // BROKEN! Do Not use as-is
2744 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2745 // CMP $src1.hi,$src2.hi
2746 emit_opcode( cbuf, 0x3B );
2747 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2748 // JNE,s done
2749 emit_opcode(cbuf,0x75);
2750 emit_d8(cbuf, 2 );
2751 // CMP $src1.lo,$src2.lo
2752 emit_opcode( cbuf, 0x3B );
2753 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2754 // done:
2755 %}
2756
2757 enc_class convert_int_long( regL dst, rRegI src ) %{
2758 // mov $dst.lo,$src
2759 int dst_encoding = $dst$$reg;
2760 int src_encoding = $src$$reg;
2761 encode_Copy( cbuf, dst_encoding , src_encoding );
2762 // mov $dst.hi,$src
2763 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2764 // sar $dst.hi,31
2765 emit_opcode( cbuf, 0xC1 );
2766 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2767 emit_d8(cbuf, 0x1F );
2768 %}
2769
2770 enc_class convert_long_double( eRegL src ) %{
2771 // push $src.hi
2772 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2773 // push $src.lo
2774 emit_opcode(cbuf, 0x50+$src$$reg );
2775 // fild 64-bits at [SP]
2776 emit_opcode(cbuf,0xdf);
2777 emit_d8(cbuf, 0x6C);
2778 emit_d8(cbuf, 0x24);
2779 emit_d8(cbuf, 0x00);
2780 // pop stack
2781 emit_opcode(cbuf, 0x83); // add SP, #8
2782 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2783 emit_d8(cbuf, 0x8);
2784 %}
2785
2786 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2787 // IMUL EDX:EAX,$src1
2788 emit_opcode( cbuf, 0xF7 );
2789 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2790 // SAR EDX,$cnt-32
2791 int shift_count = ((int)$cnt$$constant) - 32;
2792 if (shift_count > 0) {
2793 emit_opcode(cbuf, 0xC1);
2794 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2795 emit_d8(cbuf, shift_count);
2796 }
2797 %}
2798
2799 // this version doesn't have add sp, 8
2800 enc_class convert_long_double2( eRegL src ) %{
2801 // push $src.hi
2802 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2803 // push $src.lo
2804 emit_opcode(cbuf, 0x50+$src$$reg );
2805 // fild 64-bits at [SP]
2806 emit_opcode(cbuf,0xdf);
2807 emit_d8(cbuf, 0x6C);
2808 emit_d8(cbuf, 0x24);
2809 emit_d8(cbuf, 0x00);
2810 %}
2811
2812 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2813 // Basic idea: long = (long)int * (long)int
2814 // IMUL EDX:EAX, src
2815 emit_opcode( cbuf, 0xF7 );
2816 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2817 %}
2818
2819 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2820 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2821 // MUL EDX:EAX, src
2822 emit_opcode( cbuf, 0xF7 );
2823 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2824 %}
2825
2826 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2827 // Basic idea: lo(result) = lo(x_lo * y_lo)
2828 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2829 // MOV $tmp,$src.lo
2830 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2831 // IMUL $tmp,EDX
2832 emit_opcode( cbuf, 0x0F );
2833 emit_opcode( cbuf, 0xAF );
2834 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2835 // MOV EDX,$src.hi
2836 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2837 // IMUL EDX,EAX
2838 emit_opcode( cbuf, 0x0F );
2839 emit_opcode( cbuf, 0xAF );
2840 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2841 // ADD $tmp,EDX
2842 emit_opcode( cbuf, 0x03 );
2843 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2844 // MUL EDX:EAX,$src.lo
2845 emit_opcode( cbuf, 0xF7 );
2846 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2847 // ADD EDX,ESI
2848 emit_opcode( cbuf, 0x03 );
2849 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2850 %}
2851
2852 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2853 // Basic idea: lo(result) = lo(src * y_lo)
2854 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2855 // IMUL $tmp,EDX,$src
2856 emit_opcode( cbuf, 0x6B );
2857 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2858 emit_d8( cbuf, (int)$src$$constant );
2859 // MOV EDX,$src
2860 emit_opcode(cbuf, 0xB8 + EDX_enc);
2861 emit_d32( cbuf, (int)$src$$constant );
2862 // MUL EDX:EAX,EDX
2863 emit_opcode( cbuf, 0xF7 );
2864 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2865 // ADD EDX,ESI
2866 emit_opcode( cbuf, 0x03 );
2867 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2868 %}
2869
2870 enc_class long_div( eRegL src1, eRegL src2 ) %{
2871 // PUSH src1.hi
2872 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2873 // PUSH src1.lo
2874 emit_opcode(cbuf, 0x50+$src1$$reg );
2875 // PUSH src2.hi
2876 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2877 // PUSH src2.lo
2878 emit_opcode(cbuf, 0x50+$src2$$reg );
2879 // CALL directly to the runtime
2880 cbuf.set_insts_mark();
2881 emit_opcode(cbuf,0xE8); // Call into runtime
2882 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2883 // Restore stack
2884 emit_opcode(cbuf, 0x83); // add SP, #framesize
2885 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2886 emit_d8(cbuf, 4*4);
2887 %}
2888
2889 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2890 // PUSH src1.hi
2891 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2892 // PUSH src1.lo
2893 emit_opcode(cbuf, 0x50+$src1$$reg );
2894 // PUSH src2.hi
2895 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2896 // PUSH src2.lo
2897 emit_opcode(cbuf, 0x50+$src2$$reg );
2898 // CALL directly to the runtime
2899 cbuf.set_insts_mark();
2900 emit_opcode(cbuf,0xE8); // Call into runtime
2901 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2902 // Restore stack
2903 emit_opcode(cbuf, 0x83); // add SP, #framesize
2904 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2905 emit_d8(cbuf, 4*4);
2906 %}
2907
2908 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2909 // MOV $tmp,$src.lo
2910 emit_opcode(cbuf, 0x8B);
2911 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2912 // OR $tmp,$src.hi
2913 emit_opcode(cbuf, 0x0B);
2914 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2915 %}
2916
2917 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2918 // CMP $src1.lo,$src2.lo
2919 emit_opcode( cbuf, 0x3B );
2920 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2921 // JNE,s skip
2922 emit_cc(cbuf, 0x70, 0x5);
2923 emit_d8(cbuf,2);
2924 // CMP $src1.hi,$src2.hi
2925 emit_opcode( cbuf, 0x3B );
2926 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2927 %}
2928
2929 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2930 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2931 emit_opcode( cbuf, 0x3B );
2932 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2933 // MOV $tmp,$src1.hi
2934 emit_opcode( cbuf, 0x8B );
2935 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2936 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2937 emit_opcode( cbuf, 0x1B );
2938 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2939 %}
2940
2941 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2942 // XOR $tmp,$tmp
2943 emit_opcode(cbuf,0x33); // XOR
2944 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2945 // CMP $tmp,$src.lo
2946 emit_opcode( cbuf, 0x3B );
2947 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2948 // SBB $tmp,$src.hi
2949 emit_opcode( cbuf, 0x1B );
2950 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2951 %}
2952
2953 // Sniff, sniff... smells like Gnu Superoptimizer
2954 enc_class neg_long( eRegL dst ) %{
2955 emit_opcode(cbuf,0xF7); // NEG hi
2956 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2957 emit_opcode(cbuf,0xF7); // NEG lo
2958 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2959 emit_opcode(cbuf,0x83); // SBB hi,0
2960 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2961 emit_d8 (cbuf,0 );
2962 %}
2963
2964
2965 // Because the transitions from emitted code to the runtime
2966 // monitorenter/exit helper stubs are so slow it's critical that
2967 // we inline both the stack-locking fast-path and the inflated fast path.
2968 //
2969 // See also: cmpFastLock and cmpFastUnlock.
2970 //
2971 // What follows is a specialized inline transliteration of the code
2972 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2973 // another option would be to emit TrySlowEnter and TrySlowExit methods
2974 // at startup-time. These methods would accept arguments as
2975 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2976 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2977 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2978 // In practice, however, the # of lock sites is bounded and is usually small.
2979 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2980 // if the processor uses simple bimodal branch predictors keyed by EIP
2981 // Since the helper routines would be called from multiple synchronization
2982 // sites.
2983 //
2984 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2985 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2986 // to those specialized methods. That'd give us a mostly platform-independent
2987 // implementation that the JITs could optimize and inline at their pleasure.
2988 // Done correctly, the only time we'd need to cross to native could would be
2989 // to park() or unpark() threads. We'd also need a few more unsafe operators
2990 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2991 // (b) explicit barriers or fence operations.
2992 //
2993 // TODO:
2994 //
2995 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2996 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2997 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2998 // the lock operators would typically be faster than reifying Self.
2999 //
3000 // * Ideally I'd define the primitives as:
3001 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3002 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3003 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3004 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3005 // Furthermore the register assignments are overconstrained, possibly resulting in
3006 // sub-optimal code near the synchronization site.
3007 //
3008 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3009 // Alternately, use a better sp-proximity test.
3010 //
3011 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3012 // Either one is sufficient to uniquely identify a thread.
3013 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3014 //
3015 // * Intrinsify notify() and notifyAll() for the common cases where the
3016 // object is locked by the calling thread but the waitlist is empty.
3017 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3018 //
3019 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3020 // But beware of excessive branch density on AMD Opterons.
3021 //
3022 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3023 // or failure of the fast-path. If the fast-path fails then we pass
3024 // control to the slow-path, typically in C. In Fast_Lock and
3025 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3026 // will emit a conditional branch immediately after the node.
3027 // So we have branches to branches and lots of ICC.ZF games.
3028 // Instead, it might be better to have C2 pass a "FailureLabel"
3029 // into Fast_Lock and Fast_Unlock. In the case of success, control
3030 // will drop through the node. ICC.ZF is undefined at exit.
3031 // In the case of failure, the node will branch directly to the
3032 // FailureLabel
3033
3034
3035 // obj: object to lock
3036 // box: on-stack box address (displaced header location) - KILLED
3037 // rax,: tmp -- KILLED
3038 // scr: tmp -- KILLED
3039 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3040
3041 Register objReg = as_Register($obj$$reg);
3042 Register boxReg = as_Register($box$$reg);
3043 Register tmpReg = as_Register($tmp$$reg);
3044 Register scrReg = as_Register($scr$$reg);
3045
3046 // Ensure the register assignents are disjoint
3047 guarantee (objReg != boxReg, "") ;
3048 guarantee (objReg != tmpReg, "") ;
3049 guarantee (objReg != scrReg, "") ;
3050 guarantee (boxReg != tmpReg, "") ;
3051 guarantee (boxReg != scrReg, "") ;
3052 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3053
3054 MacroAssembler masm(&cbuf);
3055
3056 if (_counters != NULL) {
3057 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3058 }
3059 if (EmitSync & 1) {
3060 // set box->dhw = unused_mark (3)
3061 // Force all sync thru slow-path: slow_enter() and slow_exit()
3062 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3063 masm.cmpptr (rsp, (int32_t)0) ;
3064 } else
3065 if (EmitSync & 2) {
3066 Label DONE_LABEL ;
3067 if (UseBiasedLocking) {
3068 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3069 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3070 }
3071
3072 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3073 masm.orptr (tmpReg, 0x1);
3074 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3075 if (os::is_MP()) { masm.lock(); }
3076 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3077 masm.jcc(Assembler::equal, DONE_LABEL);
3078 // Recursive locking
3079 masm.subptr(tmpReg, rsp);
3080 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3081 masm.movptr(Address(boxReg, 0), tmpReg);
3082 masm.bind(DONE_LABEL) ;
3083 } else {
3084 // Possible cases that we'll encounter in fast_lock
3085 // ------------------------------------------------
3086 // * Inflated
3087 // -- unlocked
3088 // -- Locked
3089 // = by self
3090 // = by other
3091 // * biased
3092 // -- by Self
3093 // -- by other
3094 // * neutral
3095 // * stack-locked
3096 // -- by self
3097 // = sp-proximity test hits
3098 // = sp-proximity test generates false-negative
3099 // -- by other
3100 //
3101
3102 Label IsInflated, DONE_LABEL, PopDone ;
3103
3104 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3105 // order to reduce the number of conditional branches in the most common cases.
3106 // Beware -- there's a subtle invariant that fetch of the markword
3107 // at [FETCH], below, will never observe a biased encoding (*101b).
3108 // If this invariant is not held we risk exclusion (safety) failure.
3109 if (UseBiasedLocking && !UseOptoBiasInlining) {
3110 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3111 }
3112
3113 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3114 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3115 masm.jccb (Assembler::notZero, IsInflated) ;
3116
3117 // Attempt stack-locking ...
3118 masm.orptr (tmpReg, 0x1);
3119 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3120 if (os::is_MP()) { masm.lock(); }
3121 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3122 if (_counters != NULL) {
3123 masm.cond_inc32(Assembler::equal,
3124 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3125 }
3126 masm.jccb (Assembler::equal, DONE_LABEL);
3127
3128 // Recursive locking
3129 masm.subptr(tmpReg, rsp);
3130 masm.andptr(tmpReg, 0xFFFFF003 );
3131 masm.movptr(Address(boxReg, 0), tmpReg);
3132 if (_counters != NULL) {
3133 masm.cond_inc32(Assembler::equal,
3134 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3135 }
3136 masm.jmp (DONE_LABEL) ;
3137
3138 masm.bind (IsInflated) ;
3139
3140 // The object is inflated.
3141 //
3142 // TODO-FIXME: eliminate the ugly use of manifest constants:
3143 // Use markOopDesc::monitor_value instead of "2".
3144 // use markOop::unused_mark() instead of "3".
3145 // The tmpReg value is an objectMonitor reference ORed with
3146 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3147 // objectmonitor pointer by masking off the "2" bit or we can just
3148 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3149 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3150 //
3151 // I use the latter as it avoids AGI stalls.
3152 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3153 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3154 //
3155 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3156
3157 // boxReg refers to the on-stack BasicLock in the current frame.
3158 // We'd like to write:
3159 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3160 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3161 // additional latency as we have another ST in the store buffer that must drain.
3162
3163 if (EmitSync & 8192) {
3164 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3165 masm.get_thread (scrReg) ;
3166 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3167 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3168 if (os::is_MP()) { masm.lock(); }
3169 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3170 } else
3171 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3172 masm.movptr(scrReg, boxReg) ;
3173 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3174
3175 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3176 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3177 // prefetchw [eax + Offset(_owner)-2]
3178 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3179 }
3180
3181 if ((EmitSync & 64) == 0) {
3182 // Optimistic form: consider XORL tmpReg,tmpReg
3183 masm.movptr(tmpReg, NULL_WORD) ;
3184 } else {
3185 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3186 // Test-And-CAS instead of CAS
3187 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3188 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3189 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3190 }
3191
3192 // Appears unlocked - try to swing _owner from null to non-null.
3193 // Ideally, I'd manifest "Self" with get_thread and then attempt
3194 // to CAS the register containing Self into m->Owner.
3195 // But we don't have enough registers, so instead we can either try to CAS
3196 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3197 // we later store "Self" into m->Owner. Transiently storing a stack address
3198 // (rsp or the address of the box) into m->owner is harmless.
3199 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3200 if (os::is_MP()) { masm.lock(); }
3201 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3202 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3203 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3204 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3205 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3206 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3207
3208 // If the CAS fails we can either retry or pass control to the slow-path.
3209 // We use the latter tactic.
3210 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3211 // If the CAS was successful ...
3212 // Self has acquired the lock
3213 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3214 // Intentional fall-through into DONE_LABEL ...
3215 } else {
3216 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3217 masm.movptr(boxReg, tmpReg) ;
3218
3219 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3220 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3221 // prefetchw [eax + Offset(_owner)-2]
3222 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3223 }
3224
3225 if ((EmitSync & 64) == 0) {
3226 // Optimistic form
3227 masm.xorptr (tmpReg, tmpReg) ;
3228 } else {
3229 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3230 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3231 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3232 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3233 }
3234
3235 // Appears unlocked - try to swing _owner from null to non-null.
3236 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3237 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3238 masm.get_thread (scrReg) ;
3239 if (os::is_MP()) { masm.lock(); }
3240 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3241
3242 // If the CAS fails we can either retry or pass control to the slow-path.
3243 // We use the latter tactic.
3244 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3245 // If the CAS was successful ...
3246 // Self has acquired the lock
3247 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3248 // Intentional fall-through into DONE_LABEL ...
3249 }
3250
3251 // DONE_LABEL is a hot target - we'd really like to place it at the
3252 // start of cache line by padding with NOPs.
3253 // See the AMD and Intel software optimization manuals for the
3254 // most efficient "long" NOP encodings.
3255 // Unfortunately none of our alignment mechanisms suffice.
3256 masm.bind(DONE_LABEL);
3257
3258 // Avoid branch-to-branch on AMD processors
3259 // This appears to be superstition.
3260 if (EmitSync & 32) masm.nop() ;
3261
3262
3263 // At DONE_LABEL the icc ZFlag is set as follows ...
3264 // Fast_Unlock uses the same protocol.
3265 // ZFlag == 1 -> Success
3266 // ZFlag == 0 -> Failure - force control through the slow-path
3267 }
3268 %}
3269
3270 // obj: object to unlock
3271 // box: box address (displaced header location), killed. Must be EAX.
3272 // rbx,: killed tmp; cannot be obj nor box.
3273 //
3274 // Some commentary on balanced locking:
3275 //
3276 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3277 // Methods that don't have provably balanced locking are forced to run in the
3278 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3279 // The interpreter provides two properties:
3280 // I1: At return-time the interpreter automatically and quietly unlocks any
3281 // objects acquired the current activation (frame). Recall that the
3282 // interpreter maintains an on-stack list of locks currently held by
3283 // a frame.
3284 // I2: If a method attempts to unlock an object that is not held by the
3285 // the frame the interpreter throws IMSX.
3286 //
3287 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3288 // B() doesn't have provably balanced locking so it runs in the interpreter.
3289 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3290 // is still locked by A().
3291 //
3292 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3293 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3294 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3295 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3296
3297 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3298
3299 Register objReg = as_Register($obj$$reg);
3300 Register boxReg = as_Register($box$$reg);
3301 Register tmpReg = as_Register($tmp$$reg);
3302
3303 guarantee (objReg != boxReg, "") ;
3304 guarantee (objReg != tmpReg, "") ;
3305 guarantee (boxReg != tmpReg, "") ;
3306 guarantee (boxReg == as_Register(EAX_enc), "") ;
3307 MacroAssembler masm(&cbuf);
3308
3309 if (EmitSync & 4) {
3310 // Disable - inhibit all inlining. Force control through the slow-path
3311 masm.cmpptr (rsp, 0) ;
3312 } else
3313 if (EmitSync & 8) {
3314 Label DONE_LABEL ;
3315 if (UseBiasedLocking) {
3316 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3317 }
3318 // classic stack-locking code ...
3319 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3320 masm.testptr(tmpReg, tmpReg) ;
3321 masm.jcc (Assembler::zero, DONE_LABEL) ;
3322 if (os::is_MP()) { masm.lock(); }
3323 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3324 masm.bind(DONE_LABEL);
3325 } else {
3326 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3327
3328 // Critically, the biased locking test must have precedence over
3329 // and appear before the (box->dhw == 0) recursive stack-lock test.
3330 if (UseBiasedLocking && !UseOptoBiasInlining) {
3331 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3332 }
3333
3334 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3335 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3336 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3337
3338 masm.testptr(tmpReg, 0x02) ; // Inflated?
3339 masm.jccb (Assembler::zero, Stacked) ;
3340
3341 masm.bind (Inflated) ;
3342 // It's inflated.
3343 // Despite our balanced locking property we still check that m->_owner == Self
3344 // as java routines or native JNI code called by this thread might
3345 // have released the lock.
3346 // Refer to the comments in synchronizer.cpp for how we might encode extra
3347 // state in _succ so we can avoid fetching EntryList|cxq.
3348 //
3349 // I'd like to add more cases in fast_lock() and fast_unlock() --
3350 // such as recursive enter and exit -- but we have to be wary of
3351 // I$ bloat, T$ effects and BP$ effects.
3352 //
3353 // If there's no contention try a 1-0 exit. That is, exit without
3354 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3355 // we detect and recover from the race that the 1-0 exit admits.
3356 //
3357 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3358 // before it STs null into _owner, releasing the lock. Updates
3359 // to data protected by the critical section must be visible before
3360 // we drop the lock (and thus before any other thread could acquire
3361 // the lock and observe the fields protected by the lock).
3362 // IA32's memory-model is SPO, so STs are ordered with respect to
3363 // each other and there's no need for an explicit barrier (fence).
3364 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3365
3366 masm.get_thread (boxReg) ;
3367 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3368 // prefetchw [ebx + Offset(_owner)-2]
3369 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3370 }
3371
3372 // Note that we could employ various encoding schemes to reduce
3373 // the number of loads below (currently 4) to just 2 or 3.
3374 // Refer to the comments in synchronizer.cpp.
3375 // In practice the chain of fetches doesn't seem to impact performance, however.
3376 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3377 // Attempt to reduce branch density - AMD's branch predictor.
3378 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3379 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3380 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3381 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3382 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3383 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3384 masm.jmpb (DONE_LABEL) ;
3385 } else {
3386 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3387 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3388 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3389 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3390 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3391 masm.jccb (Assembler::notZero, CheckSucc) ;
3392 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3393 masm.jmpb (DONE_LABEL) ;
3394 }
3395
3396 // The Following code fragment (EmitSync & 65536) improves the performance of
3397 // contended applications and contended synchronization microbenchmarks.
3398 // Unfortunately the emission of the code - even though not executed - causes regressions
3399 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3400 // with an equal number of never-executed NOPs results in the same regression.
3401 // We leave it off by default.
3402
3403 if ((EmitSync & 65536) != 0) {
3404 Label LSuccess, LGoSlowPath ;
3405
3406 masm.bind (CheckSucc) ;
3407
3408 // Optional pre-test ... it's safe to elide this
3409 if ((EmitSync & 16) == 0) {
3410 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3411 masm.jccb (Assembler::zero, LGoSlowPath) ;
3412 }
3413
3414 // We have a classic Dekker-style idiom:
3415 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3416 // There are a number of ways to implement the barrier:
3417 // (1) lock:andl &m->_owner, 0
3418 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3419 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3420 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3421 // (2) If supported, an explicit MFENCE is appealing.
3422 // In older IA32 processors MFENCE is slower than lock:add or xchg
3423 // particularly if the write-buffer is full as might be the case if
3424 // if stores closely precede the fence or fence-equivalent instruction.
3425 // In more modern implementations MFENCE appears faster, however.
3426 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3427 // The $lines underlying the top-of-stack should be in M-state.
3428 // The locked add instruction is serializing, of course.
3429 // (4) Use xchg, which is serializing
3430 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3431 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3432 // The integer condition codes will tell us if succ was 0.
3433 // Since _succ and _owner should reside in the same $line and
3434 // we just stored into _owner, it's likely that the $line
3435 // remains in M-state for the lock:orl.
3436 //
3437 // We currently use (3), although it's likely that switching to (2)
3438 // is correct for the future.
3439
3440 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3441 if (os::is_MP()) {
3442 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3443 masm.mfence();
3444 } else {
3445 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3446 }
3447 }
3448 // Ratify _succ remains non-null
3449 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3450 masm.jccb (Assembler::notZero, LSuccess) ;
3451
3452 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3453 if (os::is_MP()) { masm.lock(); }
3454 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3455 masm.jccb (Assembler::notEqual, LSuccess) ;
3456 // Since we're low on registers we installed rsp as a placeholding in _owner.
3457 // Now install Self over rsp. This is safe as we're transitioning from
3458 // non-null to non=null
3459 masm.get_thread (boxReg) ;
3460 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3461 // Intentional fall-through into LGoSlowPath ...
3462
3463 masm.bind (LGoSlowPath) ;
3464 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3465 masm.jmpb (DONE_LABEL) ;
3466
3467 masm.bind (LSuccess) ;
3468 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3469 masm.jmpb (DONE_LABEL) ;
3470 }
3471
3472 masm.bind (Stacked) ;
3473 // It's not inflated and it's not recursively stack-locked and it's not biased.
3474 // It must be stack-locked.
3475 // Try to reset the header to displaced header.
3476 // The "box" value on the stack is stable, so we can reload
3477 // and be assured we observe the same value as above.
3478 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3479 if (os::is_MP()) { masm.lock(); }
3480 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3481 // Intention fall-thru into DONE_LABEL
3482
3483
3484 // DONE_LABEL is a hot target - we'd really like to place it at the
3485 // start of cache line by padding with NOPs.
3486 // See the AMD and Intel software optimization manuals for the
3487 // most efficient "long" NOP encodings.
3488 // Unfortunately none of our alignment mechanisms suffice.
3489 if ((EmitSync & 65536) == 0) {
3490 masm.bind (CheckSucc) ;
3491 }
3492 masm.bind(DONE_LABEL);
3493
3494 // Avoid branch to branch on AMD processors
3495 if (EmitSync & 32768) { masm.nop() ; }
3496 }
3497 %}
3498
3499
3500 enc_class enc_pop_rdx() %{
3501 emit_opcode(cbuf,0x5A);
3502 %}
3503
3504 enc_class enc_rethrow() %{
3505 cbuf.set_insts_mark();
3506 emit_opcode(cbuf, 0xE9); // jmp entry
3507 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3508 runtime_call_Relocation::spec(), RELOC_IMM32 );
3509 %}
3510
3511
3512 // Convert a double to an int. Java semantics require we do complex
3513 // manglelations in the corner cases. So we set the rounding mode to
3514 // 'zero', store the darned double down as an int, and reset the
3515 // rounding mode to 'nearest'. The hardware throws an exception which
3516 // patches up the correct value directly to the stack.
3517 enc_class DPR2I_encoding( regDPR src ) %{
3518 // Flip to round-to-zero mode. We attempted to allow invalid-op
3519 // exceptions here, so that a NAN or other corner-case value will
3520 // thrown an exception (but normal values get converted at full speed).
3521 // However, I2C adapters and other float-stack manglers leave pending
3522 // invalid-op exceptions hanging. We would have to clear them before
3523 // enabling them and that is more expensive than just testing for the
3524 // invalid value Intel stores down in the corner cases.
3525 emit_opcode(cbuf,0xD9); // FLDCW trunc
3526 emit_opcode(cbuf,0x2D);
3527 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3528 // Allocate a word
3529 emit_opcode(cbuf,0x83); // SUB ESP,4
3530 emit_opcode(cbuf,0xEC);
3531 emit_d8(cbuf,0x04);
3532 // Encoding assumes a double has been pushed into FPR0.
3533 // Store down the double as an int, popping the FPU stack
3534 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3535 emit_opcode(cbuf,0x1C);
3536 emit_d8(cbuf,0x24);
3537 // Restore the rounding mode; mask the exception
3538 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3539 emit_opcode(cbuf,0x2D);
3540 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3541 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3542 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3543
3544 // Load the converted int; adjust CPU stack
3545 emit_opcode(cbuf,0x58); // POP EAX
3546 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3547 emit_d32 (cbuf,0x80000000); // 0x80000000
3548 emit_opcode(cbuf,0x75); // JNE around_slow_call
3549 emit_d8 (cbuf,0x07); // Size of slow_call
3550 // Push src onto stack slow-path
3551 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3552 emit_d8 (cbuf,0xC0-1+$src$$reg );
3553 // CALL directly to the runtime
3554 cbuf.set_insts_mark();
3555 emit_opcode(cbuf,0xE8); // Call into runtime
3556 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3557 // Carry on here...
3558 %}
3559
3560 enc_class DPR2L_encoding( regDPR src ) %{
3561 emit_opcode(cbuf,0xD9); // FLDCW trunc
3562 emit_opcode(cbuf,0x2D);
3563 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3564 // Allocate a word
3565 emit_opcode(cbuf,0x83); // SUB ESP,8
3566 emit_opcode(cbuf,0xEC);
3567 emit_d8(cbuf,0x08);
3568 // Encoding assumes a double has been pushed into FPR0.
3569 // Store down the double as a long, popping the FPU stack
3570 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3571 emit_opcode(cbuf,0x3C);
3572 emit_d8(cbuf,0x24);
3573 // Restore the rounding mode; mask the exception
3574 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3575 emit_opcode(cbuf,0x2D);
3576 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3577 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3578 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3579
3580 // Load the converted int; adjust CPU stack
3581 emit_opcode(cbuf,0x58); // POP EAX
3582 emit_opcode(cbuf,0x5A); // POP EDX
3583 emit_opcode(cbuf,0x81); // CMP EDX,imm
3584 emit_d8 (cbuf,0xFA); // rdx
3585 emit_d32 (cbuf,0x80000000); // 0x80000000
3586 emit_opcode(cbuf,0x75); // JNE around_slow_call
3587 emit_d8 (cbuf,0x07+4); // Size of slow_call
3588 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3589 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3590 emit_opcode(cbuf,0x75); // JNE around_slow_call
3591 emit_d8 (cbuf,0x07); // Size of slow_call
3592 // Push src onto stack slow-path
3593 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3594 emit_d8 (cbuf,0xC0-1+$src$$reg );
3595 // CALL directly to the runtime
3596 cbuf.set_insts_mark();
3597 emit_opcode(cbuf,0xE8); // Call into runtime
3598 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3599 // Carry on here...
3600 %}
3601
3602 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3603 // Operand was loaded from memory into fp ST (stack top)
3604 // FMUL ST,$src /* D8 C8+i */
3605 emit_opcode(cbuf, 0xD8);
3606 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3607 %}
3608
3609 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3610 // FADDP ST,src2 /* D8 C0+i */
3611 emit_opcode(cbuf, 0xD8);
3612 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3613 //could use FADDP src2,fpST /* DE C0+i */
3614 %}
3615
3616 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3617 // FADDP src2,ST /* DE C0+i */
3618 emit_opcode(cbuf, 0xDE);
3619 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3620 %}
3621
3622 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3623 // Operand has been loaded into fp ST (stack top)
3624 // FSUB ST,$src1
3625 emit_opcode(cbuf, 0xD8);
3626 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3627
3628 // FDIV
3629 emit_opcode(cbuf, 0xD8);
3630 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3631 %}
3632
3633 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3634 // Operand was loaded from memory into fp ST (stack top)
3635 // FADD ST,$src /* D8 C0+i */
3636 emit_opcode(cbuf, 0xD8);
3637 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3638
3639 // FMUL ST,src2 /* D8 C*+i */
3640 emit_opcode(cbuf, 0xD8);
3641 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3642 %}
3643
3644
3645 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3646 // Operand was loaded from memory into fp ST (stack top)
3647 // FADD ST,$src /* D8 C0+i */
3648 emit_opcode(cbuf, 0xD8);
3649 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3650
3651 // FMULP src2,ST /* DE C8+i */
3652 emit_opcode(cbuf, 0xDE);
3653 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3654 %}
3655
3656 // Atomically load the volatile long
3657 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3658 emit_opcode(cbuf,0xDF);
3659 int rm_byte_opcode = 0x05;
3660 int base = $mem$$base;
3661 int index = $mem$$index;
3662 int scale = $mem$$scale;
3663 int displace = $mem$$disp;
3664 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3665 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3666 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3667 %}
3668
3669 // Volatile Store Long. Must be atomic, so move it into
3670 // the FP TOS and then do a 64-bit FIST. Has to probe the
3671 // target address before the store (for null-ptr checks)
3672 // so the memory operand is used twice in the encoding.
3673 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3674 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3675 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3676 emit_opcode(cbuf,0xDF);
3677 int rm_byte_opcode = 0x07;
3678 int base = $mem$$base;
3679 int index = $mem$$index;
3680 int scale = $mem$$scale;
3681 int displace = $mem$$disp;
3682 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3683 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3684 %}
3685
3686 // Safepoint Poll. This polls the safepoint page, and causes an
3687 // exception if it is not readable. Unfortunately, it kills the condition code
3688 // in the process
3689 // We current use TESTL [spp],EDI
3690 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3691
3692 enc_class Safepoint_Poll() %{
3693 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3694 emit_opcode(cbuf,0x85);
3695 emit_rm (cbuf, 0x0, 0x7, 0x5);
3696 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3697 %}
3698 %}
3699
3700
3701 //----------FRAME--------------------------------------------------------------
3702 // Definition of frame structure and management information.
3703 //
3704 // S T A C K L A Y O U T Allocators stack-slot number
3705 // | (to get allocators register number
3706 // G Owned by | | v add OptoReg::stack0())
3707 // r CALLER | |
3708 // o | +--------+ pad to even-align allocators stack-slot
3709 // w V | pad0 | numbers; owned by CALLER
3710 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3711 // h ^ | in | 5
3712 // | | args | 4 Holes in incoming args owned by SELF
3713 // | | | | 3
3714 // | | +--------+
3715 // V | | old out| Empty on Intel, window on Sparc
3716 // | old |preserve| Must be even aligned.
3717 // | SP-+--------+----> Matcher::_old_SP, even aligned
3718 // | | in | 3 area for Intel ret address
3719 // Owned by |preserve| Empty on Sparc.
3720 // SELF +--------+
3721 // | | pad2 | 2 pad to align old SP
3722 // | +--------+ 1
3723 // | | locks | 0
3724 // | +--------+----> OptoReg::stack0(), even aligned
3725 // | | pad1 | 11 pad to align new SP
3726 // | +--------+
3727 // | | | 10
3728 // | | spills | 9 spills
3729 // V | | 8 (pad0 slot for callee)
3730 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3731 // ^ | out | 7
3732 // | | args | 6 Holes in outgoing args owned by CALLEE
3733 // Owned by +--------+
3734 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3735 // | new |preserve| Must be even-aligned.
3736 // | SP-+--------+----> Matcher::_new_SP, even aligned
3737 // | | |
3738 //
3739 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3740 // known from SELF's arguments and the Java calling convention.
3741 // Region 6-7 is determined per call site.
3742 // Note 2: If the calling convention leaves holes in the incoming argument
3743 // area, those holes are owned by SELF. Holes in the outgoing area
3744 // are owned by the CALLEE. Holes should not be nessecary in the
3745 // incoming area, as the Java calling convention is completely under
3746 // the control of the AD file. Doubles can be sorted and packed to
3747 // avoid holes. Holes in the outgoing arguments may be nessecary for
3748 // varargs C calling conventions.
3749 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3750 // even aligned with pad0 as needed.
3751 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3752 // region 6-11 is even aligned; it may be padded out more so that
3753 // the region from SP to FP meets the minimum stack alignment.
3754
3755 frame %{
3756 // What direction does stack grow in (assumed to be same for C & Java)
3757 stack_direction(TOWARDS_LOW);
3758
3759 // These three registers define part of the calling convention
3760 // between compiled code and the interpreter.
3761 inline_cache_reg(EAX); // Inline Cache Register
3762 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3763
3764 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3765 cisc_spilling_operand_name(indOffset32);
3766
3767 // Number of stack slots consumed by locking an object
3768 sync_stack_slots(1);
3769
3770 // Compiled code's Frame Pointer
3771 frame_pointer(ESP);
3772 // Interpreter stores its frame pointer in a register which is
3773 // stored to the stack by I2CAdaptors.
3774 // I2CAdaptors convert from interpreted java to compiled java.
3775 interpreter_frame_pointer(EBP);
3776
3777 // Stack alignment requirement
3778 // Alignment size in bytes (128-bit -> 16 bytes)
3779 stack_alignment(StackAlignmentInBytes);
3780
3781 // Number of stack slots between incoming argument block and the start of
3782 // a new frame. The PROLOG must add this many slots to the stack. The
3783 // EPILOG must remove this many slots. Intel needs one slot for
3784 // return address and one for rbp, (must save rbp)
3785 in_preserve_stack_slots(2+VerifyStackAtCalls);
3786
3787 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3788 // for calls to C. Supports the var-args backing area for register parms.
3789 varargs_C_out_slots_killed(0);
3790
3791 // The after-PROLOG location of the return address. Location of
3792 // return address specifies a type (REG or STACK) and a number
3793 // representing the register number (i.e. - use a register name) or
3794 // stack slot.
3795 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3796 // Otherwise, it is above the locks and verification slot and alignment word
3797 return_addr(STACK - 1 +
3798 round_to((Compile::current()->in_preserve_stack_slots() +
3799 Compile::current()->fixed_slots()),
3800 stack_alignment_in_slots()));
3801
3802 // Body of function which returns an integer array locating
3803 // arguments either in registers or in stack slots. Passed an array
3804 // of ideal registers called "sig" and a "length" count. Stack-slot
3805 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3806 // arguments for a CALLEE. Incoming stack arguments are
3807 // automatically biased by the preserve_stack_slots field above.
3808 calling_convention %{
3809 // No difference between ingoing/outgoing just pass false
3810 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3811 %}
3812
3813
3814 // Body of function which returns an integer array locating
3815 // arguments either in registers or in stack slots. Passed an array
3816 // of ideal registers called "sig" and a "length" count. Stack-slot
3817 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3818 // arguments for a CALLEE. Incoming stack arguments are
3819 // automatically biased by the preserve_stack_slots field above.
3820 c_calling_convention %{
3821 // This is obviously always outgoing
3822 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3823 %}
3824
3825 // Location of C & interpreter return values
3826 c_return_value %{
3827 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3828 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3829 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3830
3831 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3832 // that C functions return float and double results in XMM0.
3833 if( ideal_reg == Op_RegD && UseSSE>=2 )
3834 return OptoRegPair(XMM0b_num,XMM0_num);
3835 if( ideal_reg == Op_RegF && UseSSE>=2 )
3836 return OptoRegPair(OptoReg::Bad,XMM0_num);
3837
3838 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3839 %}
3840
3841 // Location of return values
3842 return_value %{
3843 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3844 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3845 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3846 if( ideal_reg == Op_RegD && UseSSE>=2 )
3847 return OptoRegPair(XMM0b_num,XMM0_num);
3848 if( ideal_reg == Op_RegF && UseSSE>=1 )
3849 return OptoRegPair(OptoReg::Bad,XMM0_num);
3850 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3851 %}
3852
3853 %}
3854
3855 //----------ATTRIBUTES---------------------------------------------------------
3856 //----------Operand Attributes-------------------------------------------------
3857 op_attrib op_cost(0); // Required cost attribute
3858
3859 //----------Instruction Attributes---------------------------------------------
3860 ins_attrib ins_cost(100); // Required cost attribute
3861 ins_attrib ins_size(8); // Required size attribute (in bits)
3862 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3863 // non-matching short branch variant of some
3864 // long branch?
3865 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3866 // specifies the alignment that some part of the instruction (not
3867 // necessarily the start) requires. If > 1, a compute_padding()
3868 // function must be provided for the instruction
3869
3870 //----------OPERANDS-----------------------------------------------------------
3871 // Operand definitions must precede instruction definitions for correct parsing
3872 // in the ADLC because operands constitute user defined types which are used in
3873 // instruction definitions.
3874
3875 //----------Simple Operands----------------------------------------------------
3876 // Immediate Operands
3877 // Integer Immediate
3878 operand immI() %{
3879 match(ConI);
3880
3881 op_cost(10);
3882 format %{ %}
3883 interface(CONST_INTER);
3884 %}
3885
3886 // Constant for test vs zero
3887 operand immI0() %{
3888 predicate(n->get_int() == 0);
3889 match(ConI);
3890
3891 op_cost(0);
3892 format %{ %}
3893 interface(CONST_INTER);
3894 %}
3895
3896 // Constant for increment
3897 operand immI1() %{
3898 predicate(n->get_int() == 1);
3899 match(ConI);
3900
3901 op_cost(0);
3902 format %{ %}
3903 interface(CONST_INTER);
3904 %}
3905
3906 // Constant for decrement
3907 operand immI_M1() %{
3908 predicate(n->get_int() == -1);
3909 match(ConI);
3910
3911 op_cost(0);
3912 format %{ %}
3913 interface(CONST_INTER);
3914 %}
3915
3916 // Valid scale values for addressing modes
3917 operand immI2() %{
3918 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3919 match(ConI);
3920
3921 format %{ %}
3922 interface(CONST_INTER);
3923 %}
3924
3925 operand immI8() %{
3926 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3927 match(ConI);
3928
3929 op_cost(5);
3930 format %{ %}
3931 interface(CONST_INTER);
3932 %}
3933
3934 operand immI16() %{
3935 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3936 match(ConI);
3937
3938 op_cost(10);
3939 format %{ %}
3940 interface(CONST_INTER);
3941 %}
3942
3943 // Constant for long shifts
3944 operand immI_32() %{
3945 predicate( n->get_int() == 32 );
3946 match(ConI);
3947
3948 op_cost(0);
3949 format %{ %}
3950 interface(CONST_INTER);
3951 %}
3952
3953 operand immI_1_31() %{
3954 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3955 match(ConI);
3956
3957 op_cost(0);
3958 format %{ %}
3959 interface(CONST_INTER);
3960 %}
3961
3962 operand immI_32_63() %{
3963 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3964 match(ConI);
3965 op_cost(0);
3966
3967 format %{ %}
3968 interface(CONST_INTER);
3969 %}
3970
3971 operand immI_1() %{
3972 predicate( n->get_int() == 1 );
3973 match(ConI);
3974
3975 op_cost(0);
3976 format %{ %}
3977 interface(CONST_INTER);
3978 %}
3979
3980 operand immI_2() %{
3981 predicate( n->get_int() == 2 );
3982 match(ConI);
3983
3984 op_cost(0);
3985 format %{ %}
3986 interface(CONST_INTER);
3987 %}
3988
3989 operand immI_3() %{
3990 predicate( n->get_int() == 3 );
3991 match(ConI);
3992
3993 op_cost(0);
3994 format %{ %}
3995 interface(CONST_INTER);
3996 %}
3997
3998 // Pointer Immediate
3999 operand immP() %{
4000 match(ConP);
4001
4002 op_cost(10);
4003 format %{ %}
4004 interface(CONST_INTER);
4005 %}
4006
4007 // NULL Pointer Immediate
4008 operand immP0() %{
4009 predicate( n->get_ptr() == 0 );
4010 match(ConP);
4011 op_cost(0);
4012
4013 format %{ %}
4014 interface(CONST_INTER);
4015 %}
4016
4017 // Long Immediate
4018 operand immL() %{
4019 match(ConL);
4020
4021 op_cost(20);
4022 format %{ %}
4023 interface(CONST_INTER);
4024 %}
4025
4026 // Long Immediate zero
4027 operand immL0() %{
4028 predicate( n->get_long() == 0L );
4029 match(ConL);
4030 op_cost(0);
4031
4032 format %{ %}
4033 interface(CONST_INTER);
4034 %}
4035
4036 // Long Immediate zero
4037 operand immL_M1() %{
4038 predicate( n->get_long() == -1L );
4039 match(ConL);
4040 op_cost(0);
4041
4042 format %{ %}
4043 interface(CONST_INTER);
4044 %}
4045
4046 // Long immediate from 0 to 127.
4047 // Used for a shorter form of long mul by 10.
4048 operand immL_127() %{
4049 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4050 match(ConL);
4051 op_cost(0);
4052
4053 format %{ %}
4054 interface(CONST_INTER);
4055 %}
4056
4057 // Long Immediate: low 32-bit mask
4058 operand immL_32bits() %{
4059 predicate(n->get_long() == 0xFFFFFFFFL);
4060 match(ConL);
4061 op_cost(0);
4062
4063 format %{ %}
4064 interface(CONST_INTER);
4065 %}
4066
4067 // Long Immediate: low 32-bit mask
4068 operand immL32() %{
4069 predicate(n->get_long() == (int)(n->get_long()));
4070 match(ConL);
4071 op_cost(20);
4072
4073 format %{ %}
4074 interface(CONST_INTER);
4075 %}
4076
4077 //Double Immediate zero
4078 operand immDPR0() %{
4079 // Do additional (and counter-intuitive) test against NaN to work around VC++
4080 // bug that generates code such that NaNs compare equal to 0.0
4081 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4082 match(ConD);
4083
4084 op_cost(5);
4085 format %{ %}
4086 interface(CONST_INTER);
4087 %}
4088
4089 // Double Immediate one
4090 operand immDPR1() %{
4091 predicate( UseSSE<=1 && n->getd() == 1.0 );
4092 match(ConD);
4093
4094 op_cost(5);
4095 format %{ %}
4096 interface(CONST_INTER);
4097 %}
4098
4099 // Double Immediate
4100 operand immDPR() %{
4101 predicate(UseSSE<=1);
4102 match(ConD);
4103
4104 op_cost(5);
4105 format %{ %}
4106 interface(CONST_INTER);
4107 %}
4108
4109 operand immD() %{
4110 predicate(UseSSE>=2);
4111 match(ConD);
4112
4113 op_cost(5);
4114 format %{ %}
4115 interface(CONST_INTER);
4116 %}
4117
4118 // Double Immediate zero
4119 operand immD0() %{
4120 // Do additional (and counter-intuitive) test against NaN to work around VC++
4121 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4122 // compare equal to -0.0.
4123 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4124 match(ConD);
4125
4126 format %{ %}
4127 interface(CONST_INTER);
4128 %}
4129
4130 // Float Immediate zero
4131 operand immFPR0() %{
4132 predicate(UseSSE == 0 && n->getf() == 0.0F);
4133 match(ConF);
4134
4135 op_cost(5);
4136 format %{ %}
4137 interface(CONST_INTER);
4138 %}
4139
4140 // Float Immediate one
4141 operand immFPR1() %{
4142 predicate(UseSSE == 0 && n->getf() == 1.0F);
4143 match(ConF);
4144
4145 op_cost(5);
4146 format %{ %}
4147 interface(CONST_INTER);
4148 %}
4149
4150 // Float Immediate
4151 operand immFPR() %{
4152 predicate( UseSSE == 0 );
4153 match(ConF);
4154
4155 op_cost(5);
4156 format %{ %}
4157 interface(CONST_INTER);
4158 %}
4159
4160 // Float Immediate
4161 operand immF() %{
4162 predicate(UseSSE >= 1);
4163 match(ConF);
4164
4165 op_cost(5);
4166 format %{ %}
4167 interface(CONST_INTER);
4168 %}
4169
4170 // Float Immediate zero. Zero and not -0.0
4171 operand immF0() %{
4172 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4173 match(ConF);
4174
4175 op_cost(5);
4176 format %{ %}
4177 interface(CONST_INTER);
4178 %}
4179
4180 // Immediates for special shifts (sign extend)
4181
4182 // Constants for increment
4183 operand immI_16() %{
4184 predicate( n->get_int() == 16 );
4185 match(ConI);
4186
4187 format %{ %}
4188 interface(CONST_INTER);
4189 %}
4190
4191 operand immI_24() %{
4192 predicate( n->get_int() == 24 );
4193 match(ConI);
4194
4195 format %{ %}
4196 interface(CONST_INTER);
4197 %}
4198
4199 // Constant for byte-wide masking
4200 operand immI_255() %{
4201 predicate( n->get_int() == 255 );
4202 match(ConI);
4203
4204 format %{ %}
4205 interface(CONST_INTER);
4206 %}
4207
4208 // Constant for short-wide masking
4209 operand immI_65535() %{
4210 predicate(n->get_int() == 65535);
4211 match(ConI);
4212
4213 format %{ %}
4214 interface(CONST_INTER);
4215 %}
4216
4217 // Register Operands
4218 // Integer Register
4219 operand rRegI() %{
4220 constraint(ALLOC_IN_RC(int_reg));
4221 match(RegI);
4222 match(xRegI);
4223 match(eAXRegI);
4224 match(eBXRegI);
4225 match(eCXRegI);
4226 match(eDXRegI);
4227 match(eDIRegI);
4228 match(eSIRegI);
4229
4230 format %{ %}
4231 interface(REG_INTER);
4232 %}
4233
4234 // Subset of Integer Register
4235 operand xRegI(rRegI reg) %{
4236 constraint(ALLOC_IN_RC(int_x_reg));
4237 match(reg);
4238 match(eAXRegI);
4239 match(eBXRegI);
4240 match(eCXRegI);
4241 match(eDXRegI);
4242
4243 format %{ %}
4244 interface(REG_INTER);
4245 %}
4246
4247 // Special Registers
4248 operand eAXRegI(xRegI reg) %{
4249 constraint(ALLOC_IN_RC(eax_reg));
4250 match(reg);
4251 match(rRegI);
4252
4253 format %{ "EAX" %}
4254 interface(REG_INTER);
4255 %}
4256
4257 // Special Registers
4258 operand eBXRegI(xRegI reg) %{
4259 constraint(ALLOC_IN_RC(ebx_reg));
4260 match(reg);
4261 match(rRegI);
4262
4263 format %{ "EBX" %}
4264 interface(REG_INTER);
4265 %}
4266
4267 operand eCXRegI(xRegI reg) %{
4268 constraint(ALLOC_IN_RC(ecx_reg));
4269 match(reg);
4270 match(rRegI);
4271
4272 format %{ "ECX" %}
4273 interface(REG_INTER);
4274 %}
4275
4276 operand eDXRegI(xRegI reg) %{
4277 constraint(ALLOC_IN_RC(edx_reg));
4278 match(reg);
4279 match(rRegI);
4280
4281 format %{ "EDX" %}
4282 interface(REG_INTER);
4283 %}
4284
4285 operand eDIRegI(xRegI reg) %{
4286 constraint(ALLOC_IN_RC(edi_reg));
4287 match(reg);
4288 match(rRegI);
4289
4290 format %{ "EDI" %}
4291 interface(REG_INTER);
4292 %}
4293
4294 operand naxRegI() %{
4295 constraint(ALLOC_IN_RC(nax_reg));
4296 match(RegI);
4297 match(eCXRegI);
4298 match(eDXRegI);
4299 match(eSIRegI);
4300 match(eDIRegI);
4301
4302 format %{ %}
4303 interface(REG_INTER);
4304 %}
4305
4306 operand nadxRegI() %{
4307 constraint(ALLOC_IN_RC(nadx_reg));
4308 match(RegI);
4309 match(eBXRegI);
4310 match(eCXRegI);
4311 match(eSIRegI);
4312 match(eDIRegI);
4313
4314 format %{ %}
4315 interface(REG_INTER);
4316 %}
4317
4318 operand ncxRegI() %{
4319 constraint(ALLOC_IN_RC(ncx_reg));
4320 match(RegI);
4321 match(eAXRegI);
4322 match(eDXRegI);
4323 match(eSIRegI);
4324 match(eDIRegI);
4325
4326 format %{ %}
4327 interface(REG_INTER);
4328 %}
4329
4330 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4331 // //
4332 operand eSIRegI(xRegI reg) %{
4333 constraint(ALLOC_IN_RC(esi_reg));
4334 match(reg);
4335 match(rRegI);
4336
4337 format %{ "ESI" %}
4338 interface(REG_INTER);
4339 %}
4340
4341 // Pointer Register
4342 operand anyRegP() %{
4343 constraint(ALLOC_IN_RC(any_reg));
4344 match(RegP);
4345 match(eAXRegP);
4346 match(eBXRegP);
4347 match(eCXRegP);
4348 match(eDIRegP);
4349 match(eRegP);
4350
4351 format %{ %}
4352 interface(REG_INTER);
4353 %}
4354
4355 operand eRegP() %{
4356 constraint(ALLOC_IN_RC(int_reg));
4357 match(RegP);
4358 match(eAXRegP);
4359 match(eBXRegP);
4360 match(eCXRegP);
4361 match(eDIRegP);
4362
4363 format %{ %}
4364 interface(REG_INTER);
4365 %}
4366
4367 // On windows95, EBP is not safe to use for implicit null tests.
4368 operand eRegP_no_EBP() %{
4369 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4370 match(RegP);
4371 match(eAXRegP);
4372 match(eBXRegP);
4373 match(eCXRegP);
4374 match(eDIRegP);
4375
4376 op_cost(100);
4377 format %{ %}
4378 interface(REG_INTER);
4379 %}
4380
4381 operand naxRegP() %{
4382 constraint(ALLOC_IN_RC(nax_reg));
4383 match(RegP);
4384 match(eBXRegP);
4385 match(eDXRegP);
4386 match(eCXRegP);
4387 match(eSIRegP);
4388 match(eDIRegP);
4389
4390 format %{ %}
4391 interface(REG_INTER);
4392 %}
4393
4394 operand nabxRegP() %{
4395 constraint(ALLOC_IN_RC(nabx_reg));
4396 match(RegP);
4397 match(eCXRegP);
4398 match(eDXRegP);
4399 match(eSIRegP);
4400 match(eDIRegP);
4401
4402 format %{ %}
4403 interface(REG_INTER);
4404 %}
4405
4406 operand pRegP() %{
4407 constraint(ALLOC_IN_RC(p_reg));
4408 match(RegP);
4409 match(eBXRegP);
4410 match(eDXRegP);
4411 match(eSIRegP);
4412 match(eDIRegP);
4413
4414 format %{ %}
4415 interface(REG_INTER);
4416 %}
4417
4418 // Special Registers
4419 // Return a pointer value
4420 operand eAXRegP(eRegP reg) %{
4421 constraint(ALLOC_IN_RC(eax_reg));
4422 match(reg);
4423 format %{ "EAX" %}
4424 interface(REG_INTER);
4425 %}
4426
4427 // Used in AtomicAdd
4428 operand eBXRegP(eRegP reg) %{
4429 constraint(ALLOC_IN_RC(ebx_reg));
4430 match(reg);
4431 format %{ "EBX" %}
4432 interface(REG_INTER);
4433 %}
4434
4435 // Tail-call (interprocedural jump) to interpreter
4436 operand eCXRegP(eRegP reg) %{
4437 constraint(ALLOC_IN_RC(ecx_reg));
4438 match(reg);
4439 format %{ "ECX" %}
4440 interface(REG_INTER);
4441 %}
4442
4443 operand eSIRegP(eRegP reg) %{
4444 constraint(ALLOC_IN_RC(esi_reg));
4445 match(reg);
4446 format %{ "ESI" %}
4447 interface(REG_INTER);
4448 %}
4449
4450 // Used in rep stosw
4451 operand eDIRegP(eRegP reg) %{
4452 constraint(ALLOC_IN_RC(edi_reg));
4453 match(reg);
4454 format %{ "EDI" %}
4455 interface(REG_INTER);
4456 %}
4457
4458 operand eBPRegP() %{
4459 constraint(ALLOC_IN_RC(ebp_reg));
4460 match(RegP);
4461 format %{ "EBP" %}
4462 interface(REG_INTER);
4463 %}
4464
4465 operand eRegL() %{
4466 constraint(ALLOC_IN_RC(long_reg));
4467 match(RegL);
4468 match(eADXRegL);
4469
4470 format %{ %}
4471 interface(REG_INTER);
4472 %}
4473
4474 operand eADXRegL( eRegL reg ) %{
4475 constraint(ALLOC_IN_RC(eadx_reg));
4476 match(reg);
4477
4478 format %{ "EDX:EAX" %}
4479 interface(REG_INTER);
4480 %}
4481
4482 operand eBCXRegL( eRegL reg ) %{
4483 constraint(ALLOC_IN_RC(ebcx_reg));
4484 match(reg);
4485
4486 format %{ "EBX:ECX" %}
4487 interface(REG_INTER);
4488 %}
4489
4490 // Special case for integer high multiply
4491 operand eADXRegL_low_only() %{
4492 constraint(ALLOC_IN_RC(eadx_reg));
4493 match(RegL);
4494
4495 format %{ "EAX" %}
4496 interface(REG_INTER);
4497 %}
4498
4499 // Flags register, used as output of compare instructions
4500 operand eFlagsReg() %{
4501 constraint(ALLOC_IN_RC(int_flags));
4502 match(RegFlags);
4503
4504 format %{ "EFLAGS" %}
4505 interface(REG_INTER);
4506 %}
4507
4508 // Flags register, used as output of FLOATING POINT compare instructions
4509 operand eFlagsRegU() %{
4510 constraint(ALLOC_IN_RC(int_flags));
4511 match(RegFlags);
4512
4513 format %{ "EFLAGS_U" %}
4514 interface(REG_INTER);
4515 %}
4516
4517 operand eFlagsRegUCF() %{
4518 constraint(ALLOC_IN_RC(int_flags));
4519 match(RegFlags);
4520 predicate(false);
4521
4522 format %{ "EFLAGS_U_CF" %}
4523 interface(REG_INTER);
4524 %}
4525
4526 // Condition Code Register used by long compare
4527 operand flagsReg_long_LTGE() %{
4528 constraint(ALLOC_IN_RC(int_flags));
4529 match(RegFlags);
4530 format %{ "FLAGS_LTGE" %}
4531 interface(REG_INTER);
4532 %}
4533 operand flagsReg_long_EQNE() %{
4534 constraint(ALLOC_IN_RC(int_flags));
4535 match(RegFlags);
4536 format %{ "FLAGS_EQNE" %}
4537 interface(REG_INTER);
4538 %}
4539 operand flagsReg_long_LEGT() %{
4540 constraint(ALLOC_IN_RC(int_flags));
4541 match(RegFlags);
4542 format %{ "FLAGS_LEGT" %}
4543 interface(REG_INTER);
4544 %}
4545
4546 // Float register operands
4547 operand regDPR() %{
4548 predicate( UseSSE < 2 );
4549 constraint(ALLOC_IN_RC(fp_dbl_reg));
4550 match(RegD);
4551 match(regDPR1);
4552 match(regDPR2);
4553 format %{ %}
4554 interface(REG_INTER);
4555 %}
4556
4557 operand regDPR1(regDPR reg) %{
4558 predicate( UseSSE < 2 );
4559 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4560 match(reg);
4561 format %{ "FPR1" %}
4562 interface(REG_INTER);
4563 %}
4564
4565 operand regDPR2(regDPR reg) %{
4566 predicate( UseSSE < 2 );
4567 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4568 match(reg);
4569 format %{ "FPR2" %}
4570 interface(REG_INTER);
4571 %}
4572
4573 operand regnotDPR1(regDPR reg) %{
4574 predicate( UseSSE < 2 );
4575 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4576 match(reg);
4577 format %{ %}
4578 interface(REG_INTER);
4579 %}
4580
4581 // Float register operands
4582 operand regFPR() %{
4583 predicate( UseSSE < 2 );
4584 constraint(ALLOC_IN_RC(fp_flt_reg));
4585 match(RegF);
4586 match(regFPR1);
4587 format %{ %}
4588 interface(REG_INTER);
4589 %}
4590
4591 // Float register operands
4592 operand regFPR1(regFPR reg) %{
4593 predicate( UseSSE < 2 );
4594 constraint(ALLOC_IN_RC(fp_flt_reg0));
4595 match(reg);
4596 format %{ "FPR1" %}
4597 interface(REG_INTER);
4598 %}
4599
4600 // XMM Float register operands
4601 operand regF() %{
4602 predicate( UseSSE>=1 );
4603 constraint(ALLOC_IN_RC(float_reg));
4604 match(RegF);
4605 format %{ %}
4606 interface(REG_INTER);
4607 %}
4608
4609 // XMM Double register operands
4610 operand regD() %{
4611 predicate( UseSSE>=2 );
4612 constraint(ALLOC_IN_RC(double_reg));
4613 match(RegD);
4614 format %{ %}
4615 interface(REG_INTER);
4616 %}
4617
4618
4619 //----------Memory Operands----------------------------------------------------
4620 // Direct Memory Operand
4621 operand direct(immP addr) %{
4622 match(addr);
4623
4624 format %{ "[$addr]" %}
4625 interface(MEMORY_INTER) %{
4626 base(0xFFFFFFFF);
4627 index(0x4);
4628 scale(0x0);
4629 disp($addr);
4630 %}
4631 %}
4632
4633 // Indirect Memory Operand
4634 operand indirect(eRegP reg) %{
4635 constraint(ALLOC_IN_RC(int_reg));
4636 match(reg);
4637
4638 format %{ "[$reg]" %}
4639 interface(MEMORY_INTER) %{
4640 base($reg);
4641 index(0x4);
4642 scale(0x0);
4643 disp(0x0);
4644 %}
4645 %}
4646
4647 // Indirect Memory Plus Short Offset Operand
4648 operand indOffset8(eRegP reg, immI8 off) %{
4649 match(AddP reg off);
4650
4651 format %{ "[$reg + $off]" %}
4652 interface(MEMORY_INTER) %{
4653 base($reg);
4654 index(0x4);
4655 scale(0x0);
4656 disp($off);
4657 %}
4658 %}
4659
4660 // Indirect Memory Plus Long Offset Operand
4661 operand indOffset32(eRegP reg, immI off) %{
4662 match(AddP reg off);
4663
4664 format %{ "[$reg + $off]" %}
4665 interface(MEMORY_INTER) %{
4666 base($reg);
4667 index(0x4);
4668 scale(0x0);
4669 disp($off);
4670 %}
4671 %}
4672
4673 // Indirect Memory Plus Long Offset Operand
4674 operand indOffset32X(rRegI reg, immP off) %{
4675 match(AddP off reg);
4676
4677 format %{ "[$reg + $off]" %}
4678 interface(MEMORY_INTER) %{
4679 base($reg);
4680 index(0x4);
4681 scale(0x0);
4682 disp($off);
4683 %}
4684 %}
4685
4686 // Indirect Memory Plus Index Register Plus Offset Operand
4687 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4688 match(AddP (AddP reg ireg) off);
4689
4690 op_cost(10);
4691 format %{"[$reg + $off + $ireg]" %}
4692 interface(MEMORY_INTER) %{
4693 base($reg);
4694 index($ireg);
4695 scale(0x0);
4696 disp($off);
4697 %}
4698 %}
4699
4700 // Indirect Memory Plus Index Register Plus Offset Operand
4701 operand indIndex(eRegP reg, rRegI ireg) %{
4702 match(AddP reg ireg);
4703
4704 op_cost(10);
4705 format %{"[$reg + $ireg]" %}
4706 interface(MEMORY_INTER) %{
4707 base($reg);
4708 index($ireg);
4709 scale(0x0);
4710 disp(0x0);
4711 %}
4712 %}
4713
4714 // // -------------------------------------------------------------------------
4715 // // 486 architecture doesn't support "scale * index + offset" with out a base
4716 // // -------------------------------------------------------------------------
4717 // // Scaled Memory Operands
4718 // // Indirect Memory Times Scale Plus Offset Operand
4719 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4720 // match(AddP off (LShiftI ireg scale));
4721 //
4722 // op_cost(10);
4723 // format %{"[$off + $ireg << $scale]" %}
4724 // interface(MEMORY_INTER) %{
4725 // base(0x4);
4726 // index($ireg);
4727 // scale($scale);
4728 // disp($off);
4729 // %}
4730 // %}
4731
4732 // Indirect Memory Times Scale Plus Index Register
4733 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4734 match(AddP reg (LShiftI ireg scale));
4735
4736 op_cost(10);
4737 format %{"[$reg + $ireg << $scale]" %}
4738 interface(MEMORY_INTER) %{
4739 base($reg);
4740 index($ireg);
4741 scale($scale);
4742 disp(0x0);
4743 %}
4744 %}
4745
4746 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4747 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4748 match(AddP (AddP reg (LShiftI ireg scale)) off);
4749
4750 op_cost(10);
4751 format %{"[$reg + $off + $ireg << $scale]" %}
4752 interface(MEMORY_INTER) %{
4753 base($reg);
4754 index($ireg);
4755 scale($scale);
4756 disp($off);
4757 %}
4758 %}
4759
4760 //----------Load Long Memory Operands------------------------------------------
4761 // The load-long idiom will use it's address expression again after loading
4762 // the first word of the long. If the load-long destination overlaps with
4763 // registers used in the addressing expression, the 2nd half will be loaded
4764 // from a clobbered address. Fix this by requiring that load-long use
4765 // address registers that do not overlap with the load-long target.
4766
4767 // load-long support
4768 operand load_long_RegP() %{
4769 constraint(ALLOC_IN_RC(esi_reg));
4770 match(RegP);
4771 match(eSIRegP);
4772 op_cost(100);
4773 format %{ %}
4774 interface(REG_INTER);
4775 %}
4776
4777 // Indirect Memory Operand Long
4778 operand load_long_indirect(load_long_RegP reg) %{
4779 constraint(ALLOC_IN_RC(esi_reg));
4780 match(reg);
4781
4782 format %{ "[$reg]" %}
4783 interface(MEMORY_INTER) %{
4784 base($reg);
4785 index(0x4);
4786 scale(0x0);
4787 disp(0x0);
4788 %}
4789 %}
4790
4791 // Indirect Memory Plus Long Offset Operand
4792 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4793 match(AddP reg off);
4794
4795 format %{ "[$reg + $off]" %}
4796 interface(MEMORY_INTER) %{
4797 base($reg);
4798 index(0x4);
4799 scale(0x0);
4800 disp($off);
4801 %}
4802 %}
4803
4804 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4805
4806
4807 //----------Special Memory Operands--------------------------------------------
4808 // Stack Slot Operand - This operand is used for loading and storing temporary
4809 // values on the stack where a match requires a value to
4810 // flow through memory.
4811 operand stackSlotP(sRegP reg) %{
4812 constraint(ALLOC_IN_RC(stack_slots));
4813 // No match rule because this operand is only generated in matching
4814 format %{ "[$reg]" %}
4815 interface(MEMORY_INTER) %{
4816 base(0x4); // ESP
4817 index(0x4); // No Index
4818 scale(0x0); // No Scale
4819 disp($reg); // Stack Offset
4820 %}
4821 %}
4822
4823 operand stackSlotI(sRegI reg) %{
4824 constraint(ALLOC_IN_RC(stack_slots));
4825 // No match rule because this operand is only generated in matching
4826 format %{ "[$reg]" %}
4827 interface(MEMORY_INTER) %{
4828 base(0x4); // ESP
4829 index(0x4); // No Index
4830 scale(0x0); // No Scale
4831 disp($reg); // Stack Offset
4832 %}
4833 %}
4834
4835 operand stackSlotF(sRegF reg) %{
4836 constraint(ALLOC_IN_RC(stack_slots));
4837 // No match rule because this operand is only generated in matching
4838 format %{ "[$reg]" %}
4839 interface(MEMORY_INTER) %{
4840 base(0x4); // ESP
4841 index(0x4); // No Index
4842 scale(0x0); // No Scale
4843 disp($reg); // Stack Offset
4844 %}
4845 %}
4846
4847 operand stackSlotD(sRegD reg) %{
4848 constraint(ALLOC_IN_RC(stack_slots));
4849 // No match rule because this operand is only generated in matching
4850 format %{ "[$reg]" %}
4851 interface(MEMORY_INTER) %{
4852 base(0x4); // ESP
4853 index(0x4); // No Index
4854 scale(0x0); // No Scale
4855 disp($reg); // Stack Offset
4856 %}
4857 %}
4858
4859 operand stackSlotL(sRegL reg) %{
4860 constraint(ALLOC_IN_RC(stack_slots));
4861 // No match rule because this operand is only generated in matching
4862 format %{ "[$reg]" %}
4863 interface(MEMORY_INTER) %{
4864 base(0x4); // ESP
4865 index(0x4); // No Index
4866 scale(0x0); // No Scale
4867 disp($reg); // Stack Offset
4868 %}
4869 %}
4870
4871 //----------Memory Operands - Win95 Implicit Null Variants----------------
4872 // Indirect Memory Operand
4873 operand indirect_win95_safe(eRegP_no_EBP reg)
4874 %{
4875 constraint(ALLOC_IN_RC(int_reg));
4876 match(reg);
4877
4878 op_cost(100);
4879 format %{ "[$reg]" %}
4880 interface(MEMORY_INTER) %{
4881 base($reg);
4882 index(0x4);
4883 scale(0x0);
4884 disp(0x0);
4885 %}
4886 %}
4887
4888 // Indirect Memory Plus Short Offset Operand
4889 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4890 %{
4891 match(AddP reg off);
4892
4893 op_cost(100);
4894 format %{ "[$reg + $off]" %}
4895 interface(MEMORY_INTER) %{
4896 base($reg);
4897 index(0x4);
4898 scale(0x0);
4899 disp($off);
4900 %}
4901 %}
4902
4903 // Indirect Memory Plus Long Offset Operand
4904 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4905 %{
4906 match(AddP reg off);
4907
4908 op_cost(100);
4909 format %{ "[$reg + $off]" %}
4910 interface(MEMORY_INTER) %{
4911 base($reg);
4912 index(0x4);
4913 scale(0x0);
4914 disp($off);
4915 %}
4916 %}
4917
4918 // Indirect Memory Plus Index Register Plus Offset Operand
4919 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4920 %{
4921 match(AddP (AddP reg ireg) off);
4922
4923 op_cost(100);
4924 format %{"[$reg + $off + $ireg]" %}
4925 interface(MEMORY_INTER) %{
4926 base($reg);
4927 index($ireg);
4928 scale(0x0);
4929 disp($off);
4930 %}
4931 %}
4932
4933 // Indirect Memory Times Scale Plus Index Register
4934 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4935 %{
4936 match(AddP reg (LShiftI ireg scale));
4937
4938 op_cost(100);
4939 format %{"[$reg + $ireg << $scale]" %}
4940 interface(MEMORY_INTER) %{
4941 base($reg);
4942 index($ireg);
4943 scale($scale);
4944 disp(0x0);
4945 %}
4946 %}
4947
4948 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4949 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4950 %{
4951 match(AddP (AddP reg (LShiftI ireg scale)) off);
4952
4953 op_cost(100);
4954 format %{"[$reg + $off + $ireg << $scale]" %}
4955 interface(MEMORY_INTER) %{
4956 base($reg);
4957 index($ireg);
4958 scale($scale);
4959 disp($off);
4960 %}
4961 %}
4962
4963 //----------Conditional Branch Operands----------------------------------------
4964 // Comparison Op - This is the operation of the comparison, and is limited to
4965 // the following set of codes:
4966 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4967 //
4968 // Other attributes of the comparison, such as unsignedness, are specified
4969 // by the comparison instruction that sets a condition code flags register.
4970 // That result is represented by a flags operand whose subtype is appropriate
4971 // to the unsignedness (etc.) of the comparison.
4972 //
4973 // Later, the instruction which matches both the Comparison Op (a Bool) and
4974 // the flags (produced by the Cmp) specifies the coding of the comparison op
4975 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4976
4977 // Comparision Code
4978 operand cmpOp() %{
4979 match(Bool);
4980
4981 format %{ "" %}
4982 interface(COND_INTER) %{
4983 equal(0x4, "e");
4984 not_equal(0x5, "ne");
4985 less(0xC, "l");
4986 greater_equal(0xD, "ge");
4987 less_equal(0xE, "le");
4988 greater(0xF, "g");
4989 %}
4990 %}
4991
4992 // Comparison Code, unsigned compare. Used by FP also, with
4993 // C2 (unordered) turned into GT or LT already. The other bits
4994 // C0 and C3 are turned into Carry & Zero flags.
4995 operand cmpOpU() %{
4996 match(Bool);
4997
4998 format %{ "" %}
4999 interface(COND_INTER) %{
5000 equal(0x4, "e");
5001 not_equal(0x5, "ne");
5002 less(0x2, "b");
5003 greater_equal(0x3, "nb");
5004 less_equal(0x6, "be");
5005 greater(0x7, "nbe");
5006 %}
5007 %}
5008
5009 // Floating comparisons that don't require any fixup for the unordered case
5010 operand cmpOpUCF() %{
5011 match(Bool);
5012 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5013 n->as_Bool()->_test._test == BoolTest::ge ||
5014 n->as_Bool()->_test._test == BoolTest::le ||
5015 n->as_Bool()->_test._test == BoolTest::gt);
5016 format %{ "" %}
5017 interface(COND_INTER) %{
5018 equal(0x4, "e");
5019 not_equal(0x5, "ne");
5020 less(0x2, "b");
5021 greater_equal(0x3, "nb");
5022 less_equal(0x6, "be");
5023 greater(0x7, "nbe");
5024 %}
5025 %}
5026
5027
5028 // Floating comparisons that can be fixed up with extra conditional jumps
5029 operand cmpOpUCF2() %{
5030 match(Bool);
5031 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5032 n->as_Bool()->_test._test == BoolTest::eq);
5033 format %{ "" %}
5034 interface(COND_INTER) %{
5035 equal(0x4, "e");
5036 not_equal(0x5, "ne");
5037 less(0x2, "b");
5038 greater_equal(0x3, "nb");
5039 less_equal(0x6, "be");
5040 greater(0x7, "nbe");
5041 %}
5042 %}
5043
5044 // Comparison Code for FP conditional move
5045 operand cmpOp_fcmov() %{
5046 match(Bool);
5047
5048 format %{ "" %}
5049 interface(COND_INTER) %{
5050 equal (0x0C8);
5051 not_equal (0x1C8);
5052 less (0x0C0);
5053 greater_equal(0x1C0);
5054 less_equal (0x0D0);
5055 greater (0x1D0);
5056 %}
5057 %}
5058
5059 // Comparision Code used in long compares
5060 operand cmpOp_commute() %{
5061 match(Bool);
5062
5063 format %{ "" %}
5064 interface(COND_INTER) %{
5065 equal(0x4, "e");
5066 not_equal(0x5, "ne");
5067 less(0xF, "g");
5068 greater_equal(0xE, "le");
5069 less_equal(0xD, "ge");
5070 greater(0xC, "l");
5071 %}
5072 %}
5073
5074 //----------OPERAND CLASSES----------------------------------------------------
5075 // Operand Classes are groups of operands that are used as to simplify
5076 // instruction definitions by not requiring the AD writer to specify separate
5077 // instructions for every form of operand when the instruction accepts
5078 // multiple operand types with the same basic encoding and format. The classic
5079 // case of this is memory operands.
5080
5081 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5082 indIndex, indIndexScale, indIndexScaleOffset);
5083
5084 // Long memory operations are encoded in 2 instructions and a +4 offset.
5085 // This means some kind of offset is always required and you cannot use
5086 // an oop as the offset (done when working on static globals).
5087 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5088 indIndex, indIndexScale, indIndexScaleOffset);
5089
5090
5091 //----------PIPELINE-----------------------------------------------------------
5092 // Rules which define the behavior of the target architectures pipeline.
5093 pipeline %{
5094
5095 //----------ATTRIBUTES---------------------------------------------------------
5096 attributes %{
5097 variable_size_instructions; // Fixed size instructions
5098 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5099 instruction_unit_size = 1; // An instruction is 1 bytes long
5100 instruction_fetch_unit_size = 16; // The processor fetches one line
5101 instruction_fetch_units = 1; // of 16 bytes
5102
5103 // List of nop instructions
5104 nops( MachNop );
5105 %}
5106
5107 //----------RESOURCES----------------------------------------------------------
5108 // Resources are the functional units available to the machine
5109
5110 // Generic P2/P3 pipeline
5111 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5112 // 3 instructions decoded per cycle.
5113 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5114 // 2 ALU op, only ALU0 handles mul/div instructions.
5115 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5116 MS0, MS1, MEM = MS0 | MS1,
5117 BR, FPU,
5118 ALU0, ALU1, ALU = ALU0 | ALU1 );
5119
5120 //----------PIPELINE DESCRIPTION-----------------------------------------------
5121 // Pipeline Description specifies the stages in the machine's pipeline
5122
5123 // Generic P2/P3 pipeline
5124 pipe_desc(S0, S1, S2, S3, S4, S5);
5125
5126 //----------PIPELINE CLASSES---------------------------------------------------
5127 // Pipeline Classes describe the stages in which input and output are
5128 // referenced by the hardware pipeline.
5129
5130 // Naming convention: ialu or fpu
5131 // Then: _reg
5132 // Then: _reg if there is a 2nd register
5133 // Then: _long if it's a pair of instructions implementing a long
5134 // Then: _fat if it requires the big decoder
5135 // Or: _mem if it requires the big decoder and a memory unit.
5136
5137 // Integer ALU reg operation
5138 pipe_class ialu_reg(rRegI dst) %{
5139 single_instruction;
5140 dst : S4(write);
5141 dst : S3(read);
5142 DECODE : S0; // any decoder
5143 ALU : S3; // any alu
5144 %}
5145
5146 // Long ALU reg operation
5147 pipe_class ialu_reg_long(eRegL dst) %{
5148 instruction_count(2);
5149 dst : S4(write);
5150 dst : S3(read);
5151 DECODE : S0(2); // any 2 decoders
5152 ALU : S3(2); // both alus
5153 %}
5154
5155 // Integer ALU reg operation using big decoder
5156 pipe_class ialu_reg_fat(rRegI dst) %{
5157 single_instruction;
5158 dst : S4(write);
5159 dst : S3(read);
5160 D0 : S0; // big decoder only
5161 ALU : S3; // any alu
5162 %}
5163
5164 // Long ALU reg operation using big decoder
5165 pipe_class ialu_reg_long_fat(eRegL dst) %{
5166 instruction_count(2);
5167 dst : S4(write);
5168 dst : S3(read);
5169 D0 : S0(2); // big decoder only; twice
5170 ALU : S3(2); // any 2 alus
5171 %}
5172
5173 // Integer ALU reg-reg operation
5174 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5175 single_instruction;
5176 dst : S4(write);
5177 src : S3(read);
5178 DECODE : S0; // any decoder
5179 ALU : S3; // any alu
5180 %}
5181
5182 // Long ALU reg-reg operation
5183 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5184 instruction_count(2);
5185 dst : S4(write);
5186 src : S3(read);
5187 DECODE : S0(2); // any 2 decoders
5188 ALU : S3(2); // both alus
5189 %}
5190
5191 // Integer ALU reg-reg operation
5192 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5193 single_instruction;
5194 dst : S4(write);
5195 src : S3(read);
5196 D0 : S0; // big decoder only
5197 ALU : S3; // any alu
5198 %}
5199
5200 // Long ALU reg-reg operation
5201 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5202 instruction_count(2);
5203 dst : S4(write);
5204 src : S3(read);
5205 D0 : S0(2); // big decoder only; twice
5206 ALU : S3(2); // both alus
5207 %}
5208
5209 // Integer ALU reg-mem operation
5210 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5211 single_instruction;
5212 dst : S5(write);
5213 mem : S3(read);
5214 D0 : S0; // big decoder only
5215 ALU : S4; // any alu
5216 MEM : S3; // any mem
5217 %}
5218
5219 // Long ALU reg-mem operation
5220 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5221 instruction_count(2);
5222 dst : S5(write);
5223 mem : S3(read);
5224 D0 : S0(2); // big decoder only; twice
5225 ALU : S4(2); // any 2 alus
5226 MEM : S3(2); // both mems
5227 %}
5228
5229 // Integer mem operation (prefetch)
5230 pipe_class ialu_mem(memory mem)
5231 %{
5232 single_instruction;
5233 mem : S3(read);
5234 D0 : S0; // big decoder only
5235 MEM : S3; // any mem
5236 %}
5237
5238 // Integer Store to Memory
5239 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5240 single_instruction;
5241 mem : S3(read);
5242 src : S5(read);
5243 D0 : S0; // big decoder only
5244 ALU : S4; // any alu
5245 MEM : S3;
5246 %}
5247
5248 // Long Store to Memory
5249 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5250 instruction_count(2);
5251 mem : S3(read);
5252 src : S5(read);
5253 D0 : S0(2); // big decoder only; twice
5254 ALU : S4(2); // any 2 alus
5255 MEM : S3(2); // Both mems
5256 %}
5257
5258 // Integer Store to Memory
5259 pipe_class ialu_mem_imm(memory mem) %{
5260 single_instruction;
5261 mem : S3(read);
5262 D0 : S0; // big decoder only
5263 ALU : S4; // any alu
5264 MEM : S3;
5265 %}
5266
5267 // Integer ALU0 reg-reg operation
5268 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5269 single_instruction;
5270 dst : S4(write);
5271 src : S3(read);
5272 D0 : S0; // Big decoder only
5273 ALU0 : S3; // only alu0
5274 %}
5275
5276 // Integer ALU0 reg-mem operation
5277 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5278 single_instruction;
5279 dst : S5(write);
5280 mem : S3(read);
5281 D0 : S0; // big decoder only
5282 ALU0 : S4; // ALU0 only
5283 MEM : S3; // any mem
5284 %}
5285
5286 // Integer ALU reg-reg operation
5287 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5288 single_instruction;
5289 cr : S4(write);
5290 src1 : S3(read);
5291 src2 : S3(read);
5292 DECODE : S0; // any decoder
5293 ALU : S3; // any alu
5294 %}
5295
5296 // Integer ALU reg-imm operation
5297 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5298 single_instruction;
5299 cr : S4(write);
5300 src1 : S3(read);
5301 DECODE : S0; // any decoder
5302 ALU : S3; // any alu
5303 %}
5304
5305 // Integer ALU reg-mem operation
5306 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5307 single_instruction;
5308 cr : S4(write);
5309 src1 : S3(read);
5310 src2 : S3(read);
5311 D0 : S0; // big decoder only
5312 ALU : S4; // any alu
5313 MEM : S3;
5314 %}
5315
5316 // Conditional move reg-reg
5317 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5318 instruction_count(4);
5319 y : S4(read);
5320 q : S3(read);
5321 p : S3(read);
5322 DECODE : S0(4); // any decoder
5323 %}
5324
5325 // Conditional move reg-reg
5326 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5327 single_instruction;
5328 dst : S4(write);
5329 src : S3(read);
5330 cr : S3(read);
5331 DECODE : S0; // any decoder
5332 %}
5333
5334 // Conditional move reg-mem
5335 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5336 single_instruction;
5337 dst : S4(write);
5338 src : S3(read);
5339 cr : S3(read);
5340 DECODE : S0; // any decoder
5341 MEM : S3;
5342 %}
5343
5344 // Conditional move reg-reg long
5345 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5346 single_instruction;
5347 dst : S4(write);
5348 src : S3(read);
5349 cr : S3(read);
5350 DECODE : S0(2); // any 2 decoders
5351 %}
5352
5353 // Conditional move double reg-reg
5354 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5355 single_instruction;
5356 dst : S4(write);
5357 src : S3(read);
5358 cr : S3(read);
5359 DECODE : S0; // any decoder
5360 %}
5361
5362 // Float reg-reg operation
5363 pipe_class fpu_reg(regDPR dst) %{
5364 instruction_count(2);
5365 dst : S3(read);
5366 DECODE : S0(2); // any 2 decoders
5367 FPU : S3;
5368 %}
5369
5370 // Float reg-reg operation
5371 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5372 instruction_count(2);
5373 dst : S4(write);
5374 src : S3(read);
5375 DECODE : S0(2); // any 2 decoders
5376 FPU : S3;
5377 %}
5378
5379 // Float reg-reg operation
5380 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5381 instruction_count(3);
5382 dst : S4(write);
5383 src1 : S3(read);
5384 src2 : S3(read);
5385 DECODE : S0(3); // any 3 decoders
5386 FPU : S3(2);
5387 %}
5388
5389 // Float reg-reg operation
5390 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5391 instruction_count(4);
5392 dst : S4(write);
5393 src1 : S3(read);
5394 src2 : S3(read);
5395 src3 : S3(read);
5396 DECODE : S0(4); // any 3 decoders
5397 FPU : S3(2);
5398 %}
5399
5400 // Float reg-reg operation
5401 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5402 instruction_count(4);
5403 dst : S4(write);
5404 src1 : S3(read);
5405 src2 : S3(read);
5406 src3 : S3(read);
5407 DECODE : S1(3); // any 3 decoders
5408 D0 : S0; // Big decoder only
5409 FPU : S3(2);
5410 MEM : S3;
5411 %}
5412
5413 // Float reg-mem operation
5414 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5415 instruction_count(2);
5416 dst : S5(write);
5417 mem : S3(read);
5418 D0 : S0; // big decoder only
5419 DECODE : S1; // any decoder for FPU POP
5420 FPU : S4;
5421 MEM : S3; // any mem
5422 %}
5423
5424 // Float reg-mem operation
5425 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5426 instruction_count(3);
5427 dst : S5(write);
5428 src1 : S3(read);
5429 mem : S3(read);
5430 D0 : S0; // big decoder only
5431 DECODE : S1(2); // any decoder for FPU POP
5432 FPU : S4;
5433 MEM : S3; // any mem
5434 %}
5435
5436 // Float mem-reg operation
5437 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5438 instruction_count(2);
5439 src : S5(read);
5440 mem : S3(read);
5441 DECODE : S0; // any decoder for FPU PUSH
5442 D0 : S1; // big decoder only
5443 FPU : S4;
5444 MEM : S3; // any mem
5445 %}
5446
5447 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5448 instruction_count(3);
5449 src1 : S3(read);
5450 src2 : S3(read);
5451 mem : S3(read);
5452 DECODE : S0(2); // any decoder for FPU PUSH
5453 D0 : S1; // big decoder only
5454 FPU : S4;
5455 MEM : S3; // any mem
5456 %}
5457
5458 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5459 instruction_count(3);
5460 src1 : S3(read);
5461 src2 : S3(read);
5462 mem : S4(read);
5463 DECODE : S0; // any decoder for FPU PUSH
5464 D0 : S0(2); // big decoder only
5465 FPU : S4;
5466 MEM : S3(2); // any mem
5467 %}
5468
5469 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5470 instruction_count(2);
5471 src1 : S3(read);
5472 dst : S4(read);
5473 D0 : S0(2); // big decoder only
5474 MEM : S3(2); // any mem
5475 %}
5476
5477 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5478 instruction_count(3);
5479 src1 : S3(read);
5480 src2 : S3(read);
5481 dst : S4(read);
5482 D0 : S0(3); // big decoder only
5483 FPU : S4;
5484 MEM : S3(3); // any mem
5485 %}
5486
5487 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5488 instruction_count(3);
5489 src1 : S4(read);
5490 mem : S4(read);
5491 DECODE : S0; // any decoder for FPU PUSH
5492 D0 : S0(2); // big decoder only
5493 FPU : S4;
5494 MEM : S3(2); // any mem
5495 %}
5496
5497 // Float load constant
5498 pipe_class fpu_reg_con(regDPR dst) %{
5499 instruction_count(2);
5500 dst : S5(write);
5501 D0 : S0; // big decoder only for the load
5502 DECODE : S1; // any decoder for FPU POP
5503 FPU : S4;
5504 MEM : S3; // any mem
5505 %}
5506
5507 // Float load constant
5508 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5509 instruction_count(3);
5510 dst : S5(write);
5511 src : S3(read);
5512 D0 : S0; // big decoder only for the load
5513 DECODE : S1(2); // any decoder for FPU POP
5514 FPU : S4;
5515 MEM : S3; // any mem
5516 %}
5517
5518 // UnConditional branch
5519 pipe_class pipe_jmp( label labl ) %{
5520 single_instruction;
5521 BR : S3;
5522 %}
5523
5524 // Conditional branch
5525 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5526 single_instruction;
5527 cr : S1(read);
5528 BR : S3;
5529 %}
5530
5531 // Allocation idiom
5532 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5533 instruction_count(1); force_serialization;
5534 fixed_latency(6);
5535 heap_ptr : S3(read);
5536 DECODE : S0(3);
5537 D0 : S2;
5538 MEM : S3;
5539 ALU : S3(2);
5540 dst : S5(write);
5541 BR : S5;
5542 %}
5543
5544 // Generic big/slow expanded idiom
5545 pipe_class pipe_slow( ) %{
5546 instruction_count(10); multiple_bundles; force_serialization;
5547 fixed_latency(100);
5548 D0 : S0(2);
5549 MEM : S3(2);
5550 %}
5551
5552 // The real do-nothing guy
5553 pipe_class empty( ) %{
5554 instruction_count(0);
5555 %}
5556
5557 // Define the class for the Nop node
5558 define %{
5559 MachNop = empty;
5560 %}
5561
5562 %}
5563
5564 //----------INSTRUCTIONS-------------------------------------------------------
5565 //
5566 // match -- States which machine-independent subtree may be replaced
5567 // by this instruction.
5568 // ins_cost -- The estimated cost of this instruction is used by instruction
5569 // selection to identify a minimum cost tree of machine
5570 // instructions that matches a tree of machine-independent
5571 // instructions.
5572 // format -- A string providing the disassembly for this instruction.
5573 // The value of an instruction's operand may be inserted
5574 // by referring to it with a '$' prefix.
5575 // opcode -- Three instruction opcodes may be provided. These are referred
5576 // to within an encode class as $primary, $secondary, and $tertiary
5577 // respectively. The primary opcode is commonly used to
5578 // indicate the type of machine instruction, while secondary
5579 // and tertiary are often used for prefix options or addressing
5580 // modes.
5581 // ins_encode -- A list of encode classes with parameters. The encode class
5582 // name must have been defined in an 'enc_class' specification
5583 // in the encode section of the architecture description.
5584
5585 //----------BSWAP-Instruction--------------------------------------------------
5586 instruct bytes_reverse_int(rRegI dst) %{
5587 match(Set dst (ReverseBytesI dst));
5588
5589 format %{ "BSWAP $dst" %}
5590 opcode(0x0F, 0xC8);
5591 ins_encode( OpcP, OpcSReg(dst) );
5592 ins_pipe( ialu_reg );
5593 %}
5594
5595 instruct bytes_reverse_long(eRegL dst) %{
5596 match(Set dst (ReverseBytesL dst));
5597
5598 format %{ "BSWAP $dst.lo\n\t"
5599 "BSWAP $dst.hi\n\t"
5600 "XCHG $dst.lo $dst.hi" %}
5601
5602 ins_cost(125);
5603 ins_encode( bswap_long_bytes(dst) );
5604 ins_pipe( ialu_reg_reg);
5605 %}
5606
5607 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5608 match(Set dst (ReverseBytesUS dst));
5609 effect(KILL cr);
5610
5611 format %{ "BSWAP $dst\n\t"
5612 "SHR $dst,16\n\t" %}
5613 ins_encode %{
5614 __ bswapl($dst$$Register);
5615 __ shrl($dst$$Register, 16);
5616 %}
5617 ins_pipe( ialu_reg );
5618 %}
5619
5620 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5621 match(Set dst (ReverseBytesS dst));
5622 effect(KILL cr);
5623
5624 format %{ "BSWAP $dst\n\t"
5625 "SAR $dst,16\n\t" %}
5626 ins_encode %{
5627 __ bswapl($dst$$Register);
5628 __ sarl($dst$$Register, 16);
5629 %}
5630 ins_pipe( ialu_reg );
5631 %}
5632
5633
5634 //---------- Zeros Count Instructions ------------------------------------------
5635
5636 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5637 predicate(UseCountLeadingZerosInstruction);
5638 match(Set dst (CountLeadingZerosI src));
5639 effect(KILL cr);
5640
5641 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5642 ins_encode %{
5643 __ lzcntl($dst$$Register, $src$$Register);
5644 %}
5645 ins_pipe(ialu_reg);
5646 %}
5647
5648 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5649 predicate(!UseCountLeadingZerosInstruction);
5650 match(Set dst (CountLeadingZerosI src));
5651 effect(KILL cr);
5652
5653 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5654 "JNZ skip\n\t"
5655 "MOV $dst, -1\n"
5656 "skip:\n\t"
5657 "NEG $dst\n\t"
5658 "ADD $dst, 31" %}
5659 ins_encode %{
5660 Register Rdst = $dst$$Register;
5661 Register Rsrc = $src$$Register;
5662 Label skip;
5663 __ bsrl(Rdst, Rsrc);
5664 __ jccb(Assembler::notZero, skip);
5665 __ movl(Rdst, -1);
5666 __ bind(skip);
5667 __ negl(Rdst);
5668 __ addl(Rdst, BitsPerInt - 1);
5669 %}
5670 ins_pipe(ialu_reg);
5671 %}
5672
5673 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5674 predicate(UseCountLeadingZerosInstruction);
5675 match(Set dst (CountLeadingZerosL src));
5676 effect(TEMP dst, KILL cr);
5677
5678 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5679 "JNC done\n\t"
5680 "LZCNT $dst, $src.lo\n\t"
5681 "ADD $dst, 32\n"
5682 "done:" %}
5683 ins_encode %{
5684 Register Rdst = $dst$$Register;
5685 Register Rsrc = $src$$Register;
5686 Label done;
5687 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5688 __ jccb(Assembler::carryClear, done);
5689 __ lzcntl(Rdst, Rsrc);
5690 __ addl(Rdst, BitsPerInt);
5691 __ bind(done);
5692 %}
5693 ins_pipe(ialu_reg);
5694 %}
5695
5696 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5697 predicate(!UseCountLeadingZerosInstruction);
5698 match(Set dst (CountLeadingZerosL src));
5699 effect(TEMP dst, KILL cr);
5700
5701 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5702 "JZ msw_is_zero\n\t"
5703 "ADD $dst, 32\n\t"
5704 "JMP not_zero\n"
5705 "msw_is_zero:\n\t"
5706 "BSR $dst, $src.lo\n\t"
5707 "JNZ not_zero\n\t"
5708 "MOV $dst, -1\n"
5709 "not_zero:\n\t"
5710 "NEG $dst\n\t"
5711 "ADD $dst, 63\n" %}
5712 ins_encode %{
5713 Register Rdst = $dst$$Register;
5714 Register Rsrc = $src$$Register;
5715 Label msw_is_zero;
5716 Label not_zero;
5717 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5718 __ jccb(Assembler::zero, msw_is_zero);
5719 __ addl(Rdst, BitsPerInt);
5720 __ jmpb(not_zero);
5721 __ bind(msw_is_zero);
5722 __ bsrl(Rdst, Rsrc);
5723 __ jccb(Assembler::notZero, not_zero);
5724 __ movl(Rdst, -1);
5725 __ bind(not_zero);
5726 __ negl(Rdst);
5727 __ addl(Rdst, BitsPerLong - 1);
5728 %}
5729 ins_pipe(ialu_reg);
5730 %}
5731
5732 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5733 match(Set dst (CountTrailingZerosI src));
5734 effect(KILL cr);
5735
5736 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5737 "JNZ done\n\t"
5738 "MOV $dst, 32\n"
5739 "done:" %}
5740 ins_encode %{
5741 Register Rdst = $dst$$Register;
5742 Label done;
5743 __ bsfl(Rdst, $src$$Register);
5744 __ jccb(Assembler::notZero, done);
5745 __ movl(Rdst, BitsPerInt);
5746 __ bind(done);
5747 %}
5748 ins_pipe(ialu_reg);
5749 %}
5750
5751 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5752 match(Set dst (CountTrailingZerosL src));
5753 effect(TEMP dst, KILL cr);
5754
5755 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5756 "JNZ done\n\t"
5757 "BSF $dst, $src.hi\n\t"
5758 "JNZ msw_not_zero\n\t"
5759 "MOV $dst, 32\n"
5760 "msw_not_zero:\n\t"
5761 "ADD $dst, 32\n"
5762 "done:" %}
5763 ins_encode %{
5764 Register Rdst = $dst$$Register;
5765 Register Rsrc = $src$$Register;
5766 Label msw_not_zero;
5767 Label done;
5768 __ bsfl(Rdst, Rsrc);
5769 __ jccb(Assembler::notZero, done);
5770 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5771 __ jccb(Assembler::notZero, msw_not_zero);
5772 __ movl(Rdst, BitsPerInt);
5773 __ bind(msw_not_zero);
5774 __ addl(Rdst, BitsPerInt);
5775 __ bind(done);
5776 %}
5777 ins_pipe(ialu_reg);
5778 %}
5779
5780
5781 //---------- Population Count Instructions -------------------------------------
5782
5783 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5784 predicate(UsePopCountInstruction);
5785 match(Set dst (PopCountI src));
5786 effect(KILL cr);
5787
5788 format %{ "POPCNT $dst, $src" %}
5789 ins_encode %{
5790 __ popcntl($dst$$Register, $src$$Register);
5791 %}
5792 ins_pipe(ialu_reg);
5793 %}
5794
5795 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5796 predicate(UsePopCountInstruction);
5797 match(Set dst (PopCountI (LoadI mem)));
5798 effect(KILL cr);
5799
5800 format %{ "POPCNT $dst, $mem" %}
5801 ins_encode %{
5802 __ popcntl($dst$$Register, $mem$$Address);
5803 %}
5804 ins_pipe(ialu_reg);
5805 %}
5806
5807 // Note: Long.bitCount(long) returns an int.
5808 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5809 predicate(UsePopCountInstruction);
5810 match(Set dst (PopCountL src));
5811 effect(KILL cr, TEMP tmp, TEMP dst);
5812
5813 format %{ "POPCNT $dst, $src.lo\n\t"
5814 "POPCNT $tmp, $src.hi\n\t"
5815 "ADD $dst, $tmp" %}
5816 ins_encode %{
5817 __ popcntl($dst$$Register, $src$$Register);
5818 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5819 __ addl($dst$$Register, $tmp$$Register);
5820 %}
5821 ins_pipe(ialu_reg);
5822 %}
5823
5824 // Note: Long.bitCount(long) returns an int.
5825 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5826 predicate(UsePopCountInstruction);
5827 match(Set dst (PopCountL (LoadL mem)));
5828 effect(KILL cr, TEMP tmp, TEMP dst);
5829
5830 format %{ "POPCNT $dst, $mem\n\t"
5831 "POPCNT $tmp, $mem+4\n\t"
5832 "ADD $dst, $tmp" %}
5833 ins_encode %{
5834 //__ popcntl($dst$$Register, $mem$$Address$$first);
5835 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5836 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
5837 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
5838 __ addl($dst$$Register, $tmp$$Register);
5839 %}
5840 ins_pipe(ialu_reg);
5841 %}
5842
5843
5844 //----------Load/Store/Move Instructions---------------------------------------
5845 //----------Load Instructions--------------------------------------------------
5846 // Load Byte (8bit signed)
5847 instruct loadB(xRegI dst, memory mem) %{
5848 match(Set dst (LoadB mem));
5849
5850 ins_cost(125);
5851 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5852
5853 ins_encode %{
5854 __ movsbl($dst$$Register, $mem$$Address);
5855 %}
5856
5857 ins_pipe(ialu_reg_mem);
5858 %}
5859
5860 // Load Byte (8bit signed) into Long Register
5861 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5862 match(Set dst (ConvI2L (LoadB mem)));
5863 effect(KILL cr);
5864
5865 ins_cost(375);
5866 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5867 "MOV $dst.hi,$dst.lo\n\t"
5868 "SAR $dst.hi,7" %}
5869
5870 ins_encode %{
5871 __ movsbl($dst$$Register, $mem$$Address);
5872 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5873 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5874 %}
5875
5876 ins_pipe(ialu_reg_mem);
5877 %}
5878
5879 // Load Unsigned Byte (8bit UNsigned)
5880 instruct loadUB(xRegI dst, memory mem) %{
5881 match(Set dst (LoadUB mem));
5882
5883 ins_cost(125);
5884 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5885
5886 ins_encode %{
5887 __ movzbl($dst$$Register, $mem$$Address);
5888 %}
5889
5890 ins_pipe(ialu_reg_mem);
5891 %}
5892
5893 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5894 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5895 match(Set dst (ConvI2L (LoadUB mem)));
5896 effect(KILL cr);
5897
5898 ins_cost(250);
5899 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5900 "XOR $dst.hi,$dst.hi" %}
5901
5902 ins_encode %{
5903 Register Rdst = $dst$$Register;
5904 __ movzbl(Rdst, $mem$$Address);
5905 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5906 %}
5907
5908 ins_pipe(ialu_reg_mem);
5909 %}
5910
5911 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5912 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5913 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5914 effect(KILL cr);
5915
5916 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5917 "XOR $dst.hi,$dst.hi\n\t"
5918 "AND $dst.lo,$mask" %}
5919 ins_encode %{
5920 Register Rdst = $dst$$Register;
5921 __ movzbl(Rdst, $mem$$Address);
5922 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5923 __ andl(Rdst, $mask$$constant);
5924 %}
5925 ins_pipe(ialu_reg_mem);
5926 %}
5927
5928 // Load Short (16bit signed)
5929 instruct loadS(rRegI dst, memory mem) %{
5930 match(Set dst (LoadS mem));
5931
5932 ins_cost(125);
5933 format %{ "MOVSX $dst,$mem\t# short" %}
5934
5935 ins_encode %{
5936 __ movswl($dst$$Register, $mem$$Address);
5937 %}
5938
5939 ins_pipe(ialu_reg_mem);
5940 %}
5941
5942 // Load Short (16 bit signed) to Byte (8 bit signed)
5943 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5944 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5945
5946 ins_cost(125);
5947 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5948 ins_encode %{
5949 __ movsbl($dst$$Register, $mem$$Address);
5950 %}
5951 ins_pipe(ialu_reg_mem);
5952 %}
5953
5954 // Load Short (16bit signed) into Long Register
5955 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5956 match(Set dst (ConvI2L (LoadS mem)));
5957 effect(KILL cr);
5958
5959 ins_cost(375);
5960 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5961 "MOV $dst.hi,$dst.lo\n\t"
5962 "SAR $dst.hi,15" %}
5963
5964 ins_encode %{
5965 __ movswl($dst$$Register, $mem$$Address);
5966 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5967 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5968 %}
5969
5970 ins_pipe(ialu_reg_mem);
5971 %}
5972
5973 // Load Unsigned Short/Char (16bit unsigned)
5974 instruct loadUS(rRegI dst, memory mem) %{
5975 match(Set dst (LoadUS mem));
5976
5977 ins_cost(125);
5978 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5979
5980 ins_encode %{
5981 __ movzwl($dst$$Register, $mem$$Address);
5982 %}
5983
5984 ins_pipe(ialu_reg_mem);
5985 %}
5986
5987 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5988 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5989 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5990
5991 ins_cost(125);
5992 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5993 ins_encode %{
5994 __ movsbl($dst$$Register, $mem$$Address);
5995 %}
5996 ins_pipe(ialu_reg_mem);
5997 %}
5998
5999 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6000 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6001 match(Set dst (ConvI2L (LoadUS mem)));
6002 effect(KILL cr);
6003
6004 ins_cost(250);
6005 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6006 "XOR $dst.hi,$dst.hi" %}
6007
6008 ins_encode %{
6009 __ movzwl($dst$$Register, $mem$$Address);
6010 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6011 %}
6012
6013 ins_pipe(ialu_reg_mem);
6014 %}
6015
6016 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6017 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6018 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6019 effect(KILL cr);
6020
6021 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6022 "XOR $dst.hi,$dst.hi" %}
6023 ins_encode %{
6024 Register Rdst = $dst$$Register;
6025 __ movzbl(Rdst, $mem$$Address);
6026 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6027 %}
6028 ins_pipe(ialu_reg_mem);
6029 %}
6030
6031 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6032 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6033 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6034 effect(KILL cr);
6035
6036 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6037 "XOR $dst.hi,$dst.hi\n\t"
6038 "AND $dst.lo,$mask" %}
6039 ins_encode %{
6040 Register Rdst = $dst$$Register;
6041 __ movzwl(Rdst, $mem$$Address);
6042 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6043 __ andl(Rdst, $mask$$constant);
6044 %}
6045 ins_pipe(ialu_reg_mem);
6046 %}
6047
6048 // Load Integer
6049 instruct loadI(rRegI dst, memory mem) %{
6050 match(Set dst (LoadI mem));
6051
6052 ins_cost(125);
6053 format %{ "MOV $dst,$mem\t# int" %}
6054
6055 ins_encode %{
6056 __ movl($dst$$Register, $mem$$Address);
6057 %}
6058
6059 ins_pipe(ialu_reg_mem);
6060 %}
6061
6062 // Load Integer (32 bit signed) to Byte (8 bit signed)
6063 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6064 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6065
6066 ins_cost(125);
6067 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6068 ins_encode %{
6069 __ movsbl($dst$$Register, $mem$$Address);
6070 %}
6071 ins_pipe(ialu_reg_mem);
6072 %}
6073
6074 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6075 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6076 match(Set dst (AndI (LoadI mem) mask));
6077
6078 ins_cost(125);
6079 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6080 ins_encode %{
6081 __ movzbl($dst$$Register, $mem$$Address);
6082 %}
6083 ins_pipe(ialu_reg_mem);
6084 %}
6085
6086 // Load Integer (32 bit signed) to Short (16 bit signed)
6087 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6088 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6089
6090 ins_cost(125);
6091 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6092 ins_encode %{
6093 __ movswl($dst$$Register, $mem$$Address);
6094 %}
6095 ins_pipe(ialu_reg_mem);
6096 %}
6097
6098 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6099 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6100 match(Set dst (AndI (LoadI mem) mask));
6101
6102 ins_cost(125);
6103 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6104 ins_encode %{
6105 __ movzwl($dst$$Register, $mem$$Address);
6106 %}
6107 ins_pipe(ialu_reg_mem);
6108 %}
6109
6110 // Load Integer into Long Register
6111 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6112 match(Set dst (ConvI2L (LoadI mem)));
6113 effect(KILL cr);
6114
6115 ins_cost(375);
6116 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6117 "MOV $dst.hi,$dst.lo\n\t"
6118 "SAR $dst.hi,31" %}
6119
6120 ins_encode %{
6121 __ movl($dst$$Register, $mem$$Address);
6122 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6123 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6124 %}
6125
6126 ins_pipe(ialu_reg_mem);
6127 %}
6128
6129 // Load Integer with mask 0xFF into Long Register
6130 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6131 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6132 effect(KILL cr);
6133
6134 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6135 "XOR $dst.hi,$dst.hi" %}
6136 ins_encode %{
6137 Register Rdst = $dst$$Register;
6138 __ movzbl(Rdst, $mem$$Address);
6139 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6140 %}
6141 ins_pipe(ialu_reg_mem);
6142 %}
6143
6144 // Load Integer with mask 0xFFFF into Long Register
6145 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6146 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6147 effect(KILL cr);
6148
6149 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6150 "XOR $dst.hi,$dst.hi" %}
6151 ins_encode %{
6152 Register Rdst = $dst$$Register;
6153 __ movzwl(Rdst, $mem$$Address);
6154 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6155 %}
6156 ins_pipe(ialu_reg_mem);
6157 %}
6158
6159 // Load Integer with 32-bit mask into Long Register
6160 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6161 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6162 effect(KILL cr);
6163
6164 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6165 "XOR $dst.hi,$dst.hi\n\t"
6166 "AND $dst.lo,$mask" %}
6167 ins_encode %{
6168 Register Rdst = $dst$$Register;
6169 __ movl(Rdst, $mem$$Address);
6170 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6171 __ andl(Rdst, $mask$$constant);
6172 %}
6173 ins_pipe(ialu_reg_mem);
6174 %}
6175
6176 // Load Unsigned Integer into Long Register
6177 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6178 match(Set dst (LoadUI2L mem));
6179 effect(KILL cr);
6180
6181 ins_cost(250);
6182 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6183 "XOR $dst.hi,$dst.hi" %}
6184
6185 ins_encode %{
6186 __ movl($dst$$Register, $mem$$Address);
6187 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6188 %}
6189
6190 ins_pipe(ialu_reg_mem);
6191 %}
6192
6193 // Load Long. Cannot clobber address while loading, so restrict address
6194 // register to ESI
6195 instruct loadL(eRegL dst, load_long_memory mem) %{
6196 predicate(!((LoadLNode*)n)->require_atomic_access());
6197 match(Set dst (LoadL mem));
6198
6199 ins_cost(250);
6200 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6201 "MOV $dst.hi,$mem+4" %}
6202
6203 ins_encode %{
6204 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6205 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6206 __ movl($dst$$Register, Amemlo);
6207 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6208 %}
6209
6210 ins_pipe(ialu_reg_long_mem);
6211 %}
6212
6213 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6214 // then store it down to the stack and reload on the int
6215 // side.
6216 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6217 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6218 match(Set dst (LoadL mem));
6219
6220 ins_cost(200);
6221 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6222 "FISTp $dst" %}
6223 ins_encode(enc_loadL_volatile(mem,dst));
6224 ins_pipe( fpu_reg_mem );
6225 %}
6226
6227 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6228 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6229 match(Set dst (LoadL mem));
6230 effect(TEMP tmp);
6231 ins_cost(180);
6232 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6233 "MOVSD $dst,$tmp" %}
6234 ins_encode %{
6235 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6236 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6237 %}
6238 ins_pipe( pipe_slow );
6239 %}
6240
6241 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6242 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6243 match(Set dst (LoadL mem));
6244 effect(TEMP tmp);
6245 ins_cost(160);
6246 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6247 "MOVD $dst.lo,$tmp\n\t"
6248 "PSRLQ $tmp,32\n\t"
6249 "MOVD $dst.hi,$tmp" %}
6250 ins_encode %{
6251 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6252 __ movdl($dst$$Register, $tmp$$XMMRegister);
6253 __ psrlq($tmp$$XMMRegister, 32);
6254 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6255 %}
6256 ins_pipe( pipe_slow );
6257 %}
6258
6259 // Load Range
6260 instruct loadRange(rRegI dst, memory mem) %{
6261 match(Set dst (LoadRange mem));
6262
6263 ins_cost(125);
6264 format %{ "MOV $dst,$mem" %}
6265 opcode(0x8B);
6266 ins_encode( OpcP, RegMem(dst,mem));
6267 ins_pipe( ialu_reg_mem );
6268 %}
6269
6270
6271 // Load Pointer
6272 instruct loadP(eRegP dst, memory mem) %{
6273 match(Set dst (LoadP mem));
6274
6275 ins_cost(125);
6276 format %{ "MOV $dst,$mem" %}
6277 opcode(0x8B);
6278 ins_encode( OpcP, RegMem(dst,mem));
6279 ins_pipe( ialu_reg_mem );
6280 %}
6281
6282 // Load Klass Pointer
6283 instruct loadKlass(eRegP dst, memory mem) %{
6284 match(Set dst (LoadKlass mem));
6285
6286 ins_cost(125);
6287 format %{ "MOV $dst,$mem" %}
6288 opcode(0x8B);
6289 ins_encode( OpcP, RegMem(dst,mem));
6290 ins_pipe( ialu_reg_mem );
6291 %}
6292
6293 // Load Double
6294 instruct loadDPR(regDPR dst, memory mem) %{
6295 predicate(UseSSE<=1);
6296 match(Set dst (LoadD mem));
6297
6298 ins_cost(150);
6299 format %{ "FLD_D ST,$mem\n\t"
6300 "FSTP $dst" %}
6301 opcode(0xDD); /* DD /0 */
6302 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6303 Pop_Reg_DPR(dst) );
6304 ins_pipe( fpu_reg_mem );
6305 %}
6306
6307 // Load Double to XMM
6308 instruct loadD(regD dst, memory mem) %{
6309 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6310 match(Set dst (LoadD mem));
6311 ins_cost(145);
6312 format %{ "MOVSD $dst,$mem" %}
6313 ins_encode %{
6314 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6315 %}
6316 ins_pipe( pipe_slow );
6317 %}
6318
6319 instruct loadD_partial(regD dst, memory mem) %{
6320 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6321 match(Set dst (LoadD mem));
6322 ins_cost(145);
6323 format %{ "MOVLPD $dst,$mem" %}
6324 ins_encode %{
6325 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6326 %}
6327 ins_pipe( pipe_slow );
6328 %}
6329
6330 // Load to XMM register (single-precision floating point)
6331 // MOVSS instruction
6332 instruct loadF(regF dst, memory mem) %{
6333 predicate(UseSSE>=1);
6334 match(Set dst (LoadF mem));
6335 ins_cost(145);
6336 format %{ "MOVSS $dst,$mem" %}
6337 ins_encode %{
6338 __ movflt ($dst$$XMMRegister, $mem$$Address);
6339 %}
6340 ins_pipe( pipe_slow );
6341 %}
6342
6343 // Load Float
6344 instruct loadFPR(regFPR dst, memory mem) %{
6345 predicate(UseSSE==0);
6346 match(Set dst (LoadF mem));
6347
6348 ins_cost(150);
6349 format %{ "FLD_S ST,$mem\n\t"
6350 "FSTP $dst" %}
6351 opcode(0xD9); /* D9 /0 */
6352 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6353 Pop_Reg_FPR(dst) );
6354 ins_pipe( fpu_reg_mem );
6355 %}
6356
6357 // Load Effective Address
6358 instruct leaP8(eRegP dst, indOffset8 mem) %{
6359 match(Set dst mem);
6360
6361 ins_cost(110);
6362 format %{ "LEA $dst,$mem" %}
6363 opcode(0x8D);
6364 ins_encode( OpcP, RegMem(dst,mem));
6365 ins_pipe( ialu_reg_reg_fat );
6366 %}
6367
6368 instruct leaP32(eRegP dst, indOffset32 mem) %{
6369 match(Set dst mem);
6370
6371 ins_cost(110);
6372 format %{ "LEA $dst,$mem" %}
6373 opcode(0x8D);
6374 ins_encode( OpcP, RegMem(dst,mem));
6375 ins_pipe( ialu_reg_reg_fat );
6376 %}
6377
6378 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6379 match(Set dst mem);
6380
6381 ins_cost(110);
6382 format %{ "LEA $dst,$mem" %}
6383 opcode(0x8D);
6384 ins_encode( OpcP, RegMem(dst,mem));
6385 ins_pipe( ialu_reg_reg_fat );
6386 %}
6387
6388 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6389 match(Set dst mem);
6390
6391 ins_cost(110);
6392 format %{ "LEA $dst,$mem" %}
6393 opcode(0x8D);
6394 ins_encode( OpcP, RegMem(dst,mem));
6395 ins_pipe( ialu_reg_reg_fat );
6396 %}
6397
6398 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6399 match(Set dst mem);
6400
6401 ins_cost(110);
6402 format %{ "LEA $dst,$mem" %}
6403 opcode(0x8D);
6404 ins_encode( OpcP, RegMem(dst,mem));
6405 ins_pipe( ialu_reg_reg_fat );
6406 %}
6407
6408 // Load Constant
6409 instruct loadConI(rRegI dst, immI src) %{
6410 match(Set dst src);
6411
6412 format %{ "MOV $dst,$src" %}
6413 ins_encode( LdImmI(dst, src) );
6414 ins_pipe( ialu_reg_fat );
6415 %}
6416
6417 // Load Constant zero
6418 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6419 match(Set dst src);
6420 effect(KILL cr);
6421
6422 ins_cost(50);
6423 format %{ "XOR $dst,$dst" %}
6424 opcode(0x33); /* + rd */
6425 ins_encode( OpcP, RegReg( dst, dst ) );
6426 ins_pipe( ialu_reg );
6427 %}
6428
6429 instruct loadConP(eRegP dst, immP src) %{
6430 match(Set dst src);
6431
6432 format %{ "MOV $dst,$src" %}
6433 opcode(0xB8); /* + rd */
6434 ins_encode( LdImmP(dst, src) );
6435 ins_pipe( ialu_reg_fat );
6436 %}
6437
6438 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6439 match(Set dst src);
6440 effect(KILL cr);
6441 ins_cost(200);
6442 format %{ "MOV $dst.lo,$src.lo\n\t"
6443 "MOV $dst.hi,$src.hi" %}
6444 opcode(0xB8);
6445 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6446 ins_pipe( ialu_reg_long_fat );
6447 %}
6448
6449 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6450 match(Set dst src);
6451 effect(KILL cr);
6452 ins_cost(150);
6453 format %{ "XOR $dst.lo,$dst.lo\n\t"
6454 "XOR $dst.hi,$dst.hi" %}
6455 opcode(0x33,0x33);
6456 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6457 ins_pipe( ialu_reg_long );
6458 %}
6459
6460 // The instruction usage is guarded by predicate in operand immFPR().
6461 instruct loadConFPR(regFPR dst, immFPR con) %{
6462 match(Set dst con);
6463 ins_cost(125);
6464 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6465 "FSTP $dst" %}
6466 ins_encode %{
6467 __ fld_s($constantaddress($con));
6468 __ fstp_d($dst$$reg);
6469 %}
6470 ins_pipe(fpu_reg_con);
6471 %}
6472
6473 // The instruction usage is guarded by predicate in operand immFPR0().
6474 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6475 match(Set dst con);
6476 ins_cost(125);
6477 format %{ "FLDZ ST\n\t"
6478 "FSTP $dst" %}
6479 ins_encode %{
6480 __ fldz();
6481 __ fstp_d($dst$$reg);
6482 %}
6483 ins_pipe(fpu_reg_con);
6484 %}
6485
6486 // The instruction usage is guarded by predicate in operand immFPR1().
6487 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6488 match(Set dst con);
6489 ins_cost(125);
6490 format %{ "FLD1 ST\n\t"
6491 "FSTP $dst" %}
6492 ins_encode %{
6493 __ fld1();
6494 __ fstp_d($dst$$reg);
6495 %}
6496 ins_pipe(fpu_reg_con);
6497 %}
6498
6499 // The instruction usage is guarded by predicate in operand immF().
6500 instruct loadConF(regF dst, immF con) %{
6501 match(Set dst con);
6502 ins_cost(125);
6503 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6504 ins_encode %{
6505 __ movflt($dst$$XMMRegister, $constantaddress($con));
6506 %}
6507 ins_pipe(pipe_slow);
6508 %}
6509
6510 // The instruction usage is guarded by predicate in operand immF0().
6511 instruct loadConF0(regF dst, immF0 src) %{
6512 match(Set dst src);
6513 ins_cost(100);
6514 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6515 ins_encode %{
6516 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6517 %}
6518 ins_pipe(pipe_slow);
6519 %}
6520
6521 // The instruction usage is guarded by predicate in operand immDPR().
6522 instruct loadConDPR(regDPR dst, immDPR con) %{
6523 match(Set dst con);
6524 ins_cost(125);
6525
6526 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6527 "FSTP $dst" %}
6528 ins_encode %{
6529 __ fld_d($constantaddress($con));
6530 __ fstp_d($dst$$reg);
6531 %}
6532 ins_pipe(fpu_reg_con);
6533 %}
6534
6535 // The instruction usage is guarded by predicate in operand immDPR0().
6536 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6537 match(Set dst con);
6538 ins_cost(125);
6539
6540 format %{ "FLDZ ST\n\t"
6541 "FSTP $dst" %}
6542 ins_encode %{
6543 __ fldz();
6544 __ fstp_d($dst$$reg);
6545 %}
6546 ins_pipe(fpu_reg_con);
6547 %}
6548
6549 // The instruction usage is guarded by predicate in operand immDPR1().
6550 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6551 match(Set dst con);
6552 ins_cost(125);
6553
6554 format %{ "FLD1 ST\n\t"
6555 "FSTP $dst" %}
6556 ins_encode %{
6557 __ fld1();
6558 __ fstp_d($dst$$reg);
6559 %}
6560 ins_pipe(fpu_reg_con);
6561 %}
6562
6563 // The instruction usage is guarded by predicate in operand immD().
6564 instruct loadConD(regD dst, immD con) %{
6565 match(Set dst con);
6566 ins_cost(125);
6567 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6568 ins_encode %{
6569 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6570 %}
6571 ins_pipe(pipe_slow);
6572 %}
6573
6574 // The instruction usage is guarded by predicate in operand immD0().
6575 instruct loadConD0(regD dst, immD0 src) %{
6576 match(Set dst src);
6577 ins_cost(100);
6578 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6579 ins_encode %{
6580 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6581 %}
6582 ins_pipe( pipe_slow );
6583 %}
6584
6585 // Load Stack Slot
6586 instruct loadSSI(rRegI dst, stackSlotI src) %{
6587 match(Set dst src);
6588 ins_cost(125);
6589
6590 format %{ "MOV $dst,$src" %}
6591 opcode(0x8B);
6592 ins_encode( OpcP, RegMem(dst,src));
6593 ins_pipe( ialu_reg_mem );
6594 %}
6595
6596 instruct loadSSL(eRegL dst, stackSlotL src) %{
6597 match(Set dst src);
6598
6599 ins_cost(200);
6600 format %{ "MOV $dst,$src.lo\n\t"
6601 "MOV $dst+4,$src.hi" %}
6602 opcode(0x8B, 0x8B);
6603 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6604 ins_pipe( ialu_mem_long_reg );
6605 %}
6606
6607 // Load Stack Slot
6608 instruct loadSSP(eRegP dst, stackSlotP src) %{
6609 match(Set dst src);
6610 ins_cost(125);
6611
6612 format %{ "MOV $dst,$src" %}
6613 opcode(0x8B);
6614 ins_encode( OpcP, RegMem(dst,src));
6615 ins_pipe( ialu_reg_mem );
6616 %}
6617
6618 // Load Stack Slot
6619 instruct loadSSF(regFPR dst, stackSlotF src) %{
6620 match(Set dst src);
6621 ins_cost(125);
6622
6623 format %{ "FLD_S $src\n\t"
6624 "FSTP $dst" %}
6625 opcode(0xD9); /* D9 /0, FLD m32real */
6626 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6627 Pop_Reg_FPR(dst) );
6628 ins_pipe( fpu_reg_mem );
6629 %}
6630
6631 // Load Stack Slot
6632 instruct loadSSD(regDPR dst, stackSlotD src) %{
6633 match(Set dst src);
6634 ins_cost(125);
6635
6636 format %{ "FLD_D $src\n\t"
6637 "FSTP $dst" %}
6638 opcode(0xDD); /* DD /0, FLD m64real */
6639 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6640 Pop_Reg_DPR(dst) );
6641 ins_pipe( fpu_reg_mem );
6642 %}
6643
6644 // Prefetch instructions.
6645 // Must be safe to execute with invalid address (cannot fault).
6646
6647 instruct prefetchr0( memory mem ) %{
6648 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6649 match(PrefetchRead mem);
6650 ins_cost(0);
6651 size(0);
6652 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6653 ins_encode();
6654 ins_pipe(empty);
6655 %}
6656
6657 instruct prefetchr( memory mem ) %{
6658 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6659 match(PrefetchRead mem);
6660 ins_cost(100);
6661
6662 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6663 ins_encode %{
6664 __ prefetchr($mem$$Address);
6665 %}
6666 ins_pipe(ialu_mem);
6667 %}
6668
6669 instruct prefetchrNTA( memory mem ) %{
6670 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6671 match(PrefetchRead mem);
6672 ins_cost(100);
6673
6674 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6675 ins_encode %{
6676 __ prefetchnta($mem$$Address);
6677 %}
6678 ins_pipe(ialu_mem);
6679 %}
6680
6681 instruct prefetchrT0( memory mem ) %{
6682 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6683 match(PrefetchRead mem);
6684 ins_cost(100);
6685
6686 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6687 ins_encode %{
6688 __ prefetcht0($mem$$Address);
6689 %}
6690 ins_pipe(ialu_mem);
6691 %}
6692
6693 instruct prefetchrT2( memory mem ) %{
6694 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6695 match(PrefetchRead mem);
6696 ins_cost(100);
6697
6698 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6699 ins_encode %{
6700 __ prefetcht2($mem$$Address);
6701 %}
6702 ins_pipe(ialu_mem);
6703 %}
6704
6705 instruct prefetchw0( memory mem ) %{
6706 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6707 match(PrefetchWrite mem);
6708 ins_cost(0);
6709 size(0);
6710 format %{ "Prefetch (non-SSE is empty encoding)" %}
6711 ins_encode();
6712 ins_pipe(empty);
6713 %}
6714
6715 instruct prefetchw( memory mem ) %{
6716 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6717 match( PrefetchWrite mem );
6718 ins_cost(100);
6719
6720 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6721 ins_encode %{
6722 __ prefetchw($mem$$Address);
6723 %}
6724 ins_pipe(ialu_mem);
6725 %}
6726
6727 instruct prefetchwNTA( memory mem ) %{
6728 predicate(UseSSE>=1);
6729 match(PrefetchWrite mem);
6730 ins_cost(100);
6731
6732 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6733 ins_encode %{
6734 __ prefetchnta($mem$$Address);
6735 %}
6736 ins_pipe(ialu_mem);
6737 %}
6738
6739 // Prefetch instructions for allocation.
6740
6741 instruct prefetchAlloc0( memory mem ) %{
6742 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6743 match(PrefetchAllocation mem);
6744 ins_cost(0);
6745 size(0);
6746 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6747 ins_encode();
6748 ins_pipe(empty);
6749 %}
6750
6751 instruct prefetchAlloc( memory mem ) %{
6752 predicate(AllocatePrefetchInstr==3);
6753 match( PrefetchAllocation mem );
6754 ins_cost(100);
6755
6756 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6757 ins_encode %{
6758 __ prefetchw($mem$$Address);
6759 %}
6760 ins_pipe(ialu_mem);
6761 %}
6762
6763 instruct prefetchAllocNTA( memory mem ) %{
6764 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6765 match(PrefetchAllocation mem);
6766 ins_cost(100);
6767
6768 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6769 ins_encode %{
6770 __ prefetchnta($mem$$Address);
6771 %}
6772 ins_pipe(ialu_mem);
6773 %}
6774
6775 instruct prefetchAllocT0( memory mem ) %{
6776 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6777 match(PrefetchAllocation mem);
6778 ins_cost(100);
6779
6780 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6781 ins_encode %{
6782 __ prefetcht0($mem$$Address);
6783 %}
6784 ins_pipe(ialu_mem);
6785 %}
6786
6787 instruct prefetchAllocT2( memory mem ) %{
6788 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6789 match(PrefetchAllocation mem);
6790 ins_cost(100);
6791
6792 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6793 ins_encode %{
6794 __ prefetcht2($mem$$Address);
6795 %}
6796 ins_pipe(ialu_mem);
6797 %}
6798
6799 //----------Store Instructions-------------------------------------------------
6800
6801 // Store Byte
6802 instruct storeB(memory mem, xRegI src) %{
6803 match(Set mem (StoreB mem src));
6804
6805 ins_cost(125);
6806 format %{ "MOV8 $mem,$src" %}
6807 opcode(0x88);
6808 ins_encode( OpcP, RegMem( src, mem ) );
6809 ins_pipe( ialu_mem_reg );
6810 %}
6811
6812 // Store Char/Short
6813 instruct storeC(memory mem, rRegI src) %{
6814 match(Set mem (StoreC mem src));
6815
6816 ins_cost(125);
6817 format %{ "MOV16 $mem,$src" %}
6818 opcode(0x89, 0x66);
6819 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6820 ins_pipe( ialu_mem_reg );
6821 %}
6822
6823 // Store Integer
6824 instruct storeI(memory mem, rRegI src) %{
6825 match(Set mem (StoreI mem src));
6826
6827 ins_cost(125);
6828 format %{ "MOV $mem,$src" %}
6829 opcode(0x89);
6830 ins_encode( OpcP, RegMem( src, mem ) );
6831 ins_pipe( ialu_mem_reg );
6832 %}
6833
6834 // Store Long
6835 instruct storeL(long_memory mem, eRegL src) %{
6836 predicate(!((StoreLNode*)n)->require_atomic_access());
6837 match(Set mem (StoreL mem src));
6838
6839 ins_cost(200);
6840 format %{ "MOV $mem,$src.lo\n\t"
6841 "MOV $mem+4,$src.hi" %}
6842 opcode(0x89, 0x89);
6843 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6844 ins_pipe( ialu_mem_long_reg );
6845 %}
6846
6847 // Store Long to Integer
6848 instruct storeL2I(memory mem, eRegL src) %{
6849 match(Set mem (StoreI mem (ConvL2I src)));
6850
6851 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6852 ins_encode %{
6853 __ movl($mem$$Address, $src$$Register);
6854 %}
6855 ins_pipe(ialu_mem_reg);
6856 %}
6857
6858 // Volatile Store Long. Must be atomic, so move it into
6859 // the FP TOS and then do a 64-bit FIST. Has to probe the
6860 // target address before the store (for null-ptr checks)
6861 // so the memory operand is used twice in the encoding.
6862 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6863 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6864 match(Set mem (StoreL mem src));
6865 effect( KILL cr );
6866 ins_cost(400);
6867 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6868 "FILD $src\n\t"
6869 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6870 opcode(0x3B);
6871 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6872 ins_pipe( fpu_reg_mem );
6873 %}
6874
6875 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6876 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6877 match(Set mem (StoreL mem src));
6878 effect( TEMP tmp, KILL cr );
6879 ins_cost(380);
6880 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6881 "MOVSD $tmp,$src\n\t"
6882 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6883 ins_encode %{
6884 __ cmpl(rax, $mem$$Address);
6885 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6886 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6887 %}
6888 ins_pipe( pipe_slow );
6889 %}
6890
6891 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6892 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6893 match(Set mem (StoreL mem src));
6894 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6895 ins_cost(360);
6896 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6897 "MOVD $tmp,$src.lo\n\t"
6898 "MOVD $tmp2,$src.hi\n\t"
6899 "PUNPCKLDQ $tmp,$tmp2\n\t"
6900 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6901 ins_encode %{
6902 __ cmpl(rax, $mem$$Address);
6903 __ movdl($tmp$$XMMRegister, $src$$Register);
6904 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6905 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6906 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6907 %}
6908 ins_pipe( pipe_slow );
6909 %}
6910
6911 // Store Pointer; for storing unknown oops and raw pointers
6912 instruct storeP(memory mem, anyRegP src) %{
6913 match(Set mem (StoreP mem src));
6914
6915 ins_cost(125);
6916 format %{ "MOV $mem,$src" %}
6917 opcode(0x89);
6918 ins_encode( OpcP, RegMem( src, mem ) );
6919 ins_pipe( ialu_mem_reg );
6920 %}
6921
6922 // Store Integer Immediate
6923 instruct storeImmI(memory mem, immI src) %{
6924 match(Set mem (StoreI mem src));
6925
6926 ins_cost(150);
6927 format %{ "MOV $mem,$src" %}
6928 opcode(0xC7); /* C7 /0 */
6929 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6930 ins_pipe( ialu_mem_imm );
6931 %}
6932
6933 // Store Short/Char Immediate
6934 instruct storeImmI16(memory mem, immI16 src) %{
6935 predicate(UseStoreImmI16);
6936 match(Set mem (StoreC mem src));
6937
6938 ins_cost(150);
6939 format %{ "MOV16 $mem,$src" %}
6940 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6941 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6942 ins_pipe( ialu_mem_imm );
6943 %}
6944
6945 // Store Pointer Immediate; null pointers or constant oops that do not
6946 // need card-mark barriers.
6947 instruct storeImmP(memory mem, immP src) %{
6948 match(Set mem (StoreP mem src));
6949
6950 ins_cost(150);
6951 format %{ "MOV $mem,$src" %}
6952 opcode(0xC7); /* C7 /0 */
6953 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6954 ins_pipe( ialu_mem_imm );
6955 %}
6956
6957 // Store Byte Immediate
6958 instruct storeImmB(memory mem, immI8 src) %{
6959 match(Set mem (StoreB mem src));
6960
6961 ins_cost(150);
6962 format %{ "MOV8 $mem,$src" %}
6963 opcode(0xC6); /* C6 /0 */
6964 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6965 ins_pipe( ialu_mem_imm );
6966 %}
6967
6968 // Store CMS card-mark Immediate
6969 instruct storeImmCM(memory mem, immI8 src) %{
6970 match(Set mem (StoreCM mem src));
6971
6972 ins_cost(150);
6973 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6974 opcode(0xC6); /* C6 /0 */
6975 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6976 ins_pipe( ialu_mem_imm );
6977 %}
6978
6979 // Store Double
6980 instruct storeDPR( memory mem, regDPR1 src) %{
6981 predicate(UseSSE<=1);
6982 match(Set mem (StoreD mem src));
6983
6984 ins_cost(100);
6985 format %{ "FST_D $mem,$src" %}
6986 opcode(0xDD); /* DD /2 */
6987 ins_encode( enc_FPR_store(mem,src) );
6988 ins_pipe( fpu_mem_reg );
6989 %}
6990
6991 // Store double does rounding on x86
6992 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6993 predicate(UseSSE<=1);
6994 match(Set mem (StoreD mem (RoundDouble src)));
6995
6996 ins_cost(100);
6997 format %{ "FST_D $mem,$src\t# round" %}
6998 opcode(0xDD); /* DD /2 */
6999 ins_encode( enc_FPR_store(mem,src) );
7000 ins_pipe( fpu_mem_reg );
7001 %}
7002
7003 // Store XMM register to memory (double-precision floating points)
7004 // MOVSD instruction
7005 instruct storeD(memory mem, regD src) %{
7006 predicate(UseSSE>=2);
7007 match(Set mem (StoreD mem src));
7008 ins_cost(95);
7009 format %{ "MOVSD $mem,$src" %}
7010 ins_encode %{
7011 __ movdbl($mem$$Address, $src$$XMMRegister);
7012 %}
7013 ins_pipe( pipe_slow );
7014 %}
7015
7016 // Store XMM register to memory (single-precision floating point)
7017 // MOVSS instruction
7018 instruct storeF(memory mem, regF src) %{
7019 predicate(UseSSE>=1);
7020 match(Set mem (StoreF mem src));
7021 ins_cost(95);
7022 format %{ "MOVSS $mem,$src" %}
7023 ins_encode %{
7024 __ movflt($mem$$Address, $src$$XMMRegister);
7025 %}
7026 ins_pipe( pipe_slow );
7027 %}
7028
7029 // Store Float
7030 instruct storeFPR( memory mem, regFPR1 src) %{
7031 predicate(UseSSE==0);
7032 match(Set mem (StoreF mem src));
7033
7034 ins_cost(100);
7035 format %{ "FST_S $mem,$src" %}
7036 opcode(0xD9); /* D9 /2 */
7037 ins_encode( enc_FPR_store(mem,src) );
7038 ins_pipe( fpu_mem_reg );
7039 %}
7040
7041 // Store Float does rounding on x86
7042 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7043 predicate(UseSSE==0);
7044 match(Set mem (StoreF mem (RoundFloat src)));
7045
7046 ins_cost(100);
7047 format %{ "FST_S $mem,$src\t# round" %}
7048 opcode(0xD9); /* D9 /2 */
7049 ins_encode( enc_FPR_store(mem,src) );
7050 ins_pipe( fpu_mem_reg );
7051 %}
7052
7053 // Store Float does rounding on x86
7054 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7055 predicate(UseSSE<=1);
7056 match(Set mem (StoreF mem (ConvD2F src)));
7057
7058 ins_cost(100);
7059 format %{ "FST_S $mem,$src\t# D-round" %}
7060 opcode(0xD9); /* D9 /2 */
7061 ins_encode( enc_FPR_store(mem,src) );
7062 ins_pipe( fpu_mem_reg );
7063 %}
7064
7065 // Store immediate Float value (it is faster than store from FPU register)
7066 // The instruction usage is guarded by predicate in operand immFPR().
7067 instruct storeFPR_imm( memory mem, immFPR src) %{
7068 match(Set mem (StoreF mem src));
7069
7070 ins_cost(50);
7071 format %{ "MOV $mem,$src\t# store float" %}
7072 opcode(0xC7); /* C7 /0 */
7073 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7074 ins_pipe( ialu_mem_imm );
7075 %}
7076
7077 // Store immediate Float value (it is faster than store from XMM register)
7078 // The instruction usage is guarded by predicate in operand immF().
7079 instruct storeF_imm( memory mem, immF src) %{
7080 match(Set mem (StoreF mem src));
7081
7082 ins_cost(50);
7083 format %{ "MOV $mem,$src\t# store float" %}
7084 opcode(0xC7); /* C7 /0 */
7085 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7086 ins_pipe( ialu_mem_imm );
7087 %}
7088
7089 // Store Integer to stack slot
7090 instruct storeSSI(stackSlotI dst, rRegI src) %{
7091 match(Set dst src);
7092
7093 ins_cost(100);
7094 format %{ "MOV $dst,$src" %}
7095 opcode(0x89);
7096 ins_encode( OpcPRegSS( dst, src ) );
7097 ins_pipe( ialu_mem_reg );
7098 %}
7099
7100 // Store Integer to stack slot
7101 instruct storeSSP(stackSlotP dst, eRegP src) %{
7102 match(Set dst src);
7103
7104 ins_cost(100);
7105 format %{ "MOV $dst,$src" %}
7106 opcode(0x89);
7107 ins_encode( OpcPRegSS( dst, src ) );
7108 ins_pipe( ialu_mem_reg );
7109 %}
7110
7111 // Store Long to stack slot
7112 instruct storeSSL(stackSlotL dst, eRegL src) %{
7113 match(Set dst src);
7114
7115 ins_cost(200);
7116 format %{ "MOV $dst,$src.lo\n\t"
7117 "MOV $dst+4,$src.hi" %}
7118 opcode(0x89, 0x89);
7119 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7120 ins_pipe( ialu_mem_long_reg );
7121 %}
7122
7123 //----------MemBar Instructions-----------------------------------------------
7124 // Memory barrier flavors
7125
7126 instruct membar_acquire() %{
7127 match(MemBarAcquire);
7128 ins_cost(400);
7129
7130 size(0);
7131 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7132 ins_encode();
7133 ins_pipe(empty);
7134 %}
7135
7136 instruct membar_acquire_lock() %{
7137 match(MemBarAcquireLock);
7138 ins_cost(0);
7139
7140 size(0);
7141 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7142 ins_encode( );
7143 ins_pipe(empty);
7144 %}
7145
7146 instruct membar_release() %{
7147 match(MemBarRelease);
7148 ins_cost(400);
7149
7150 size(0);
7151 format %{ "MEMBAR-release ! (empty encoding)" %}
7152 ins_encode( );
7153 ins_pipe(empty);
7154 %}
7155
7156 instruct membar_release_lock() %{
7157 match(MemBarReleaseLock);
7158 ins_cost(0);
7159
7160 size(0);
7161 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7162 ins_encode( );
7163 ins_pipe(empty);
7164 %}
7165
7166 instruct membar_volatile(eFlagsReg cr) %{
7167 match(MemBarVolatile);
7168 effect(KILL cr);
7169 ins_cost(400);
7170
7171 format %{
7172 $$template
7173 if (os::is_MP()) {
7174 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7175 } else {
7176 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7177 }
7178 %}
7179 ins_encode %{
7180 __ membar(Assembler::StoreLoad);
7181 %}
7182 ins_pipe(pipe_slow);
7183 %}
7184
7185 instruct unnecessary_membar_volatile() %{
7186 match(MemBarVolatile);
7187 predicate(Matcher::post_store_load_barrier(n));
7188 ins_cost(0);
7189
7190 size(0);
7191 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7192 ins_encode( );
7193 ins_pipe(empty);
7194 %}
7195
7196 instruct membar_storestore() %{
7197 match(MemBarStoreStore);
7198 ins_cost(0);
7199
7200 size(0);
7201 format %{ "MEMBAR-storestore (empty encoding)" %}
7202 ins_encode( );
7203 ins_pipe(empty);
7204 %}
7205
7206 //----------Move Instructions--------------------------------------------------
7207 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7208 match(Set dst (CastX2P src));
7209 format %{ "# X2P $dst, $src" %}
7210 ins_encode( /*empty encoding*/ );
7211 ins_cost(0);
7212 ins_pipe(empty);
7213 %}
7214
7215 instruct castP2X(rRegI dst, eRegP src ) %{
7216 match(Set dst (CastP2X src));
7217 ins_cost(50);
7218 format %{ "MOV $dst, $src\t# CastP2X" %}
7219 ins_encode( enc_Copy( dst, src) );
7220 ins_pipe( ialu_reg_reg );
7221 %}
7222
7223 //----------Conditional Move---------------------------------------------------
7224 // Conditional move
7225 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7226 predicate(!VM_Version::supports_cmov() );
7227 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7228 ins_cost(200);
7229 format %{ "J$cop,us skip\t# signed cmove\n\t"
7230 "MOV $dst,$src\n"
7231 "skip:" %}
7232 ins_encode %{
7233 Label Lskip;
7234 // Invert sense of branch from sense of CMOV
7235 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7236 __ movl($dst$$Register, $src$$Register);
7237 __ bind(Lskip);
7238 %}
7239 ins_pipe( pipe_cmov_reg );
7240 %}
7241
7242 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7243 predicate(!VM_Version::supports_cmov() );
7244 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7245 ins_cost(200);
7246 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7247 "MOV $dst,$src\n"
7248 "skip:" %}
7249 ins_encode %{
7250 Label Lskip;
7251 // Invert sense of branch from sense of CMOV
7252 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7253 __ movl($dst$$Register, $src$$Register);
7254 __ bind(Lskip);
7255 %}
7256 ins_pipe( pipe_cmov_reg );
7257 %}
7258
7259 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7260 predicate(VM_Version::supports_cmov() );
7261 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7262 ins_cost(200);
7263 format %{ "CMOV$cop $dst,$src" %}
7264 opcode(0x0F,0x40);
7265 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7266 ins_pipe( pipe_cmov_reg );
7267 %}
7268
7269 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7270 predicate(VM_Version::supports_cmov() );
7271 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7272 ins_cost(200);
7273 format %{ "CMOV$cop $dst,$src" %}
7274 opcode(0x0F,0x40);
7275 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7276 ins_pipe( pipe_cmov_reg );
7277 %}
7278
7279 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7280 predicate(VM_Version::supports_cmov() );
7281 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7282 ins_cost(200);
7283 expand %{
7284 cmovI_regU(cop, cr, dst, src);
7285 %}
7286 %}
7287
7288 // Conditional move
7289 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7290 predicate(VM_Version::supports_cmov() );
7291 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7292 ins_cost(250);
7293 format %{ "CMOV$cop $dst,$src" %}
7294 opcode(0x0F,0x40);
7295 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7296 ins_pipe( pipe_cmov_mem );
7297 %}
7298
7299 // Conditional move
7300 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7301 predicate(VM_Version::supports_cmov() );
7302 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7303 ins_cost(250);
7304 format %{ "CMOV$cop $dst,$src" %}
7305 opcode(0x0F,0x40);
7306 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7307 ins_pipe( pipe_cmov_mem );
7308 %}
7309
7310 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7311 predicate(VM_Version::supports_cmov() );
7312 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7313 ins_cost(250);
7314 expand %{
7315 cmovI_memU(cop, cr, dst, src);
7316 %}
7317 %}
7318
7319 // Conditional move
7320 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7321 predicate(VM_Version::supports_cmov() );
7322 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7323 ins_cost(200);
7324 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7325 opcode(0x0F,0x40);
7326 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7327 ins_pipe( pipe_cmov_reg );
7328 %}
7329
7330 // Conditional move (non-P6 version)
7331 // Note: a CMoveP is generated for stubs and native wrappers
7332 // regardless of whether we are on a P6, so we
7333 // emulate a cmov here
7334 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7335 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7336 ins_cost(300);
7337 format %{ "Jn$cop skip\n\t"
7338 "MOV $dst,$src\t# pointer\n"
7339 "skip:" %}
7340 opcode(0x8b);
7341 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7342 ins_pipe( pipe_cmov_reg );
7343 %}
7344
7345 // Conditional move
7346 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7347 predicate(VM_Version::supports_cmov() );
7348 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7349 ins_cost(200);
7350 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7351 opcode(0x0F,0x40);
7352 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7353 ins_pipe( pipe_cmov_reg );
7354 %}
7355
7356 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7357 predicate(VM_Version::supports_cmov() );
7358 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7359 ins_cost(200);
7360 expand %{
7361 cmovP_regU(cop, cr, dst, src);
7362 %}
7363 %}
7364
7365 // DISABLED: Requires the ADLC to emit a bottom_type call that
7366 // correctly meets the two pointer arguments; one is an incoming
7367 // register but the other is a memory operand. ALSO appears to
7368 // be buggy with implicit null checks.
7369 //
7370 //// Conditional move
7371 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7372 // predicate(VM_Version::supports_cmov() );
7373 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7374 // ins_cost(250);
7375 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7376 // opcode(0x0F,0x40);
7377 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7378 // ins_pipe( pipe_cmov_mem );
7379 //%}
7380 //
7381 //// Conditional move
7382 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7383 // predicate(VM_Version::supports_cmov() );
7384 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7385 // ins_cost(250);
7386 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7387 // opcode(0x0F,0x40);
7388 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7389 // ins_pipe( pipe_cmov_mem );
7390 //%}
7391
7392 // Conditional move
7393 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7394 predicate(UseSSE<=1);
7395 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7396 ins_cost(200);
7397 format %{ "FCMOV$cop $dst,$src\t# double" %}
7398 opcode(0xDA);
7399 ins_encode( enc_cmov_dpr(cop,src) );
7400 ins_pipe( pipe_cmovDPR_reg );
7401 %}
7402
7403 // Conditional move
7404 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7405 predicate(UseSSE==0);
7406 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7407 ins_cost(200);
7408 format %{ "FCMOV$cop $dst,$src\t# float" %}
7409 opcode(0xDA);
7410 ins_encode( enc_cmov_dpr(cop,src) );
7411 ins_pipe( pipe_cmovDPR_reg );
7412 %}
7413
7414 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7415 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7416 predicate(UseSSE<=1);
7417 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7418 ins_cost(200);
7419 format %{ "Jn$cop skip\n\t"
7420 "MOV $dst,$src\t# double\n"
7421 "skip:" %}
7422 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7423 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7424 ins_pipe( pipe_cmovDPR_reg );
7425 %}
7426
7427 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7428 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7429 predicate(UseSSE==0);
7430 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7431 ins_cost(200);
7432 format %{ "Jn$cop skip\n\t"
7433 "MOV $dst,$src\t# float\n"
7434 "skip:" %}
7435 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7436 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7437 ins_pipe( pipe_cmovDPR_reg );
7438 %}
7439
7440 // No CMOVE with SSE/SSE2
7441 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7442 predicate (UseSSE>=1);
7443 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7444 ins_cost(200);
7445 format %{ "Jn$cop skip\n\t"
7446 "MOVSS $dst,$src\t# float\n"
7447 "skip:" %}
7448 ins_encode %{
7449 Label skip;
7450 // Invert sense of branch from sense of CMOV
7451 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7452 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7453 __ bind(skip);
7454 %}
7455 ins_pipe( pipe_slow );
7456 %}
7457
7458 // No CMOVE with SSE/SSE2
7459 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7460 predicate (UseSSE>=2);
7461 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7462 ins_cost(200);
7463 format %{ "Jn$cop skip\n\t"
7464 "MOVSD $dst,$src\t# float\n"
7465 "skip:" %}
7466 ins_encode %{
7467 Label skip;
7468 // Invert sense of branch from sense of CMOV
7469 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7470 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7471 __ bind(skip);
7472 %}
7473 ins_pipe( pipe_slow );
7474 %}
7475
7476 // unsigned version
7477 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7478 predicate (UseSSE>=1);
7479 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7480 ins_cost(200);
7481 format %{ "Jn$cop skip\n\t"
7482 "MOVSS $dst,$src\t# float\n"
7483 "skip:" %}
7484 ins_encode %{
7485 Label skip;
7486 // Invert sense of branch from sense of CMOV
7487 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7488 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7489 __ bind(skip);
7490 %}
7491 ins_pipe( pipe_slow );
7492 %}
7493
7494 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7495 predicate (UseSSE>=1);
7496 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7497 ins_cost(200);
7498 expand %{
7499 fcmovF_regU(cop, cr, dst, src);
7500 %}
7501 %}
7502
7503 // unsigned version
7504 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7505 predicate (UseSSE>=2);
7506 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7507 ins_cost(200);
7508 format %{ "Jn$cop skip\n\t"
7509 "MOVSD $dst,$src\t# float\n"
7510 "skip:" %}
7511 ins_encode %{
7512 Label skip;
7513 // Invert sense of branch from sense of CMOV
7514 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7515 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7516 __ bind(skip);
7517 %}
7518 ins_pipe( pipe_slow );
7519 %}
7520
7521 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7522 predicate (UseSSE>=2);
7523 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7524 ins_cost(200);
7525 expand %{
7526 fcmovD_regU(cop, cr, dst, src);
7527 %}
7528 %}
7529
7530 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7531 predicate(VM_Version::supports_cmov() );
7532 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7533 ins_cost(200);
7534 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7535 "CMOV$cop $dst.hi,$src.hi" %}
7536 opcode(0x0F,0x40);
7537 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7538 ins_pipe( pipe_cmov_reg_long );
7539 %}
7540
7541 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7542 predicate(VM_Version::supports_cmov() );
7543 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7544 ins_cost(200);
7545 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7546 "CMOV$cop $dst.hi,$src.hi" %}
7547 opcode(0x0F,0x40);
7548 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7549 ins_pipe( pipe_cmov_reg_long );
7550 %}
7551
7552 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7553 predicate(VM_Version::supports_cmov() );
7554 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7555 ins_cost(200);
7556 expand %{
7557 cmovL_regU(cop, cr, dst, src);
7558 %}
7559 %}
7560
7561 //----------Arithmetic Instructions--------------------------------------------
7562 //----------Addition Instructions----------------------------------------------
7563 // Integer Addition Instructions
7564 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7565 match(Set dst (AddI dst src));
7566 effect(KILL cr);
7567
7568 size(2);
7569 format %{ "ADD $dst,$src" %}
7570 opcode(0x03);
7571 ins_encode( OpcP, RegReg( dst, src) );
7572 ins_pipe( ialu_reg_reg );
7573 %}
7574
7575 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7576 match(Set dst (AddI dst src));
7577 effect(KILL cr);
7578
7579 format %{ "ADD $dst,$src" %}
7580 opcode(0x81, 0x00); /* /0 id */
7581 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7582 ins_pipe( ialu_reg );
7583 %}
7584
7585 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7586 predicate(UseIncDec);
7587 match(Set dst (AddI dst src));
7588 effect(KILL cr);
7589
7590 size(1);
7591 format %{ "INC $dst" %}
7592 opcode(0x40); /* */
7593 ins_encode( Opc_plus( primary, dst ) );
7594 ins_pipe( ialu_reg );
7595 %}
7596
7597 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7598 match(Set dst (AddI src0 src1));
7599 ins_cost(110);
7600
7601 format %{ "LEA $dst,[$src0 + $src1]" %}
7602 opcode(0x8D); /* 0x8D /r */
7603 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7604 ins_pipe( ialu_reg_reg );
7605 %}
7606
7607 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7608 match(Set dst (AddP src0 src1));
7609 ins_cost(110);
7610
7611 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7612 opcode(0x8D); /* 0x8D /r */
7613 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7614 ins_pipe( ialu_reg_reg );
7615 %}
7616
7617 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7618 predicate(UseIncDec);
7619 match(Set dst (AddI dst src));
7620 effect(KILL cr);
7621
7622 size(1);
7623 format %{ "DEC $dst" %}
7624 opcode(0x48); /* */
7625 ins_encode( Opc_plus( primary, dst ) );
7626 ins_pipe( ialu_reg );
7627 %}
7628
7629 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7630 match(Set dst (AddP dst src));
7631 effect(KILL cr);
7632
7633 size(2);
7634 format %{ "ADD $dst,$src" %}
7635 opcode(0x03);
7636 ins_encode( OpcP, RegReg( dst, src) );
7637 ins_pipe( ialu_reg_reg );
7638 %}
7639
7640 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7641 match(Set dst (AddP dst src));
7642 effect(KILL cr);
7643
7644 format %{ "ADD $dst,$src" %}
7645 opcode(0x81,0x00); /* Opcode 81 /0 id */
7646 // ins_encode( RegImm( dst, src) );
7647 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7648 ins_pipe( ialu_reg );
7649 %}
7650
7651 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7652 match(Set dst (AddI dst (LoadI src)));
7653 effect(KILL cr);
7654
7655 ins_cost(125);
7656 format %{ "ADD $dst,$src" %}
7657 opcode(0x03);
7658 ins_encode( OpcP, RegMem( dst, src) );
7659 ins_pipe( ialu_reg_mem );
7660 %}
7661
7662 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7663 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7664 effect(KILL cr);
7665
7666 ins_cost(150);
7667 format %{ "ADD $dst,$src" %}
7668 opcode(0x01); /* Opcode 01 /r */
7669 ins_encode( OpcP, RegMem( src, dst ) );
7670 ins_pipe( ialu_mem_reg );
7671 %}
7672
7673 // Add Memory with Immediate
7674 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7675 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7676 effect(KILL cr);
7677
7678 ins_cost(125);
7679 format %{ "ADD $dst,$src" %}
7680 opcode(0x81); /* Opcode 81 /0 id */
7681 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7682 ins_pipe( ialu_mem_imm );
7683 %}
7684
7685 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7686 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7687 effect(KILL cr);
7688
7689 ins_cost(125);
7690 format %{ "INC $dst" %}
7691 opcode(0xFF); /* Opcode FF /0 */
7692 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7693 ins_pipe( ialu_mem_imm );
7694 %}
7695
7696 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7697 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7698 effect(KILL cr);
7699
7700 ins_cost(125);
7701 format %{ "DEC $dst" %}
7702 opcode(0xFF); /* Opcode FF /1 */
7703 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7704 ins_pipe( ialu_mem_imm );
7705 %}
7706
7707
7708 instruct checkCastPP( eRegP dst ) %{
7709 match(Set dst (CheckCastPP dst));
7710
7711 size(0);
7712 format %{ "#checkcastPP of $dst" %}
7713 ins_encode( /*empty encoding*/ );
7714 ins_pipe( empty );
7715 %}
7716
7717 instruct castPP( eRegP dst ) %{
7718 match(Set dst (CastPP dst));
7719 format %{ "#castPP of $dst" %}
7720 ins_encode( /*empty encoding*/ );
7721 ins_pipe( empty );
7722 %}
7723
7724 instruct castII( rRegI dst ) %{
7725 match(Set dst (CastII dst));
7726 format %{ "#castII of $dst" %}
7727 ins_encode( /*empty encoding*/ );
7728 ins_cost(0);
7729 ins_pipe( empty );
7730 %}
7731
7732
7733 // Load-locked - same as a regular pointer load when used with compare-swap
7734 instruct loadPLocked(eRegP dst, memory mem) %{
7735 match(Set dst (LoadPLocked mem));
7736
7737 ins_cost(125);
7738 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7739 opcode(0x8B);
7740 ins_encode( OpcP, RegMem(dst,mem));
7741 ins_pipe( ialu_reg_mem );
7742 %}
7743
7744 // Conditional-store of the updated heap-top.
7745 // Used during allocation of the shared heap.
7746 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7747 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7748 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7749 // EAX is killed if there is contention, but then it's also unused.
7750 // In the common case of no contention, EAX holds the new oop address.
7751 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7752 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7753 ins_pipe( pipe_cmpxchg );
7754 %}
7755
7756 // Conditional-store of an int value.
7757 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7758 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7759 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7760 effect(KILL oldval);
7761 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7762 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7763 ins_pipe( pipe_cmpxchg );
7764 %}
7765
7766 // Conditional-store of a long value.
7767 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7768 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7769 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7770 effect(KILL oldval);
7771 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7772 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7773 "XCHG EBX,ECX"
7774 %}
7775 ins_encode %{
7776 // Note: we need to swap rbx, and rcx before and after the
7777 // cmpxchg8 instruction because the instruction uses
7778 // rcx as the high order word of the new value to store but
7779 // our register encoding uses rbx.
7780 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7781 if( os::is_MP() )
7782 __ lock();
7783 __ cmpxchg8($mem$$Address);
7784 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7785 %}
7786 ins_pipe( pipe_cmpxchg );
7787 %}
7788
7789 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7790
7791 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7792 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7793 effect(KILL cr, KILL oldval);
7794 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7795 "MOV $res,0\n\t"
7796 "JNE,s fail\n\t"
7797 "MOV $res,1\n"
7798 "fail:" %}
7799 ins_encode( enc_cmpxchg8(mem_ptr),
7800 enc_flags_ne_to_boolean(res) );
7801 ins_pipe( pipe_cmpxchg );
7802 %}
7803
7804 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7805 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7806 effect(KILL cr, KILL oldval);
7807 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7808 "MOV $res,0\n\t"
7809 "JNE,s fail\n\t"
7810 "MOV $res,1\n"
7811 "fail:" %}
7812 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7813 ins_pipe( pipe_cmpxchg );
7814 %}
7815
7816 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7817 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7818 effect(KILL cr, KILL oldval);
7819 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7820 "MOV $res,0\n\t"
7821 "JNE,s fail\n\t"
7822 "MOV $res,1\n"
7823 "fail:" %}
7824 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7825 ins_pipe( pipe_cmpxchg );
7826 %}
7827
7828 //----------Subtraction Instructions-------------------------------------------
7829 // Integer Subtraction Instructions
7830 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7831 match(Set dst (SubI dst src));
7832 effect(KILL cr);
7833
7834 size(2);
7835 format %{ "SUB $dst,$src" %}
7836 opcode(0x2B);
7837 ins_encode( OpcP, RegReg( dst, src) );
7838 ins_pipe( ialu_reg_reg );
7839 %}
7840
7841 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7842 match(Set dst (SubI dst src));
7843 effect(KILL cr);
7844
7845 format %{ "SUB $dst,$src" %}
7846 opcode(0x81,0x05); /* Opcode 81 /5 */
7847 // ins_encode( RegImm( dst, src) );
7848 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7849 ins_pipe( ialu_reg );
7850 %}
7851
7852 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7853 match(Set dst (SubI dst (LoadI src)));
7854 effect(KILL cr);
7855
7856 ins_cost(125);
7857 format %{ "SUB $dst,$src" %}
7858 opcode(0x2B);
7859 ins_encode( OpcP, RegMem( dst, src) );
7860 ins_pipe( ialu_reg_mem );
7861 %}
7862
7863 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7864 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7865 effect(KILL cr);
7866
7867 ins_cost(150);
7868 format %{ "SUB $dst,$src" %}
7869 opcode(0x29); /* Opcode 29 /r */
7870 ins_encode( OpcP, RegMem( src, dst ) );
7871 ins_pipe( ialu_mem_reg );
7872 %}
7873
7874 // Subtract from a pointer
7875 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7876 match(Set dst (AddP dst (SubI zero src)));
7877 effect(KILL cr);
7878
7879 size(2);
7880 format %{ "SUB $dst,$src" %}
7881 opcode(0x2B);
7882 ins_encode( OpcP, RegReg( dst, src) );
7883 ins_pipe( ialu_reg_reg );
7884 %}
7885
7886 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7887 match(Set dst (SubI zero dst));
7888 effect(KILL cr);
7889
7890 size(2);
7891 format %{ "NEG $dst" %}
7892 opcode(0xF7,0x03); // Opcode F7 /3
7893 ins_encode( OpcP, RegOpc( dst ) );
7894 ins_pipe( ialu_reg );
7895 %}
7896
7897
7898 //----------Multiplication/Division Instructions-------------------------------
7899 // Integer Multiplication Instructions
7900 // Multiply Register
7901 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7902 match(Set dst (MulI dst src));
7903 effect(KILL cr);
7904
7905 size(3);
7906 ins_cost(300);
7907 format %{ "IMUL $dst,$src" %}
7908 opcode(0xAF, 0x0F);
7909 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7910 ins_pipe( ialu_reg_reg_alu0 );
7911 %}
7912
7913 // Multiply 32-bit Immediate
7914 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7915 match(Set dst (MulI src imm));
7916 effect(KILL cr);
7917
7918 ins_cost(300);
7919 format %{ "IMUL $dst,$src,$imm" %}
7920 opcode(0x69); /* 69 /r id */
7921 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7922 ins_pipe( ialu_reg_reg_alu0 );
7923 %}
7924
7925 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7926 match(Set dst src);
7927 effect(KILL cr);
7928
7929 // Note that this is artificially increased to make it more expensive than loadConL
7930 ins_cost(250);
7931 format %{ "MOV EAX,$src\t// low word only" %}
7932 opcode(0xB8);
7933 ins_encode( LdImmL_Lo(dst, src) );
7934 ins_pipe( ialu_reg_fat );
7935 %}
7936
7937 // Multiply by 32-bit Immediate, taking the shifted high order results
7938 // (special case for shift by 32)
7939 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7940 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7941 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7942 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7943 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7944 effect(USE src1, KILL cr);
7945
7946 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7947 ins_cost(0*100 + 1*400 - 150);
7948 format %{ "IMUL EDX:EAX,$src1" %}
7949 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7950 ins_pipe( pipe_slow );
7951 %}
7952
7953 // Multiply by 32-bit Immediate, taking the shifted high order results
7954 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7955 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7956 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7957 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7958 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7959 effect(USE src1, KILL cr);
7960
7961 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7962 ins_cost(1*100 + 1*400 - 150);
7963 format %{ "IMUL EDX:EAX,$src1\n\t"
7964 "SAR EDX,$cnt-32" %}
7965 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7966 ins_pipe( pipe_slow );
7967 %}
7968
7969 // Multiply Memory 32-bit Immediate
7970 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7971 match(Set dst (MulI (LoadI src) imm));
7972 effect(KILL cr);
7973
7974 ins_cost(300);
7975 format %{ "IMUL $dst,$src,$imm" %}
7976 opcode(0x69); /* 69 /r id */
7977 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7978 ins_pipe( ialu_reg_mem_alu0 );
7979 %}
7980
7981 // Multiply Memory
7982 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
7983 match(Set dst (MulI dst (LoadI src)));
7984 effect(KILL cr);
7985
7986 ins_cost(350);
7987 format %{ "IMUL $dst,$src" %}
7988 opcode(0xAF, 0x0F);
7989 ins_encode( OpcS, OpcP, RegMem( dst, src) );
7990 ins_pipe( ialu_reg_mem_alu0 );
7991 %}
7992
7993 // Multiply Register Int to Long
7994 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
7995 // Basic Idea: long = (long)int * (long)int
7996 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
7997 effect(DEF dst, USE src, USE src1, KILL flags);
7998
7999 ins_cost(300);
8000 format %{ "IMUL $dst,$src1" %}
8001
8002 ins_encode( long_int_multiply( dst, src1 ) );
8003 ins_pipe( ialu_reg_reg_alu0 );
8004 %}
8005
8006 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8007 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8008 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8009 effect(KILL flags);
8010
8011 ins_cost(300);
8012 format %{ "MUL $dst,$src1" %}
8013
8014 ins_encode( long_uint_multiply(dst, src1) );
8015 ins_pipe( ialu_reg_reg_alu0 );
8016 %}
8017
8018 // Multiply Register Long
8019 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8020 match(Set dst (MulL dst src));
8021 effect(KILL cr, TEMP tmp);
8022 ins_cost(4*100+3*400);
8023 // Basic idea: lo(result) = lo(x_lo * y_lo)
8024 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8025 format %{ "MOV $tmp,$src.lo\n\t"
8026 "IMUL $tmp,EDX\n\t"
8027 "MOV EDX,$src.hi\n\t"
8028 "IMUL EDX,EAX\n\t"
8029 "ADD $tmp,EDX\n\t"
8030 "MUL EDX:EAX,$src.lo\n\t"
8031 "ADD EDX,$tmp" %}
8032 ins_encode( long_multiply( dst, src, tmp ) );
8033 ins_pipe( pipe_slow );
8034 %}
8035
8036 // Multiply Register Long where the left operand's high 32 bits are zero
8037 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8038 predicate(is_operand_hi32_zero(n->in(1)));
8039 match(Set dst (MulL dst src));
8040 effect(KILL cr, TEMP tmp);
8041 ins_cost(2*100+2*400);
8042 // Basic idea: lo(result) = lo(x_lo * y_lo)
8043 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8044 format %{ "MOV $tmp,$src.hi\n\t"
8045 "IMUL $tmp,EAX\n\t"
8046 "MUL EDX:EAX,$src.lo\n\t"
8047 "ADD EDX,$tmp" %}
8048 ins_encode %{
8049 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8050 __ imull($tmp$$Register, rax);
8051 __ mull($src$$Register);
8052 __ addl(rdx, $tmp$$Register);
8053 %}
8054 ins_pipe( pipe_slow );
8055 %}
8056
8057 // Multiply Register Long where the right operand's high 32 bits are zero
8058 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8059 predicate(is_operand_hi32_zero(n->in(2)));
8060 match(Set dst (MulL dst src));
8061 effect(KILL cr, TEMP tmp);
8062 ins_cost(2*100+2*400);
8063 // Basic idea: lo(result) = lo(x_lo * y_lo)
8064 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8065 format %{ "MOV $tmp,$src.lo\n\t"
8066 "IMUL $tmp,EDX\n\t"
8067 "MUL EDX:EAX,$src.lo\n\t"
8068 "ADD EDX,$tmp" %}
8069 ins_encode %{
8070 __ movl($tmp$$Register, $src$$Register);
8071 __ imull($tmp$$Register, rdx);
8072 __ mull($src$$Register);
8073 __ addl(rdx, $tmp$$Register);
8074 %}
8075 ins_pipe( pipe_slow );
8076 %}
8077
8078 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8079 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8080 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8081 match(Set dst (MulL dst src));
8082 effect(KILL cr);
8083 ins_cost(1*400);
8084 // Basic idea: lo(result) = lo(x_lo * y_lo)
8085 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8086 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8087 ins_encode %{
8088 __ mull($src$$Register);
8089 %}
8090 ins_pipe( pipe_slow );
8091 %}
8092
8093 // Multiply Register Long by small constant
8094 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8095 match(Set dst (MulL dst src));
8096 effect(KILL cr, TEMP tmp);
8097 ins_cost(2*100+2*400);
8098 size(12);
8099 // Basic idea: lo(result) = lo(src * EAX)
8100 // hi(result) = hi(src * EAX) + lo(src * EDX)
8101 format %{ "IMUL $tmp,EDX,$src\n\t"
8102 "MOV EDX,$src\n\t"
8103 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8104 "ADD EDX,$tmp" %}
8105 ins_encode( long_multiply_con( dst, src, tmp ) );
8106 ins_pipe( pipe_slow );
8107 %}
8108
8109 // Integer DIV with Register
8110 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8111 match(Set rax (DivI rax div));
8112 effect(KILL rdx, KILL cr);
8113 size(26);
8114 ins_cost(30*100+10*100);
8115 format %{ "CMP EAX,0x80000000\n\t"
8116 "JNE,s normal\n\t"
8117 "XOR EDX,EDX\n\t"
8118 "CMP ECX,-1\n\t"
8119 "JE,s done\n"
8120 "normal: CDQ\n\t"
8121 "IDIV $div\n\t"
8122 "done:" %}
8123 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8124 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8125 ins_pipe( ialu_reg_reg_alu0 );
8126 %}
8127
8128 // Divide Register Long
8129 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8130 match(Set dst (DivL src1 src2));
8131 effect( KILL cr, KILL cx, KILL bx );
8132 ins_cost(10000);
8133 format %{ "PUSH $src1.hi\n\t"
8134 "PUSH $src1.lo\n\t"
8135 "PUSH $src2.hi\n\t"
8136 "PUSH $src2.lo\n\t"
8137 "CALL SharedRuntime::ldiv\n\t"
8138 "ADD ESP,16" %}
8139 ins_encode( long_div(src1,src2) );
8140 ins_pipe( pipe_slow );
8141 %}
8142
8143 // Integer DIVMOD with Register, both quotient and mod results
8144 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8145 match(DivModI rax div);
8146 effect(KILL cr);
8147 size(26);
8148 ins_cost(30*100+10*100);
8149 format %{ "CMP EAX,0x80000000\n\t"
8150 "JNE,s normal\n\t"
8151 "XOR EDX,EDX\n\t"
8152 "CMP ECX,-1\n\t"
8153 "JE,s done\n"
8154 "normal: CDQ\n\t"
8155 "IDIV $div\n\t"
8156 "done:" %}
8157 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8158 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8159 ins_pipe( pipe_slow );
8160 %}
8161
8162 // Integer MOD with Register
8163 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8164 match(Set rdx (ModI rax div));
8165 effect(KILL rax, KILL cr);
8166
8167 size(26);
8168 ins_cost(300);
8169 format %{ "CDQ\n\t"
8170 "IDIV $div" %}
8171 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8172 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8173 ins_pipe( ialu_reg_reg_alu0 );
8174 %}
8175
8176 // Remainder Register Long
8177 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8178 match(Set dst (ModL src1 src2));
8179 effect( KILL cr, KILL cx, KILL bx );
8180 ins_cost(10000);
8181 format %{ "PUSH $src1.hi\n\t"
8182 "PUSH $src1.lo\n\t"
8183 "PUSH $src2.hi\n\t"
8184 "PUSH $src2.lo\n\t"
8185 "CALL SharedRuntime::lrem\n\t"
8186 "ADD ESP,16" %}
8187 ins_encode( long_mod(src1,src2) );
8188 ins_pipe( pipe_slow );
8189 %}
8190
8191 // Divide Register Long (no special case since divisor != -1)
8192 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8193 match(Set dst (DivL dst imm));
8194 effect( TEMP tmp, TEMP tmp2, KILL cr );
8195 ins_cost(1000);
8196 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8197 "XOR $tmp2,$tmp2\n\t"
8198 "CMP $tmp,EDX\n\t"
8199 "JA,s fast\n\t"
8200 "MOV $tmp2,EAX\n\t"
8201 "MOV EAX,EDX\n\t"
8202 "MOV EDX,0\n\t"
8203 "JLE,s pos\n\t"
8204 "LNEG EAX : $tmp2\n\t"
8205 "DIV $tmp # unsigned division\n\t"
8206 "XCHG EAX,$tmp2\n\t"
8207 "DIV $tmp\n\t"
8208 "LNEG $tmp2 : EAX\n\t"
8209 "JMP,s done\n"
8210 "pos:\n\t"
8211 "DIV $tmp\n\t"
8212 "XCHG EAX,$tmp2\n"
8213 "fast:\n\t"
8214 "DIV $tmp\n"
8215 "done:\n\t"
8216 "MOV EDX,$tmp2\n\t"
8217 "NEG EDX:EAX # if $imm < 0" %}
8218 ins_encode %{
8219 int con = (int)$imm$$constant;
8220 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8221 int pcon = (con > 0) ? con : -con;
8222 Label Lfast, Lpos, Ldone;
8223
8224 __ movl($tmp$$Register, pcon);
8225 __ xorl($tmp2$$Register,$tmp2$$Register);
8226 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8227 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8228
8229 __ movl($tmp2$$Register, $dst$$Register); // save
8230 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8231 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8232 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8233
8234 // Negative dividend.
8235 // convert value to positive to use unsigned division
8236 __ lneg($dst$$Register, $tmp2$$Register);
8237 __ divl($tmp$$Register);
8238 __ xchgl($dst$$Register, $tmp2$$Register);
8239 __ divl($tmp$$Register);
8240 // revert result back to negative
8241 __ lneg($tmp2$$Register, $dst$$Register);
8242 __ jmpb(Ldone);
8243
8244 __ bind(Lpos);
8245 __ divl($tmp$$Register); // Use unsigned division
8246 __ xchgl($dst$$Register, $tmp2$$Register);
8247 // Fallthrow for final divide, tmp2 has 32 bit hi result
8248
8249 __ bind(Lfast);
8250 // fast path: src is positive
8251 __ divl($tmp$$Register); // Use unsigned division
8252
8253 __ bind(Ldone);
8254 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8255 if (con < 0) {
8256 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8257 }
8258 %}
8259 ins_pipe( pipe_slow );
8260 %}
8261
8262 // Remainder Register Long (remainder fit into 32 bits)
8263 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8264 match(Set dst (ModL dst imm));
8265 effect( TEMP tmp, TEMP tmp2, KILL cr );
8266 ins_cost(1000);
8267 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8268 "CMP $tmp,EDX\n\t"
8269 "JA,s fast\n\t"
8270 "MOV $tmp2,EAX\n\t"
8271 "MOV EAX,EDX\n\t"
8272 "MOV EDX,0\n\t"
8273 "JLE,s pos\n\t"
8274 "LNEG EAX : $tmp2\n\t"
8275 "DIV $tmp # unsigned division\n\t"
8276 "MOV EAX,$tmp2\n\t"
8277 "DIV $tmp\n\t"
8278 "NEG EDX\n\t"
8279 "JMP,s done\n"
8280 "pos:\n\t"
8281 "DIV $tmp\n\t"
8282 "MOV EAX,$tmp2\n"
8283 "fast:\n\t"
8284 "DIV $tmp\n"
8285 "done:\n\t"
8286 "MOV EAX,EDX\n\t"
8287 "SAR EDX,31\n\t" %}
8288 ins_encode %{
8289 int con = (int)$imm$$constant;
8290 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8291 int pcon = (con > 0) ? con : -con;
8292 Label Lfast, Lpos, Ldone;
8293
8294 __ movl($tmp$$Register, pcon);
8295 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8296 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8297
8298 __ movl($tmp2$$Register, $dst$$Register); // save
8299 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8300 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8301 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8302
8303 // Negative dividend.
8304 // convert value to positive to use unsigned division
8305 __ lneg($dst$$Register, $tmp2$$Register);
8306 __ divl($tmp$$Register);
8307 __ movl($dst$$Register, $tmp2$$Register);
8308 __ divl($tmp$$Register);
8309 // revert remainder back to negative
8310 __ negl(HIGH_FROM_LOW($dst$$Register));
8311 __ jmpb(Ldone);
8312
8313 __ bind(Lpos);
8314 __ divl($tmp$$Register);
8315 __ movl($dst$$Register, $tmp2$$Register);
8316
8317 __ bind(Lfast);
8318 // fast path: src is positive
8319 __ divl($tmp$$Register);
8320
8321 __ bind(Ldone);
8322 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8323 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8324
8325 %}
8326 ins_pipe( pipe_slow );
8327 %}
8328
8329 // Integer Shift Instructions
8330 // Shift Left by one
8331 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8332 match(Set dst (LShiftI dst shift));
8333 effect(KILL cr);
8334
8335 size(2);
8336 format %{ "SHL $dst,$shift" %}
8337 opcode(0xD1, 0x4); /* D1 /4 */
8338 ins_encode( OpcP, RegOpc( dst ) );
8339 ins_pipe( ialu_reg );
8340 %}
8341
8342 // Shift Left by 8-bit immediate
8343 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8344 match(Set dst (LShiftI dst shift));
8345 effect(KILL cr);
8346
8347 size(3);
8348 format %{ "SHL $dst,$shift" %}
8349 opcode(0xC1, 0x4); /* C1 /4 ib */
8350 ins_encode( RegOpcImm( dst, shift) );
8351 ins_pipe( ialu_reg );
8352 %}
8353
8354 // Shift Left by variable
8355 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8356 match(Set dst (LShiftI dst shift));
8357 effect(KILL cr);
8358
8359 size(2);
8360 format %{ "SHL $dst,$shift" %}
8361 opcode(0xD3, 0x4); /* D3 /4 */
8362 ins_encode( OpcP, RegOpc( dst ) );
8363 ins_pipe( ialu_reg_reg );
8364 %}
8365
8366 // Arithmetic shift right by one
8367 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8368 match(Set dst (RShiftI dst shift));
8369 effect(KILL cr);
8370
8371 size(2);
8372 format %{ "SAR $dst,$shift" %}
8373 opcode(0xD1, 0x7); /* D1 /7 */
8374 ins_encode( OpcP, RegOpc( dst ) );
8375 ins_pipe( ialu_reg );
8376 %}
8377
8378 // Arithmetic shift right by one
8379 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8380 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8381 effect(KILL cr);
8382 format %{ "SAR $dst,$shift" %}
8383 opcode(0xD1, 0x7); /* D1 /7 */
8384 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8385 ins_pipe( ialu_mem_imm );
8386 %}
8387
8388 // Arithmetic Shift Right by 8-bit immediate
8389 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8390 match(Set dst (RShiftI dst shift));
8391 effect(KILL cr);
8392
8393 size(3);
8394 format %{ "SAR $dst,$shift" %}
8395 opcode(0xC1, 0x7); /* C1 /7 ib */
8396 ins_encode( RegOpcImm( dst, shift ) );
8397 ins_pipe( ialu_mem_imm );
8398 %}
8399
8400 // Arithmetic Shift Right by 8-bit immediate
8401 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8402 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8403 effect(KILL cr);
8404
8405 format %{ "SAR $dst,$shift" %}
8406 opcode(0xC1, 0x7); /* C1 /7 ib */
8407 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8408 ins_pipe( ialu_mem_imm );
8409 %}
8410
8411 // Arithmetic Shift Right by variable
8412 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8413 match(Set dst (RShiftI dst shift));
8414 effect(KILL cr);
8415
8416 size(2);
8417 format %{ "SAR $dst,$shift" %}
8418 opcode(0xD3, 0x7); /* D3 /7 */
8419 ins_encode( OpcP, RegOpc( dst ) );
8420 ins_pipe( ialu_reg_reg );
8421 %}
8422
8423 // Logical shift right by one
8424 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8425 match(Set dst (URShiftI dst shift));
8426 effect(KILL cr);
8427
8428 size(2);
8429 format %{ "SHR $dst,$shift" %}
8430 opcode(0xD1, 0x5); /* D1 /5 */
8431 ins_encode( OpcP, RegOpc( dst ) );
8432 ins_pipe( ialu_reg );
8433 %}
8434
8435 // Logical Shift Right by 8-bit immediate
8436 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8437 match(Set dst (URShiftI dst shift));
8438 effect(KILL cr);
8439
8440 size(3);
8441 format %{ "SHR $dst,$shift" %}
8442 opcode(0xC1, 0x5); /* C1 /5 ib */
8443 ins_encode( RegOpcImm( dst, shift) );
8444 ins_pipe( ialu_reg );
8445 %}
8446
8447
8448 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8449 // This idiom is used by the compiler for the i2b bytecode.
8450 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8451 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8452
8453 size(3);
8454 format %{ "MOVSX $dst,$src :8" %}
8455 ins_encode %{
8456 __ movsbl($dst$$Register, $src$$Register);
8457 %}
8458 ins_pipe(ialu_reg_reg);
8459 %}
8460
8461 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8462 // This idiom is used by the compiler the i2s bytecode.
8463 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8464 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8465
8466 size(3);
8467 format %{ "MOVSX $dst,$src :16" %}
8468 ins_encode %{
8469 __ movswl($dst$$Register, $src$$Register);
8470 %}
8471 ins_pipe(ialu_reg_reg);
8472 %}
8473
8474
8475 // Logical Shift Right by variable
8476 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8477 match(Set dst (URShiftI dst shift));
8478 effect(KILL cr);
8479
8480 size(2);
8481 format %{ "SHR $dst,$shift" %}
8482 opcode(0xD3, 0x5); /* D3 /5 */
8483 ins_encode( OpcP, RegOpc( dst ) );
8484 ins_pipe( ialu_reg_reg );
8485 %}
8486
8487
8488 //----------Logical Instructions-----------------------------------------------
8489 //----------Integer Logical Instructions---------------------------------------
8490 // And Instructions
8491 // And Register with Register
8492 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8493 match(Set dst (AndI dst src));
8494 effect(KILL cr);
8495
8496 size(2);
8497 format %{ "AND $dst,$src" %}
8498 opcode(0x23);
8499 ins_encode( OpcP, RegReg( dst, src) );
8500 ins_pipe( ialu_reg_reg );
8501 %}
8502
8503 // And Register with Immediate
8504 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8505 match(Set dst (AndI dst src));
8506 effect(KILL cr);
8507
8508 format %{ "AND $dst,$src" %}
8509 opcode(0x81,0x04); /* Opcode 81 /4 */
8510 // ins_encode( RegImm( dst, src) );
8511 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8512 ins_pipe( ialu_reg );
8513 %}
8514
8515 // And Register with Memory
8516 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8517 match(Set dst (AndI dst (LoadI src)));
8518 effect(KILL cr);
8519
8520 ins_cost(125);
8521 format %{ "AND $dst,$src" %}
8522 opcode(0x23);
8523 ins_encode( OpcP, RegMem( dst, src) );
8524 ins_pipe( ialu_reg_mem );
8525 %}
8526
8527 // And Memory with Register
8528 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8529 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8530 effect(KILL cr);
8531
8532 ins_cost(150);
8533 format %{ "AND $dst,$src" %}
8534 opcode(0x21); /* Opcode 21 /r */
8535 ins_encode( OpcP, RegMem( src, dst ) );
8536 ins_pipe( ialu_mem_reg );
8537 %}
8538
8539 // And Memory with Immediate
8540 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8541 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8542 effect(KILL cr);
8543
8544 ins_cost(125);
8545 format %{ "AND $dst,$src" %}
8546 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8547 // ins_encode( MemImm( dst, src) );
8548 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8549 ins_pipe( ialu_mem_imm );
8550 %}
8551
8552 // Or Instructions
8553 // Or Register with Register
8554 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8555 match(Set dst (OrI dst src));
8556 effect(KILL cr);
8557
8558 size(2);
8559 format %{ "OR $dst,$src" %}
8560 opcode(0x0B);
8561 ins_encode( OpcP, RegReg( dst, src) );
8562 ins_pipe( ialu_reg_reg );
8563 %}
8564
8565 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8566 match(Set dst (OrI dst (CastP2X src)));
8567 effect(KILL cr);
8568
8569 size(2);
8570 format %{ "OR $dst,$src" %}
8571 opcode(0x0B);
8572 ins_encode( OpcP, RegReg( dst, src) );
8573 ins_pipe( ialu_reg_reg );
8574 %}
8575
8576
8577 // Or Register with Immediate
8578 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8579 match(Set dst (OrI dst src));
8580 effect(KILL cr);
8581
8582 format %{ "OR $dst,$src" %}
8583 opcode(0x81,0x01); /* Opcode 81 /1 id */
8584 // ins_encode( RegImm( dst, src) );
8585 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8586 ins_pipe( ialu_reg );
8587 %}
8588
8589 // Or Register with Memory
8590 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8591 match(Set dst (OrI dst (LoadI src)));
8592 effect(KILL cr);
8593
8594 ins_cost(125);
8595 format %{ "OR $dst,$src" %}
8596 opcode(0x0B);
8597 ins_encode( OpcP, RegMem( dst, src) );
8598 ins_pipe( ialu_reg_mem );
8599 %}
8600
8601 // Or Memory with Register
8602 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8603 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8604 effect(KILL cr);
8605
8606 ins_cost(150);
8607 format %{ "OR $dst,$src" %}
8608 opcode(0x09); /* Opcode 09 /r */
8609 ins_encode( OpcP, RegMem( src, dst ) );
8610 ins_pipe( ialu_mem_reg );
8611 %}
8612
8613 // Or Memory with Immediate
8614 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8615 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8616 effect(KILL cr);
8617
8618 ins_cost(125);
8619 format %{ "OR $dst,$src" %}
8620 opcode(0x81,0x1); /* Opcode 81 /1 id */
8621 // ins_encode( MemImm( dst, src) );
8622 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8623 ins_pipe( ialu_mem_imm );
8624 %}
8625
8626 // ROL/ROR
8627 // ROL expand
8628 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8629 effect(USE_DEF dst, USE shift, KILL cr);
8630
8631 format %{ "ROL $dst, $shift" %}
8632 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8633 ins_encode( OpcP, RegOpc( dst ));
8634 ins_pipe( ialu_reg );
8635 %}
8636
8637 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8638 effect(USE_DEF dst, USE shift, KILL cr);
8639
8640 format %{ "ROL $dst, $shift" %}
8641 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8642 ins_encode( RegOpcImm(dst, shift) );
8643 ins_pipe(ialu_reg);
8644 %}
8645
8646 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8647 effect(USE_DEF dst, USE shift, KILL cr);
8648
8649 format %{ "ROL $dst, $shift" %}
8650 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8651 ins_encode(OpcP, RegOpc(dst));
8652 ins_pipe( ialu_reg_reg );
8653 %}
8654 // end of ROL expand
8655
8656 // ROL 32bit by one once
8657 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8658 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8659
8660 expand %{
8661 rolI_eReg_imm1(dst, lshift, cr);
8662 %}
8663 %}
8664
8665 // ROL 32bit var by imm8 once
8666 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8667 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8668 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8669
8670 expand %{
8671 rolI_eReg_imm8(dst, lshift, cr);
8672 %}
8673 %}
8674
8675 // ROL 32bit var by var once
8676 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8677 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8678
8679 expand %{
8680 rolI_eReg_CL(dst, shift, cr);
8681 %}
8682 %}
8683
8684 // ROL 32bit var by var once
8685 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8686 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8687
8688 expand %{
8689 rolI_eReg_CL(dst, shift, cr);
8690 %}
8691 %}
8692
8693 // ROR expand
8694 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8695 effect(USE_DEF dst, USE shift, KILL cr);
8696
8697 format %{ "ROR $dst, $shift" %}
8698 opcode(0xD1,0x1); /* Opcode D1 /1 */
8699 ins_encode( OpcP, RegOpc( dst ) );
8700 ins_pipe( ialu_reg );
8701 %}
8702
8703 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8704 effect (USE_DEF dst, USE shift, KILL cr);
8705
8706 format %{ "ROR $dst, $shift" %}
8707 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8708 ins_encode( RegOpcImm(dst, shift) );
8709 ins_pipe( ialu_reg );
8710 %}
8711
8712 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8713 effect(USE_DEF dst, USE shift, KILL cr);
8714
8715 format %{ "ROR $dst, $shift" %}
8716 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8717 ins_encode(OpcP, RegOpc(dst));
8718 ins_pipe( ialu_reg_reg );
8719 %}
8720 // end of ROR expand
8721
8722 // ROR right once
8723 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8724 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8725
8726 expand %{
8727 rorI_eReg_imm1(dst, rshift, cr);
8728 %}
8729 %}
8730
8731 // ROR 32bit by immI8 once
8732 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8733 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8734 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8735
8736 expand %{
8737 rorI_eReg_imm8(dst, rshift, cr);
8738 %}
8739 %}
8740
8741 // ROR 32bit var by var once
8742 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8743 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8744
8745 expand %{
8746 rorI_eReg_CL(dst, shift, cr);
8747 %}
8748 %}
8749
8750 // ROR 32bit var by var once
8751 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8752 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8753
8754 expand %{
8755 rorI_eReg_CL(dst, shift, cr);
8756 %}
8757 %}
8758
8759 // Xor Instructions
8760 // Xor Register with Register
8761 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8762 match(Set dst (XorI dst src));
8763 effect(KILL cr);
8764
8765 size(2);
8766 format %{ "XOR $dst,$src" %}
8767 opcode(0x33);
8768 ins_encode( OpcP, RegReg( dst, src) );
8769 ins_pipe( ialu_reg_reg );
8770 %}
8771
8772 // Xor Register with Immediate -1
8773 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8774 match(Set dst (XorI dst imm));
8775
8776 size(2);
8777 format %{ "NOT $dst" %}
8778 ins_encode %{
8779 __ notl($dst$$Register);
8780 %}
8781 ins_pipe( ialu_reg );
8782 %}
8783
8784 // Xor Register with Immediate
8785 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8786 match(Set dst (XorI dst src));
8787 effect(KILL cr);
8788
8789 format %{ "XOR $dst,$src" %}
8790 opcode(0x81,0x06); /* Opcode 81 /6 id */
8791 // ins_encode( RegImm( dst, src) );
8792 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8793 ins_pipe( ialu_reg );
8794 %}
8795
8796 // Xor Register with Memory
8797 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8798 match(Set dst (XorI dst (LoadI src)));
8799 effect(KILL cr);
8800
8801 ins_cost(125);
8802 format %{ "XOR $dst,$src" %}
8803 opcode(0x33);
8804 ins_encode( OpcP, RegMem(dst, src) );
8805 ins_pipe( ialu_reg_mem );
8806 %}
8807
8808 // Xor Memory with Register
8809 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8810 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8811 effect(KILL cr);
8812
8813 ins_cost(150);
8814 format %{ "XOR $dst,$src" %}
8815 opcode(0x31); /* Opcode 31 /r */
8816 ins_encode( OpcP, RegMem( src, dst ) );
8817 ins_pipe( ialu_mem_reg );
8818 %}
8819
8820 // Xor Memory with Immediate
8821 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8822 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8823 effect(KILL cr);
8824
8825 ins_cost(125);
8826 format %{ "XOR $dst,$src" %}
8827 opcode(0x81,0x6); /* Opcode 81 /6 id */
8828 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8829 ins_pipe( ialu_mem_imm );
8830 %}
8831
8832 //----------Convert Int to Boolean---------------------------------------------
8833
8834 instruct movI_nocopy(rRegI dst, rRegI src) %{
8835 effect( DEF dst, USE src );
8836 format %{ "MOV $dst,$src" %}
8837 ins_encode( enc_Copy( dst, src) );
8838 ins_pipe( ialu_reg_reg );
8839 %}
8840
8841 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8842 effect( USE_DEF dst, USE src, KILL cr );
8843
8844 size(4);
8845 format %{ "NEG $dst\n\t"
8846 "ADC $dst,$src" %}
8847 ins_encode( neg_reg(dst),
8848 OpcRegReg(0x13,dst,src) );
8849 ins_pipe( ialu_reg_reg_long );
8850 %}
8851
8852 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8853 match(Set dst (Conv2B src));
8854
8855 expand %{
8856 movI_nocopy(dst,src);
8857 ci2b(dst,src,cr);
8858 %}
8859 %}
8860
8861 instruct movP_nocopy(rRegI dst, eRegP src) %{
8862 effect( DEF dst, USE src );
8863 format %{ "MOV $dst,$src" %}
8864 ins_encode( enc_Copy( dst, src) );
8865 ins_pipe( ialu_reg_reg );
8866 %}
8867
8868 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8869 effect( USE_DEF dst, USE src, KILL cr );
8870 format %{ "NEG $dst\n\t"
8871 "ADC $dst,$src" %}
8872 ins_encode( neg_reg(dst),
8873 OpcRegReg(0x13,dst,src) );
8874 ins_pipe( ialu_reg_reg_long );
8875 %}
8876
8877 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8878 match(Set dst (Conv2B src));
8879
8880 expand %{
8881 movP_nocopy(dst,src);
8882 cp2b(dst,src,cr);
8883 %}
8884 %}
8885
8886 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
8887 match(Set dst (CmpLTMask p q));
8888 effect( KILL cr );
8889 ins_cost(400);
8890
8891 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8892 format %{ "XOR $dst,$dst\n\t"
8893 "CMP $p,$q\n\t"
8894 "SETlt $dst\n\t"
8895 "NEG $dst" %}
8896 ins_encode( OpcRegReg(0x33,dst,dst),
8897 OpcRegReg(0x3B,p,q),
8898 setLT_reg(dst), neg_reg(dst) );
8899 ins_pipe( pipe_slow );
8900 %}
8901
8902 instruct cmpLTMask0( rRegI dst, immI0 zero, eFlagsReg cr ) %{
8903 match(Set dst (CmpLTMask dst zero));
8904 effect( DEF dst, KILL cr );
8905 ins_cost(100);
8906
8907 format %{ "SAR $dst,31" %}
8908 opcode(0xC1, 0x7); /* C1 /7 ib */
8909 ins_encode( RegOpcImm( dst, 0x1F ) );
8910 ins_pipe( ialu_reg );
8911 %}
8912
8913
8914 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
8915 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8916 effect( KILL tmp, KILL cr );
8917 ins_cost(400);
8918 // annoyingly, $tmp has no edges so you cant ask for it in
8919 // any format or encoding
8920 format %{ "SUB $p,$q\n\t"
8921 "SBB ECX,ECX\n\t"
8922 "AND ECX,$y\n\t"
8923 "ADD $p,ECX" %}
8924 ins_encode( enc_cmpLTP(p,q,y,tmp) );
8925 ins_pipe( pipe_cmplt );
8926 %}
8927
8928 /* If I enable this, I encourage spilling in the inner loop of compress.
8929 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
8930 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8931 effect( USE_KILL tmp, KILL cr );
8932 ins_cost(400);
8933
8934 format %{ "SUB $p,$q\n\t"
8935 "SBB ECX,ECX\n\t"
8936 "AND ECX,$y\n\t"
8937 "ADD $p,ECX" %}
8938 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
8939 %}
8940 */
8941
8942 //----------Long Instructions------------------------------------------------
8943 // Add Long Register with Register
8944 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8945 match(Set dst (AddL dst src));
8946 effect(KILL cr);
8947 ins_cost(200);
8948 format %{ "ADD $dst.lo,$src.lo\n\t"
8949 "ADC $dst.hi,$src.hi" %}
8950 opcode(0x03, 0x13);
8951 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8952 ins_pipe( ialu_reg_reg_long );
8953 %}
8954
8955 // Add Long Register with Immediate
8956 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8957 match(Set dst (AddL dst src));
8958 effect(KILL cr);
8959 format %{ "ADD $dst.lo,$src.lo\n\t"
8960 "ADC $dst.hi,$src.hi" %}
8961 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
8962 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8963 ins_pipe( ialu_reg_long );
8964 %}
8965
8966 // Add Long Register with Memory
8967 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8968 match(Set dst (AddL dst (LoadL mem)));
8969 effect(KILL cr);
8970 ins_cost(125);
8971 format %{ "ADD $dst.lo,$mem\n\t"
8972 "ADC $dst.hi,$mem+4" %}
8973 opcode(0x03, 0x13);
8974 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8975 ins_pipe( ialu_reg_long_mem );
8976 %}
8977
8978 // Subtract Long Register with Register.
8979 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8980 match(Set dst (SubL dst src));
8981 effect(KILL cr);
8982 ins_cost(200);
8983 format %{ "SUB $dst.lo,$src.lo\n\t"
8984 "SBB $dst.hi,$src.hi" %}
8985 opcode(0x2B, 0x1B);
8986 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8987 ins_pipe( ialu_reg_reg_long );
8988 %}
8989
8990 // Subtract Long Register with Immediate
8991 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8992 match(Set dst (SubL dst src));
8993 effect(KILL cr);
8994 format %{ "SUB $dst.lo,$src.lo\n\t"
8995 "SBB $dst.hi,$src.hi" %}
8996 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
8997 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8998 ins_pipe( ialu_reg_long );
8999 %}
9000
9001 // Subtract Long Register with Memory
9002 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9003 match(Set dst (SubL dst (LoadL mem)));
9004 effect(KILL cr);
9005 ins_cost(125);
9006 format %{ "SUB $dst.lo,$mem\n\t"
9007 "SBB $dst.hi,$mem+4" %}
9008 opcode(0x2B, 0x1B);
9009 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9010 ins_pipe( ialu_reg_long_mem );
9011 %}
9012
9013 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9014 match(Set dst (SubL zero dst));
9015 effect(KILL cr);
9016 ins_cost(300);
9017 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9018 ins_encode( neg_long(dst) );
9019 ins_pipe( ialu_reg_reg_long );
9020 %}
9021
9022 // And Long Register with Register
9023 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9024 match(Set dst (AndL dst src));
9025 effect(KILL cr);
9026 format %{ "AND $dst.lo,$src.lo\n\t"
9027 "AND $dst.hi,$src.hi" %}
9028 opcode(0x23,0x23);
9029 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9030 ins_pipe( ialu_reg_reg_long );
9031 %}
9032
9033 // And Long Register with Immediate
9034 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9035 match(Set dst (AndL dst src));
9036 effect(KILL cr);
9037 format %{ "AND $dst.lo,$src.lo\n\t"
9038 "AND $dst.hi,$src.hi" %}
9039 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9040 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9041 ins_pipe( ialu_reg_long );
9042 %}
9043
9044 // And Long Register with Memory
9045 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9046 match(Set dst (AndL dst (LoadL mem)));
9047 effect(KILL cr);
9048 ins_cost(125);
9049 format %{ "AND $dst.lo,$mem\n\t"
9050 "AND $dst.hi,$mem+4" %}
9051 opcode(0x23, 0x23);
9052 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9053 ins_pipe( ialu_reg_long_mem );
9054 %}
9055
9056 // Or Long Register with Register
9057 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9058 match(Set dst (OrL dst src));
9059 effect(KILL cr);
9060 format %{ "OR $dst.lo,$src.lo\n\t"
9061 "OR $dst.hi,$src.hi" %}
9062 opcode(0x0B,0x0B);
9063 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9064 ins_pipe( ialu_reg_reg_long );
9065 %}
9066
9067 // Or Long Register with Immediate
9068 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9069 match(Set dst (OrL dst src));
9070 effect(KILL cr);
9071 format %{ "OR $dst.lo,$src.lo\n\t"
9072 "OR $dst.hi,$src.hi" %}
9073 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9074 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9075 ins_pipe( ialu_reg_long );
9076 %}
9077
9078 // Or Long Register with Memory
9079 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9080 match(Set dst (OrL dst (LoadL mem)));
9081 effect(KILL cr);
9082 ins_cost(125);
9083 format %{ "OR $dst.lo,$mem\n\t"
9084 "OR $dst.hi,$mem+4" %}
9085 opcode(0x0B,0x0B);
9086 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9087 ins_pipe( ialu_reg_long_mem );
9088 %}
9089
9090 // Xor Long Register with Register
9091 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9092 match(Set dst (XorL dst src));
9093 effect(KILL cr);
9094 format %{ "XOR $dst.lo,$src.lo\n\t"
9095 "XOR $dst.hi,$src.hi" %}
9096 opcode(0x33,0x33);
9097 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9098 ins_pipe( ialu_reg_reg_long );
9099 %}
9100
9101 // Xor Long Register with Immediate -1
9102 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9103 match(Set dst (XorL dst imm));
9104 format %{ "NOT $dst.lo\n\t"
9105 "NOT $dst.hi" %}
9106 ins_encode %{
9107 __ notl($dst$$Register);
9108 __ notl(HIGH_FROM_LOW($dst$$Register));
9109 %}
9110 ins_pipe( ialu_reg_long );
9111 %}
9112
9113 // Xor Long Register with Immediate
9114 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9115 match(Set dst (XorL dst src));
9116 effect(KILL cr);
9117 format %{ "XOR $dst.lo,$src.lo\n\t"
9118 "XOR $dst.hi,$src.hi" %}
9119 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9120 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9121 ins_pipe( ialu_reg_long );
9122 %}
9123
9124 // Xor Long Register with Memory
9125 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9126 match(Set dst (XorL dst (LoadL mem)));
9127 effect(KILL cr);
9128 ins_cost(125);
9129 format %{ "XOR $dst.lo,$mem\n\t"
9130 "XOR $dst.hi,$mem+4" %}
9131 opcode(0x33,0x33);
9132 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9133 ins_pipe( ialu_reg_long_mem );
9134 %}
9135
9136 // Shift Left Long by 1
9137 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9138 predicate(UseNewLongLShift);
9139 match(Set dst (LShiftL dst cnt));
9140 effect(KILL cr);
9141 ins_cost(100);
9142 format %{ "ADD $dst.lo,$dst.lo\n\t"
9143 "ADC $dst.hi,$dst.hi" %}
9144 ins_encode %{
9145 __ addl($dst$$Register,$dst$$Register);
9146 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9147 %}
9148 ins_pipe( ialu_reg_long );
9149 %}
9150
9151 // Shift Left Long by 2
9152 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9153 predicate(UseNewLongLShift);
9154 match(Set dst (LShiftL dst cnt));
9155 effect(KILL cr);
9156 ins_cost(100);
9157 format %{ "ADD $dst.lo,$dst.lo\n\t"
9158 "ADC $dst.hi,$dst.hi\n\t"
9159 "ADD $dst.lo,$dst.lo\n\t"
9160 "ADC $dst.hi,$dst.hi" %}
9161 ins_encode %{
9162 __ addl($dst$$Register,$dst$$Register);
9163 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9164 __ addl($dst$$Register,$dst$$Register);
9165 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9166 %}
9167 ins_pipe( ialu_reg_long );
9168 %}
9169
9170 // Shift Left Long by 3
9171 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9172 predicate(UseNewLongLShift);
9173 match(Set dst (LShiftL dst cnt));
9174 effect(KILL cr);
9175 ins_cost(100);
9176 format %{ "ADD $dst.lo,$dst.lo\n\t"
9177 "ADC $dst.hi,$dst.hi\n\t"
9178 "ADD $dst.lo,$dst.lo\n\t"
9179 "ADC $dst.hi,$dst.hi\n\t"
9180 "ADD $dst.lo,$dst.lo\n\t"
9181 "ADC $dst.hi,$dst.hi" %}
9182 ins_encode %{
9183 __ addl($dst$$Register,$dst$$Register);
9184 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9185 __ addl($dst$$Register,$dst$$Register);
9186 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9187 __ addl($dst$$Register,$dst$$Register);
9188 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9189 %}
9190 ins_pipe( ialu_reg_long );
9191 %}
9192
9193 // Shift Left Long by 1-31
9194 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9195 match(Set dst (LShiftL dst cnt));
9196 effect(KILL cr);
9197 ins_cost(200);
9198 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9199 "SHL $dst.lo,$cnt" %}
9200 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9201 ins_encode( move_long_small_shift(dst,cnt) );
9202 ins_pipe( ialu_reg_long );
9203 %}
9204
9205 // Shift Left Long by 32-63
9206 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9207 match(Set dst (LShiftL dst cnt));
9208 effect(KILL cr);
9209 ins_cost(300);
9210 format %{ "MOV $dst.hi,$dst.lo\n"
9211 "\tSHL $dst.hi,$cnt-32\n"
9212 "\tXOR $dst.lo,$dst.lo" %}
9213 opcode(0xC1, 0x4); /* C1 /4 ib */
9214 ins_encode( move_long_big_shift_clr(dst,cnt) );
9215 ins_pipe( ialu_reg_long );
9216 %}
9217
9218 // Shift Left Long by variable
9219 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9220 match(Set dst (LShiftL dst shift));
9221 effect(KILL cr);
9222 ins_cost(500+200);
9223 size(17);
9224 format %{ "TEST $shift,32\n\t"
9225 "JEQ,s small\n\t"
9226 "MOV $dst.hi,$dst.lo\n\t"
9227 "XOR $dst.lo,$dst.lo\n"
9228 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9229 "SHL $dst.lo,$shift" %}
9230 ins_encode( shift_left_long( dst, shift ) );
9231 ins_pipe( pipe_slow );
9232 %}
9233
9234 // Shift Right Long by 1-31
9235 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9236 match(Set dst (URShiftL dst cnt));
9237 effect(KILL cr);
9238 ins_cost(200);
9239 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9240 "SHR $dst.hi,$cnt" %}
9241 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9242 ins_encode( move_long_small_shift(dst,cnt) );
9243 ins_pipe( ialu_reg_long );
9244 %}
9245
9246 // Shift Right Long by 32-63
9247 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9248 match(Set dst (URShiftL dst cnt));
9249 effect(KILL cr);
9250 ins_cost(300);
9251 format %{ "MOV $dst.lo,$dst.hi\n"
9252 "\tSHR $dst.lo,$cnt-32\n"
9253 "\tXOR $dst.hi,$dst.hi" %}
9254 opcode(0xC1, 0x5); /* C1 /5 ib */
9255 ins_encode( move_long_big_shift_clr(dst,cnt) );
9256 ins_pipe( ialu_reg_long );
9257 %}
9258
9259 // Shift Right Long by variable
9260 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9261 match(Set dst (URShiftL dst shift));
9262 effect(KILL cr);
9263 ins_cost(600);
9264 size(17);
9265 format %{ "TEST $shift,32\n\t"
9266 "JEQ,s small\n\t"
9267 "MOV $dst.lo,$dst.hi\n\t"
9268 "XOR $dst.hi,$dst.hi\n"
9269 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9270 "SHR $dst.hi,$shift" %}
9271 ins_encode( shift_right_long( dst, shift ) );
9272 ins_pipe( pipe_slow );
9273 %}
9274
9275 // Shift Right Long by 1-31
9276 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9277 match(Set dst (RShiftL dst cnt));
9278 effect(KILL cr);
9279 ins_cost(200);
9280 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9281 "SAR $dst.hi,$cnt" %}
9282 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9283 ins_encode( move_long_small_shift(dst,cnt) );
9284 ins_pipe( ialu_reg_long );
9285 %}
9286
9287 // Shift Right Long by 32-63
9288 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9289 match(Set dst (RShiftL dst cnt));
9290 effect(KILL cr);
9291 ins_cost(300);
9292 format %{ "MOV $dst.lo,$dst.hi\n"
9293 "\tSAR $dst.lo,$cnt-32\n"
9294 "\tSAR $dst.hi,31" %}
9295 opcode(0xC1, 0x7); /* C1 /7 ib */
9296 ins_encode( move_long_big_shift_sign(dst,cnt) );
9297 ins_pipe( ialu_reg_long );
9298 %}
9299
9300 // Shift Right arithmetic Long by variable
9301 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9302 match(Set dst (RShiftL dst shift));
9303 effect(KILL cr);
9304 ins_cost(600);
9305 size(18);
9306 format %{ "TEST $shift,32\n\t"
9307 "JEQ,s small\n\t"
9308 "MOV $dst.lo,$dst.hi\n\t"
9309 "SAR $dst.hi,31\n"
9310 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9311 "SAR $dst.hi,$shift" %}
9312 ins_encode( shift_right_arith_long( dst, shift ) );
9313 ins_pipe( pipe_slow );
9314 %}
9315
9316
9317 //----------Double Instructions------------------------------------------------
9318 // Double Math
9319
9320 // Compare & branch
9321
9322 // P6 version of float compare, sets condition codes in EFLAGS
9323 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9324 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9325 match(Set cr (CmpD src1 src2));
9326 effect(KILL rax);
9327 ins_cost(150);
9328 format %{ "FLD $src1\n\t"
9329 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9330 "JNP exit\n\t"
9331 "MOV ah,1 // saw a NaN, set CF\n\t"
9332 "SAHF\n"
9333 "exit:\tNOP // avoid branch to branch" %}
9334 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9335 ins_encode( Push_Reg_DPR(src1),
9336 OpcP, RegOpc(src2),
9337 cmpF_P6_fixup );
9338 ins_pipe( pipe_slow );
9339 %}
9340
9341 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9342 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9343 match(Set cr (CmpD src1 src2));
9344 ins_cost(150);
9345 format %{ "FLD $src1\n\t"
9346 "FUCOMIP ST,$src2 // P6 instruction" %}
9347 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9348 ins_encode( Push_Reg_DPR(src1),
9349 OpcP, RegOpc(src2));
9350 ins_pipe( pipe_slow );
9351 %}
9352
9353 // Compare & branch
9354 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9355 predicate(UseSSE<=1);
9356 match(Set cr (CmpD src1 src2));
9357 effect(KILL rax);
9358 ins_cost(200);
9359 format %{ "FLD $src1\n\t"
9360 "FCOMp $src2\n\t"
9361 "FNSTSW AX\n\t"
9362 "TEST AX,0x400\n\t"
9363 "JZ,s flags\n\t"
9364 "MOV AH,1\t# unordered treat as LT\n"
9365 "flags:\tSAHF" %}
9366 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9367 ins_encode( Push_Reg_DPR(src1),
9368 OpcP, RegOpc(src2),
9369 fpu_flags);
9370 ins_pipe( pipe_slow );
9371 %}
9372
9373 // Compare vs zero into -1,0,1
9374 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9375 predicate(UseSSE<=1);
9376 match(Set dst (CmpD3 src1 zero));
9377 effect(KILL cr, KILL rax);
9378 ins_cost(280);
9379 format %{ "FTSTD $dst,$src1" %}
9380 opcode(0xE4, 0xD9);
9381 ins_encode( Push_Reg_DPR(src1),
9382 OpcS, OpcP, PopFPU,
9383 CmpF_Result(dst));
9384 ins_pipe( pipe_slow );
9385 %}
9386
9387 // Compare into -1,0,1
9388 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9389 predicate(UseSSE<=1);
9390 match(Set dst (CmpD3 src1 src2));
9391 effect(KILL cr, KILL rax);
9392 ins_cost(300);
9393 format %{ "FCMPD $dst,$src1,$src2" %}
9394 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9395 ins_encode( Push_Reg_DPR(src1),
9396 OpcP, RegOpc(src2),
9397 CmpF_Result(dst));
9398 ins_pipe( pipe_slow );
9399 %}
9400
9401 // float compare and set condition codes in EFLAGS by XMM regs
9402 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9403 predicate(UseSSE>=2);
9404 match(Set cr (CmpD src1 src2));
9405 ins_cost(145);
9406 format %{ "UCOMISD $src1,$src2\n\t"
9407 "JNP,s exit\n\t"
9408 "PUSHF\t# saw NaN, set CF\n\t"
9409 "AND [rsp], #0xffffff2b\n\t"
9410 "POPF\n"
9411 "exit:" %}
9412 ins_encode %{
9413 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9414 emit_cmpfp_fixup(_masm);
9415 %}
9416 ins_pipe( pipe_slow );
9417 %}
9418
9419 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9420 predicate(UseSSE>=2);
9421 match(Set cr (CmpD src1 src2));
9422 ins_cost(100);
9423 format %{ "UCOMISD $src1,$src2" %}
9424 ins_encode %{
9425 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9426 %}
9427 ins_pipe( pipe_slow );
9428 %}
9429
9430 // float compare and set condition codes in EFLAGS by XMM regs
9431 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9432 predicate(UseSSE>=2);
9433 match(Set cr (CmpD src1 (LoadD src2)));
9434 ins_cost(145);
9435 format %{ "UCOMISD $src1,$src2\n\t"
9436 "JNP,s exit\n\t"
9437 "PUSHF\t# saw NaN, set CF\n\t"
9438 "AND [rsp], #0xffffff2b\n\t"
9439 "POPF\n"
9440 "exit:" %}
9441 ins_encode %{
9442 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9443 emit_cmpfp_fixup(_masm);
9444 %}
9445 ins_pipe( pipe_slow );
9446 %}
9447
9448 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9449 predicate(UseSSE>=2);
9450 match(Set cr (CmpD src1 (LoadD src2)));
9451 ins_cost(100);
9452 format %{ "UCOMISD $src1,$src2" %}
9453 ins_encode %{
9454 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9455 %}
9456 ins_pipe( pipe_slow );
9457 %}
9458
9459 // Compare into -1,0,1 in XMM
9460 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9461 predicate(UseSSE>=2);
9462 match(Set dst (CmpD3 src1 src2));
9463 effect(KILL cr);
9464 ins_cost(255);
9465 format %{ "UCOMISD $src1, $src2\n\t"
9466 "MOV $dst, #-1\n\t"
9467 "JP,s done\n\t"
9468 "JB,s done\n\t"
9469 "SETNE $dst\n\t"
9470 "MOVZB $dst, $dst\n"
9471 "done:" %}
9472 ins_encode %{
9473 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9474 emit_cmpfp3(_masm, $dst$$Register);
9475 %}
9476 ins_pipe( pipe_slow );
9477 %}
9478
9479 // Compare into -1,0,1 in XMM and memory
9480 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9481 predicate(UseSSE>=2);
9482 match(Set dst (CmpD3 src1 (LoadD src2)));
9483 effect(KILL cr);
9484 ins_cost(275);
9485 format %{ "UCOMISD $src1, $src2\n\t"
9486 "MOV $dst, #-1\n\t"
9487 "JP,s done\n\t"
9488 "JB,s done\n\t"
9489 "SETNE $dst\n\t"
9490 "MOVZB $dst, $dst\n"
9491 "done:" %}
9492 ins_encode %{
9493 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9494 emit_cmpfp3(_masm, $dst$$Register);
9495 %}
9496 ins_pipe( pipe_slow );
9497 %}
9498
9499
9500 instruct subDPR_reg(regDPR dst, regDPR src) %{
9501 predicate (UseSSE <=1);
9502 match(Set dst (SubD dst src));
9503
9504 format %{ "FLD $src\n\t"
9505 "DSUBp $dst,ST" %}
9506 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9507 ins_cost(150);
9508 ins_encode( Push_Reg_DPR(src),
9509 OpcP, RegOpc(dst) );
9510 ins_pipe( fpu_reg_reg );
9511 %}
9512
9513 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9514 predicate (UseSSE <=1);
9515 match(Set dst (RoundDouble (SubD src1 src2)));
9516 ins_cost(250);
9517
9518 format %{ "FLD $src2\n\t"
9519 "DSUB ST,$src1\n\t"
9520 "FSTP_D $dst\t# D-round" %}
9521 opcode(0xD8, 0x5);
9522 ins_encode( Push_Reg_DPR(src2),
9523 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9524 ins_pipe( fpu_mem_reg_reg );
9525 %}
9526
9527
9528 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9529 predicate (UseSSE <=1);
9530 match(Set dst (SubD dst (LoadD src)));
9531 ins_cost(150);
9532
9533 format %{ "FLD $src\n\t"
9534 "DSUBp $dst,ST" %}
9535 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9536 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9537 OpcP, RegOpc(dst) );
9538 ins_pipe( fpu_reg_mem );
9539 %}
9540
9541 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9542 predicate (UseSSE<=1);
9543 match(Set dst (AbsD src));
9544 ins_cost(100);
9545 format %{ "FABS" %}
9546 opcode(0xE1, 0xD9);
9547 ins_encode( OpcS, OpcP );
9548 ins_pipe( fpu_reg_reg );
9549 %}
9550
9551 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9552 predicate(UseSSE<=1);
9553 match(Set dst (NegD src));
9554 ins_cost(100);
9555 format %{ "FCHS" %}
9556 opcode(0xE0, 0xD9);
9557 ins_encode( OpcS, OpcP );
9558 ins_pipe( fpu_reg_reg );
9559 %}
9560
9561 instruct addDPR_reg(regDPR dst, regDPR src) %{
9562 predicate(UseSSE<=1);
9563 match(Set dst (AddD dst src));
9564 format %{ "FLD $src\n\t"
9565 "DADD $dst,ST" %}
9566 size(4);
9567 ins_cost(150);
9568 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9569 ins_encode( Push_Reg_DPR(src),
9570 OpcP, RegOpc(dst) );
9571 ins_pipe( fpu_reg_reg );
9572 %}
9573
9574
9575 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9576 predicate(UseSSE<=1);
9577 match(Set dst (RoundDouble (AddD src1 src2)));
9578 ins_cost(250);
9579
9580 format %{ "FLD $src2\n\t"
9581 "DADD ST,$src1\n\t"
9582 "FSTP_D $dst\t# D-round" %}
9583 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9584 ins_encode( Push_Reg_DPR(src2),
9585 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9586 ins_pipe( fpu_mem_reg_reg );
9587 %}
9588
9589
9590 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9591 predicate(UseSSE<=1);
9592 match(Set dst (AddD dst (LoadD src)));
9593 ins_cost(150);
9594
9595 format %{ "FLD $src\n\t"
9596 "DADDp $dst,ST" %}
9597 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9598 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9599 OpcP, RegOpc(dst) );
9600 ins_pipe( fpu_reg_mem );
9601 %}
9602
9603 // add-to-memory
9604 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9605 predicate(UseSSE<=1);
9606 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9607 ins_cost(150);
9608
9609 format %{ "FLD_D $dst\n\t"
9610 "DADD ST,$src\n\t"
9611 "FST_D $dst" %}
9612 opcode(0xDD, 0x0);
9613 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9614 Opcode(0xD8), RegOpc(src),
9615 set_instruction_start,
9616 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9617 ins_pipe( fpu_reg_mem );
9618 %}
9619
9620 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9621 predicate(UseSSE<=1);
9622 match(Set dst (AddD dst con));
9623 ins_cost(125);
9624 format %{ "FLD1\n\t"
9625 "DADDp $dst,ST" %}
9626 ins_encode %{
9627 __ fld1();
9628 __ faddp($dst$$reg);
9629 %}
9630 ins_pipe(fpu_reg);
9631 %}
9632
9633 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9634 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9635 match(Set dst (AddD dst con));
9636 ins_cost(200);
9637 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9638 "DADDp $dst,ST" %}
9639 ins_encode %{
9640 __ fld_d($constantaddress($con));
9641 __ faddp($dst$$reg);
9642 %}
9643 ins_pipe(fpu_reg_mem);
9644 %}
9645
9646 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9647 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9648 match(Set dst (RoundDouble (AddD src con)));
9649 ins_cost(200);
9650 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9651 "DADD ST,$src\n\t"
9652 "FSTP_D $dst\t# D-round" %}
9653 ins_encode %{
9654 __ fld_d($constantaddress($con));
9655 __ fadd($src$$reg);
9656 __ fstp_d(Address(rsp, $dst$$disp));
9657 %}
9658 ins_pipe(fpu_mem_reg_con);
9659 %}
9660
9661 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9662 predicate(UseSSE<=1);
9663 match(Set dst (MulD dst src));
9664 format %{ "FLD $src\n\t"
9665 "DMULp $dst,ST" %}
9666 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9667 ins_cost(150);
9668 ins_encode( Push_Reg_DPR(src),
9669 OpcP, RegOpc(dst) );
9670 ins_pipe( fpu_reg_reg );
9671 %}
9672
9673 // Strict FP instruction biases argument before multiply then
9674 // biases result to avoid double rounding of subnormals.
9675 //
9676 // scale arg1 by multiplying arg1 by 2^(-15360)
9677 // load arg2
9678 // multiply scaled arg1 by arg2
9679 // rescale product by 2^(15360)
9680 //
9681 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9682 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9683 match(Set dst (MulD dst src));
9684 ins_cost(1); // Select this instruction for all strict FP double multiplies
9685
9686 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9687 "DMULp $dst,ST\n\t"
9688 "FLD $src\n\t"
9689 "DMULp $dst,ST\n\t"
9690 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9691 "DMULp $dst,ST\n\t" %}
9692 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9693 ins_encode( strictfp_bias1(dst),
9694 Push_Reg_DPR(src),
9695 OpcP, RegOpc(dst),
9696 strictfp_bias2(dst) );
9697 ins_pipe( fpu_reg_reg );
9698 %}
9699
9700 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9701 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9702 match(Set dst (MulD dst con));
9703 ins_cost(200);
9704 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9705 "DMULp $dst,ST" %}
9706 ins_encode %{
9707 __ fld_d($constantaddress($con));
9708 __ fmulp($dst$$reg);
9709 %}
9710 ins_pipe(fpu_reg_mem);
9711 %}
9712
9713
9714 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9715 predicate( UseSSE<=1 );
9716 match(Set dst (MulD dst (LoadD src)));
9717 ins_cost(200);
9718 format %{ "FLD_D $src\n\t"
9719 "DMULp $dst,ST" %}
9720 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9721 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9722 OpcP, RegOpc(dst) );
9723 ins_pipe( fpu_reg_mem );
9724 %}
9725
9726 //
9727 // Cisc-alternate to reg-reg multiply
9728 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9729 predicate( UseSSE<=1 );
9730 match(Set dst (MulD src (LoadD mem)));
9731 ins_cost(250);
9732 format %{ "FLD_D $mem\n\t"
9733 "DMUL ST,$src\n\t"
9734 "FSTP_D $dst" %}
9735 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9736 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9737 OpcReg_FPR(src),
9738 Pop_Reg_DPR(dst) );
9739 ins_pipe( fpu_reg_reg_mem );
9740 %}
9741
9742
9743 // MACRO3 -- addDPR a mulDPR
9744 // This instruction is a '2-address' instruction in that the result goes
9745 // back to src2. This eliminates a move from the macro; possibly the
9746 // register allocator will have to add it back (and maybe not).
9747 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9748 predicate( UseSSE<=1 );
9749 match(Set src2 (AddD (MulD src0 src1) src2));
9750 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9751 "DMUL ST,$src1\n\t"
9752 "DADDp $src2,ST" %}
9753 ins_cost(250);
9754 opcode(0xDD); /* LoadD DD /0 */
9755 ins_encode( Push_Reg_FPR(src0),
9756 FMul_ST_reg(src1),
9757 FAddP_reg_ST(src2) );
9758 ins_pipe( fpu_reg_reg_reg );
9759 %}
9760
9761
9762 // MACRO3 -- subDPR a mulDPR
9763 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9764 predicate( UseSSE<=1 );
9765 match(Set src2 (SubD (MulD src0 src1) src2));
9766 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9767 "DMUL ST,$src1\n\t"
9768 "DSUBRp $src2,ST" %}
9769 ins_cost(250);
9770 ins_encode( Push_Reg_FPR(src0),
9771 FMul_ST_reg(src1),
9772 Opcode(0xDE), Opc_plus(0xE0,src2));
9773 ins_pipe( fpu_reg_reg_reg );
9774 %}
9775
9776
9777 instruct divDPR_reg(regDPR dst, regDPR src) %{
9778 predicate( UseSSE<=1 );
9779 match(Set dst (DivD dst src));
9780
9781 format %{ "FLD $src\n\t"
9782 "FDIVp $dst,ST" %}
9783 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9784 ins_cost(150);
9785 ins_encode( Push_Reg_DPR(src),
9786 OpcP, RegOpc(dst) );
9787 ins_pipe( fpu_reg_reg );
9788 %}
9789
9790 // Strict FP instruction biases argument before division then
9791 // biases result, to avoid double rounding of subnormals.
9792 //
9793 // scale dividend by multiplying dividend by 2^(-15360)
9794 // load divisor
9795 // divide scaled dividend by divisor
9796 // rescale quotient by 2^(15360)
9797 //
9798 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9799 predicate (UseSSE<=1);
9800 match(Set dst (DivD dst src));
9801 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9802 ins_cost(01);
9803
9804 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9805 "DMULp $dst,ST\n\t"
9806 "FLD $src\n\t"
9807 "FDIVp $dst,ST\n\t"
9808 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9809 "DMULp $dst,ST\n\t" %}
9810 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9811 ins_encode( strictfp_bias1(dst),
9812 Push_Reg_DPR(src),
9813 OpcP, RegOpc(dst),
9814 strictfp_bias2(dst) );
9815 ins_pipe( fpu_reg_reg );
9816 %}
9817
9818 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9819 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9820 match(Set dst (RoundDouble (DivD src1 src2)));
9821
9822 format %{ "FLD $src1\n\t"
9823 "FDIV ST,$src2\n\t"
9824 "FSTP_D $dst\t# D-round" %}
9825 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9826 ins_encode( Push_Reg_DPR(src1),
9827 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9828 ins_pipe( fpu_mem_reg_reg );
9829 %}
9830
9831
9832 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9833 predicate(UseSSE<=1);
9834 match(Set dst (ModD dst src));
9835 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9836
9837 format %{ "DMOD $dst,$src" %}
9838 ins_cost(250);
9839 ins_encode(Push_Reg_Mod_DPR(dst, src),
9840 emitModDPR(),
9841 Push_Result_Mod_DPR(src),
9842 Pop_Reg_DPR(dst));
9843 ins_pipe( pipe_slow );
9844 %}
9845
9846 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9847 predicate(UseSSE>=2);
9848 match(Set dst (ModD src0 src1));
9849 effect(KILL rax, KILL cr);
9850
9851 format %{ "SUB ESP,8\t # DMOD\n"
9852 "\tMOVSD [ESP+0],$src1\n"
9853 "\tFLD_D [ESP+0]\n"
9854 "\tMOVSD [ESP+0],$src0\n"
9855 "\tFLD_D [ESP+0]\n"
9856 "loop:\tFPREM\n"
9857 "\tFWAIT\n"
9858 "\tFNSTSW AX\n"
9859 "\tSAHF\n"
9860 "\tJP loop\n"
9861 "\tFSTP_D [ESP+0]\n"
9862 "\tMOVSD $dst,[ESP+0]\n"
9863 "\tADD ESP,8\n"
9864 "\tFSTP ST0\t # Restore FPU Stack"
9865 %}
9866 ins_cost(250);
9867 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9868 ins_pipe( pipe_slow );
9869 %}
9870
9871 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9872 predicate (UseSSE<=1);
9873 match(Set dst (SinD src));
9874 ins_cost(1800);
9875 format %{ "DSIN $dst" %}
9876 opcode(0xD9, 0xFE);
9877 ins_encode( OpcP, OpcS );
9878 ins_pipe( pipe_slow );
9879 %}
9880
9881 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9882 predicate (UseSSE>=2);
9883 match(Set dst (SinD dst));
9884 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9885 ins_cost(1800);
9886 format %{ "DSIN $dst" %}
9887 opcode(0xD9, 0xFE);
9888 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9889 ins_pipe( pipe_slow );
9890 %}
9891
9892 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9893 predicate (UseSSE<=1);
9894 match(Set dst (CosD src));
9895 ins_cost(1800);
9896 format %{ "DCOS $dst" %}
9897 opcode(0xD9, 0xFF);
9898 ins_encode( OpcP, OpcS );
9899 ins_pipe( pipe_slow );
9900 %}
9901
9902 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9903 predicate (UseSSE>=2);
9904 match(Set dst (CosD dst));
9905 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9906 ins_cost(1800);
9907 format %{ "DCOS $dst" %}
9908 opcode(0xD9, 0xFF);
9909 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9910 ins_pipe( pipe_slow );
9911 %}
9912
9913 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9914 predicate (UseSSE<=1);
9915 match(Set dst(TanD src));
9916 format %{ "DTAN $dst" %}
9917 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9918 Opcode(0xDD), Opcode(0xD8)); // fstp st
9919 ins_pipe( pipe_slow );
9920 %}
9921
9922 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9923 predicate (UseSSE>=2);
9924 match(Set dst(TanD dst));
9925 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9926 format %{ "DTAN $dst" %}
9927 ins_encode( Push_SrcD(dst),
9928 Opcode(0xD9), Opcode(0xF2), // fptan
9929 Opcode(0xDD), Opcode(0xD8), // fstp st
9930 Push_ResultD(dst) );
9931 ins_pipe( pipe_slow );
9932 %}
9933
9934 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9935 predicate (UseSSE<=1);
9936 match(Set dst(AtanD dst src));
9937 format %{ "DATA $dst,$src" %}
9938 opcode(0xD9, 0xF3);
9939 ins_encode( Push_Reg_DPR(src),
9940 OpcP, OpcS, RegOpc(dst) );
9941 ins_pipe( pipe_slow );
9942 %}
9943
9944 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9945 predicate (UseSSE>=2);
9946 match(Set dst(AtanD dst src));
9947 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9948 format %{ "DATA $dst,$src" %}
9949 opcode(0xD9, 0xF3);
9950 ins_encode( Push_SrcD(src),
9951 OpcP, OpcS, Push_ResultD(dst) );
9952 ins_pipe( pipe_slow );
9953 %}
9954
9955 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9956 predicate (UseSSE<=1);
9957 match(Set dst (SqrtD src));
9958 format %{ "DSQRT $dst,$src" %}
9959 opcode(0xFA, 0xD9);
9960 ins_encode( Push_Reg_DPR(src),
9961 OpcS, OpcP, Pop_Reg_DPR(dst) );
9962 ins_pipe( pipe_slow );
9963 %}
9964
9965 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9966 predicate (UseSSE<=1);
9967 match(Set Y (PowD X Y)); // Raise X to the Yth power
9968 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9969 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
9970 ins_encode %{
9971 __ subptr(rsp, 8);
9972 __ fld_s($X$$reg - 1);
9973 __ fast_pow();
9974 __ addptr(rsp, 8);
9975 %}
9976 ins_pipe( pipe_slow );
9977 %}
9978
9979 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9980 predicate (UseSSE>=2);
9981 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9982 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9983 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9984 ins_encode %{
9985 __ subptr(rsp, 8);
9986 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9987 __ fld_d(Address(rsp, 0));
9988 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9989 __ fld_d(Address(rsp, 0));
9990 __ fast_pow();
9991 __ fstp_d(Address(rsp, 0));
9992 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9993 __ addptr(rsp, 8);
9994 %}
9995 ins_pipe( pipe_slow );
9996 %}
9997
9998
9999 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10000 predicate (UseSSE<=1);
10001 match(Set dpr1 (ExpD dpr1));
10002 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10003 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10004 ins_encode %{
10005 __ fast_exp();
10006 %}
10007 ins_pipe( pipe_slow );
10008 %}
10009
10010 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10011 predicate (UseSSE>=2);
10012 match(Set dst (ExpD src));
10013 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10014 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10015 ins_encode %{
10016 __ subptr(rsp, 8);
10017 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10018 __ fld_d(Address(rsp, 0));
10019 __ fast_exp();
10020 __ fstp_d(Address(rsp, 0));
10021 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10022 __ addptr(rsp, 8);
10023 %}
10024 ins_pipe( pipe_slow );
10025 %}
10026
10027 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10028 predicate (UseSSE<=1);
10029 // The source Double operand on FPU stack
10030 match(Set dst (Log10D src));
10031 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10032 // fxch ; swap ST(0) with ST(1)
10033 // fyl2x ; compute log_10(2) * log_2(x)
10034 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10035 "FXCH \n\t"
10036 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10037 %}
10038 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10039 Opcode(0xD9), Opcode(0xC9), // fxch
10040 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10041
10042 ins_pipe( pipe_slow );
10043 %}
10044
10045 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10046 predicate (UseSSE>=2);
10047 effect(KILL cr);
10048 match(Set dst (Log10D src));
10049 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10050 // fyl2x ; compute log_10(2) * log_2(x)
10051 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10052 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10053 %}
10054 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10055 Push_SrcD(src),
10056 Opcode(0xD9), Opcode(0xF1), // fyl2x
10057 Push_ResultD(dst));
10058
10059 ins_pipe( pipe_slow );
10060 %}
10061
10062 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10063 predicate (UseSSE<=1);
10064 // The source Double operand on FPU stack
10065 match(Set dst (LogD src));
10066 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10067 // fxch ; swap ST(0) with ST(1)
10068 // fyl2x ; compute log_e(2) * log_2(x)
10069 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10070 "FXCH \n\t"
10071 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10072 %}
10073 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10074 Opcode(0xD9), Opcode(0xC9), // fxch
10075 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10076
10077 ins_pipe( pipe_slow );
10078 %}
10079
10080 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10081 predicate (UseSSE>=2);
10082 effect(KILL cr);
10083 // The source and result Double operands in XMM registers
10084 match(Set dst (LogD src));
10085 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10086 // fyl2x ; compute log_e(2) * log_2(x)
10087 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10088 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10089 %}
10090 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10091 Push_SrcD(src),
10092 Opcode(0xD9), Opcode(0xF1), // fyl2x
10093 Push_ResultD(dst));
10094 ins_pipe( pipe_slow );
10095 %}
10096
10097 //-------------Float Instructions-------------------------------
10098 // Float Math
10099
10100 // Code for float compare:
10101 // fcompp();
10102 // fwait(); fnstsw_ax();
10103 // sahf();
10104 // movl(dst, unordered_result);
10105 // jcc(Assembler::parity, exit);
10106 // movl(dst, less_result);
10107 // jcc(Assembler::below, exit);
10108 // movl(dst, equal_result);
10109 // jcc(Assembler::equal, exit);
10110 // movl(dst, greater_result);
10111 // exit:
10112
10113 // P6 version of float compare, sets condition codes in EFLAGS
10114 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10115 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10116 match(Set cr (CmpF src1 src2));
10117 effect(KILL rax);
10118 ins_cost(150);
10119 format %{ "FLD $src1\n\t"
10120 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10121 "JNP exit\n\t"
10122 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10123 "SAHF\n"
10124 "exit:\tNOP // avoid branch to branch" %}
10125 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10126 ins_encode( Push_Reg_DPR(src1),
10127 OpcP, RegOpc(src2),
10128 cmpF_P6_fixup );
10129 ins_pipe( pipe_slow );
10130 %}
10131
10132 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10133 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10134 match(Set cr (CmpF src1 src2));
10135 ins_cost(100);
10136 format %{ "FLD $src1\n\t"
10137 "FUCOMIP ST,$src2 // P6 instruction" %}
10138 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10139 ins_encode( Push_Reg_DPR(src1),
10140 OpcP, RegOpc(src2));
10141 ins_pipe( pipe_slow );
10142 %}
10143
10144
10145 // Compare & branch
10146 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10147 predicate(UseSSE == 0);
10148 match(Set cr (CmpF src1 src2));
10149 effect(KILL rax);
10150 ins_cost(200);
10151 format %{ "FLD $src1\n\t"
10152 "FCOMp $src2\n\t"
10153 "FNSTSW AX\n\t"
10154 "TEST AX,0x400\n\t"
10155 "JZ,s flags\n\t"
10156 "MOV AH,1\t# unordered treat as LT\n"
10157 "flags:\tSAHF" %}
10158 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10159 ins_encode( Push_Reg_DPR(src1),
10160 OpcP, RegOpc(src2),
10161 fpu_flags);
10162 ins_pipe( pipe_slow );
10163 %}
10164
10165 // Compare vs zero into -1,0,1
10166 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10167 predicate(UseSSE == 0);
10168 match(Set dst (CmpF3 src1 zero));
10169 effect(KILL cr, KILL rax);
10170 ins_cost(280);
10171 format %{ "FTSTF $dst,$src1" %}
10172 opcode(0xE4, 0xD9);
10173 ins_encode( Push_Reg_DPR(src1),
10174 OpcS, OpcP, PopFPU,
10175 CmpF_Result(dst));
10176 ins_pipe( pipe_slow );
10177 %}
10178
10179 // Compare into -1,0,1
10180 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10181 predicate(UseSSE == 0);
10182 match(Set dst (CmpF3 src1 src2));
10183 effect(KILL cr, KILL rax);
10184 ins_cost(300);
10185 format %{ "FCMPF $dst,$src1,$src2" %}
10186 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10187 ins_encode( Push_Reg_DPR(src1),
10188 OpcP, RegOpc(src2),
10189 CmpF_Result(dst));
10190 ins_pipe( pipe_slow );
10191 %}
10192
10193 // float compare and set condition codes in EFLAGS by XMM regs
10194 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10195 predicate(UseSSE>=1);
10196 match(Set cr (CmpF src1 src2));
10197 ins_cost(145);
10198 format %{ "UCOMISS $src1,$src2\n\t"
10199 "JNP,s exit\n\t"
10200 "PUSHF\t# saw NaN, set CF\n\t"
10201 "AND [rsp], #0xffffff2b\n\t"
10202 "POPF\n"
10203 "exit:" %}
10204 ins_encode %{
10205 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10206 emit_cmpfp_fixup(_masm);
10207 %}
10208 ins_pipe( pipe_slow );
10209 %}
10210
10211 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10212 predicate(UseSSE>=1);
10213 match(Set cr (CmpF src1 src2));
10214 ins_cost(100);
10215 format %{ "UCOMISS $src1,$src2" %}
10216 ins_encode %{
10217 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10218 %}
10219 ins_pipe( pipe_slow );
10220 %}
10221
10222 // float compare and set condition codes in EFLAGS by XMM regs
10223 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10224 predicate(UseSSE>=1);
10225 match(Set cr (CmpF src1 (LoadF src2)));
10226 ins_cost(165);
10227 format %{ "UCOMISS $src1,$src2\n\t"
10228 "JNP,s exit\n\t"
10229 "PUSHF\t# saw NaN, set CF\n\t"
10230 "AND [rsp], #0xffffff2b\n\t"
10231 "POPF\n"
10232 "exit:" %}
10233 ins_encode %{
10234 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10235 emit_cmpfp_fixup(_masm);
10236 %}
10237 ins_pipe( pipe_slow );
10238 %}
10239
10240 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10241 predicate(UseSSE>=1);
10242 match(Set cr (CmpF src1 (LoadF src2)));
10243 ins_cost(100);
10244 format %{ "UCOMISS $src1,$src2" %}
10245 ins_encode %{
10246 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10247 %}
10248 ins_pipe( pipe_slow );
10249 %}
10250
10251 // Compare into -1,0,1 in XMM
10252 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10253 predicate(UseSSE>=1);
10254 match(Set dst (CmpF3 src1 src2));
10255 effect(KILL cr);
10256 ins_cost(255);
10257 format %{ "UCOMISS $src1, $src2\n\t"
10258 "MOV $dst, #-1\n\t"
10259 "JP,s done\n\t"
10260 "JB,s done\n\t"
10261 "SETNE $dst\n\t"
10262 "MOVZB $dst, $dst\n"
10263 "done:" %}
10264 ins_encode %{
10265 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10266 emit_cmpfp3(_masm, $dst$$Register);
10267 %}
10268 ins_pipe( pipe_slow );
10269 %}
10270
10271 // Compare into -1,0,1 in XMM and memory
10272 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10273 predicate(UseSSE>=1);
10274 match(Set dst (CmpF3 src1 (LoadF src2)));
10275 effect(KILL cr);
10276 ins_cost(275);
10277 format %{ "UCOMISS $src1, $src2\n\t"
10278 "MOV $dst, #-1\n\t"
10279 "JP,s done\n\t"
10280 "JB,s done\n\t"
10281 "SETNE $dst\n\t"
10282 "MOVZB $dst, $dst\n"
10283 "done:" %}
10284 ins_encode %{
10285 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10286 emit_cmpfp3(_masm, $dst$$Register);
10287 %}
10288 ins_pipe( pipe_slow );
10289 %}
10290
10291 // Spill to obtain 24-bit precision
10292 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10293 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10294 match(Set dst (SubF src1 src2));
10295
10296 format %{ "FSUB $dst,$src1 - $src2" %}
10297 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10298 ins_encode( Push_Reg_FPR(src1),
10299 OpcReg_FPR(src2),
10300 Pop_Mem_FPR(dst) );
10301 ins_pipe( fpu_mem_reg_reg );
10302 %}
10303 //
10304 // This instruction does not round to 24-bits
10305 instruct subFPR_reg(regFPR dst, regFPR src) %{
10306 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10307 match(Set dst (SubF dst src));
10308
10309 format %{ "FSUB $dst,$src" %}
10310 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10311 ins_encode( Push_Reg_FPR(src),
10312 OpcP, RegOpc(dst) );
10313 ins_pipe( fpu_reg_reg );
10314 %}
10315
10316 // Spill to obtain 24-bit precision
10317 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10318 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10319 match(Set dst (AddF src1 src2));
10320
10321 format %{ "FADD $dst,$src1,$src2" %}
10322 opcode(0xD8, 0x0); /* D8 C0+i */
10323 ins_encode( Push_Reg_FPR(src2),
10324 OpcReg_FPR(src1),
10325 Pop_Mem_FPR(dst) );
10326 ins_pipe( fpu_mem_reg_reg );
10327 %}
10328 //
10329 // This instruction does not round to 24-bits
10330 instruct addFPR_reg(regFPR dst, regFPR src) %{
10331 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10332 match(Set dst (AddF dst src));
10333
10334 format %{ "FLD $src\n\t"
10335 "FADDp $dst,ST" %}
10336 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10337 ins_encode( Push_Reg_FPR(src),
10338 OpcP, RegOpc(dst) );
10339 ins_pipe( fpu_reg_reg );
10340 %}
10341
10342 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10343 predicate(UseSSE==0);
10344 match(Set dst (AbsF src));
10345 ins_cost(100);
10346 format %{ "FABS" %}
10347 opcode(0xE1, 0xD9);
10348 ins_encode( OpcS, OpcP );
10349 ins_pipe( fpu_reg_reg );
10350 %}
10351
10352 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10353 predicate(UseSSE==0);
10354 match(Set dst (NegF src));
10355 ins_cost(100);
10356 format %{ "FCHS" %}
10357 opcode(0xE0, 0xD9);
10358 ins_encode( OpcS, OpcP );
10359 ins_pipe( fpu_reg_reg );
10360 %}
10361
10362 // Cisc-alternate to addFPR_reg
10363 // Spill to obtain 24-bit precision
10364 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10365 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10366 match(Set dst (AddF src1 (LoadF src2)));
10367
10368 format %{ "FLD $src2\n\t"
10369 "FADD ST,$src1\n\t"
10370 "FSTP_S $dst" %}
10371 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10372 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10373 OpcReg_FPR(src1),
10374 Pop_Mem_FPR(dst) );
10375 ins_pipe( fpu_mem_reg_mem );
10376 %}
10377 //
10378 // Cisc-alternate to addFPR_reg
10379 // This instruction does not round to 24-bits
10380 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10381 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10382 match(Set dst (AddF dst (LoadF src)));
10383
10384 format %{ "FADD $dst,$src" %}
10385 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10386 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10387 OpcP, RegOpc(dst) );
10388 ins_pipe( fpu_reg_mem );
10389 %}
10390
10391 // // Following two instructions for _222_mpegaudio
10392 // Spill to obtain 24-bit precision
10393 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10394 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10395 match(Set dst (AddF src1 src2));
10396
10397 format %{ "FADD $dst,$src1,$src2" %}
10398 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10399 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10400 OpcReg_FPR(src2),
10401 Pop_Mem_FPR(dst) );
10402 ins_pipe( fpu_mem_reg_mem );
10403 %}
10404
10405 // Cisc-spill variant
10406 // Spill to obtain 24-bit precision
10407 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10408 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10409 match(Set dst (AddF src1 (LoadF src2)));
10410
10411 format %{ "FADD $dst,$src1,$src2 cisc" %}
10412 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10413 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10414 set_instruction_start,
10415 OpcP, RMopc_Mem(secondary,src1),
10416 Pop_Mem_FPR(dst) );
10417 ins_pipe( fpu_mem_mem_mem );
10418 %}
10419
10420 // Spill to obtain 24-bit precision
10421 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10422 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10423 match(Set dst (AddF src1 src2));
10424
10425 format %{ "FADD $dst,$src1,$src2" %}
10426 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10427 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10428 set_instruction_start,
10429 OpcP, RMopc_Mem(secondary,src1),
10430 Pop_Mem_FPR(dst) );
10431 ins_pipe( fpu_mem_mem_mem );
10432 %}
10433
10434
10435 // Spill to obtain 24-bit precision
10436 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10437 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10438 match(Set dst (AddF src con));
10439 format %{ "FLD $src\n\t"
10440 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10441 "FSTP_S $dst" %}
10442 ins_encode %{
10443 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10444 __ fadd_s($constantaddress($con));
10445 __ fstp_s(Address(rsp, $dst$$disp));
10446 %}
10447 ins_pipe(fpu_mem_reg_con);
10448 %}
10449 //
10450 // This instruction does not round to 24-bits
10451 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10452 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10453 match(Set dst (AddF src con));
10454 format %{ "FLD $src\n\t"
10455 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10456 "FSTP $dst" %}
10457 ins_encode %{
10458 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10459 __ fadd_s($constantaddress($con));
10460 __ fstp_d($dst$$reg);
10461 %}
10462 ins_pipe(fpu_reg_reg_con);
10463 %}
10464
10465 // Spill to obtain 24-bit precision
10466 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10467 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10468 match(Set dst (MulF src1 src2));
10469
10470 format %{ "FLD $src1\n\t"
10471 "FMUL $src2\n\t"
10472 "FSTP_S $dst" %}
10473 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10474 ins_encode( Push_Reg_FPR(src1),
10475 OpcReg_FPR(src2),
10476 Pop_Mem_FPR(dst) );
10477 ins_pipe( fpu_mem_reg_reg );
10478 %}
10479 //
10480 // This instruction does not round to 24-bits
10481 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10482 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10483 match(Set dst (MulF src1 src2));
10484
10485 format %{ "FLD $src1\n\t"
10486 "FMUL $src2\n\t"
10487 "FSTP_S $dst" %}
10488 opcode(0xD8, 0x1); /* D8 C8+i */
10489 ins_encode( Push_Reg_FPR(src2),
10490 OpcReg_FPR(src1),
10491 Pop_Reg_FPR(dst) );
10492 ins_pipe( fpu_reg_reg_reg );
10493 %}
10494
10495
10496 // Spill to obtain 24-bit precision
10497 // Cisc-alternate to reg-reg multiply
10498 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10499 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10500 match(Set dst (MulF src1 (LoadF src2)));
10501
10502 format %{ "FLD_S $src2\n\t"
10503 "FMUL $src1\n\t"
10504 "FSTP_S $dst" %}
10505 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10506 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10507 OpcReg_FPR(src1),
10508 Pop_Mem_FPR(dst) );
10509 ins_pipe( fpu_mem_reg_mem );
10510 %}
10511 //
10512 // This instruction does not round to 24-bits
10513 // Cisc-alternate to reg-reg multiply
10514 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10515 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10516 match(Set dst (MulF src1 (LoadF src2)));
10517
10518 format %{ "FMUL $dst,$src1,$src2" %}
10519 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10520 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10521 OpcReg_FPR(src1),
10522 Pop_Reg_FPR(dst) );
10523 ins_pipe( fpu_reg_reg_mem );
10524 %}
10525
10526 // Spill to obtain 24-bit precision
10527 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10528 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10529 match(Set dst (MulF src1 src2));
10530
10531 format %{ "FMUL $dst,$src1,$src2" %}
10532 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10533 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10534 set_instruction_start,
10535 OpcP, RMopc_Mem(secondary,src1),
10536 Pop_Mem_FPR(dst) );
10537 ins_pipe( fpu_mem_mem_mem );
10538 %}
10539
10540 // Spill to obtain 24-bit precision
10541 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10542 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10543 match(Set dst (MulF src con));
10544
10545 format %{ "FLD $src\n\t"
10546 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10547 "FSTP_S $dst" %}
10548 ins_encode %{
10549 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10550 __ fmul_s($constantaddress($con));
10551 __ fstp_s(Address(rsp, $dst$$disp));
10552 %}
10553 ins_pipe(fpu_mem_reg_con);
10554 %}
10555 //
10556 // This instruction does not round to 24-bits
10557 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10558 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10559 match(Set dst (MulF src con));
10560
10561 format %{ "FLD $src\n\t"
10562 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10563 "FSTP $dst" %}
10564 ins_encode %{
10565 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10566 __ fmul_s($constantaddress($con));
10567 __ fstp_d($dst$$reg);
10568 %}
10569 ins_pipe(fpu_reg_reg_con);
10570 %}
10571
10572
10573 //
10574 // MACRO1 -- subsume unshared load into mulFPR
10575 // This instruction does not round to 24-bits
10576 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10577 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10578 match(Set dst (MulF (LoadF mem1) src));
10579
10580 format %{ "FLD $mem1 ===MACRO1===\n\t"
10581 "FMUL ST,$src\n\t"
10582 "FSTP $dst" %}
10583 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10584 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10585 OpcReg_FPR(src),
10586 Pop_Reg_FPR(dst) );
10587 ins_pipe( fpu_reg_reg_mem );
10588 %}
10589 //
10590 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10591 // This instruction does not round to 24-bits
10592 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10593 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10594 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10595 ins_cost(95);
10596
10597 format %{ "FLD $mem1 ===MACRO2===\n\t"
10598 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10599 "FADD ST,$src2\n\t"
10600 "FSTP $dst" %}
10601 opcode(0xD9); /* LoadF D9 /0 */
10602 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10603 FMul_ST_reg(src1),
10604 FAdd_ST_reg(src2),
10605 Pop_Reg_FPR(dst) );
10606 ins_pipe( fpu_reg_mem_reg_reg );
10607 %}
10608
10609 // MACRO3 -- addFPR a mulFPR
10610 // This instruction does not round to 24-bits. It is a '2-address'
10611 // instruction in that the result goes back to src2. This eliminates
10612 // a move from the macro; possibly the register allocator will have
10613 // to add it back (and maybe not).
10614 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10615 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10616 match(Set src2 (AddF (MulF src0 src1) src2));
10617
10618 format %{ "FLD $src0 ===MACRO3===\n\t"
10619 "FMUL ST,$src1\n\t"
10620 "FADDP $src2,ST" %}
10621 opcode(0xD9); /* LoadF D9 /0 */
10622 ins_encode( Push_Reg_FPR(src0),
10623 FMul_ST_reg(src1),
10624 FAddP_reg_ST(src2) );
10625 ins_pipe( fpu_reg_reg_reg );
10626 %}
10627
10628 // MACRO4 -- divFPR subFPR
10629 // This instruction does not round to 24-bits
10630 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10631 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10632 match(Set dst (DivF (SubF src2 src1) src3));
10633
10634 format %{ "FLD $src2 ===MACRO4===\n\t"
10635 "FSUB ST,$src1\n\t"
10636 "FDIV ST,$src3\n\t"
10637 "FSTP $dst" %}
10638 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10639 ins_encode( Push_Reg_FPR(src2),
10640 subFPR_divFPR_encode(src1,src3),
10641 Pop_Reg_FPR(dst) );
10642 ins_pipe( fpu_reg_reg_reg_reg );
10643 %}
10644
10645 // Spill to obtain 24-bit precision
10646 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10647 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10648 match(Set dst (DivF src1 src2));
10649
10650 format %{ "FDIV $dst,$src1,$src2" %}
10651 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10652 ins_encode( Push_Reg_FPR(src1),
10653 OpcReg_FPR(src2),
10654 Pop_Mem_FPR(dst) );
10655 ins_pipe( fpu_mem_reg_reg );
10656 %}
10657 //
10658 // This instruction does not round to 24-bits
10659 instruct divFPR_reg(regFPR dst, regFPR src) %{
10660 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10661 match(Set dst (DivF dst src));
10662
10663 format %{ "FDIV $dst,$src" %}
10664 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10665 ins_encode( Push_Reg_FPR(src),
10666 OpcP, RegOpc(dst) );
10667 ins_pipe( fpu_reg_reg );
10668 %}
10669
10670
10671 // Spill to obtain 24-bit precision
10672 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10673 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10674 match(Set dst (ModF src1 src2));
10675 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10676
10677 format %{ "FMOD $dst,$src1,$src2" %}
10678 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10679 emitModDPR(),
10680 Push_Result_Mod_DPR(src2),
10681 Pop_Mem_FPR(dst));
10682 ins_pipe( pipe_slow );
10683 %}
10684 //
10685 // This instruction does not round to 24-bits
10686 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10687 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10688 match(Set dst (ModF dst src));
10689 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10690
10691 format %{ "FMOD $dst,$src" %}
10692 ins_encode(Push_Reg_Mod_DPR(dst, src),
10693 emitModDPR(),
10694 Push_Result_Mod_DPR(src),
10695 Pop_Reg_FPR(dst));
10696 ins_pipe( pipe_slow );
10697 %}
10698
10699 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10700 predicate(UseSSE>=1);
10701 match(Set dst (ModF src0 src1));
10702 effect(KILL rax, KILL cr);
10703 format %{ "SUB ESP,4\t # FMOD\n"
10704 "\tMOVSS [ESP+0],$src1\n"
10705 "\tFLD_S [ESP+0]\n"
10706 "\tMOVSS [ESP+0],$src0\n"
10707 "\tFLD_S [ESP+0]\n"
10708 "loop:\tFPREM\n"
10709 "\tFWAIT\n"
10710 "\tFNSTSW AX\n"
10711 "\tSAHF\n"
10712 "\tJP loop\n"
10713 "\tFSTP_S [ESP+0]\n"
10714 "\tMOVSS $dst,[ESP+0]\n"
10715 "\tADD ESP,4\n"
10716 "\tFSTP ST0\t # Restore FPU Stack"
10717 %}
10718 ins_cost(250);
10719 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10720 ins_pipe( pipe_slow );
10721 %}
10722
10723
10724 //----------Arithmetic Conversion Instructions---------------------------------
10725 // The conversions operations are all Alpha sorted. Please keep it that way!
10726
10727 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10728 predicate(UseSSE==0);
10729 match(Set dst (RoundFloat src));
10730 ins_cost(125);
10731 format %{ "FST_S $dst,$src\t# F-round" %}
10732 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10733 ins_pipe( fpu_mem_reg );
10734 %}
10735
10736 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10737 predicate(UseSSE<=1);
10738 match(Set dst (RoundDouble src));
10739 ins_cost(125);
10740 format %{ "FST_D $dst,$src\t# D-round" %}
10741 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10742 ins_pipe( fpu_mem_reg );
10743 %}
10744
10745 // Force rounding to 24-bit precision and 6-bit exponent
10746 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10747 predicate(UseSSE==0);
10748 match(Set dst (ConvD2F src));
10749 format %{ "FST_S $dst,$src\t# F-round" %}
10750 expand %{
10751 roundFloat_mem_reg(dst,src);
10752 %}
10753 %}
10754
10755 // Force rounding to 24-bit precision and 6-bit exponent
10756 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10757 predicate(UseSSE==1);
10758 match(Set dst (ConvD2F src));
10759 effect( KILL cr );
10760 format %{ "SUB ESP,4\n\t"
10761 "FST_S [ESP],$src\t# F-round\n\t"
10762 "MOVSS $dst,[ESP]\n\t"
10763 "ADD ESP,4" %}
10764 ins_encode %{
10765 __ subptr(rsp, 4);
10766 if ($src$$reg != FPR1L_enc) {
10767 __ fld_s($src$$reg-1);
10768 __ fstp_s(Address(rsp, 0));
10769 } else {
10770 __ fst_s(Address(rsp, 0));
10771 }
10772 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10773 __ addptr(rsp, 4);
10774 %}
10775 ins_pipe( pipe_slow );
10776 %}
10777
10778 // Force rounding double precision to single precision
10779 instruct convD2F_reg(regF dst, regD src) %{
10780 predicate(UseSSE>=2);
10781 match(Set dst (ConvD2F src));
10782 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10783 ins_encode %{
10784 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10785 %}
10786 ins_pipe( pipe_slow );
10787 %}
10788
10789 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10790 predicate(UseSSE==0);
10791 match(Set dst (ConvF2D src));
10792 format %{ "FST_S $dst,$src\t# D-round" %}
10793 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10794 ins_pipe( fpu_reg_reg );
10795 %}
10796
10797 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10798 predicate(UseSSE==1);
10799 match(Set dst (ConvF2D src));
10800 format %{ "FST_D $dst,$src\t# D-round" %}
10801 expand %{
10802 roundDouble_mem_reg(dst,src);
10803 %}
10804 %}
10805
10806 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10807 predicate(UseSSE==1);
10808 match(Set dst (ConvF2D src));
10809 effect( KILL cr );
10810 format %{ "SUB ESP,4\n\t"
10811 "MOVSS [ESP] $src\n\t"
10812 "FLD_S [ESP]\n\t"
10813 "ADD ESP,4\n\t"
10814 "FSTP $dst\t# D-round" %}
10815 ins_encode %{
10816 __ subptr(rsp, 4);
10817 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10818 __ fld_s(Address(rsp, 0));
10819 __ addptr(rsp, 4);
10820 __ fstp_d($dst$$reg);
10821 %}
10822 ins_pipe( pipe_slow );
10823 %}
10824
10825 instruct convF2D_reg(regD dst, regF src) %{
10826 predicate(UseSSE>=2);
10827 match(Set dst (ConvF2D src));
10828 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10829 ins_encode %{
10830 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10831 %}
10832 ins_pipe( pipe_slow );
10833 %}
10834
10835 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10836 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10837 predicate(UseSSE<=1);
10838 match(Set dst (ConvD2I src));
10839 effect( KILL tmp, KILL cr );
10840 format %{ "FLD $src\t# Convert double to int \n\t"
10841 "FLDCW trunc mode\n\t"
10842 "SUB ESP,4\n\t"
10843 "FISTp [ESP + #0]\n\t"
10844 "FLDCW std/24-bit mode\n\t"
10845 "POP EAX\n\t"
10846 "CMP EAX,0x80000000\n\t"
10847 "JNE,s fast\n\t"
10848 "FLD_D $src\n\t"
10849 "CALL d2i_wrapper\n"
10850 "fast:" %}
10851 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10852 ins_pipe( pipe_slow );
10853 %}
10854
10855 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10856 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10857 predicate(UseSSE>=2);
10858 match(Set dst (ConvD2I src));
10859 effect( KILL tmp, KILL cr );
10860 format %{ "CVTTSD2SI $dst, $src\n\t"
10861 "CMP $dst,0x80000000\n\t"
10862 "JNE,s fast\n\t"
10863 "SUB ESP, 8\n\t"
10864 "MOVSD [ESP], $src\n\t"
10865 "FLD_D [ESP]\n\t"
10866 "ADD ESP, 8\n\t"
10867 "CALL d2i_wrapper\n"
10868 "fast:" %}
10869 ins_encode %{
10870 Label fast;
10871 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10872 __ cmpl($dst$$Register, 0x80000000);
10873 __ jccb(Assembler::notEqual, fast);
10874 __ subptr(rsp, 8);
10875 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10876 __ fld_d(Address(rsp, 0));
10877 __ addptr(rsp, 8);
10878 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10879 __ bind(fast);
10880 %}
10881 ins_pipe( pipe_slow );
10882 %}
10883
10884 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10885 predicate(UseSSE<=1);
10886 match(Set dst (ConvD2L src));
10887 effect( KILL cr );
10888 format %{ "FLD $src\t# Convert double to long\n\t"
10889 "FLDCW trunc mode\n\t"
10890 "SUB ESP,8\n\t"
10891 "FISTp [ESP + #0]\n\t"
10892 "FLDCW std/24-bit mode\n\t"
10893 "POP EAX\n\t"
10894 "POP EDX\n\t"
10895 "CMP EDX,0x80000000\n\t"
10896 "JNE,s fast\n\t"
10897 "TEST EAX,EAX\n\t"
10898 "JNE,s fast\n\t"
10899 "FLD $src\n\t"
10900 "CALL d2l_wrapper\n"
10901 "fast:" %}
10902 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10903 ins_pipe( pipe_slow );
10904 %}
10905
10906 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10907 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10908 predicate (UseSSE>=2);
10909 match(Set dst (ConvD2L src));
10910 effect( KILL cr );
10911 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10912 "MOVSD [ESP],$src\n\t"
10913 "FLD_D [ESP]\n\t"
10914 "FLDCW trunc mode\n\t"
10915 "FISTp [ESP + #0]\n\t"
10916 "FLDCW std/24-bit mode\n\t"
10917 "POP EAX\n\t"
10918 "POP EDX\n\t"
10919 "CMP EDX,0x80000000\n\t"
10920 "JNE,s fast\n\t"
10921 "TEST EAX,EAX\n\t"
10922 "JNE,s fast\n\t"
10923 "SUB ESP,8\n\t"
10924 "MOVSD [ESP],$src\n\t"
10925 "FLD_D [ESP]\n\t"
10926 "ADD ESP,8\n\t"
10927 "CALL d2l_wrapper\n"
10928 "fast:" %}
10929 ins_encode %{
10930 Label fast;
10931 __ subptr(rsp, 8);
10932 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10933 __ fld_d(Address(rsp, 0));
10934 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10935 __ fistp_d(Address(rsp, 0));
10936 // Restore the rounding mode, mask the exception
10937 if (Compile::current()->in_24_bit_fp_mode()) {
10938 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10939 } else {
10940 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10941 }
10942 // Load the converted long, adjust CPU stack
10943 __ pop(rax);
10944 __ pop(rdx);
10945 __ cmpl(rdx, 0x80000000);
10946 __ jccb(Assembler::notEqual, fast);
10947 __ testl(rax, rax);
10948 __ jccb(Assembler::notEqual, fast);
10949 __ subptr(rsp, 8);
10950 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10951 __ fld_d(Address(rsp, 0));
10952 __ addptr(rsp, 8);
10953 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10954 __ bind(fast);
10955 %}
10956 ins_pipe( pipe_slow );
10957 %}
10958
10959 // Convert a double to an int. Java semantics require we do complex
10960 // manglations in the corner cases. So we set the rounding mode to
10961 // 'zero', store the darned double down as an int, and reset the
10962 // rounding mode to 'nearest'. The hardware stores a flag value down
10963 // if we would overflow or converted a NAN; we check for this and
10964 // and go the slow path if needed.
10965 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
10966 predicate(UseSSE==0);
10967 match(Set dst (ConvF2I src));
10968 effect( KILL tmp, KILL cr );
10969 format %{ "FLD $src\t# Convert float to int \n\t"
10970 "FLDCW trunc mode\n\t"
10971 "SUB ESP,4\n\t"
10972 "FISTp [ESP + #0]\n\t"
10973 "FLDCW std/24-bit mode\n\t"
10974 "POP EAX\n\t"
10975 "CMP EAX,0x80000000\n\t"
10976 "JNE,s fast\n\t"
10977 "FLD $src\n\t"
10978 "CALL d2i_wrapper\n"
10979 "fast:" %}
10980 // DPR2I_encoding works for FPR2I
10981 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
10982 ins_pipe( pipe_slow );
10983 %}
10984
10985 // Convert a float in xmm to an int reg.
10986 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
10987 predicate(UseSSE>=1);
10988 match(Set dst (ConvF2I src));
10989 effect( KILL tmp, KILL cr );
10990 format %{ "CVTTSS2SI $dst, $src\n\t"
10991 "CMP $dst,0x80000000\n\t"
10992 "JNE,s fast\n\t"
10993 "SUB ESP, 4\n\t"
10994 "MOVSS [ESP], $src\n\t"
10995 "FLD [ESP]\n\t"
10996 "ADD ESP, 4\n\t"
10997 "CALL d2i_wrapper\n"
10998 "fast:" %}
10999 ins_encode %{
11000 Label fast;
11001 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11002 __ cmpl($dst$$Register, 0x80000000);
11003 __ jccb(Assembler::notEqual, fast);
11004 __ subptr(rsp, 4);
11005 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11006 __ fld_s(Address(rsp, 0));
11007 __ addptr(rsp, 4);
11008 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11009 __ bind(fast);
11010 %}
11011 ins_pipe( pipe_slow );
11012 %}
11013
11014 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11015 predicate(UseSSE==0);
11016 match(Set dst (ConvF2L src));
11017 effect( KILL cr );
11018 format %{ "FLD $src\t# Convert float to long\n\t"
11019 "FLDCW trunc mode\n\t"
11020 "SUB ESP,8\n\t"
11021 "FISTp [ESP + #0]\n\t"
11022 "FLDCW std/24-bit mode\n\t"
11023 "POP EAX\n\t"
11024 "POP EDX\n\t"
11025 "CMP EDX,0x80000000\n\t"
11026 "JNE,s fast\n\t"
11027 "TEST EAX,EAX\n\t"
11028 "JNE,s fast\n\t"
11029 "FLD $src\n\t"
11030 "CALL d2l_wrapper\n"
11031 "fast:" %}
11032 // DPR2L_encoding works for FPR2L
11033 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11034 ins_pipe( pipe_slow );
11035 %}
11036
11037 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11038 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11039 predicate (UseSSE>=1);
11040 match(Set dst (ConvF2L src));
11041 effect( KILL cr );
11042 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11043 "MOVSS [ESP],$src\n\t"
11044 "FLD_S [ESP]\n\t"
11045 "FLDCW trunc mode\n\t"
11046 "FISTp [ESP + #0]\n\t"
11047 "FLDCW std/24-bit mode\n\t"
11048 "POP EAX\n\t"
11049 "POP EDX\n\t"
11050 "CMP EDX,0x80000000\n\t"
11051 "JNE,s fast\n\t"
11052 "TEST EAX,EAX\n\t"
11053 "JNE,s fast\n\t"
11054 "SUB ESP,4\t# Convert float to long\n\t"
11055 "MOVSS [ESP],$src\n\t"
11056 "FLD_S [ESP]\n\t"
11057 "ADD ESP,4\n\t"
11058 "CALL d2l_wrapper\n"
11059 "fast:" %}
11060 ins_encode %{
11061 Label fast;
11062 __ subptr(rsp, 8);
11063 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11064 __ fld_s(Address(rsp, 0));
11065 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11066 __ fistp_d(Address(rsp, 0));
11067 // Restore the rounding mode, mask the exception
11068 if (Compile::current()->in_24_bit_fp_mode()) {
11069 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11070 } else {
11071 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11072 }
11073 // Load the converted long, adjust CPU stack
11074 __ pop(rax);
11075 __ pop(rdx);
11076 __ cmpl(rdx, 0x80000000);
11077 __ jccb(Assembler::notEqual, fast);
11078 __ testl(rax, rax);
11079 __ jccb(Assembler::notEqual, fast);
11080 __ subptr(rsp, 4);
11081 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11082 __ fld_s(Address(rsp, 0));
11083 __ addptr(rsp, 4);
11084 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11085 __ bind(fast);
11086 %}
11087 ins_pipe( pipe_slow );
11088 %}
11089
11090 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11091 predicate( UseSSE<=1 );
11092 match(Set dst (ConvI2D src));
11093 format %{ "FILD $src\n\t"
11094 "FSTP $dst" %}
11095 opcode(0xDB, 0x0); /* DB /0 */
11096 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11097 ins_pipe( fpu_reg_mem );
11098 %}
11099
11100 instruct convI2D_reg(regD dst, rRegI src) %{
11101 predicate( UseSSE>=2 && !UseXmmI2D );
11102 match(Set dst (ConvI2D src));
11103 format %{ "CVTSI2SD $dst,$src" %}
11104 ins_encode %{
11105 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11106 %}
11107 ins_pipe( pipe_slow );
11108 %}
11109
11110 instruct convI2D_mem(regD dst, memory mem) %{
11111 predicate( UseSSE>=2 );
11112 match(Set dst (ConvI2D (LoadI mem)));
11113 format %{ "CVTSI2SD $dst,$mem" %}
11114 ins_encode %{
11115 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11116 %}
11117 ins_pipe( pipe_slow );
11118 %}
11119
11120 instruct convXI2D_reg(regD dst, rRegI src)
11121 %{
11122 predicate( UseSSE>=2 && UseXmmI2D );
11123 match(Set dst (ConvI2D src));
11124
11125 format %{ "MOVD $dst,$src\n\t"
11126 "CVTDQ2PD $dst,$dst\t# i2d" %}
11127 ins_encode %{
11128 __ movdl($dst$$XMMRegister, $src$$Register);
11129 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11130 %}
11131 ins_pipe(pipe_slow); // XXX
11132 %}
11133
11134 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11135 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11136 match(Set dst (ConvI2D (LoadI mem)));
11137 format %{ "FILD $mem\n\t"
11138 "FSTP $dst" %}
11139 opcode(0xDB); /* DB /0 */
11140 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11141 Pop_Reg_DPR(dst));
11142 ins_pipe( fpu_reg_mem );
11143 %}
11144
11145 // Convert a byte to a float; no rounding step needed.
11146 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11147 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11148 match(Set dst (ConvI2F src));
11149 format %{ "FILD $src\n\t"
11150 "FSTP $dst" %}
11151
11152 opcode(0xDB, 0x0); /* DB /0 */
11153 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11154 ins_pipe( fpu_reg_mem );
11155 %}
11156
11157 // In 24-bit mode, force exponent rounding by storing back out
11158 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11159 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11160 match(Set dst (ConvI2F src));
11161 ins_cost(200);
11162 format %{ "FILD $src\n\t"
11163 "FSTP_S $dst" %}
11164 opcode(0xDB, 0x0); /* DB /0 */
11165 ins_encode( Push_Mem_I(src),
11166 Pop_Mem_FPR(dst));
11167 ins_pipe( fpu_mem_mem );
11168 %}
11169
11170 // In 24-bit mode, force exponent rounding by storing back out
11171 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11172 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11173 match(Set dst (ConvI2F (LoadI mem)));
11174 ins_cost(200);
11175 format %{ "FILD $mem\n\t"
11176 "FSTP_S $dst" %}
11177 opcode(0xDB); /* DB /0 */
11178 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11179 Pop_Mem_FPR(dst));
11180 ins_pipe( fpu_mem_mem );
11181 %}
11182
11183 // This instruction does not round to 24-bits
11184 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11185 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11186 match(Set dst (ConvI2F src));
11187 format %{ "FILD $src\n\t"
11188 "FSTP $dst" %}
11189 opcode(0xDB, 0x0); /* DB /0 */
11190 ins_encode( Push_Mem_I(src),
11191 Pop_Reg_FPR(dst));
11192 ins_pipe( fpu_reg_mem );
11193 %}
11194
11195 // This instruction does not round to 24-bits
11196 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11197 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11198 match(Set dst (ConvI2F (LoadI mem)));
11199 format %{ "FILD $mem\n\t"
11200 "FSTP $dst" %}
11201 opcode(0xDB); /* DB /0 */
11202 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11203 Pop_Reg_FPR(dst));
11204 ins_pipe( fpu_reg_mem );
11205 %}
11206
11207 // Convert an int to a float in xmm; no rounding step needed.
11208 instruct convI2F_reg(regF dst, rRegI src) %{
11209 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11210 match(Set dst (ConvI2F src));
11211 format %{ "CVTSI2SS $dst, $src" %}
11212 ins_encode %{
11213 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11214 %}
11215 ins_pipe( pipe_slow );
11216 %}
11217
11218 instruct convXI2F_reg(regF dst, rRegI src)
11219 %{
11220 predicate( UseSSE>=2 && UseXmmI2F );
11221 match(Set dst (ConvI2F src));
11222
11223 format %{ "MOVD $dst,$src\n\t"
11224 "CVTDQ2PS $dst,$dst\t# i2f" %}
11225 ins_encode %{
11226 __ movdl($dst$$XMMRegister, $src$$Register);
11227 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11228 %}
11229 ins_pipe(pipe_slow); // XXX
11230 %}
11231
11232 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11233 match(Set dst (ConvI2L src));
11234 effect(KILL cr);
11235 ins_cost(375);
11236 format %{ "MOV $dst.lo,$src\n\t"
11237 "MOV $dst.hi,$src\n\t"
11238 "SAR $dst.hi,31" %}
11239 ins_encode(convert_int_long(dst,src));
11240 ins_pipe( ialu_reg_reg_long );
11241 %}
11242
11243 // Zero-extend convert int to long
11244 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11245 match(Set dst (AndL (ConvI2L src) mask) );
11246 effect( KILL flags );
11247 ins_cost(250);
11248 format %{ "MOV $dst.lo,$src\n\t"
11249 "XOR $dst.hi,$dst.hi" %}
11250 opcode(0x33); // XOR
11251 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11252 ins_pipe( ialu_reg_reg_long );
11253 %}
11254
11255 // Zero-extend long
11256 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11257 match(Set dst (AndL src mask) );
11258 effect( KILL flags );
11259 ins_cost(250);
11260 format %{ "MOV $dst.lo,$src.lo\n\t"
11261 "XOR $dst.hi,$dst.hi\n\t" %}
11262 opcode(0x33); // XOR
11263 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11264 ins_pipe( ialu_reg_reg_long );
11265 %}
11266
11267 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11268 predicate (UseSSE<=1);
11269 match(Set dst (ConvL2D src));
11270 effect( KILL cr );
11271 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11272 "PUSH $src.lo\n\t"
11273 "FILD ST,[ESP + #0]\n\t"
11274 "ADD ESP,8\n\t"
11275 "FSTP_D $dst\t# D-round" %}
11276 opcode(0xDF, 0x5); /* DF /5 */
11277 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11278 ins_pipe( pipe_slow );
11279 %}
11280
11281 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11282 predicate (UseSSE>=2);
11283 match(Set dst (ConvL2D src));
11284 effect( KILL cr );
11285 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11286 "PUSH $src.lo\n\t"
11287 "FILD_D [ESP]\n\t"
11288 "FSTP_D [ESP]\n\t"
11289 "MOVSD $dst,[ESP]\n\t"
11290 "ADD ESP,8" %}
11291 opcode(0xDF, 0x5); /* DF /5 */
11292 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11293 ins_pipe( pipe_slow );
11294 %}
11295
11296 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11297 predicate (UseSSE>=1);
11298 match(Set dst (ConvL2F src));
11299 effect( KILL cr );
11300 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11301 "PUSH $src.lo\n\t"
11302 "FILD_D [ESP]\n\t"
11303 "FSTP_S [ESP]\n\t"
11304 "MOVSS $dst,[ESP]\n\t"
11305 "ADD ESP,8" %}
11306 opcode(0xDF, 0x5); /* DF /5 */
11307 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11308 ins_pipe( pipe_slow );
11309 %}
11310
11311 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11312 match(Set dst (ConvL2F src));
11313 effect( KILL cr );
11314 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11315 "PUSH $src.lo\n\t"
11316 "FILD ST,[ESP + #0]\n\t"
11317 "ADD ESP,8\n\t"
11318 "FSTP_S $dst\t# F-round" %}
11319 opcode(0xDF, 0x5); /* DF /5 */
11320 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11321 ins_pipe( pipe_slow );
11322 %}
11323
11324 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11325 match(Set dst (ConvL2I src));
11326 effect( DEF dst, USE src );
11327 format %{ "MOV $dst,$src.lo" %}
11328 ins_encode(enc_CopyL_Lo(dst,src));
11329 ins_pipe( ialu_reg_reg );
11330 %}
11331
11332
11333 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11334 match(Set dst (MoveF2I src));
11335 effect( DEF dst, USE src );
11336 ins_cost(100);
11337 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11338 ins_encode %{
11339 __ movl($dst$$Register, Address(rsp, $src$$disp));
11340 %}
11341 ins_pipe( ialu_reg_mem );
11342 %}
11343
11344 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11345 predicate(UseSSE==0);
11346 match(Set dst (MoveF2I src));
11347 effect( DEF dst, USE src );
11348
11349 ins_cost(125);
11350 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11351 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11352 ins_pipe( fpu_mem_reg );
11353 %}
11354
11355 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11356 predicate(UseSSE>=1);
11357 match(Set dst (MoveF2I src));
11358 effect( DEF dst, USE src );
11359
11360 ins_cost(95);
11361 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11362 ins_encode %{
11363 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11364 %}
11365 ins_pipe( pipe_slow );
11366 %}
11367
11368 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11369 predicate(UseSSE>=2);
11370 match(Set dst (MoveF2I src));
11371 effect( DEF dst, USE src );
11372 ins_cost(85);
11373 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11374 ins_encode %{
11375 __ movdl($dst$$Register, $src$$XMMRegister);
11376 %}
11377 ins_pipe( pipe_slow );
11378 %}
11379
11380 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11381 match(Set dst (MoveI2F src));
11382 effect( DEF dst, USE src );
11383
11384 ins_cost(100);
11385 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11386 ins_encode %{
11387 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11388 %}
11389 ins_pipe( ialu_mem_reg );
11390 %}
11391
11392
11393 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11394 predicate(UseSSE==0);
11395 match(Set dst (MoveI2F src));
11396 effect(DEF dst, USE src);
11397
11398 ins_cost(125);
11399 format %{ "FLD_S $src\n\t"
11400 "FSTP $dst\t# MoveI2F_stack_reg" %}
11401 opcode(0xD9); /* D9 /0, FLD m32real */
11402 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11403 Pop_Reg_FPR(dst) );
11404 ins_pipe( fpu_reg_mem );
11405 %}
11406
11407 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11408 predicate(UseSSE>=1);
11409 match(Set dst (MoveI2F src));
11410 effect( DEF dst, USE src );
11411
11412 ins_cost(95);
11413 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11414 ins_encode %{
11415 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11416 %}
11417 ins_pipe( pipe_slow );
11418 %}
11419
11420 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11421 predicate(UseSSE>=2);
11422 match(Set dst (MoveI2F src));
11423 effect( DEF dst, USE src );
11424
11425 ins_cost(85);
11426 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11427 ins_encode %{
11428 __ movdl($dst$$XMMRegister, $src$$Register);
11429 %}
11430 ins_pipe( pipe_slow );
11431 %}
11432
11433 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11434 match(Set dst (MoveD2L src));
11435 effect(DEF dst, USE src);
11436
11437 ins_cost(250);
11438 format %{ "MOV $dst.lo,$src\n\t"
11439 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11440 opcode(0x8B, 0x8B);
11441 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11442 ins_pipe( ialu_mem_long_reg );
11443 %}
11444
11445 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11446 predicate(UseSSE<=1);
11447 match(Set dst (MoveD2L src));
11448 effect(DEF dst, USE src);
11449
11450 ins_cost(125);
11451 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11452 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11453 ins_pipe( fpu_mem_reg );
11454 %}
11455
11456 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11457 predicate(UseSSE>=2);
11458 match(Set dst (MoveD2L src));
11459 effect(DEF dst, USE src);
11460 ins_cost(95);
11461 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11462 ins_encode %{
11463 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11464 %}
11465 ins_pipe( pipe_slow );
11466 %}
11467
11468 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11469 predicate(UseSSE>=2);
11470 match(Set dst (MoveD2L src));
11471 effect(DEF dst, USE src, TEMP tmp);
11472 ins_cost(85);
11473 format %{ "MOVD $dst.lo,$src\n\t"
11474 "PSHUFLW $tmp,$src,0x4E\n\t"
11475 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11476 ins_encode %{
11477 __ movdl($dst$$Register, $src$$XMMRegister);
11478 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11479 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11480 %}
11481 ins_pipe( pipe_slow );
11482 %}
11483
11484 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11485 match(Set dst (MoveL2D src));
11486 effect(DEF dst, USE src);
11487
11488 ins_cost(200);
11489 format %{ "MOV $dst,$src.lo\n\t"
11490 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11491 opcode(0x89, 0x89);
11492 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11493 ins_pipe( ialu_mem_long_reg );
11494 %}
11495
11496
11497 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11498 predicate(UseSSE<=1);
11499 match(Set dst (MoveL2D src));
11500 effect(DEF dst, USE src);
11501 ins_cost(125);
11502
11503 format %{ "FLD_D $src\n\t"
11504 "FSTP $dst\t# MoveL2D_stack_reg" %}
11505 opcode(0xDD); /* DD /0, FLD m64real */
11506 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11507 Pop_Reg_DPR(dst) );
11508 ins_pipe( fpu_reg_mem );
11509 %}
11510
11511
11512 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11513 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11514 match(Set dst (MoveL2D src));
11515 effect(DEF dst, USE src);
11516
11517 ins_cost(95);
11518 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11519 ins_encode %{
11520 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11521 %}
11522 ins_pipe( pipe_slow );
11523 %}
11524
11525 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11526 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11527 match(Set dst (MoveL2D src));
11528 effect(DEF dst, USE src);
11529
11530 ins_cost(95);
11531 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11532 ins_encode %{
11533 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11534 %}
11535 ins_pipe( pipe_slow );
11536 %}
11537
11538 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11539 predicate(UseSSE>=2);
11540 match(Set dst (MoveL2D src));
11541 effect(TEMP dst, USE src, TEMP tmp);
11542 ins_cost(85);
11543 format %{ "MOVD $dst,$src.lo\n\t"
11544 "MOVD $tmp,$src.hi\n\t"
11545 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11546 ins_encode %{
11547 __ movdl($dst$$XMMRegister, $src$$Register);
11548 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11549 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11550 %}
11551 ins_pipe( pipe_slow );
11552 %}
11553
11554
11555 // =======================================================================
11556 // fast clearing of an array
11557 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11558 match(Set dummy (ClearArray cnt base));
11559 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11560 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
11561 "XOR EAX,EAX\n\t"
11562 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11563 opcode(0,0x4);
11564 ins_encode( Opcode(0xD1), RegOpc(ECX),
11565 OpcRegReg(0x33,EAX,EAX),
11566 Opcode(0xF3), Opcode(0xAB) );
11567 ins_pipe( pipe_slow );
11568 %}
11569
11570 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11571 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11572 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11573 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11574
11575 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11576 ins_encode %{
11577 __ string_compare($str1$$Register, $str2$$Register,
11578 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11579 $tmp1$$XMMRegister);
11580 %}
11581 ins_pipe( pipe_slow );
11582 %}
11583
11584 // fast string equals
11585 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11586 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11587 match(Set result (StrEquals (Binary str1 str2) cnt));
11588 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11589
11590 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11591 ins_encode %{
11592 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11593 $cnt$$Register, $result$$Register, $tmp3$$Register,
11594 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11595 %}
11596 ins_pipe( pipe_slow );
11597 %}
11598
11599 // fast search of substring with known size.
11600 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11601 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11602 predicate(UseSSE42Intrinsics);
11603 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11604 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11605
11606 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11607 ins_encode %{
11608 int icnt2 = (int)$int_cnt2$$constant;
11609 if (icnt2 >= 8) {
11610 // IndexOf for constant substrings with size >= 8 elements
11611 // which don't need to be loaded through stack.
11612 __ string_indexofC8($str1$$Register, $str2$$Register,
11613 $cnt1$$Register, $cnt2$$Register,
11614 icnt2, $result$$Register,
11615 $vec$$XMMRegister, $tmp$$Register);
11616 } else {
11617 // Small strings are loaded through stack if they cross page boundary.
11618 __ string_indexof($str1$$Register, $str2$$Register,
11619 $cnt1$$Register, $cnt2$$Register,
11620 icnt2, $result$$Register,
11621 $vec$$XMMRegister, $tmp$$Register);
11622 }
11623 %}
11624 ins_pipe( pipe_slow );
11625 %}
11626
11627 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11628 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11629 predicate(UseSSE42Intrinsics);
11630 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11631 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11632
11633 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11634 ins_encode %{
11635 __ string_indexof($str1$$Register, $str2$$Register,
11636 $cnt1$$Register, $cnt2$$Register,
11637 (-1), $result$$Register,
11638 $vec$$XMMRegister, $tmp$$Register);
11639 %}
11640 ins_pipe( pipe_slow );
11641 %}
11642
11643 // fast array equals
11644 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11645 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11646 %{
11647 match(Set result (AryEq ary1 ary2));
11648 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11649 //ins_cost(300);
11650
11651 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11652 ins_encode %{
11653 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11654 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11655 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11656 %}
11657 ins_pipe( pipe_slow );
11658 %}
11659
11660 //----------Control Flow Instructions------------------------------------------
11661 // Signed compare Instructions
11662 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11663 match(Set cr (CmpI op1 op2));
11664 effect( DEF cr, USE op1, USE op2 );
11665 format %{ "CMP $op1,$op2" %}
11666 opcode(0x3B); /* Opcode 3B /r */
11667 ins_encode( OpcP, RegReg( op1, op2) );
11668 ins_pipe( ialu_cr_reg_reg );
11669 %}
11670
11671 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11672 match(Set cr (CmpI op1 op2));
11673 effect( DEF cr, USE op1 );
11674 format %{ "CMP $op1,$op2" %}
11675 opcode(0x81,0x07); /* Opcode 81 /7 */
11676 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11677 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11678 ins_pipe( ialu_cr_reg_imm );
11679 %}
11680
11681 // Cisc-spilled version of cmpI_eReg
11682 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11683 match(Set cr (CmpI op1 (LoadI op2)));
11684
11685 format %{ "CMP $op1,$op2" %}
11686 ins_cost(500);
11687 opcode(0x3B); /* Opcode 3B /r */
11688 ins_encode( OpcP, RegMem( op1, op2) );
11689 ins_pipe( ialu_cr_reg_mem );
11690 %}
11691
11692 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11693 match(Set cr (CmpI src zero));
11694 effect( DEF cr, USE src );
11695
11696 format %{ "TEST $src,$src" %}
11697 opcode(0x85);
11698 ins_encode( OpcP, RegReg( src, src ) );
11699 ins_pipe( ialu_cr_reg_imm );
11700 %}
11701
11702 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11703 match(Set cr (CmpI (AndI src con) zero));
11704
11705 format %{ "TEST $src,$con" %}
11706 opcode(0xF7,0x00);
11707 ins_encode( OpcP, RegOpc(src), Con32(con) );
11708 ins_pipe( ialu_cr_reg_imm );
11709 %}
11710
11711 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11712 match(Set cr (CmpI (AndI src mem) zero));
11713
11714 format %{ "TEST $src,$mem" %}
11715 opcode(0x85);
11716 ins_encode( OpcP, RegMem( src, mem ) );
11717 ins_pipe( ialu_cr_reg_mem );
11718 %}
11719
11720 // Unsigned compare Instructions; really, same as signed except they
11721 // produce an eFlagsRegU instead of eFlagsReg.
11722 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11723 match(Set cr (CmpU op1 op2));
11724
11725 format %{ "CMPu $op1,$op2" %}
11726 opcode(0x3B); /* Opcode 3B /r */
11727 ins_encode( OpcP, RegReg( op1, op2) );
11728 ins_pipe( ialu_cr_reg_reg );
11729 %}
11730
11731 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11732 match(Set cr (CmpU op1 op2));
11733
11734 format %{ "CMPu $op1,$op2" %}
11735 opcode(0x81,0x07); /* Opcode 81 /7 */
11736 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11737 ins_pipe( ialu_cr_reg_imm );
11738 %}
11739
11740 // // Cisc-spilled version of cmpU_eReg
11741 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11742 match(Set cr (CmpU op1 (LoadI op2)));
11743
11744 format %{ "CMPu $op1,$op2" %}
11745 ins_cost(500);
11746 opcode(0x3B); /* Opcode 3B /r */
11747 ins_encode( OpcP, RegMem( op1, op2) );
11748 ins_pipe( ialu_cr_reg_mem );
11749 %}
11750
11751 // // Cisc-spilled version of cmpU_eReg
11752 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11753 // match(Set cr (CmpU (LoadI op1) op2));
11754 //
11755 // format %{ "CMPu $op1,$op2" %}
11756 // ins_cost(500);
11757 // opcode(0x39); /* Opcode 39 /r */
11758 // ins_encode( OpcP, RegMem( op1, op2) );
11759 //%}
11760
11761 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11762 match(Set cr (CmpU src zero));
11763
11764 format %{ "TESTu $src,$src" %}
11765 opcode(0x85);
11766 ins_encode( OpcP, RegReg( src, src ) );
11767 ins_pipe( ialu_cr_reg_imm );
11768 %}
11769
11770 // Unsigned pointer compare Instructions
11771 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11772 match(Set cr (CmpP op1 op2));
11773
11774 format %{ "CMPu $op1,$op2" %}
11775 opcode(0x3B); /* Opcode 3B /r */
11776 ins_encode( OpcP, RegReg( op1, op2) );
11777 ins_pipe( ialu_cr_reg_reg );
11778 %}
11779
11780 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11781 match(Set cr (CmpP op1 op2));
11782
11783 format %{ "CMPu $op1,$op2" %}
11784 opcode(0x81,0x07); /* Opcode 81 /7 */
11785 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11786 ins_pipe( ialu_cr_reg_imm );
11787 %}
11788
11789 // // Cisc-spilled version of cmpP_eReg
11790 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11791 match(Set cr (CmpP op1 (LoadP op2)));
11792
11793 format %{ "CMPu $op1,$op2" %}
11794 ins_cost(500);
11795 opcode(0x3B); /* Opcode 3B /r */
11796 ins_encode( OpcP, RegMem( op1, op2) );
11797 ins_pipe( ialu_cr_reg_mem );
11798 %}
11799
11800 // // Cisc-spilled version of cmpP_eReg
11801 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11802 // match(Set cr (CmpP (LoadP op1) op2));
11803 //
11804 // format %{ "CMPu $op1,$op2" %}
11805 // ins_cost(500);
11806 // opcode(0x39); /* Opcode 39 /r */
11807 // ins_encode( OpcP, RegMem( op1, op2) );
11808 //%}
11809
11810 // Compare raw pointer (used in out-of-heap check).
11811 // Only works because non-oop pointers must be raw pointers
11812 // and raw pointers have no anti-dependencies.
11813 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11814 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
11815 match(Set cr (CmpP op1 (LoadP op2)));
11816
11817 format %{ "CMPu $op1,$op2" %}
11818 opcode(0x3B); /* Opcode 3B /r */
11819 ins_encode( OpcP, RegMem( op1, op2) );
11820 ins_pipe( ialu_cr_reg_mem );
11821 %}
11822
11823 //
11824 // This will generate a signed flags result. This should be ok
11825 // since any compare to a zero should be eq/neq.
11826 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11827 match(Set cr (CmpP src zero));
11828
11829 format %{ "TEST $src,$src" %}
11830 opcode(0x85);
11831 ins_encode( OpcP, RegReg( src, src ) );
11832 ins_pipe( ialu_cr_reg_imm );
11833 %}
11834
11835 // Cisc-spilled version of testP_reg
11836 // This will generate a signed flags result. This should be ok
11837 // since any compare to a zero should be eq/neq.
11838 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11839 match(Set cr (CmpP (LoadP op) zero));
11840
11841 format %{ "TEST $op,0xFFFFFFFF" %}
11842 ins_cost(500);
11843 opcode(0xF7); /* Opcode F7 /0 */
11844 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11845 ins_pipe( ialu_cr_reg_imm );
11846 %}
11847
11848 // Yanked all unsigned pointer compare operations.
11849 // Pointer compares are done with CmpP which is already unsigned.
11850
11851 //----------Max and Min--------------------------------------------------------
11852 // Min Instructions
11853 ////
11854 // *** Min and Max using the conditional move are slower than the
11855 // *** branch version on a Pentium III.
11856 // // Conditional move for min
11857 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11858 // effect( USE_DEF op2, USE op1, USE cr );
11859 // format %{ "CMOVlt $op2,$op1\t! min" %}
11860 // opcode(0x4C,0x0F);
11861 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11862 // ins_pipe( pipe_cmov_reg );
11863 //%}
11864 //
11865 //// Min Register with Register (P6 version)
11866 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11867 // predicate(VM_Version::supports_cmov() );
11868 // match(Set op2 (MinI op1 op2));
11869 // ins_cost(200);
11870 // expand %{
11871 // eFlagsReg cr;
11872 // compI_eReg(cr,op1,op2);
11873 // cmovI_reg_lt(op2,op1,cr);
11874 // %}
11875 //%}
11876
11877 // Min Register with Register (generic version)
11878 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11879 match(Set dst (MinI dst src));
11880 effect(KILL flags);
11881 ins_cost(300);
11882
11883 format %{ "MIN $dst,$src" %}
11884 opcode(0xCC);
11885 ins_encode( min_enc(dst,src) );
11886 ins_pipe( pipe_slow );
11887 %}
11888
11889 // Max Register with Register
11890 // *** Min and Max using the conditional move are slower than the
11891 // *** branch version on a Pentium III.
11892 // // Conditional move for max
11893 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11894 // effect( USE_DEF op2, USE op1, USE cr );
11895 // format %{ "CMOVgt $op2,$op1\t! max" %}
11896 // opcode(0x4F,0x0F);
11897 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11898 // ins_pipe( pipe_cmov_reg );
11899 //%}
11900 //
11901 // // Max Register with Register (P6 version)
11902 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11903 // predicate(VM_Version::supports_cmov() );
11904 // match(Set op2 (MaxI op1 op2));
11905 // ins_cost(200);
11906 // expand %{
11907 // eFlagsReg cr;
11908 // compI_eReg(cr,op1,op2);
11909 // cmovI_reg_gt(op2,op1,cr);
11910 // %}
11911 //%}
11912
11913 // Max Register with Register (generic version)
11914 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11915 match(Set dst (MaxI dst src));
11916 effect(KILL flags);
11917 ins_cost(300);
11918
11919 format %{ "MAX $dst,$src" %}
11920 opcode(0xCC);
11921 ins_encode( max_enc(dst,src) );
11922 ins_pipe( pipe_slow );
11923 %}
11924
11925 // ============================================================================
11926 // Counted Loop limit node which represents exact final iterator value.
11927 // Note: the resulting value should fit into integer range since
11928 // counted loops have limit check on overflow.
11929 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11930 match(Set limit (LoopLimit (Binary init limit) stride));
11931 effect(TEMP limit_hi, TEMP tmp, KILL flags);
11932 ins_cost(300);
11933
11934 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11935 ins_encode %{
11936 int strd = (int)$stride$$constant;
11937 assert(strd != 1 && strd != -1, "sanity");
11938 int m1 = (strd > 0) ? 1 : -1;
11939 // Convert limit to long (EAX:EDX)
11940 __ cdql();
11941 // Convert init to long (init:tmp)
11942 __ movl($tmp$$Register, $init$$Register);
11943 __ sarl($tmp$$Register, 31);
11944 // $limit - $init
11945 __ subl($limit$$Register, $init$$Register);
11946 __ sbbl($limit_hi$$Register, $tmp$$Register);
11947 // + ($stride - 1)
11948 if (strd > 0) {
11949 __ addl($limit$$Register, (strd - 1));
11950 __ adcl($limit_hi$$Register, 0);
11951 __ movl($tmp$$Register, strd);
11952 } else {
11953 __ addl($limit$$Register, (strd + 1));
11954 __ adcl($limit_hi$$Register, -1);
11955 __ lneg($limit_hi$$Register, $limit$$Register);
11956 __ movl($tmp$$Register, -strd);
11957 }
11958 // signed devision: (EAX:EDX) / pos_stride
11959 __ idivl($tmp$$Register);
11960 if (strd < 0) {
11961 // restore sign
11962 __ negl($tmp$$Register);
11963 }
11964 // (EAX) * stride
11965 __ mull($tmp$$Register);
11966 // + init (ignore upper bits)
11967 __ addl($limit$$Register, $init$$Register);
11968 %}
11969 ins_pipe( pipe_slow );
11970 %}
11971
11972 // ============================================================================
11973 // Branch Instructions
11974 // Jump Table
11975 instruct jumpXtnd(rRegI switch_val) %{
11976 match(Jump switch_val);
11977 ins_cost(350);
11978 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
11979 ins_encode %{
11980 // Jump to Address(table_base + switch_reg)
11981 Address index(noreg, $switch_val$$Register, Address::times_1);
11982 __ jump(ArrayAddress($constantaddress, index));
11983 %}
11984 ins_pipe(pipe_jmp);
11985 %}
11986
11987 // Jump Direct - Label defines a relative address from JMP+1
11988 instruct jmpDir(label labl) %{
11989 match(Goto);
11990 effect(USE labl);
11991
11992 ins_cost(300);
11993 format %{ "JMP $labl" %}
11994 size(5);
11995 ins_encode %{
11996 Label* L = $labl$$label;
11997 __ jmp(*L, false); // Always long jump
11998 %}
11999 ins_pipe( pipe_jmp );
12000 %}
12001
12002 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12003 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12004 match(If cop cr);
12005 effect(USE labl);
12006
12007 ins_cost(300);
12008 format %{ "J$cop $labl" %}
12009 size(6);
12010 ins_encode %{
12011 Label* L = $labl$$label;
12012 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12013 %}
12014 ins_pipe( pipe_jcc );
12015 %}
12016
12017 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12018 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12019 match(CountedLoopEnd cop cr);
12020 effect(USE labl);
12021
12022 ins_cost(300);
12023 format %{ "J$cop $labl\t# Loop end" %}
12024 size(6);
12025 ins_encode %{
12026 Label* L = $labl$$label;
12027 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12028 %}
12029 ins_pipe( pipe_jcc );
12030 %}
12031
12032 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12033 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12034 match(CountedLoopEnd cop cmp);
12035 effect(USE labl);
12036
12037 ins_cost(300);
12038 format %{ "J$cop,u $labl\t# Loop end" %}
12039 size(6);
12040 ins_encode %{
12041 Label* L = $labl$$label;
12042 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12043 %}
12044 ins_pipe( pipe_jcc );
12045 %}
12046
12047 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12048 match(CountedLoopEnd cop cmp);
12049 effect(USE labl);
12050
12051 ins_cost(200);
12052 format %{ "J$cop,u $labl\t# Loop end" %}
12053 size(6);
12054 ins_encode %{
12055 Label* L = $labl$$label;
12056 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12057 %}
12058 ins_pipe( pipe_jcc );
12059 %}
12060
12061 // Jump Direct Conditional - using unsigned comparison
12062 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12063 match(If cop cmp);
12064 effect(USE labl);
12065
12066 ins_cost(300);
12067 format %{ "J$cop,u $labl" %}
12068 size(6);
12069 ins_encode %{
12070 Label* L = $labl$$label;
12071 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12072 %}
12073 ins_pipe(pipe_jcc);
12074 %}
12075
12076 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12077 match(If cop cmp);
12078 effect(USE labl);
12079
12080 ins_cost(200);
12081 format %{ "J$cop,u $labl" %}
12082 size(6);
12083 ins_encode %{
12084 Label* L = $labl$$label;
12085 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12086 %}
12087 ins_pipe(pipe_jcc);
12088 %}
12089
12090 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12091 match(If cop cmp);
12092 effect(USE labl);
12093
12094 ins_cost(200);
12095 format %{ $$template
12096 if ($cop$$cmpcode == Assembler::notEqual) {
12097 $$emit$$"JP,u $labl\n\t"
12098 $$emit$$"J$cop,u $labl"
12099 } else {
12100 $$emit$$"JP,u done\n\t"
12101 $$emit$$"J$cop,u $labl\n\t"
12102 $$emit$$"done:"
12103 }
12104 %}
12105 ins_encode %{
12106 Label* l = $labl$$label;
12107 if ($cop$$cmpcode == Assembler::notEqual) {
12108 __ jcc(Assembler::parity, *l, false);
12109 __ jcc(Assembler::notEqual, *l, false);
12110 } else if ($cop$$cmpcode == Assembler::equal) {
12111 Label done;
12112 __ jccb(Assembler::parity, done);
12113 __ jcc(Assembler::equal, *l, false);
12114 __ bind(done);
12115 } else {
12116 ShouldNotReachHere();
12117 }
12118 %}
12119 ins_pipe(pipe_jcc);
12120 %}
12121
12122 // ============================================================================
12123 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12124 // array for an instance of the superklass. Set a hidden internal cache on a
12125 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12126 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12127 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12128 match(Set result (PartialSubtypeCheck sub super));
12129 effect( KILL rcx, KILL cr );
12130
12131 ins_cost(1100); // slightly larger than the next version
12132 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12133 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12134 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12135 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12136 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12137 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12138 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12139 "miss:\t" %}
12140
12141 opcode(0x1); // Force a XOR of EDI
12142 ins_encode( enc_PartialSubtypeCheck() );
12143 ins_pipe( pipe_slow );
12144 %}
12145
12146 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12147 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12148 effect( KILL rcx, KILL result );
12149
12150 ins_cost(1000);
12151 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12152 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12153 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12154 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12155 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12156 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12157 "miss:\t" %}
12158
12159 opcode(0x0); // No need to XOR EDI
12160 ins_encode( enc_PartialSubtypeCheck() );
12161 ins_pipe( pipe_slow );
12162 %}
12163
12164 // ============================================================================
12165 // Branch Instructions -- short offset versions
12166 //
12167 // These instructions are used to replace jumps of a long offset (the default
12168 // match) with jumps of a shorter offset. These instructions are all tagged
12169 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12170 // match rules in general matching. Instead, the ADLC generates a conversion
12171 // method in the MachNode which can be used to do in-place replacement of the
12172 // long variant with the shorter variant. The compiler will determine if a
12173 // branch can be taken by the is_short_branch_offset() predicate in the machine
12174 // specific code section of the file.
12175
12176 // Jump Direct - Label defines a relative address from JMP+1
12177 instruct jmpDir_short(label labl) %{
12178 match(Goto);
12179 effect(USE labl);
12180
12181 ins_cost(300);
12182 format %{ "JMP,s $labl" %}
12183 size(2);
12184 ins_encode %{
12185 Label* L = $labl$$label;
12186 __ jmpb(*L);
12187 %}
12188 ins_pipe( pipe_jmp );
12189 ins_short_branch(1);
12190 %}
12191
12192 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12193 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12194 match(If cop cr);
12195 effect(USE labl);
12196
12197 ins_cost(300);
12198 format %{ "J$cop,s $labl" %}
12199 size(2);
12200 ins_encode %{
12201 Label* L = $labl$$label;
12202 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12203 %}
12204 ins_pipe( pipe_jcc );
12205 ins_short_branch(1);
12206 %}
12207
12208 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12209 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12210 match(CountedLoopEnd cop cr);
12211 effect(USE labl);
12212
12213 ins_cost(300);
12214 format %{ "J$cop,s $labl\t# Loop end" %}
12215 size(2);
12216 ins_encode %{
12217 Label* L = $labl$$label;
12218 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12219 %}
12220 ins_pipe( pipe_jcc );
12221 ins_short_branch(1);
12222 %}
12223
12224 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12225 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12226 match(CountedLoopEnd cop cmp);
12227 effect(USE labl);
12228
12229 ins_cost(300);
12230 format %{ "J$cop,us $labl\t# Loop end" %}
12231 size(2);
12232 ins_encode %{
12233 Label* L = $labl$$label;
12234 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12235 %}
12236 ins_pipe( pipe_jcc );
12237 ins_short_branch(1);
12238 %}
12239
12240 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12241 match(CountedLoopEnd cop cmp);
12242 effect(USE labl);
12243
12244 ins_cost(300);
12245 format %{ "J$cop,us $labl\t# Loop end" %}
12246 size(2);
12247 ins_encode %{
12248 Label* L = $labl$$label;
12249 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12250 %}
12251 ins_pipe( pipe_jcc );
12252 ins_short_branch(1);
12253 %}
12254
12255 // Jump Direct Conditional - using unsigned comparison
12256 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12257 match(If cop cmp);
12258 effect(USE labl);
12259
12260 ins_cost(300);
12261 format %{ "J$cop,us $labl" %}
12262 size(2);
12263 ins_encode %{
12264 Label* L = $labl$$label;
12265 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12266 %}
12267 ins_pipe( pipe_jcc );
12268 ins_short_branch(1);
12269 %}
12270
12271 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12272 match(If cop cmp);
12273 effect(USE labl);
12274
12275 ins_cost(300);
12276 format %{ "J$cop,us $labl" %}
12277 size(2);
12278 ins_encode %{
12279 Label* L = $labl$$label;
12280 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12281 %}
12282 ins_pipe( pipe_jcc );
12283 ins_short_branch(1);
12284 %}
12285
12286 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12287 match(If cop cmp);
12288 effect(USE labl);
12289
12290 ins_cost(300);
12291 format %{ $$template
12292 if ($cop$$cmpcode == Assembler::notEqual) {
12293 $$emit$$"JP,u,s $labl\n\t"
12294 $$emit$$"J$cop,u,s $labl"
12295 } else {
12296 $$emit$$"JP,u,s done\n\t"
12297 $$emit$$"J$cop,u,s $labl\n\t"
12298 $$emit$$"done:"
12299 }
12300 %}
12301 size(4);
12302 ins_encode %{
12303 Label* l = $labl$$label;
12304 if ($cop$$cmpcode == Assembler::notEqual) {
12305 __ jccb(Assembler::parity, *l);
12306 __ jccb(Assembler::notEqual, *l);
12307 } else if ($cop$$cmpcode == Assembler::equal) {
12308 Label done;
12309 __ jccb(Assembler::parity, done);
12310 __ jccb(Assembler::equal, *l);
12311 __ bind(done);
12312 } else {
12313 ShouldNotReachHere();
12314 }
12315 %}
12316 ins_pipe(pipe_jcc);
12317 ins_short_branch(1);
12318 %}
12319
12320 // ============================================================================
12321 // Long Compare
12322 //
12323 // Currently we hold longs in 2 registers. Comparing such values efficiently
12324 // is tricky. The flavor of compare used depends on whether we are testing
12325 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12326 // The GE test is the negated LT test. The LE test can be had by commuting
12327 // the operands (yielding a GE test) and then negating; negate again for the
12328 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12329 // NE test is negated from that.
12330
12331 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12332 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12333 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12334 // are collapsed internally in the ADLC's dfa-gen code. The match for
12335 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12336 // foo match ends up with the wrong leaf. One fix is to not match both
12337 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12338 // both forms beat the trinary form of long-compare and both are very useful
12339 // on Intel which has so few registers.
12340
12341 // Manifest a CmpL result in an integer register. Very painful.
12342 // This is the test to avoid.
12343 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12344 match(Set dst (CmpL3 src1 src2));
12345 effect( KILL flags );
12346 ins_cost(1000);
12347 format %{ "XOR $dst,$dst\n\t"
12348 "CMP $src1.hi,$src2.hi\n\t"
12349 "JLT,s m_one\n\t"
12350 "JGT,s p_one\n\t"
12351 "CMP $src1.lo,$src2.lo\n\t"
12352 "JB,s m_one\n\t"
12353 "JEQ,s done\n"
12354 "p_one:\tINC $dst\n\t"
12355 "JMP,s done\n"
12356 "m_one:\tDEC $dst\n"
12357 "done:" %}
12358 ins_encode %{
12359 Label p_one, m_one, done;
12360 __ xorptr($dst$$Register, $dst$$Register);
12361 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12362 __ jccb(Assembler::less, m_one);
12363 __ jccb(Assembler::greater, p_one);
12364 __ cmpl($src1$$Register, $src2$$Register);
12365 __ jccb(Assembler::below, m_one);
12366 __ jccb(Assembler::equal, done);
12367 __ bind(p_one);
12368 __ incrementl($dst$$Register);
12369 __ jmpb(done);
12370 __ bind(m_one);
12371 __ decrementl($dst$$Register);
12372 __ bind(done);
12373 %}
12374 ins_pipe( pipe_slow );
12375 %}
12376
12377 //======
12378 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12379 // compares. Can be used for LE or GT compares by reversing arguments.
12380 // NOT GOOD FOR EQ/NE tests.
12381 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12382 match( Set flags (CmpL src zero ));
12383 ins_cost(100);
12384 format %{ "TEST $src.hi,$src.hi" %}
12385 opcode(0x85);
12386 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12387 ins_pipe( ialu_cr_reg_reg );
12388 %}
12389
12390 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12391 // compares. Can be used for LE or GT compares by reversing arguments.
12392 // NOT GOOD FOR EQ/NE tests.
12393 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12394 match( Set flags (CmpL src1 src2 ));
12395 effect( TEMP tmp );
12396 ins_cost(300);
12397 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12398 "MOV $tmp,$src1.hi\n\t"
12399 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12400 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12401 ins_pipe( ialu_cr_reg_reg );
12402 %}
12403
12404 // Long compares reg < zero/req OR reg >= zero/req.
12405 // Just a wrapper for a normal branch, plus the predicate test.
12406 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12407 match(If cmp flags);
12408 effect(USE labl);
12409 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12410 expand %{
12411 jmpCon(cmp,flags,labl); // JLT or JGE...
12412 %}
12413 %}
12414
12415 // Compare 2 longs and CMOVE longs.
12416 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12417 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12418 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12419 ins_cost(400);
12420 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12421 "CMOV$cmp $dst.hi,$src.hi" %}
12422 opcode(0x0F,0x40);
12423 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12424 ins_pipe( pipe_cmov_reg_long );
12425 %}
12426
12427 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12428 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12429 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12430 ins_cost(500);
12431 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12432 "CMOV$cmp $dst.hi,$src.hi" %}
12433 opcode(0x0F,0x40);
12434 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12435 ins_pipe( pipe_cmov_reg_long );
12436 %}
12437
12438 // Compare 2 longs and CMOVE ints.
12439 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12440 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12441 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12442 ins_cost(200);
12443 format %{ "CMOV$cmp $dst,$src" %}
12444 opcode(0x0F,0x40);
12445 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12446 ins_pipe( pipe_cmov_reg );
12447 %}
12448
12449 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12450 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12451 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12452 ins_cost(250);
12453 format %{ "CMOV$cmp $dst,$src" %}
12454 opcode(0x0F,0x40);
12455 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12456 ins_pipe( pipe_cmov_mem );
12457 %}
12458
12459 // Compare 2 longs and CMOVE ints.
12460 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12461 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12462 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12463 ins_cost(200);
12464 format %{ "CMOV$cmp $dst,$src" %}
12465 opcode(0x0F,0x40);
12466 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12467 ins_pipe( pipe_cmov_reg );
12468 %}
12469
12470 // Compare 2 longs and CMOVE doubles
12471 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12472 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12473 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12474 ins_cost(200);
12475 expand %{
12476 fcmovDPR_regS(cmp,flags,dst,src);
12477 %}
12478 %}
12479
12480 // Compare 2 longs and CMOVE doubles
12481 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12482 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12483 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12484 ins_cost(200);
12485 expand %{
12486 fcmovD_regS(cmp,flags,dst,src);
12487 %}
12488 %}
12489
12490 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12491 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12492 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12493 ins_cost(200);
12494 expand %{
12495 fcmovFPR_regS(cmp,flags,dst,src);
12496 %}
12497 %}
12498
12499 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12500 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12501 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12502 ins_cost(200);
12503 expand %{
12504 fcmovF_regS(cmp,flags,dst,src);
12505 %}
12506 %}
12507
12508 //======
12509 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12510 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12511 match( Set flags (CmpL src zero ));
12512 effect(TEMP tmp);
12513 ins_cost(200);
12514 format %{ "MOV $tmp,$src.lo\n\t"
12515 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12516 ins_encode( long_cmp_flags0( src, tmp ) );
12517 ins_pipe( ialu_reg_reg_long );
12518 %}
12519
12520 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12521 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12522 match( Set flags (CmpL src1 src2 ));
12523 ins_cost(200+300);
12524 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12525 "JNE,s skip\n\t"
12526 "CMP $src1.hi,$src2.hi\n\t"
12527 "skip:\t" %}
12528 ins_encode( long_cmp_flags1( src1, src2 ) );
12529 ins_pipe( ialu_cr_reg_reg );
12530 %}
12531
12532 // Long compare reg == zero/reg OR reg != zero/reg
12533 // Just a wrapper for a normal branch, plus the predicate test.
12534 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12535 match(If cmp flags);
12536 effect(USE labl);
12537 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12538 expand %{
12539 jmpCon(cmp,flags,labl); // JEQ or JNE...
12540 %}
12541 %}
12542
12543 // Compare 2 longs and CMOVE longs.
12544 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12545 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12546 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12547 ins_cost(400);
12548 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12549 "CMOV$cmp $dst.hi,$src.hi" %}
12550 opcode(0x0F,0x40);
12551 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12552 ins_pipe( pipe_cmov_reg_long );
12553 %}
12554
12555 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12556 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12557 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12558 ins_cost(500);
12559 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12560 "CMOV$cmp $dst.hi,$src.hi" %}
12561 opcode(0x0F,0x40);
12562 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12563 ins_pipe( pipe_cmov_reg_long );
12564 %}
12565
12566 // Compare 2 longs and CMOVE ints.
12567 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12568 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12569 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12570 ins_cost(200);
12571 format %{ "CMOV$cmp $dst,$src" %}
12572 opcode(0x0F,0x40);
12573 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12574 ins_pipe( pipe_cmov_reg );
12575 %}
12576
12577 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12578 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12579 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12580 ins_cost(250);
12581 format %{ "CMOV$cmp $dst,$src" %}
12582 opcode(0x0F,0x40);
12583 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12584 ins_pipe( pipe_cmov_mem );
12585 %}
12586
12587 // Compare 2 longs and CMOVE ints.
12588 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12589 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12590 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12591 ins_cost(200);
12592 format %{ "CMOV$cmp $dst,$src" %}
12593 opcode(0x0F,0x40);
12594 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12595 ins_pipe( pipe_cmov_reg );
12596 %}
12597
12598 // Compare 2 longs and CMOVE doubles
12599 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12600 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12601 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12602 ins_cost(200);
12603 expand %{
12604 fcmovDPR_regS(cmp,flags,dst,src);
12605 %}
12606 %}
12607
12608 // Compare 2 longs and CMOVE doubles
12609 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12610 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12611 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12612 ins_cost(200);
12613 expand %{
12614 fcmovD_regS(cmp,flags,dst,src);
12615 %}
12616 %}
12617
12618 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12619 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12620 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12621 ins_cost(200);
12622 expand %{
12623 fcmovFPR_regS(cmp,flags,dst,src);
12624 %}
12625 %}
12626
12627 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12628 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12629 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12630 ins_cost(200);
12631 expand %{
12632 fcmovF_regS(cmp,flags,dst,src);
12633 %}
12634 %}
12635
12636 //======
12637 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12638 // Same as cmpL_reg_flags_LEGT except must negate src
12639 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12640 match( Set flags (CmpL src zero ));
12641 effect( TEMP tmp );
12642 ins_cost(300);
12643 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12644 "CMP $tmp,$src.lo\n\t"
12645 "SBB $tmp,$src.hi\n\t" %}
12646 ins_encode( long_cmp_flags3(src, tmp) );
12647 ins_pipe( ialu_reg_reg_long );
12648 %}
12649
12650 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12651 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12652 // requires a commuted test to get the same result.
12653 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12654 match( Set flags (CmpL src1 src2 ));
12655 effect( TEMP tmp );
12656 ins_cost(300);
12657 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12658 "MOV $tmp,$src2.hi\n\t"
12659 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12660 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12661 ins_pipe( ialu_cr_reg_reg );
12662 %}
12663
12664 // Long compares reg < zero/req OR reg >= zero/req.
12665 // Just a wrapper for a normal branch, plus the predicate test
12666 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12667 match(If cmp flags);
12668 effect(USE labl);
12669 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12670 ins_cost(300);
12671 expand %{
12672 jmpCon(cmp,flags,labl); // JGT or JLE...
12673 %}
12674 %}
12675
12676 // Compare 2 longs and CMOVE longs.
12677 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12678 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12679 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12680 ins_cost(400);
12681 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12682 "CMOV$cmp $dst.hi,$src.hi" %}
12683 opcode(0x0F,0x40);
12684 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12685 ins_pipe( pipe_cmov_reg_long );
12686 %}
12687
12688 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12689 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12690 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12691 ins_cost(500);
12692 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12693 "CMOV$cmp $dst.hi,$src.hi+4" %}
12694 opcode(0x0F,0x40);
12695 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12696 ins_pipe( pipe_cmov_reg_long );
12697 %}
12698
12699 // Compare 2 longs and CMOVE ints.
12700 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12701 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12702 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12703 ins_cost(200);
12704 format %{ "CMOV$cmp $dst,$src" %}
12705 opcode(0x0F,0x40);
12706 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12707 ins_pipe( pipe_cmov_reg );
12708 %}
12709
12710 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12711 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12712 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12713 ins_cost(250);
12714 format %{ "CMOV$cmp $dst,$src" %}
12715 opcode(0x0F,0x40);
12716 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12717 ins_pipe( pipe_cmov_mem );
12718 %}
12719
12720 // Compare 2 longs and CMOVE ptrs.
12721 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12722 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12723 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12724 ins_cost(200);
12725 format %{ "CMOV$cmp $dst,$src" %}
12726 opcode(0x0F,0x40);
12727 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12728 ins_pipe( pipe_cmov_reg );
12729 %}
12730
12731 // Compare 2 longs and CMOVE doubles
12732 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12733 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12734 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12735 ins_cost(200);
12736 expand %{
12737 fcmovDPR_regS(cmp,flags,dst,src);
12738 %}
12739 %}
12740
12741 // Compare 2 longs and CMOVE doubles
12742 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12743 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12744 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12745 ins_cost(200);
12746 expand %{
12747 fcmovD_regS(cmp,flags,dst,src);
12748 %}
12749 %}
12750
12751 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12752 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12753 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12754 ins_cost(200);
12755 expand %{
12756 fcmovFPR_regS(cmp,flags,dst,src);
12757 %}
12758 %}
12759
12760
12761 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12762 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12763 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12764 ins_cost(200);
12765 expand %{
12766 fcmovF_regS(cmp,flags,dst,src);
12767 %}
12768 %}
12769
12770
12771 // ============================================================================
12772 // Procedure Call/Return Instructions
12773 // Call Java Static Instruction
12774 // Note: If this code changes, the corresponding ret_addr_offset() and
12775 // compute_padding() functions will have to be adjusted.
12776 instruct CallStaticJavaDirect(method meth) %{
12777 match(CallStaticJava);
12778 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12779 effect(USE meth);
12780
12781 ins_cost(300);
12782 format %{ "CALL,static " %}
12783 opcode(0xE8); /* E8 cd */
12784 ins_encode( pre_call_FPU,
12785 Java_Static_Call( meth ),
12786 call_epilog,
12787 post_call_FPU );
12788 ins_pipe( pipe_slow );
12789 ins_alignment(4);
12790 %}
12791
12792 // Call Java Static Instruction (method handle version)
12793 // Note: If this code changes, the corresponding ret_addr_offset() and
12794 // compute_padding() functions will have to be adjusted.
12795 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12796 match(CallStaticJava);
12797 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12798 effect(USE meth);
12799 // EBP is saved by all callees (for interpreter stack correction).
12800 // We use it here for a similar purpose, in {preserve,restore}_SP.
12801
12802 ins_cost(300);
12803 format %{ "CALL,static/MethodHandle " %}
12804 opcode(0xE8); /* E8 cd */
12805 ins_encode( pre_call_FPU,
12806 preserve_SP,
12807 Java_Static_Call( meth ),
12808 restore_SP,
12809 call_epilog,
12810 post_call_FPU );
12811 ins_pipe( pipe_slow );
12812 ins_alignment(4);
12813 %}
12814
12815 // Call Java Dynamic Instruction
12816 // Note: If this code changes, the corresponding ret_addr_offset() and
12817 // compute_padding() functions will have to be adjusted.
12818 instruct CallDynamicJavaDirect(method meth) %{
12819 match(CallDynamicJava);
12820 effect(USE meth);
12821
12822 ins_cost(300);
12823 format %{ "MOV EAX,(oop)-1\n\t"
12824 "CALL,dynamic" %}
12825 opcode(0xE8); /* E8 cd */
12826 ins_encode( pre_call_FPU,
12827 Java_Dynamic_Call( meth ),
12828 call_epilog,
12829 post_call_FPU );
12830 ins_pipe( pipe_slow );
12831 ins_alignment(4);
12832 %}
12833
12834 // Call Runtime Instruction
12835 instruct CallRuntimeDirect(method meth) %{
12836 match(CallRuntime );
12837 effect(USE meth);
12838
12839 ins_cost(300);
12840 format %{ "CALL,runtime " %}
12841 opcode(0xE8); /* E8 cd */
12842 // Use FFREEs to clear entries in float stack
12843 ins_encode( pre_call_FPU,
12844 FFree_Float_Stack_All,
12845 Java_To_Runtime( meth ),
12846 post_call_FPU );
12847 ins_pipe( pipe_slow );
12848 %}
12849
12850 // Call runtime without safepoint
12851 instruct CallLeafDirect(method meth) %{
12852 match(CallLeaf);
12853 effect(USE meth);
12854
12855 ins_cost(300);
12856 format %{ "CALL_LEAF,runtime " %}
12857 opcode(0xE8); /* E8 cd */
12858 ins_encode( pre_call_FPU,
12859 FFree_Float_Stack_All,
12860 Java_To_Runtime( meth ),
12861 Verify_FPU_For_Leaf, post_call_FPU );
12862 ins_pipe( pipe_slow );
12863 %}
12864
12865 instruct CallLeafNoFPDirect(method meth) %{
12866 match(CallLeafNoFP);
12867 effect(USE meth);
12868
12869 ins_cost(300);
12870 format %{ "CALL_LEAF_NOFP,runtime " %}
12871 opcode(0xE8); /* E8 cd */
12872 ins_encode(Java_To_Runtime(meth));
12873 ins_pipe( pipe_slow );
12874 %}
12875
12876
12877 // Return Instruction
12878 // Remove the return address & jump to it.
12879 instruct Ret() %{
12880 match(Return);
12881 format %{ "RET" %}
12882 opcode(0xC3);
12883 ins_encode(OpcP);
12884 ins_pipe( pipe_jmp );
12885 %}
12886
12887 // Tail Call; Jump from runtime stub to Java code.
12888 // Also known as an 'interprocedural jump'.
12889 // Target of jump will eventually return to caller.
12890 // TailJump below removes the return address.
12891 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12892 match(TailCall jump_target method_oop );
12893 ins_cost(300);
12894 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12895 opcode(0xFF, 0x4); /* Opcode FF /4 */
12896 ins_encode( OpcP, RegOpc(jump_target) );
12897 ins_pipe( pipe_jmp );
12898 %}
12899
12900
12901 // Tail Jump; remove the return address; jump to target.
12902 // TailCall above leaves the return address around.
12903 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12904 match( TailJump jump_target ex_oop );
12905 ins_cost(300);
12906 format %{ "POP EDX\t# pop return address into dummy\n\t"
12907 "JMP $jump_target " %}
12908 opcode(0xFF, 0x4); /* Opcode FF /4 */
12909 ins_encode( enc_pop_rdx,
12910 OpcP, RegOpc(jump_target) );
12911 ins_pipe( pipe_jmp );
12912 %}
12913
12914 // Create exception oop: created by stack-crawling runtime code.
12915 // Created exception is now available to this handler, and is setup
12916 // just prior to jumping to this handler. No code emitted.
12917 instruct CreateException( eAXRegP ex_oop )
12918 %{
12919 match(Set ex_oop (CreateEx));
12920
12921 size(0);
12922 // use the following format syntax
12923 format %{ "# exception oop is in EAX; no code emitted" %}
12924 ins_encode();
12925 ins_pipe( empty );
12926 %}
12927
12928
12929 // Rethrow exception:
12930 // The exception oop will come in the first argument position.
12931 // Then JUMP (not call) to the rethrow stub code.
12932 instruct RethrowException()
12933 %{
12934 match(Rethrow);
12935
12936 // use the following format syntax
12937 format %{ "JMP rethrow_stub" %}
12938 ins_encode(enc_rethrow);
12939 ins_pipe( pipe_jmp );
12940 %}
12941
12942 // inlined locking and unlocking
12943
12944
12945 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12946 match( Set cr (FastLock object box) );
12947 effect( TEMP tmp, TEMP scr, USE_KILL box );
12948 ins_cost(300);
12949 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12950 ins_encode( Fast_Lock(object,box,tmp,scr) );
12951 ins_pipe( pipe_slow );
12952 %}
12953
12954 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12955 match( Set cr (FastUnlock object box) );
12956 effect( TEMP tmp, USE_KILL box );
12957 ins_cost(300);
12958 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
12959 ins_encode( Fast_Unlock(object,box,tmp) );
12960 ins_pipe( pipe_slow );
12961 %}
12962
12963
12964
12965 // ============================================================================
12966 // Safepoint Instruction
12967 instruct safePoint_poll(eFlagsReg cr) %{
12968 match(SafePoint);
12969 effect(KILL cr);
12970
12971 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
12972 // On SPARC that might be acceptable as we can generate the address with
12973 // just a sethi, saving an or. By polling at offset 0 we can end up
12974 // putting additional pressure on the index-0 in the D$. Because of
12975 // alignment (just like the situation at hand) the lower indices tend
12976 // to see more traffic. It'd be better to change the polling address
12977 // to offset 0 of the last $line in the polling page.
12978
12979 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
12980 ins_cost(125);
12981 size(6) ;
12982 ins_encode( Safepoint_Poll() );
12983 ins_pipe( ialu_reg_mem );
12984 %}
12985
12986
12987 // ============================================================================
12988 // This name is KNOWN by the ADLC and cannot be changed.
12989 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12990 // for this guy.
12991 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
12992 match(Set dst (ThreadLocal));
12993 effect(DEF dst, KILL cr);
12994
12995 format %{ "MOV $dst, Thread::current()" %}
12996 ins_encode %{
12997 Register dstReg = as_Register($dst$$reg);
12998 __ get_thread(dstReg);
12999 %}
13000 ins_pipe( ialu_reg_fat );
13001 %}
13002
13003
13004
13005 //----------PEEPHOLE RULES-----------------------------------------------------
13006 // These must follow all instruction definitions as they use the names
13007 // defined in the instructions definitions.
13008 //
13009 // peepmatch ( root_instr_name [preceding_instruction]* );
13010 //
13011 // peepconstraint %{
13012 // (instruction_number.operand_name relational_op instruction_number.operand_name
13013 // [, ...] );
13014 // // instruction numbers are zero-based using left to right order in peepmatch
13015 //
13016 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13017 // // provide an instruction_number.operand_name for each operand that appears
13018 // // in the replacement instruction's match rule
13019 //
13020 // ---------VM FLAGS---------------------------------------------------------
13021 //
13022 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13023 //
13024 // Each peephole rule is given an identifying number starting with zero and
13025 // increasing by one in the order seen by the parser. An individual peephole
13026 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13027 // on the command-line.
13028 //
13029 // ---------CURRENT LIMITATIONS----------------------------------------------
13030 //
13031 // Only match adjacent instructions in same basic block
13032 // Only equality constraints
13033 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13034 // Only one replacement instruction
13035 //
13036 // ---------EXAMPLE----------------------------------------------------------
13037 //
13038 // // pertinent parts of existing instructions in architecture description
13039 // instruct movI(rRegI dst, rRegI src) %{
13040 // match(Set dst (CopyI src));
13041 // %}
13042 //
13043 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13044 // match(Set dst (AddI dst src));
13045 // effect(KILL cr);
13046 // %}
13047 //
13048 // // Change (inc mov) to lea
13049 // peephole %{
13050 // // increment preceeded by register-register move
13051 // peepmatch ( incI_eReg movI );
13052 // // require that the destination register of the increment
13053 // // match the destination register of the move
13054 // peepconstraint ( 0.dst == 1.dst );
13055 // // construct a replacement instruction that sets
13056 // // the destination to ( move's source register + one )
13057 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13058 // %}
13059 //
13060 // Implementation no longer uses movX instructions since
13061 // machine-independent system no longer uses CopyX nodes.
13062 //
13063 // peephole %{
13064 // peepmatch ( incI_eReg movI );
13065 // peepconstraint ( 0.dst == 1.dst );
13066 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13067 // %}
13068 //
13069 // peephole %{
13070 // peepmatch ( decI_eReg movI );
13071 // peepconstraint ( 0.dst == 1.dst );
13072 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13073 // %}
13074 //
13075 // peephole %{
13076 // peepmatch ( addI_eReg_imm movI );
13077 // peepconstraint ( 0.dst == 1.dst );
13078 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13079 // %}
13080 //
13081 // peephole %{
13082 // peepmatch ( addP_eReg_imm movP );
13083 // peepconstraint ( 0.dst == 1.dst );
13084 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13085 // %}
13086
13087 // // Change load of spilled value to only a spill
13088 // instruct storeI(memory mem, rRegI src) %{
13089 // match(Set mem (StoreI mem src));
13090 // %}
13091 //
13092 // instruct loadI(rRegI dst, memory mem) %{
13093 // match(Set dst (LoadI mem));
13094 // %}
13095 //
13096 peephole %{
13097 peepmatch ( loadI storeI );
13098 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13099 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13100 %}
13101
13102 //----------SMARTSPILL RULES---------------------------------------------------
13103 // These must follow all instruction definitions as they use the names
13104 // defined in the instructions definitions.