1 //
2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_FPU_size() {
232 if (Compile::current()->in_24_bit_fp_mode())
233 return 6; // fldcw
234 return 0;
235 }
236
237 static int preserve_SP_size() {
238 return 2; // op, rm(reg/reg)
239 }
240
241 // !!!!! Special hack to get all type of calls to specify the byte offset
242 // from the start of the call to the point where the return address
243 // will point.
244 int MachCallStaticJavaNode::ret_addr_offset() {
245 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points
246 if (_method_handle_invoke)
247 offset += preserve_SP_size();
248 return offset;
249 }
250
251 int MachCallDynamicJavaNode::ret_addr_offset() {
252 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points
253 }
254
255 static int sizeof_FFree_Float_Stack_All = -1;
256
257 int MachCallRuntimeNode::ret_addr_offset() {
258 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
259 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size();
260 }
261
262 // Indicate if the safepoint node needs the polling page as an input.
263 // Since x86 does have absolute addressing, it doesn't.
264 bool SafePointNode::needs_polling_address_input() {
265 return false;
266 }
267
268 //
269 // Compute padding required for nodes which need alignment
270 //
271
272 // The address of the call instruction needs to be 4-byte aligned to
273 // ensure that it does not span a cache line so that it can be patched.
274 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
275 current_offset += pre_call_FPU_size(); // skip fldcw, if any
276 current_offset += 1; // skip call opcode byte
277 return round_to(current_offset, alignment_required()) - current_offset;
278 }
279
280 // The address of the call instruction needs to be 4-byte aligned to
281 // ensure that it does not span a cache line so that it can be patched.
282 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
283 current_offset += pre_call_FPU_size(); // skip fldcw, if any
284 current_offset += preserve_SP_size(); // skip mov rbp, rsp
285 current_offset += 1; // skip call opcode byte
286 return round_to(current_offset, alignment_required()) - current_offset;
287 }
288
289 // The address of the call instruction needs to be 4-byte aligned to
290 // ensure that it does not span a cache line so that it can be patched.
291 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
292 current_offset += pre_call_FPU_size(); // skip fldcw, if any
293 current_offset += 5; // skip MOV instruction
294 current_offset += 1; // skip call opcode byte
295 return round_to(current_offset, alignment_required()) - current_offset;
296 }
297
298 // EMIT_RM()
299 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
300 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
301 cbuf.insts()->emit_int8(c);
302 }
303
304 // EMIT_CC()
305 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
306 unsigned char c = (unsigned char)( f1 | f2 );
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_OPCODE()
311 void emit_opcode(CodeBuffer &cbuf, int code) {
312 cbuf.insts()->emit_int8((unsigned char) code);
313 }
314
315 // EMIT_OPCODE() w/ relocation information
316 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
317 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
318 emit_opcode(cbuf, code);
319 }
320
321 // EMIT_D8()
322 void emit_d8(CodeBuffer &cbuf, int d8) {
323 cbuf.insts()->emit_int8((unsigned char) d8);
324 }
325
326 // EMIT_D16()
327 void emit_d16(CodeBuffer &cbuf, int d16) {
328 cbuf.insts()->emit_int16(d16);
329 }
330
331 // EMIT_D32()
332 void emit_d32(CodeBuffer &cbuf, int d32) {
333 cbuf.insts()->emit_int32(d32);
334 }
335
336 // emit 32 bit value and construct relocation entry from relocInfo::relocType
337 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
338 int format) {
339 cbuf.relocate(cbuf.insts_mark(), reloc, format);
340 cbuf.insts()->emit_int32(d32);
341 }
342
343 // emit 32 bit value and construct relocation entry from RelocationHolder
344 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
345 int format) {
346 #ifdef ASSERT
347 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
348 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
349 }
350 #endif
351 cbuf.relocate(cbuf.insts_mark(), rspec, format);
352 cbuf.insts()->emit_int32(d32);
353 }
354
355 // Access stack slot for load or store
356 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
357 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
358 if( -128 <= disp && disp <= 127 ) {
359 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
360 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
361 emit_d8 (cbuf, disp); // Displacement // R/M byte
362 } else {
363 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
364 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
365 emit_d32(cbuf, disp); // Displacement // R/M byte
366 }
367 }
368
369 // rRegI ereg, memory mem) %{ // emit_reg_mem
370 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
371 // There is no index & no scale, use form without SIB byte
372 if ((index == 0x4) &&
373 (scale == 0) && (base != ESP_enc)) {
374 // If no displacement, mode is 0x0; unless base is [EBP]
375 if ( (displace == 0) && (base != EBP_enc) ) {
376 emit_rm(cbuf, 0x0, reg_encoding, base);
377 }
378 else { // If 8-bit displacement, mode 0x1
379 if ((displace >= -128) && (displace <= 127)
380 && !(displace_is_oop) ) {
381 emit_rm(cbuf, 0x1, reg_encoding, base);
382 emit_d8(cbuf, displace);
383 }
384 else { // If 32-bit displacement
385 if (base == -1) { // Special flag for absolute address
386 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
387 // (manual lies; no SIB needed here)
388 if ( displace_is_oop ) {
389 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
390 } else {
391 emit_d32 (cbuf, displace);
392 }
393 }
394 else { // Normal base + offset
395 emit_rm(cbuf, 0x2, reg_encoding, base);
396 if ( displace_is_oop ) {
397 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
398 } else {
399 emit_d32 (cbuf, displace);
400 }
401 }
402 }
403 }
404 }
405 else { // Else, encode with the SIB byte
406 // If no displacement, mode is 0x0; unless base is [EBP]
407 if (displace == 0 && (base != EBP_enc)) { // If no displacement
408 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
409 emit_rm(cbuf, scale, index, base);
410 }
411 else { // If 8-bit displacement, mode 0x1
412 if ((displace >= -128) && (displace <= 127)
413 && !(displace_is_oop) ) {
414 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 emit_d8(cbuf, displace);
417 }
418 else { // If 32-bit displacement
419 if (base == 0x04 ) {
420 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, 0x04);
422 } else {
423 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
424 emit_rm(cbuf, scale, index, base);
425 }
426 if ( displace_is_oop ) {
427 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
428 } else {
429 emit_d32 (cbuf, displace);
430 }
431 }
432 }
433 }
434 }
435
436
437 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
438 if( dst_encoding == src_encoding ) {
439 // reg-reg copy, use an empty encoding
440 } else {
441 emit_opcode( cbuf, 0x8B );
442 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
443 }
444 }
445
446 void emit_cmpfp_fixup(MacroAssembler& _masm) {
447 Label exit;
448 __ jccb(Assembler::noParity, exit);
449 __ pushf();
450 //
451 // comiss/ucomiss instructions set ZF,PF,CF flags and
452 // zero OF,AF,SF for NaN values.
453 // Fixup flags by zeroing ZF,PF so that compare of NaN
454 // values returns 'less than' result (CF is set).
455 // Leave the rest of flags unchanged.
456 //
457 // 7 6 5 4 3 2 1 0
458 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
459 // 0 0 1 0 1 0 1 1 (0x2B)
460 //
461 __ andl(Address(rsp, 0), 0xffffff2b);
462 __ popf();
463 __ bind(exit);
464 }
465
466 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
467 Label done;
468 __ movl(dst, -1);
469 __ jcc(Assembler::parity, done);
470 __ jcc(Assembler::below, done);
471 __ setb(Assembler::notEqual, dst);
472 __ movzbl(dst, dst);
473 __ bind(done);
474 }
475
476
477 //=============================================================================
478 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
479
480 int Compile::ConstantTable::calculate_table_base_offset() const {
481 return 0; // absolute addressing, no offset
482 }
483
484 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
485 // Empty encoding
486 }
487
488 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
489 return 0;
490 }
491
492 #ifndef PRODUCT
493 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
494 st->print("# MachConstantBaseNode (empty encoding)");
495 }
496 #endif
497
498
499 //=============================================================================
500 #ifndef PRODUCT
501 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
502 Compile* C = ra_->C;
503
504 int framesize = C->frame_slots() << LogBytesPerInt;
505 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
506 // Remove wordSize for return addr which is already pushed.
507 framesize -= wordSize;
508
509 if (C->need_stack_bang(framesize)) {
510 framesize -= wordSize;
511 st->print("# stack bang");
512 st->print("\n\t");
513 st->print("PUSH EBP\t# Save EBP");
514 if (framesize) {
515 st->print("\n\t");
516 st->print("SUB ESP, #%d\t# Create frame",framesize);
517 }
518 } else {
519 st->print("SUB ESP, #%d\t# Create frame",framesize);
520 st->print("\n\t");
521 framesize -= wordSize;
522 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
523 }
524
525 if (VerifyStackAtCalls) {
526 st->print("\n\t");
527 framesize -= wordSize;
528 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
529 }
530
531 if( C->in_24_bit_fp_mode() ) {
532 st->print("\n\t");
533 st->print("FLDCW \t# load 24 bit fpu control word");
534 }
535 if (UseSSE >= 2 && VerifyFPU) {
536 st->print("\n\t");
537 st->print("# verify FPU stack (must be clean on entry)");
538 }
539
540 #ifdef ASSERT
541 if (VerifyStackAtCalls) {
542 st->print("\n\t");
543 st->print("# stack alignment check");
544 }
545 #endif
546 st->cr();
547 }
548 #endif
549
550
551 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
552 Compile* C = ra_->C;
553 MacroAssembler _masm(&cbuf);
554
555 int framesize = C->frame_slots() << LogBytesPerInt;
556
557 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
558
559 C->set_frame_complete(cbuf.insts_size());
560
561 if (C->has_mach_constant_base_node()) {
562 // NOTE: We set the table base offset here because users might be
563 // emitted before MachConstantBaseNode.
564 Compile::ConstantTable& constant_table = C->constant_table();
565 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
566 }
567 }
568
569 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
570 return MachNode::size(ra_); // too many variables; just compute it the hard way
571 }
572
573 int MachPrologNode::reloc() const {
574 return 0; // a large enough number
575 }
576
577 //=============================================================================
578 #ifndef PRODUCT
579 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
580 Compile *C = ra_->C;
581 int framesize = C->frame_slots() << LogBytesPerInt;
582 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
583 // Remove two words for return addr and rbp,
584 framesize -= 2*wordSize;
585
586 if( C->in_24_bit_fp_mode() ) {
587 st->print("FLDCW standard control word");
588 st->cr(); st->print("\t");
589 }
590 if( framesize ) {
591 st->print("ADD ESP,%d\t# Destroy frame",framesize);
592 st->cr(); st->print("\t");
593 }
594 st->print_cr("POPL EBP"); st->print("\t");
595 if( do_polling() && C->is_method_compilation() ) {
596 st->print("TEST PollPage,EAX\t! Poll Safepoint");
597 st->cr(); st->print("\t");
598 }
599 }
600 #endif
601
602 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
603 Compile *C = ra_->C;
604
605 // If method set FPU control word, restore to standard control word
606 if( C->in_24_bit_fp_mode() ) {
607 MacroAssembler masm(&cbuf);
608 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
609 }
610
611 int framesize = C->frame_slots() << LogBytesPerInt;
612 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
613 // Remove two words for return addr and rbp,
614 framesize -= 2*wordSize;
615
616 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
617
618 if( framesize >= 128 ) {
619 emit_opcode(cbuf, 0x81); // add SP, #framesize
620 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
621 emit_d32(cbuf, framesize);
622 }
623 else if( framesize ) {
624 emit_opcode(cbuf, 0x83); // add SP, #framesize
625 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
626 emit_d8(cbuf, framesize);
627 }
628
629 emit_opcode(cbuf, 0x58 | EBP_enc);
630
631 if( do_polling() && C->is_method_compilation() ) {
632 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
633 emit_opcode(cbuf,0x85);
634 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
635 emit_d32(cbuf, (intptr_t)os::get_polling_page());
636 }
637 }
638
639 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
640 Compile *C = ra_->C;
641 // If method set FPU control word, restore to standard control word
642 int size = C->in_24_bit_fp_mode() ? 6 : 0;
643 if( do_polling() && C->is_method_compilation() ) size += 6;
644
645 int framesize = C->frame_slots() << LogBytesPerInt;
646 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
647 // Remove two words for return addr and rbp,
648 framesize -= 2*wordSize;
649
650 size++; // popl rbp,
651
652 if( framesize >= 128 ) {
653 size += 6;
654 } else {
655 size += framesize ? 3 : 0;
656 }
657 return size;
658 }
659
660 int MachEpilogNode::reloc() const {
661 return 0; // a large enough number
662 }
663
664 const Pipeline * MachEpilogNode::pipeline() const {
665 return MachNode::pipeline_class();
666 }
667
668 int MachEpilogNode::safepoint_offset() const { return 0; }
669
670 //=============================================================================
671
672 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
673 static enum RC rc_class( OptoReg::Name reg ) {
674
675 if( !OptoReg::is_valid(reg) ) return rc_bad;
676 if (OptoReg::is_stack(reg)) return rc_stack;
677
678 VMReg r = OptoReg::as_VMReg(reg);
679 if (r->is_Register()) return rc_int;
680 if (r->is_FloatRegister()) {
681 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
682 return rc_float;
683 }
684 assert(r->is_XMMRegister(), "must be");
685 return rc_xmm;
686 }
687
688 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
689 int opcode, const char *op_str, int size, outputStream* st ) {
690 if( cbuf ) {
691 emit_opcode (*cbuf, opcode );
692 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
693 #ifndef PRODUCT
694 } else if( !do_size ) {
695 if( size != 0 ) st->print("\n\t");
696 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
697 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
698 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
699 } else { // FLD, FST, PUSH, POP
700 st->print("%s [ESP + #%d]",op_str,offset);
701 }
702 #endif
703 }
704 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
705 return size+3+offset_size;
706 }
707
708 // Helper for XMM registers. Extra opcode bits, limited syntax.
709 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
710 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
711 if (cbuf) {
712 MacroAssembler _masm(cbuf);
713 if (reg_lo+1 == reg_hi) { // double move?
714 if (is_load) {
715 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
716 } else {
717 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
718 }
719 } else {
720 if (is_load) {
721 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
722 } else {
723 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
724 }
725 }
726 #ifndef PRODUCT
727 } else if (!do_size) {
728 if (size != 0) st->print("\n\t");
729 if (reg_lo+1 == reg_hi) { // double move?
730 if (is_load) st->print("%s %s,[ESP + #%d]",
731 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
732 Matcher::regName[reg_lo], offset);
733 else st->print("MOVSD [ESP + #%d],%s",
734 offset, Matcher::regName[reg_lo]);
735 } else {
736 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
737 Matcher::regName[reg_lo], offset);
738 else st->print("MOVSS [ESP + #%d],%s",
739 offset, Matcher::regName[reg_lo]);
740 }
741 #endif
742 }
743 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
744 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
745 return size+5+offset_size;
746 }
747
748
749 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
750 int src_hi, int dst_hi, int size, outputStream* st ) {
751 if (cbuf) {
752 MacroAssembler _masm(cbuf);
753 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
754 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
755 as_XMMRegister(Matcher::_regEncode[src_lo]));
756 } else {
757 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
758 as_XMMRegister(Matcher::_regEncode[src_lo]));
759 }
760 #ifndef PRODUCT
761 } else if (!do_size) {
762 if (size != 0) st->print("\n\t");
763 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
764 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
765 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
766 } else {
767 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
768 }
769 } else {
770 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
771 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
772 } else {
773 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
774 }
775 }
776 #endif
777 }
778 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
779 // Only MOVAPS SSE prefix uses 1 byte.
780 int sz = 4;
781 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
782 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
783 return size + sz;
784 }
785
786 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
787 int src_hi, int dst_hi, int size, outputStream* st ) {
788 // 32-bit
789 if (cbuf) {
790 MacroAssembler _masm(cbuf);
791 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
792 as_Register(Matcher::_regEncode[src_lo]));
793 #ifndef PRODUCT
794 } else if (!do_size) {
795 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
796 #endif
797 }
798 return 4;
799 }
800
801
802 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
803 int src_hi, int dst_hi, int size, outputStream* st ) {
804 // 32-bit
805 if (cbuf) {
806 MacroAssembler _masm(cbuf);
807 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
808 as_XMMRegister(Matcher::_regEncode[src_lo]));
809 #ifndef PRODUCT
810 } else if (!do_size) {
811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
812 #endif
813 }
814 return 4;
815 }
816
817 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
818 if( cbuf ) {
819 emit_opcode(*cbuf, 0x8B );
820 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
821 #ifndef PRODUCT
822 } else if( !do_size ) {
823 if( size != 0 ) st->print("\n\t");
824 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
825 #endif
826 }
827 return size+2;
828 }
829
830 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
831 int offset, int size, outputStream* st ) {
832 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
833 if( cbuf ) {
834 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
835 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
836 #ifndef PRODUCT
837 } else if( !do_size ) {
838 if( size != 0 ) st->print("\n\t");
839 st->print("FLD %s",Matcher::regName[src_lo]);
840 #endif
841 }
842 size += 2;
843 }
844
845 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
846 const char *op_str;
847 int op;
848 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
849 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
850 op = 0xDD;
851 } else { // 32-bit store
852 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
853 op = 0xD9;
854 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
855 }
856
857 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
858 }
859
860 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
861 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
862 int src_hi, int dst_hi, uint ireg, outputStream* st);
863
864 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
865 int stack_offset, int reg, uint ireg, outputStream* st);
866
867 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
868 int dst_offset, uint ireg, outputStream* st) {
869 int calc_size = 0;
870 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
871 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
872 switch (ireg) {
873 case Op_VecS:
874 calc_size = 3+src_offset_size + 3+dst_offset_size;
875 break;
876 case Op_VecD:
877 calc_size = 3+src_offset_size + 3+dst_offset_size;
878 src_offset += 4;
879 dst_offset += 4;
880 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
881 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
882 calc_size += 3+src_offset_size + 3+dst_offset_size;
883 break;
884 case Op_VecX:
885 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
886 break;
887 case Op_VecY:
888 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
889 break;
890 default:
891 ShouldNotReachHere();
892 }
893 if (cbuf) {
894 MacroAssembler _masm(cbuf);
895 int offset = __ offset();
896 switch (ireg) {
897 case Op_VecS:
898 __ pushl(Address(rsp, src_offset));
899 __ popl (Address(rsp, dst_offset));
900 break;
901 case Op_VecD:
902 __ pushl(Address(rsp, src_offset));
903 __ popl (Address(rsp, dst_offset));
904 __ pushl(Address(rsp, src_offset+4));
905 __ popl (Address(rsp, dst_offset+4));
906 break;
907 case Op_VecX:
908 __ movdqu(Address(rsp, -16), xmm0);
909 __ movdqu(xmm0, Address(rsp, src_offset));
910 __ movdqu(Address(rsp, dst_offset), xmm0);
911 __ movdqu(xmm0, Address(rsp, -16));
912 break;
913 case Op_VecY:
914 __ vmovdqu(Address(rsp, -32), xmm0);
915 __ vmovdqu(xmm0, Address(rsp, src_offset));
916 __ vmovdqu(Address(rsp, dst_offset), xmm0);
917 __ vmovdqu(xmm0, Address(rsp, -32));
918 break;
919 default:
920 ShouldNotReachHere();
921 }
922 int size = __ offset() - offset;
923 assert(size == calc_size, "incorrect size calculattion");
924 return size;
925 #ifndef PRODUCT
926 } else if (!do_size) {
927 switch (ireg) {
928 case Op_VecS:
929 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
930 "popl [rsp + #%d]",
931 src_offset, dst_offset);
932 break;
933 case Op_VecD:
934 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
935 "popq [rsp + #%d]\n\t"
936 "pushl [rsp + #%d]\n\t"
937 "popq [rsp + #%d]",
938 src_offset, dst_offset, src_offset+4, dst_offset+4);
939 break;
940 case Op_VecX:
941 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
942 "movdqu xmm0, [rsp + #%d]\n\t"
943 "movdqu [rsp + #%d], xmm0\n\t"
944 "movdqu xmm0, [rsp - #16]",
945 src_offset, dst_offset);
946 break;
947 case Op_VecY:
948 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
949 "vmovdqu xmm0, [rsp + #%d]\n\t"
950 "vmovdqu [rsp + #%d], xmm0\n\t"
951 "vmovdqu xmm0, [rsp - #32]",
952 src_offset, dst_offset);
953 break;
954 default:
955 ShouldNotReachHere();
956 }
957 #endif
958 }
959 return calc_size;
960 }
961
962 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
963 // Get registers to move
964 OptoReg::Name src_second = ra_->get_reg_second(in(1));
965 OptoReg::Name src_first = ra_->get_reg_first(in(1));
966 OptoReg::Name dst_second = ra_->get_reg_second(this );
967 OptoReg::Name dst_first = ra_->get_reg_first(this );
968
969 enum RC src_second_rc = rc_class(src_second);
970 enum RC src_first_rc = rc_class(src_first);
971 enum RC dst_second_rc = rc_class(dst_second);
972 enum RC dst_first_rc = rc_class(dst_first);
973
974 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
975
976 // Generate spill code!
977 int size = 0;
978
979 if( src_first == dst_first && src_second == dst_second )
980 return size; // Self copy, no move
981
982 if (bottom_type()->isa_vect() != NULL) {
983 uint ireg = ideal_reg();
984 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
985 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
986 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
987 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
988 // mem -> mem
989 int src_offset = ra_->reg2offset(src_first);
990 int dst_offset = ra_->reg2offset(dst_first);
991 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
992 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
993 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
994 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
995 int stack_offset = ra_->reg2offset(dst_first);
996 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
997 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
998 int stack_offset = ra_->reg2offset(src_first);
999 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1000 } else {
1001 ShouldNotReachHere();
1002 }
1003 }
1004
1005 // --------------------------------------
1006 // Check for mem-mem move. push/pop to move.
1007 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1008 if( src_second == dst_first ) { // overlapping stack copy ranges
1009 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1010 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1011 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1012 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1013 }
1014 // move low bits
1015 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1016 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1017 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1018 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1019 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1020 }
1021 return size;
1022 }
1023
1024 // --------------------------------------
1025 // Check for integer reg-reg copy
1026 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1027 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1028
1029 // Check for integer store
1030 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1031 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1032
1033 // Check for integer load
1034 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1035 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1036
1037 // Check for integer reg-xmm reg copy
1038 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1039 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1040 "no 64 bit integer-float reg moves" );
1041 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1042 }
1043 // --------------------------------------
1044 // Check for float reg-reg copy
1045 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1046 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1047 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1048 if( cbuf ) {
1049
1050 // Note the mucking with the register encode to compensate for the 0/1
1051 // indexing issue mentioned in a comment in the reg_def sections
1052 // for FPR registers many lines above here.
1053
1054 if( src_first != FPR1L_num ) {
1055 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1056 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1057 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1058 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1059 } else {
1060 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1061 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1062 }
1063 #ifndef PRODUCT
1064 } else if( !do_size ) {
1065 if( size != 0 ) st->print("\n\t");
1066 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1067 else st->print( "FST %s", Matcher::regName[dst_first]);
1068 #endif
1069 }
1070 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1071 }
1072
1073 // Check for float store
1074 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1075 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1076 }
1077
1078 // Check for float load
1079 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1080 int offset = ra_->reg2offset(src_first);
1081 const char *op_str;
1082 int op;
1083 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1084 op_str = "FLD_D";
1085 op = 0xDD;
1086 } else { // 32-bit load
1087 op_str = "FLD_S";
1088 op = 0xD9;
1089 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1090 }
1091 if( cbuf ) {
1092 emit_opcode (*cbuf, op );
1093 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
1094 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1095 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1096 #ifndef PRODUCT
1097 } else if( !do_size ) {
1098 if( size != 0 ) st->print("\n\t");
1099 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1100 #endif
1101 }
1102 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1103 return size + 3+offset_size+2;
1104 }
1105
1106 // Check for xmm reg-reg copy
1107 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1108 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1109 (src_first+1 == src_second && dst_first+1 == dst_second),
1110 "no non-adjacent float-moves" );
1111 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1112 }
1113
1114 // Check for xmm reg-integer reg copy
1115 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1116 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1117 "no 64 bit float-integer reg moves" );
1118 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1119 }
1120
1121 // Check for xmm store
1122 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1123 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1124 }
1125
1126 // Check for float xmm load
1127 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1128 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1129 }
1130
1131 // Copy from float reg to xmm reg
1132 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1133 // copy to the top of stack from floating point reg
1134 // and use LEA to preserve flags
1135 if( cbuf ) {
1136 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1137 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1138 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1139 emit_d8(*cbuf,0xF8);
1140 #ifndef PRODUCT
1141 } else if( !do_size ) {
1142 if( size != 0 ) st->print("\n\t");
1143 st->print("LEA ESP,[ESP-8]");
1144 #endif
1145 }
1146 size += 4;
1147
1148 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1149
1150 // Copy from the temp memory to the xmm reg.
1151 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1152
1153 if( cbuf ) {
1154 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1155 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1156 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1157 emit_d8(*cbuf,0x08);
1158 #ifndef PRODUCT
1159 } else if( !do_size ) {
1160 if( size != 0 ) st->print("\n\t");
1161 st->print("LEA ESP,[ESP+8]");
1162 #endif
1163 }
1164 size += 4;
1165 return size;
1166 }
1167
1168 assert( size > 0, "missed a case" );
1169
1170 // --------------------------------------------------------------------
1171 // Check for second bits still needing moving.
1172 if( src_second == dst_second )
1173 return size; // Self copy; no move
1174 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1175
1176 // Check for second word int-int move
1177 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1178 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1179
1180 // Check for second word integer store
1181 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1182 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1183
1184 // Check for second word integer load
1185 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1186 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1187
1188
1189 Unimplemented();
1190 }
1191
1192 #ifndef PRODUCT
1193 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1194 implementation( NULL, ra_, false, st );
1195 }
1196 #endif
1197
1198 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1199 implementation( &cbuf, ra_, false, NULL );
1200 }
1201
1202 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1203 return implementation( NULL, ra_, true, NULL );
1204 }
1205
1206
1207 //=============================================================================
1208 #ifndef PRODUCT
1209 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1210 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1211 int reg = ra_->get_reg_first(this);
1212 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1213 }
1214 #endif
1215
1216 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1217 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1218 int reg = ra_->get_encode(this);
1219 if( offset >= 128 ) {
1220 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1221 emit_rm(cbuf, 0x2, reg, 0x04);
1222 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1223 emit_d32(cbuf, offset);
1224 }
1225 else {
1226 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1227 emit_rm(cbuf, 0x1, reg, 0x04);
1228 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1229 emit_d8(cbuf, offset);
1230 }
1231 }
1232
1233 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1234 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1235 if( offset >= 128 ) {
1236 return 7;
1237 }
1238 else {
1239 return 4;
1240 }
1241 }
1242
1243 //=============================================================================
1244
1245 // emit call stub, compiled java to interpreter
1246 void emit_java_to_interp(CodeBuffer &cbuf ) {
1247 // Stub is fixed up when the corresponding call is converted from calling
1248 // compiled code to calling interpreted code.
1249 // mov rbx,0
1250 // jmp -1
1251
1252 address mark = cbuf.insts_mark(); // get mark within main instrs section
1253
1254 // Note that the code buffer's insts_mark is always relative to insts.
1255 // That's why we must use the macroassembler to generate a stub.
1256 MacroAssembler _masm(&cbuf);
1257
1258 address base =
1259 __ start_a_stub(Compile::MAX_stubs_size);
1260 if (base == NULL) return; // CodeBuffer::expand failed
1261 // static stub relocation stores the instruction address of the call
1262 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1263 // static stub relocation also tags the methodOop in the code-stream.
1264 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1265 // This is recognized as unresolved by relocs/nativeInst/ic code
1266 __ jump(RuntimeAddress(__ pc()));
1267
1268 __ end_a_stub();
1269 // Update current stubs pointer and restore insts_end.
1270 }
1271 // size of call stub, compiled java to interpretor
1272 uint size_java_to_interp() {
1273 return 10; // movl; jmp
1274 }
1275 // relocation entries for call stub, compiled java to interpretor
1276 uint reloc_java_to_interp() {
1277 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1278 }
1279
1280 //=============================================================================
1281 #ifndef PRODUCT
1282 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1283 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1284 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1285 st->print_cr("\tNOP");
1286 st->print_cr("\tNOP");
1287 if( !OptoBreakpoint )
1288 st->print_cr("\tNOP");
1289 }
1290 #endif
1291
1292 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1293 MacroAssembler masm(&cbuf);
1294 #ifdef ASSERT
1295 uint insts_size = cbuf.insts_size();
1296 #endif
1297 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1298 masm.jump_cc(Assembler::notEqual,
1299 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1300 /* WARNING these NOPs are critical so that verified entry point is properly
1301 aligned for patching by NativeJump::patch_verified_entry() */
1302 int nops_cnt = 2;
1303 if( !OptoBreakpoint ) // Leave space for int3
1304 nops_cnt += 1;
1305 masm.nop(nops_cnt);
1306
1307 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1308 }
1309
1310 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1311 return OptoBreakpoint ? 11 : 12;
1312 }
1313
1314
1315 //=============================================================================
1316 uint size_exception_handler() {
1317 // NativeCall instruction size is the same as NativeJump.
1318 // exception handler starts out as jump and can be patched to
1319 // a call be deoptimization. (4932387)
1320 // Note that this value is also credited (in output.cpp) to
1321 // the size of the code section.
1322 return NativeJump::instruction_size;
1323 }
1324
1325 // Emit exception handler code. Stuff framesize into a register
1326 // and call a VM stub routine.
1327 int emit_exception_handler(CodeBuffer& cbuf) {
1328
1329 // Note that the code buffer's insts_mark is always relative to insts.
1330 // That's why we must use the macroassembler to generate a handler.
1331 MacroAssembler _masm(&cbuf);
1332 address base =
1333 __ start_a_stub(size_exception_handler());
1334 if (base == NULL) return 0; // CodeBuffer::expand failed
1335 int offset = __ offset();
1336 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1337 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1338 __ end_a_stub();
1339 return offset;
1340 }
1341
1342 uint size_deopt_handler() {
1343 // NativeCall instruction size is the same as NativeJump.
1344 // exception handler starts out as jump and can be patched to
1345 // a call be deoptimization. (4932387)
1346 // Note that this value is also credited (in output.cpp) to
1347 // the size of the code section.
1348 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1349 }
1350
1351 // Emit deopt handler code.
1352 int emit_deopt_handler(CodeBuffer& cbuf) {
1353
1354 // Note that the code buffer's insts_mark is always relative to insts.
1355 // That's why we must use the macroassembler to generate a handler.
1356 MacroAssembler _masm(&cbuf);
1357 address base =
1358 __ start_a_stub(size_exception_handler());
1359 if (base == NULL) return 0; // CodeBuffer::expand failed
1360 int offset = __ offset();
1361 InternalAddress here(__ pc());
1362 __ pushptr(here.addr());
1363
1364 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1365 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1366 __ end_a_stub();
1367 return offset;
1368 }
1369
1370 int Matcher::regnum_to_fpu_offset(int regnum) {
1371 return regnum - 32; // The FP registers are in the second chunk
1372 }
1373
1374 // This is UltraSparc specific, true just means we have fast l2f conversion
1375 const bool Matcher::convL2FSupported(void) {
1376 return true;
1377 }
1378
1379 // Is this branch offset short enough that a short branch can be used?
1380 //
1381 // NOTE: If the platform does not provide any short branch variants, then
1382 // this method should return false for offset 0.
1383 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1384 // The passed offset is relative to address of the branch.
1385 // On 86 a branch displacement is calculated relative to address
1386 // of a next instruction.
1387 offset -= br_size;
1388
1389 // the short version of jmpConUCF2 contains multiple branches,
1390 // making the reach slightly less
1391 if (rule == jmpConUCF2_rule)
1392 return (-126 <= offset && offset <= 125);
1393 return (-128 <= offset && offset <= 127);
1394 }
1395
1396 const bool Matcher::isSimpleConstant64(jlong value) {
1397 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1398 return false;
1399 }
1400
1401 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1402 const bool Matcher::init_array_count_is_in_bytes = false;
1403
1404 // Threshold size for cleararray.
1405 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1406
1407 // Needs 2 CMOV's for longs.
1408 const int Matcher::long_cmove_cost() { return 1; }
1409
1410 // No CMOVF/CMOVD with SSE/SSE2
1411 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1412
1413 // Should the Matcher clone shifts on addressing modes, expecting them to
1414 // be subsumed into complex addressing expressions or compute them into
1415 // registers? True for Intel but false for most RISCs
1416 const bool Matcher::clone_shift_expressions = true;
1417
1418 // Do we need to mask the count passed to shift instructions or does
1419 // the cpu only look at the lower 5/6 bits anyway?
1420 const bool Matcher::need_masked_shift_count = false;
1421
1422 bool Matcher::narrow_oop_use_complex_address() {
1423 ShouldNotCallThis();
1424 return true;
1425 }
1426
1427
1428 // Is it better to copy float constants, or load them directly from memory?
1429 // Intel can load a float constant from a direct address, requiring no
1430 // extra registers. Most RISCs will have to materialize an address into a
1431 // register first, so they would do better to copy the constant from stack.
1432 const bool Matcher::rematerialize_float_constants = true;
1433
1434 // If CPU can load and store mis-aligned doubles directly then no fixup is
1435 // needed. Else we split the double into 2 integer pieces and move it
1436 // piece-by-piece. Only happens when passing doubles into C code as the
1437 // Java calling convention forces doubles to be aligned.
1438 const bool Matcher::misaligned_doubles_ok = true;
1439
1440
1441 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1442 // Get the memory operand from the node
1443 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1444 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1445 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1446 uint opcnt = 1; // First operand
1447 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1448 while( idx >= skipped+num_edges ) {
1449 skipped += num_edges;
1450 opcnt++; // Bump operand count
1451 assert( opcnt < numopnds, "Accessing non-existent operand" );
1452 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1453 }
1454
1455 MachOper *memory = node->_opnds[opcnt];
1456 MachOper *new_memory = NULL;
1457 switch (memory->opcode()) {
1458 case DIRECT:
1459 case INDOFFSET32X:
1460 // No transformation necessary.
1461 return;
1462 case INDIRECT:
1463 new_memory = new (C) indirect_win95_safeOper( );
1464 break;
1465 case INDOFFSET8:
1466 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1467 break;
1468 case INDOFFSET32:
1469 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1470 break;
1471 case INDINDEXOFFSET:
1472 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1473 break;
1474 case INDINDEXSCALE:
1475 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1476 break;
1477 case INDINDEXSCALEOFFSET:
1478 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1479 break;
1480 case LOAD_LONG_INDIRECT:
1481 case LOAD_LONG_INDOFFSET32:
1482 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1483 return;
1484 default:
1485 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1486 return;
1487 }
1488 node->_opnds[opcnt] = new_memory;
1489 }
1490
1491 // Advertise here if the CPU requires explicit rounding operations
1492 // to implement the UseStrictFP mode.
1493 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1494
1495 // Are floats conerted to double when stored to stack during deoptimization?
1496 // On x32 it is stored with convertion only when FPU is used for floats.
1497 bool Matcher::float_in_double() { return (UseSSE == 0); }
1498
1499 // Do ints take an entire long register or just half?
1500 const bool Matcher::int_in_long = false;
1501
1502 // Return whether or not this register is ever used as an argument. This
1503 // function is used on startup to build the trampoline stubs in generateOptoStub.
1504 // Registers not mentioned will be killed by the VM call in the trampoline, and
1505 // arguments in those registers not be available to the callee.
1506 bool Matcher::can_be_java_arg( int reg ) {
1507 if( reg == ECX_num || reg == EDX_num ) return true;
1508 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1509 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1510 return false;
1511 }
1512
1513 bool Matcher::is_spillable_arg( int reg ) {
1514 return can_be_java_arg(reg);
1515 }
1516
1517 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1518 // Use hardware integer DIV instruction when
1519 // it is faster than a code which use multiply.
1520 // Only when constant divisor fits into 32 bit
1521 // (min_jint is excluded to get only correct
1522 // positive 32 bit values from negative).
1523 return VM_Version::has_fast_idiv() &&
1524 (divisor == (int)divisor && divisor != min_jint);
1525 }
1526
1527 // Register for DIVI projection of divmodI
1528 RegMask Matcher::divI_proj_mask() {
1529 return EAX_REG_mask();
1530 }
1531
1532 // Register for MODI projection of divmodI
1533 RegMask Matcher::modI_proj_mask() {
1534 return EDX_REG_mask();
1535 }
1536
1537 // Register for DIVL projection of divmodL
1538 RegMask Matcher::divL_proj_mask() {
1539 ShouldNotReachHere();
1540 return RegMask();
1541 }
1542
1543 // Register for MODL projection of divmodL
1544 RegMask Matcher::modL_proj_mask() {
1545 ShouldNotReachHere();
1546 return RegMask();
1547 }
1548
1549 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1550 return EBP_REG_mask();
1551 }
1552
1553 // Returns true if the high 32 bits of the value is known to be zero.
1554 bool is_operand_hi32_zero(Node* n) {
1555 int opc = n->Opcode();
1556 if (opc == Op_LoadUI2L) {
1557 return true;
1558 }
1559 if (opc == Op_AndL) {
1560 Node* o2 = n->in(2);
1561 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1562 return true;
1563 }
1564 }
1565 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1566 return true;
1567 }
1568 return false;
1569 }
1570
1571 %}
1572
1573 //----------ENCODING BLOCK-----------------------------------------------------
1574 // This block specifies the encoding classes used by the compiler to output
1575 // byte streams. Encoding classes generate functions which are called by
1576 // Machine Instruction Nodes in order to generate the bit encoding of the
1577 // instruction. Operands specify their base encoding interface with the
1578 // interface keyword. There are currently supported four interfaces,
1579 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1580 // operand to generate a function which returns its register number when
1581 // queried. CONST_INTER causes an operand to generate a function which
1582 // returns the value of the constant when queried. MEMORY_INTER causes an
1583 // operand to generate four functions which return the Base Register, the
1584 // Index Register, the Scale Value, and the Offset Value of the operand when
1585 // queried. COND_INTER causes an operand to generate six functions which
1586 // return the encoding code (ie - encoding bits for the instruction)
1587 // associated with each basic boolean condition for a conditional instruction.
1588 // Instructions specify two basic values for encoding. They use the
1589 // ins_encode keyword to specify their encoding class (which must be one of
1590 // the class names specified in the encoding block), and they use the
1591 // opcode keyword to specify, in order, their primary, secondary, and
1592 // tertiary opcode. Only the opcode sections which a particular instruction
1593 // needs for encoding need to be specified.
1594 encode %{
1595 // Build emit functions for each basic byte or larger field in the intel
1596 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1597 // code in the enc_class source block. Emit functions will live in the
1598 // main source block for now. In future, we can generalize this by
1599 // adding a syntax that specifies the sizes of fields in an order,
1600 // so that the adlc can build the emit functions automagically
1601
1602 // Emit primary opcode
1603 enc_class OpcP %{
1604 emit_opcode(cbuf, $primary);
1605 %}
1606
1607 // Emit secondary opcode
1608 enc_class OpcS %{
1609 emit_opcode(cbuf, $secondary);
1610 %}
1611
1612 // Emit opcode directly
1613 enc_class Opcode(immI d8) %{
1614 emit_opcode(cbuf, $d8$$constant);
1615 %}
1616
1617 enc_class SizePrefix %{
1618 emit_opcode(cbuf,0x66);
1619 %}
1620
1621 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1622 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1623 %}
1624
1625 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1626 emit_opcode(cbuf,$opcode$$constant);
1627 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1628 %}
1629
1630 enc_class mov_r32_imm0( rRegI dst ) %{
1631 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1632 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1633 %}
1634
1635 enc_class cdq_enc %{
1636 // Full implementation of Java idiv and irem; checks for
1637 // special case as described in JVM spec., p.243 & p.271.
1638 //
1639 // normal case special case
1640 //
1641 // input : rax,: dividend min_int
1642 // reg: divisor -1
1643 //
1644 // output: rax,: quotient (= rax, idiv reg) min_int
1645 // rdx: remainder (= rax, irem reg) 0
1646 //
1647 // Code sequnce:
1648 //
1649 // 81 F8 00 00 00 80 cmp rax,80000000h
1650 // 0F 85 0B 00 00 00 jne normal_case
1651 // 33 D2 xor rdx,edx
1652 // 83 F9 FF cmp rcx,0FFh
1653 // 0F 84 03 00 00 00 je done
1654 // normal_case:
1655 // 99 cdq
1656 // F7 F9 idiv rax,ecx
1657 // done:
1658 //
1659 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1660 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1661 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1662 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1663 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1664 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1665 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1666 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1667 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1668 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1669 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1670 // normal_case:
1671 emit_opcode(cbuf,0x99); // cdq
1672 // idiv (note: must be emitted by the user of this rule)
1673 // normal:
1674 %}
1675
1676 // Dense encoding for older common ops
1677 enc_class Opc_plus(immI opcode, rRegI reg) %{
1678 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1679 %}
1680
1681
1682 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1683 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1684 // Check for 8-bit immediate, and set sign extend bit in opcode
1685 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1686 emit_opcode(cbuf, $primary | 0x02);
1687 }
1688 else { // If 32-bit immediate
1689 emit_opcode(cbuf, $primary);
1690 }
1691 %}
1692
1693 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1694 // Emit primary opcode and set sign-extend bit
1695 // Check for 8-bit immediate, and set sign extend bit in opcode
1696 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1697 emit_opcode(cbuf, $primary | 0x02); }
1698 else { // If 32-bit immediate
1699 emit_opcode(cbuf, $primary);
1700 }
1701 // Emit r/m byte with secondary opcode, after primary opcode.
1702 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1703 %}
1704
1705 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1706 // Check for 8-bit immediate, and set sign extend bit in opcode
1707 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1708 $$$emit8$imm$$constant;
1709 }
1710 else { // If 32-bit immediate
1711 // Output immediate
1712 $$$emit32$imm$$constant;
1713 }
1714 %}
1715
1716 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1717 // Emit primary opcode and set sign-extend bit
1718 // Check for 8-bit immediate, and set sign extend bit in opcode
1719 int con = (int)$imm$$constant; // Throw away top bits
1720 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1721 // Emit r/m byte with secondary opcode, after primary opcode.
1722 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1723 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1724 else emit_d32(cbuf,con);
1725 %}
1726
1727 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1728 // Emit primary opcode and set sign-extend bit
1729 // Check for 8-bit immediate, and set sign extend bit in opcode
1730 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1731 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1732 // Emit r/m byte with tertiary opcode, after primary opcode.
1733 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1734 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1735 else emit_d32(cbuf,con);
1736 %}
1737
1738 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1739 emit_cc(cbuf, $secondary, $dst$$reg );
1740 %}
1741
1742 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1743 int destlo = $dst$$reg;
1744 int desthi = HIGH_FROM_LOW(destlo);
1745 // bswap lo
1746 emit_opcode(cbuf, 0x0F);
1747 emit_cc(cbuf, 0xC8, destlo);
1748 // bswap hi
1749 emit_opcode(cbuf, 0x0F);
1750 emit_cc(cbuf, 0xC8, desthi);
1751 // xchg lo and hi
1752 emit_opcode(cbuf, 0x87);
1753 emit_rm(cbuf, 0x3, destlo, desthi);
1754 %}
1755
1756 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1757 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1758 %}
1759
1760 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1761 $$$emit8$primary;
1762 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1763 %}
1764
1765 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1766 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1767 emit_d8(cbuf, op >> 8 );
1768 emit_d8(cbuf, op & 255);
1769 %}
1770
1771 // emulate a CMOV with a conditional branch around a MOV
1772 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1773 // Invert sense of branch from sense of CMOV
1774 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1775 emit_d8( cbuf, $brOffs$$constant );
1776 %}
1777
1778 enc_class enc_PartialSubtypeCheck( ) %{
1779 Register Redi = as_Register(EDI_enc); // result register
1780 Register Reax = as_Register(EAX_enc); // super class
1781 Register Recx = as_Register(ECX_enc); // killed
1782 Register Resi = as_Register(ESI_enc); // sub class
1783 Label miss;
1784
1785 MacroAssembler _masm(&cbuf);
1786 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1787 NULL, &miss,
1788 /*set_cond_codes:*/ true);
1789 if ($primary) {
1790 __ xorptr(Redi, Redi);
1791 }
1792 __ bind(miss);
1793 %}
1794
1795 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1796 MacroAssembler masm(&cbuf);
1797 int start = masm.offset();
1798 if (UseSSE >= 2) {
1799 if (VerifyFPU) {
1800 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1801 }
1802 } else {
1803 // External c_calling_convention expects the FPU stack to be 'clean'.
1804 // Compiled code leaves it dirty. Do cleanup now.
1805 masm.empty_FPU_stack();
1806 }
1807 if (sizeof_FFree_Float_Stack_All == -1) {
1808 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1809 } else {
1810 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1811 }
1812 %}
1813
1814 enc_class Verify_FPU_For_Leaf %{
1815 if( VerifyFPU ) {
1816 MacroAssembler masm(&cbuf);
1817 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1818 }
1819 %}
1820
1821 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1822 // This is the instruction starting address for relocation info.
1823 cbuf.set_insts_mark();
1824 $$$emit8$primary;
1825 // CALL directly to the runtime
1826 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1827 runtime_call_Relocation::spec(), RELOC_IMM32 );
1828
1829 if (UseSSE >= 2) {
1830 MacroAssembler _masm(&cbuf);
1831 BasicType rt = tf()->return_type();
1832
1833 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1834 // A C runtime call where the return value is unused. In SSE2+
1835 // mode the result needs to be removed from the FPU stack. It's
1836 // likely that this function call could be removed by the
1837 // optimizer if the C function is a pure function.
1838 __ ffree(0);
1839 } else if (rt == T_FLOAT) {
1840 __ lea(rsp, Address(rsp, -4));
1841 __ fstp_s(Address(rsp, 0));
1842 __ movflt(xmm0, Address(rsp, 0));
1843 __ lea(rsp, Address(rsp, 4));
1844 } else if (rt == T_DOUBLE) {
1845 __ lea(rsp, Address(rsp, -8));
1846 __ fstp_d(Address(rsp, 0));
1847 __ movdbl(xmm0, Address(rsp, 0));
1848 __ lea(rsp, Address(rsp, 8));
1849 }
1850 }
1851 %}
1852
1853
1854 enc_class pre_call_FPU %{
1855 // If method sets FPU control word restore it here
1856 debug_only(int off0 = cbuf.insts_size());
1857 if( Compile::current()->in_24_bit_fp_mode() ) {
1858 MacroAssembler masm(&cbuf);
1859 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1860 }
1861 debug_only(int off1 = cbuf.insts_size());
1862 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction");
1863 %}
1864
1865 enc_class post_call_FPU %{
1866 // If method sets FPU control word do it here also
1867 if( Compile::current()->in_24_bit_fp_mode() ) {
1868 MacroAssembler masm(&cbuf);
1869 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1870 }
1871 %}
1872
1873 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1874 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1875 // who we intended to call.
1876 cbuf.set_insts_mark();
1877 $$$emit8$primary;
1878 if ( !_method ) {
1879 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1880 runtime_call_Relocation::spec(), RELOC_IMM32 );
1881 } else if(_optimized_virtual) {
1882 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1883 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1884 } else {
1885 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1886 static_call_Relocation::spec(), RELOC_IMM32 );
1887 }
1888 if( _method ) { // Emit stub for static call
1889 emit_java_to_interp(cbuf);
1890 }
1891 %}
1892
1893 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1894 // !!!!!
1895 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1896 // emit_call_dynamic_prologue( cbuf );
1897 cbuf.set_insts_mark();
1898 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1899 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1900 address virtual_call_oop_addr = cbuf.insts_mark();
1901 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1902 // who we intended to call.
1903 cbuf.set_insts_mark();
1904 $$$emit8$primary;
1905 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1906 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1907 %}
1908
1909 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1910 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1911 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1912
1913 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1914 cbuf.set_insts_mark();
1915 $$$emit8$primary;
1916 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1917 emit_d8(cbuf, disp); // Displacement
1918
1919 %}
1920
1921 // Following encoding is no longer used, but may be restored if calling
1922 // convention changes significantly.
1923 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1924 //
1925 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1926 // // int ic_reg = Matcher::inline_cache_reg();
1927 // // int ic_encode = Matcher::_regEncode[ic_reg];
1928 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1929 // // int imo_encode = Matcher::_regEncode[imo_reg];
1930 //
1931 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1932 // // // so we load it immediately before the call
1933 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1934 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1935 //
1936 // // xor rbp,ebp
1937 // emit_opcode(cbuf, 0x33);
1938 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1939 //
1940 // // CALL to interpreter.
1941 // cbuf.set_insts_mark();
1942 // $$$emit8$primary;
1943 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1944 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1945 // %}
1946
1947 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1948 $$$emit8$primary;
1949 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1950 $$$emit8$shift$$constant;
1951 %}
1952
1953 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1954 // Load immediate does not have a zero or sign extended version
1955 // for 8-bit immediates
1956 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1957 $$$emit32$src$$constant;
1958 %}
1959
1960 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1961 // Load immediate does not have a zero or sign extended version
1962 // for 8-bit immediates
1963 emit_opcode(cbuf, $primary + $dst$$reg);
1964 $$$emit32$src$$constant;
1965 %}
1966
1967 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1968 // Load immediate does not have a zero or sign extended version
1969 // for 8-bit immediates
1970 int dst_enc = $dst$$reg;
1971 int src_con = $src$$constant & 0x0FFFFFFFFL;
1972 if (src_con == 0) {
1973 // xor dst, dst
1974 emit_opcode(cbuf, 0x33);
1975 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1976 } else {
1977 emit_opcode(cbuf, $primary + dst_enc);
1978 emit_d32(cbuf, src_con);
1979 }
1980 %}
1981
1982 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1983 // Load immediate does not have a zero or sign extended version
1984 // for 8-bit immediates
1985 int dst_enc = $dst$$reg + 2;
1986 int src_con = ((julong)($src$$constant)) >> 32;
1987 if (src_con == 0) {
1988 // xor dst, dst
1989 emit_opcode(cbuf, 0x33);
1990 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1991 } else {
1992 emit_opcode(cbuf, $primary + dst_enc);
1993 emit_d32(cbuf, src_con);
1994 }
1995 %}
1996
1997
1998 // Encode a reg-reg copy. If it is useless, then empty encoding.
1999 enc_class enc_Copy( rRegI dst, rRegI src ) %{
2000 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2001 %}
2002
2003 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
2004 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2005 %}
2006
2007 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
2008 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2009 %}
2010
2011 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2012 $$$emit8$primary;
2013 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2014 %}
2015
2016 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2017 $$$emit8$secondary;
2018 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2019 %}
2020
2021 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2022 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2023 %}
2024
2025 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2026 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2027 %}
2028
2029 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2030 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2031 %}
2032
2033 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2034 // Output immediate
2035 $$$emit32$src$$constant;
2036 %}
2037
2038 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2039 // Output Float immediate bits
2040 jfloat jf = $src$$constant;
2041 int jf_as_bits = jint_cast( jf );
2042 emit_d32(cbuf, jf_as_bits);
2043 %}
2044
2045 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2046 // Output Float immediate bits
2047 jfloat jf = $src$$constant;
2048 int jf_as_bits = jint_cast( jf );
2049 emit_d32(cbuf, jf_as_bits);
2050 %}
2051
2052 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2053 // Output immediate
2054 $$$emit16$src$$constant;
2055 %}
2056
2057 enc_class Con_d32(immI src) %{
2058 emit_d32(cbuf,$src$$constant);
2059 %}
2060
2061 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2062 // Output immediate memory reference
2063 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2064 emit_d32(cbuf, 0x00);
2065 %}
2066
2067 enc_class lock_prefix( ) %{
2068 if( os::is_MP() )
2069 emit_opcode(cbuf,0xF0); // [Lock]
2070 %}
2071
2072 // Cmp-xchg long value.
2073 // Note: we need to swap rbx, and rcx before and after the
2074 // cmpxchg8 instruction because the instruction uses
2075 // rcx as the high order word of the new value to store but
2076 // our register encoding uses rbx,.
2077 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2078
2079 // XCHG rbx,ecx
2080 emit_opcode(cbuf,0x87);
2081 emit_opcode(cbuf,0xD9);
2082 // [Lock]
2083 if( os::is_MP() )
2084 emit_opcode(cbuf,0xF0);
2085 // CMPXCHG8 [Eptr]
2086 emit_opcode(cbuf,0x0F);
2087 emit_opcode(cbuf,0xC7);
2088 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2089 // XCHG rbx,ecx
2090 emit_opcode(cbuf,0x87);
2091 emit_opcode(cbuf,0xD9);
2092 %}
2093
2094 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2095 // [Lock]
2096 if( os::is_MP() )
2097 emit_opcode(cbuf,0xF0);
2098
2099 // CMPXCHG [Eptr]
2100 emit_opcode(cbuf,0x0F);
2101 emit_opcode(cbuf,0xB1);
2102 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2103 %}
2104
2105 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2106 int res_encoding = $res$$reg;
2107
2108 // MOV res,0
2109 emit_opcode( cbuf, 0xB8 + res_encoding);
2110 emit_d32( cbuf, 0 );
2111 // JNE,s fail
2112 emit_opcode(cbuf,0x75);
2113 emit_d8(cbuf, 5 );
2114 // MOV res,1
2115 emit_opcode( cbuf, 0xB8 + res_encoding);
2116 emit_d32( cbuf, 1 );
2117 // fail:
2118 %}
2119
2120 enc_class set_instruction_start( ) %{
2121 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2122 %}
2123
2124 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2125 int reg_encoding = $ereg$$reg;
2126 int base = $mem$$base;
2127 int index = $mem$$index;
2128 int scale = $mem$$scale;
2129 int displace = $mem$$disp;
2130 bool disp_is_oop = $mem->disp_is_oop();
2131 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2132 %}
2133
2134 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2135 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2136 int base = $mem$$base;
2137 int index = $mem$$index;
2138 int scale = $mem$$scale;
2139 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2140 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2141 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2142 %}
2143
2144 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2145 int r1, r2;
2146 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2147 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2148 emit_opcode(cbuf,0x0F);
2149 emit_opcode(cbuf,$tertiary);
2150 emit_rm(cbuf, 0x3, r1, r2);
2151 emit_d8(cbuf,$cnt$$constant);
2152 emit_d8(cbuf,$primary);
2153 emit_rm(cbuf, 0x3, $secondary, r1);
2154 emit_d8(cbuf,$cnt$$constant);
2155 %}
2156
2157 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2158 emit_opcode( cbuf, 0x8B ); // Move
2159 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2160 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2161 emit_d8(cbuf,$primary);
2162 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2163 emit_d8(cbuf,$cnt$$constant-32);
2164 }
2165 emit_d8(cbuf,$primary);
2166 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2167 emit_d8(cbuf,31);
2168 %}
2169
2170 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2171 int r1, r2;
2172 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2173 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2174
2175 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2176 emit_rm(cbuf, 0x3, r1, r2);
2177 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2178 emit_opcode(cbuf,$primary);
2179 emit_rm(cbuf, 0x3, $secondary, r1);
2180 emit_d8(cbuf,$cnt$$constant-32);
2181 }
2182 emit_opcode(cbuf,0x33); // XOR r2,r2
2183 emit_rm(cbuf, 0x3, r2, r2);
2184 %}
2185
2186 // Clone of RegMem but accepts an extra parameter to access each
2187 // half of a double in memory; it never needs relocation info.
2188 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2189 emit_opcode(cbuf,$opcode$$constant);
2190 int reg_encoding = $rm_reg$$reg;
2191 int base = $mem$$base;
2192 int index = $mem$$index;
2193 int scale = $mem$$scale;
2194 int displace = $mem$$disp + $disp_for_half$$constant;
2195 bool disp_is_oop = false;
2196 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2197 %}
2198
2199 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2200 //
2201 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2202 // and it never needs relocation information.
2203 // Frequently used to move data between FPU's Stack Top and memory.
2204 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2205 int rm_byte_opcode = $rm_opcode$$constant;
2206 int base = $mem$$base;
2207 int index = $mem$$index;
2208 int scale = $mem$$scale;
2209 int displace = $mem$$disp;
2210 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2211 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2212 %}
2213
2214 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2215 int rm_byte_opcode = $rm_opcode$$constant;
2216 int base = $mem$$base;
2217 int index = $mem$$index;
2218 int scale = $mem$$scale;
2219 int displace = $mem$$disp;
2220 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2221 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2222 %}
2223
2224 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2225 int reg_encoding = $dst$$reg;
2226 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2227 int index = 0x04; // 0x04 indicates no index
2228 int scale = 0x00; // 0x00 indicates no scale
2229 int displace = $src1$$constant; // 0x00 indicates no displacement
2230 bool disp_is_oop = false;
2231 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2232 %}
2233
2234 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2235 // Compare dst,src
2236 emit_opcode(cbuf,0x3B);
2237 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2238 // jmp dst < src around move
2239 emit_opcode(cbuf,0x7C);
2240 emit_d8(cbuf,2);
2241 // move dst,src
2242 emit_opcode(cbuf,0x8B);
2243 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2244 %}
2245
2246 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2247 // Compare dst,src
2248 emit_opcode(cbuf,0x3B);
2249 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2250 // jmp dst > src around move
2251 emit_opcode(cbuf,0x7F);
2252 emit_d8(cbuf,2);
2253 // move dst,src
2254 emit_opcode(cbuf,0x8B);
2255 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2256 %}
2257
2258 enc_class enc_FPR_store(memory mem, regDPR src) %{
2259 // If src is FPR1, we can just FST to store it.
2260 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2261 int reg_encoding = 0x2; // Just store
2262 int base = $mem$$base;
2263 int index = $mem$$index;
2264 int scale = $mem$$scale;
2265 int displace = $mem$$disp;
2266 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2267 if( $src$$reg != FPR1L_enc ) {
2268 reg_encoding = 0x3; // Store & pop
2269 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2270 emit_d8( cbuf, 0xC0-1+$src$$reg );
2271 }
2272 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2273 emit_opcode(cbuf,$primary);
2274 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2275 %}
2276
2277 enc_class neg_reg(rRegI dst) %{
2278 // NEG $dst
2279 emit_opcode(cbuf,0xF7);
2280 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2281 %}
2282
2283 enc_class setLT_reg(eCXRegI dst) %{
2284 // SETLT $dst
2285 emit_opcode(cbuf,0x0F);
2286 emit_opcode(cbuf,0x9C);
2287 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2288 %}
2289
2290 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2291 int tmpReg = $tmp$$reg;
2292
2293 // SUB $p,$q
2294 emit_opcode(cbuf,0x2B);
2295 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2296 // SBB $tmp,$tmp
2297 emit_opcode(cbuf,0x1B);
2298 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2299 // AND $tmp,$y
2300 emit_opcode(cbuf,0x23);
2301 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2302 // ADD $p,$tmp
2303 emit_opcode(cbuf,0x03);
2304 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2305 %}
2306
2307 enc_class enc_cmpLTP_mem(rRegI p, rRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2308 int tmpReg = $tmp$$reg;
2309
2310 // SUB $p,$q
2311 emit_opcode(cbuf,0x2B);
2312 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2313 // SBB $tmp,$tmp
2314 emit_opcode(cbuf,0x1B);
2315 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2316 // AND $tmp,$y
2317 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2318 emit_opcode(cbuf,0x23);
2319 int reg_encoding = tmpReg;
2320 int base = $mem$$base;
2321 int index = $mem$$index;
2322 int scale = $mem$$scale;
2323 int displace = $mem$$disp;
2324 bool disp_is_oop = $mem->disp_is_oop();
2325 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2326 // ADD $p,$tmp
2327 emit_opcode(cbuf,0x03);
2328 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2329 %}
2330
2331 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2332 // TEST shift,32
2333 emit_opcode(cbuf,0xF7);
2334 emit_rm(cbuf, 0x3, 0, ECX_enc);
2335 emit_d32(cbuf,0x20);
2336 // JEQ,s small
2337 emit_opcode(cbuf, 0x74);
2338 emit_d8(cbuf, 0x04);
2339 // MOV $dst.hi,$dst.lo
2340 emit_opcode( cbuf, 0x8B );
2341 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2342 // CLR $dst.lo
2343 emit_opcode(cbuf, 0x33);
2344 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2345 // small:
2346 // SHLD $dst.hi,$dst.lo,$shift
2347 emit_opcode(cbuf,0x0F);
2348 emit_opcode(cbuf,0xA5);
2349 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2350 // SHL $dst.lo,$shift"
2351 emit_opcode(cbuf,0xD3);
2352 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2353 %}
2354
2355 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2356 // TEST shift,32
2357 emit_opcode(cbuf,0xF7);
2358 emit_rm(cbuf, 0x3, 0, ECX_enc);
2359 emit_d32(cbuf,0x20);
2360 // JEQ,s small
2361 emit_opcode(cbuf, 0x74);
2362 emit_d8(cbuf, 0x04);
2363 // MOV $dst.lo,$dst.hi
2364 emit_opcode( cbuf, 0x8B );
2365 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2366 // CLR $dst.hi
2367 emit_opcode(cbuf, 0x33);
2368 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2369 // small:
2370 // SHRD $dst.lo,$dst.hi,$shift
2371 emit_opcode(cbuf,0x0F);
2372 emit_opcode(cbuf,0xAD);
2373 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2374 // SHR $dst.hi,$shift"
2375 emit_opcode(cbuf,0xD3);
2376 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2377 %}
2378
2379 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2380 // TEST shift,32
2381 emit_opcode(cbuf,0xF7);
2382 emit_rm(cbuf, 0x3, 0, ECX_enc);
2383 emit_d32(cbuf,0x20);
2384 // JEQ,s small
2385 emit_opcode(cbuf, 0x74);
2386 emit_d8(cbuf, 0x05);
2387 // MOV $dst.lo,$dst.hi
2388 emit_opcode( cbuf, 0x8B );
2389 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2390 // SAR $dst.hi,31
2391 emit_opcode(cbuf, 0xC1);
2392 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2393 emit_d8(cbuf, 0x1F );
2394 // small:
2395 // SHRD $dst.lo,$dst.hi,$shift
2396 emit_opcode(cbuf,0x0F);
2397 emit_opcode(cbuf,0xAD);
2398 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2399 // SAR $dst.hi,$shift"
2400 emit_opcode(cbuf,0xD3);
2401 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2402 %}
2403
2404
2405 // ----------------- Encodings for floating point unit -----------------
2406 // May leave result in FPU-TOS or FPU reg depending on opcodes
2407 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2408 $$$emit8$primary;
2409 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2410 %}
2411
2412 // Pop argument in FPR0 with FSTP ST(0)
2413 enc_class PopFPU() %{
2414 emit_opcode( cbuf, 0xDD );
2415 emit_d8( cbuf, 0xD8 );
2416 %}
2417
2418 // !!!!! equivalent to Pop_Reg_F
2419 enc_class Pop_Reg_DPR( regDPR dst ) %{
2420 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2421 emit_d8( cbuf, 0xD8+$dst$$reg );
2422 %}
2423
2424 enc_class Push_Reg_DPR( regDPR dst ) %{
2425 emit_opcode( cbuf, 0xD9 );
2426 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2427 %}
2428
2429 enc_class strictfp_bias1( regDPR dst ) %{
2430 emit_opcode( cbuf, 0xDB ); // FLD m80real
2431 emit_opcode( cbuf, 0x2D );
2432 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2433 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2434 emit_opcode( cbuf, 0xC8+$dst$$reg );
2435 %}
2436
2437 enc_class strictfp_bias2( regDPR dst ) %{
2438 emit_opcode( cbuf, 0xDB ); // FLD m80real
2439 emit_opcode( cbuf, 0x2D );
2440 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2441 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2442 emit_opcode( cbuf, 0xC8+$dst$$reg );
2443 %}
2444
2445 // Special case for moving an integer register to a stack slot.
2446 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2447 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2448 %}
2449
2450 // Special case for moving a register to a stack slot.
2451 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2452 // Opcode already emitted
2453 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2454 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2455 emit_d32(cbuf, $dst$$disp); // Displacement
2456 %}
2457
2458 // Push the integer in stackSlot 'src' onto FP-stack
2459 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2460 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2461 %}
2462
2463 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2464 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2465 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2466 %}
2467
2468 // Same as Pop_Mem_F except for opcode
2469 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2470 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2471 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2472 %}
2473
2474 enc_class Pop_Reg_FPR( regFPR dst ) %{
2475 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2476 emit_d8( cbuf, 0xD8+$dst$$reg );
2477 %}
2478
2479 enc_class Push_Reg_FPR( regFPR dst ) %{
2480 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2481 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2482 %}
2483
2484 // Push FPU's float to a stack-slot, and pop FPU-stack
2485 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2486 int pop = 0x02;
2487 if ($src$$reg != FPR1L_enc) {
2488 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2489 emit_d8( cbuf, 0xC0-1+$src$$reg );
2490 pop = 0x03;
2491 }
2492 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2493 %}
2494
2495 // Push FPU's double to a stack-slot, and pop FPU-stack
2496 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2497 int pop = 0x02;
2498 if ($src$$reg != FPR1L_enc) {
2499 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2500 emit_d8( cbuf, 0xC0-1+$src$$reg );
2501 pop = 0x03;
2502 }
2503 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2504 %}
2505
2506 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2507 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2508 int pop = 0xD0 - 1; // -1 since we skip FLD
2509 if ($src$$reg != FPR1L_enc) {
2510 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2511 emit_d8( cbuf, 0xC0-1+$src$$reg );
2512 pop = 0xD8;
2513 }
2514 emit_opcode( cbuf, 0xDD );
2515 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2516 %}
2517
2518
2519 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2520 // load dst in FPR0
2521 emit_opcode( cbuf, 0xD9 );
2522 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2523 if ($src$$reg != FPR1L_enc) {
2524 // fincstp
2525 emit_opcode (cbuf, 0xD9);
2526 emit_opcode (cbuf, 0xF7);
2527 // swap src with FPR1:
2528 // FXCH FPR1 with src
2529 emit_opcode(cbuf, 0xD9);
2530 emit_d8(cbuf, 0xC8-1+$src$$reg );
2531 // fdecstp
2532 emit_opcode (cbuf, 0xD9);
2533 emit_opcode (cbuf, 0xF6);
2534 }
2535 %}
2536
2537 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2538 MacroAssembler _masm(&cbuf);
2539 __ subptr(rsp, 8);
2540 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2541 __ fld_d(Address(rsp, 0));
2542 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2543 __ fld_d(Address(rsp, 0));
2544 %}
2545
2546 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2547 MacroAssembler _masm(&cbuf);
2548 __ subptr(rsp, 4);
2549 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2550 __ fld_s(Address(rsp, 0));
2551 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2552 __ fld_s(Address(rsp, 0));
2553 %}
2554
2555 enc_class Push_ResultD(regD dst) %{
2556 MacroAssembler _masm(&cbuf);
2557 __ fstp_d(Address(rsp, 0));
2558 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2559 __ addptr(rsp, 8);
2560 %}
2561
2562 enc_class Push_ResultF(regF dst, immI d8) %{
2563 MacroAssembler _masm(&cbuf);
2564 __ fstp_s(Address(rsp, 0));
2565 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2566 __ addptr(rsp, $d8$$constant);
2567 %}
2568
2569 enc_class Push_SrcD(regD src) %{
2570 MacroAssembler _masm(&cbuf);
2571 __ subptr(rsp, 8);
2572 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2573 __ fld_d(Address(rsp, 0));
2574 %}
2575
2576 enc_class push_stack_temp_qword() %{
2577 MacroAssembler _masm(&cbuf);
2578 __ subptr(rsp, 8);
2579 %}
2580
2581 enc_class pop_stack_temp_qword() %{
2582 MacroAssembler _masm(&cbuf);
2583 __ addptr(rsp, 8);
2584 %}
2585
2586 enc_class push_xmm_to_fpr1(regD src) %{
2587 MacroAssembler _masm(&cbuf);
2588 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2589 __ fld_d(Address(rsp, 0));
2590 %}
2591
2592 enc_class Push_Result_Mod_DPR( regDPR src) %{
2593 if ($src$$reg != FPR1L_enc) {
2594 // fincstp
2595 emit_opcode (cbuf, 0xD9);
2596 emit_opcode (cbuf, 0xF7);
2597 // FXCH FPR1 with src
2598 emit_opcode(cbuf, 0xD9);
2599 emit_d8(cbuf, 0xC8-1+$src$$reg );
2600 // fdecstp
2601 emit_opcode (cbuf, 0xD9);
2602 emit_opcode (cbuf, 0xF6);
2603 }
2604 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2605 // // FSTP FPR$dst$$reg
2606 // emit_opcode( cbuf, 0xDD );
2607 // emit_d8( cbuf, 0xD8+$dst$$reg );
2608 %}
2609
2610 enc_class fnstsw_sahf_skip_parity() %{
2611 // fnstsw ax
2612 emit_opcode( cbuf, 0xDF );
2613 emit_opcode( cbuf, 0xE0 );
2614 // sahf
2615 emit_opcode( cbuf, 0x9E );
2616 // jnp ::skip
2617 emit_opcode( cbuf, 0x7B );
2618 emit_opcode( cbuf, 0x05 );
2619 %}
2620
2621 enc_class emitModDPR() %{
2622 // fprem must be iterative
2623 // :: loop
2624 // fprem
2625 emit_opcode( cbuf, 0xD9 );
2626 emit_opcode( cbuf, 0xF8 );
2627 // wait
2628 emit_opcode( cbuf, 0x9b );
2629 // fnstsw ax
2630 emit_opcode( cbuf, 0xDF );
2631 emit_opcode( cbuf, 0xE0 );
2632 // sahf
2633 emit_opcode( cbuf, 0x9E );
2634 // jp ::loop
2635 emit_opcode( cbuf, 0x0F );
2636 emit_opcode( cbuf, 0x8A );
2637 emit_opcode( cbuf, 0xF4 );
2638 emit_opcode( cbuf, 0xFF );
2639 emit_opcode( cbuf, 0xFF );
2640 emit_opcode( cbuf, 0xFF );
2641 %}
2642
2643 enc_class fpu_flags() %{
2644 // fnstsw_ax
2645 emit_opcode( cbuf, 0xDF);
2646 emit_opcode( cbuf, 0xE0);
2647 // test ax,0x0400
2648 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2649 emit_opcode( cbuf, 0xA9 );
2650 emit_d16 ( cbuf, 0x0400 );
2651 // // // This sequence works, but stalls for 12-16 cycles on PPro
2652 // // test rax,0x0400
2653 // emit_opcode( cbuf, 0xA9 );
2654 // emit_d32 ( cbuf, 0x00000400 );
2655 //
2656 // jz exit (no unordered comparison)
2657 emit_opcode( cbuf, 0x74 );
2658 emit_d8 ( cbuf, 0x02 );
2659 // mov ah,1 - treat as LT case (set carry flag)
2660 emit_opcode( cbuf, 0xB4 );
2661 emit_d8 ( cbuf, 0x01 );
2662 // sahf
2663 emit_opcode( cbuf, 0x9E);
2664 %}
2665
2666 enc_class cmpF_P6_fixup() %{
2667 // Fixup the integer flags in case comparison involved a NaN
2668 //
2669 // JNP exit (no unordered comparison, P-flag is set by NaN)
2670 emit_opcode( cbuf, 0x7B );
2671 emit_d8 ( cbuf, 0x03 );
2672 // MOV AH,1 - treat as LT case (set carry flag)
2673 emit_opcode( cbuf, 0xB4 );
2674 emit_d8 ( cbuf, 0x01 );
2675 // SAHF
2676 emit_opcode( cbuf, 0x9E);
2677 // NOP // target for branch to avoid branch to branch
2678 emit_opcode( cbuf, 0x90);
2679 %}
2680
2681 // fnstsw_ax();
2682 // sahf();
2683 // movl(dst, nan_result);
2684 // jcc(Assembler::parity, exit);
2685 // movl(dst, less_result);
2686 // jcc(Assembler::below, exit);
2687 // movl(dst, equal_result);
2688 // jcc(Assembler::equal, exit);
2689 // movl(dst, greater_result);
2690
2691 // less_result = 1;
2692 // greater_result = -1;
2693 // equal_result = 0;
2694 // nan_result = -1;
2695
2696 enc_class CmpF_Result(rRegI dst) %{
2697 // fnstsw_ax();
2698 emit_opcode( cbuf, 0xDF);
2699 emit_opcode( cbuf, 0xE0);
2700 // sahf
2701 emit_opcode( cbuf, 0x9E);
2702 // movl(dst, nan_result);
2703 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2704 emit_d32( cbuf, -1 );
2705 // jcc(Assembler::parity, exit);
2706 emit_opcode( cbuf, 0x7A );
2707 emit_d8 ( cbuf, 0x13 );
2708 // movl(dst, less_result);
2709 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2710 emit_d32( cbuf, -1 );
2711 // jcc(Assembler::below, exit);
2712 emit_opcode( cbuf, 0x72 );
2713 emit_d8 ( cbuf, 0x0C );
2714 // movl(dst, equal_result);
2715 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2716 emit_d32( cbuf, 0 );
2717 // jcc(Assembler::equal, exit);
2718 emit_opcode( cbuf, 0x74 );
2719 emit_d8 ( cbuf, 0x05 );
2720 // movl(dst, greater_result);
2721 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2722 emit_d32( cbuf, 1 );
2723 %}
2724
2725
2726 // Compare the longs and set flags
2727 // BROKEN! Do Not use as-is
2728 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2729 // CMP $src1.hi,$src2.hi
2730 emit_opcode( cbuf, 0x3B );
2731 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2732 // JNE,s done
2733 emit_opcode(cbuf,0x75);
2734 emit_d8(cbuf, 2 );
2735 // CMP $src1.lo,$src2.lo
2736 emit_opcode( cbuf, 0x3B );
2737 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2738 // done:
2739 %}
2740
2741 enc_class convert_int_long( regL dst, rRegI src ) %{
2742 // mov $dst.lo,$src
2743 int dst_encoding = $dst$$reg;
2744 int src_encoding = $src$$reg;
2745 encode_Copy( cbuf, dst_encoding , src_encoding );
2746 // mov $dst.hi,$src
2747 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2748 // sar $dst.hi,31
2749 emit_opcode( cbuf, 0xC1 );
2750 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2751 emit_d8(cbuf, 0x1F );
2752 %}
2753
2754 enc_class convert_long_double( eRegL src ) %{
2755 // push $src.hi
2756 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2757 // push $src.lo
2758 emit_opcode(cbuf, 0x50+$src$$reg );
2759 // fild 64-bits at [SP]
2760 emit_opcode(cbuf,0xdf);
2761 emit_d8(cbuf, 0x6C);
2762 emit_d8(cbuf, 0x24);
2763 emit_d8(cbuf, 0x00);
2764 // pop stack
2765 emit_opcode(cbuf, 0x83); // add SP, #8
2766 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2767 emit_d8(cbuf, 0x8);
2768 %}
2769
2770 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2771 // IMUL EDX:EAX,$src1
2772 emit_opcode( cbuf, 0xF7 );
2773 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2774 // SAR EDX,$cnt-32
2775 int shift_count = ((int)$cnt$$constant) - 32;
2776 if (shift_count > 0) {
2777 emit_opcode(cbuf, 0xC1);
2778 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2779 emit_d8(cbuf, shift_count);
2780 }
2781 %}
2782
2783 // this version doesn't have add sp, 8
2784 enc_class convert_long_double2( eRegL src ) %{
2785 // push $src.hi
2786 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2787 // push $src.lo
2788 emit_opcode(cbuf, 0x50+$src$$reg );
2789 // fild 64-bits at [SP]
2790 emit_opcode(cbuf,0xdf);
2791 emit_d8(cbuf, 0x6C);
2792 emit_d8(cbuf, 0x24);
2793 emit_d8(cbuf, 0x00);
2794 %}
2795
2796 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2797 // Basic idea: long = (long)int * (long)int
2798 // IMUL EDX:EAX, src
2799 emit_opcode( cbuf, 0xF7 );
2800 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2801 %}
2802
2803 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2804 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2805 // MUL EDX:EAX, src
2806 emit_opcode( cbuf, 0xF7 );
2807 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2808 %}
2809
2810 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2811 // Basic idea: lo(result) = lo(x_lo * y_lo)
2812 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2813 // MOV $tmp,$src.lo
2814 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2815 // IMUL $tmp,EDX
2816 emit_opcode( cbuf, 0x0F );
2817 emit_opcode( cbuf, 0xAF );
2818 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2819 // MOV EDX,$src.hi
2820 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2821 // IMUL EDX,EAX
2822 emit_opcode( cbuf, 0x0F );
2823 emit_opcode( cbuf, 0xAF );
2824 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2825 // ADD $tmp,EDX
2826 emit_opcode( cbuf, 0x03 );
2827 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2828 // MUL EDX:EAX,$src.lo
2829 emit_opcode( cbuf, 0xF7 );
2830 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2831 // ADD EDX,ESI
2832 emit_opcode( cbuf, 0x03 );
2833 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2834 %}
2835
2836 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2837 // Basic idea: lo(result) = lo(src * y_lo)
2838 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2839 // IMUL $tmp,EDX,$src
2840 emit_opcode( cbuf, 0x6B );
2841 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2842 emit_d8( cbuf, (int)$src$$constant );
2843 // MOV EDX,$src
2844 emit_opcode(cbuf, 0xB8 + EDX_enc);
2845 emit_d32( cbuf, (int)$src$$constant );
2846 // MUL EDX:EAX,EDX
2847 emit_opcode( cbuf, 0xF7 );
2848 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2849 // ADD EDX,ESI
2850 emit_opcode( cbuf, 0x03 );
2851 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2852 %}
2853
2854 enc_class long_div( eRegL src1, eRegL src2 ) %{
2855 // PUSH src1.hi
2856 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2857 // PUSH src1.lo
2858 emit_opcode(cbuf, 0x50+$src1$$reg );
2859 // PUSH src2.hi
2860 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2861 // PUSH src2.lo
2862 emit_opcode(cbuf, 0x50+$src2$$reg );
2863 // CALL directly to the runtime
2864 cbuf.set_insts_mark();
2865 emit_opcode(cbuf,0xE8); // Call into runtime
2866 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2867 // Restore stack
2868 emit_opcode(cbuf, 0x83); // add SP, #framesize
2869 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2870 emit_d8(cbuf, 4*4);
2871 %}
2872
2873 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2874 // PUSH src1.hi
2875 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2876 // PUSH src1.lo
2877 emit_opcode(cbuf, 0x50+$src1$$reg );
2878 // PUSH src2.hi
2879 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2880 // PUSH src2.lo
2881 emit_opcode(cbuf, 0x50+$src2$$reg );
2882 // CALL directly to the runtime
2883 cbuf.set_insts_mark();
2884 emit_opcode(cbuf,0xE8); // Call into runtime
2885 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2886 // Restore stack
2887 emit_opcode(cbuf, 0x83); // add SP, #framesize
2888 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2889 emit_d8(cbuf, 4*4);
2890 %}
2891
2892 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2893 // MOV $tmp,$src.lo
2894 emit_opcode(cbuf, 0x8B);
2895 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2896 // OR $tmp,$src.hi
2897 emit_opcode(cbuf, 0x0B);
2898 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2899 %}
2900
2901 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2902 // CMP $src1.lo,$src2.lo
2903 emit_opcode( cbuf, 0x3B );
2904 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2905 // JNE,s skip
2906 emit_cc(cbuf, 0x70, 0x5);
2907 emit_d8(cbuf,2);
2908 // CMP $src1.hi,$src2.hi
2909 emit_opcode( cbuf, 0x3B );
2910 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2911 %}
2912
2913 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2914 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2915 emit_opcode( cbuf, 0x3B );
2916 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2917 // MOV $tmp,$src1.hi
2918 emit_opcode( cbuf, 0x8B );
2919 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2920 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2921 emit_opcode( cbuf, 0x1B );
2922 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2923 %}
2924
2925 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2926 // XOR $tmp,$tmp
2927 emit_opcode(cbuf,0x33); // XOR
2928 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2929 // CMP $tmp,$src.lo
2930 emit_opcode( cbuf, 0x3B );
2931 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2932 // SBB $tmp,$src.hi
2933 emit_opcode( cbuf, 0x1B );
2934 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2935 %}
2936
2937 // Sniff, sniff... smells like Gnu Superoptimizer
2938 enc_class neg_long( eRegL dst ) %{
2939 emit_opcode(cbuf,0xF7); // NEG hi
2940 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2941 emit_opcode(cbuf,0xF7); // NEG lo
2942 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2943 emit_opcode(cbuf,0x83); // SBB hi,0
2944 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2945 emit_d8 (cbuf,0 );
2946 %}
2947
2948
2949 // Because the transitions from emitted code to the runtime
2950 // monitorenter/exit helper stubs are so slow it's critical that
2951 // we inline both the stack-locking fast-path and the inflated fast path.
2952 //
2953 // See also: cmpFastLock and cmpFastUnlock.
2954 //
2955 // What follows is a specialized inline transliteration of the code
2956 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2957 // another option would be to emit TrySlowEnter and TrySlowExit methods
2958 // at startup-time. These methods would accept arguments as
2959 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2960 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2961 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2962 // In practice, however, the # of lock sites is bounded and is usually small.
2963 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2964 // if the processor uses simple bimodal branch predictors keyed by EIP
2965 // Since the helper routines would be called from multiple synchronization
2966 // sites.
2967 //
2968 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2969 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2970 // to those specialized methods. That'd give us a mostly platform-independent
2971 // implementation that the JITs could optimize and inline at their pleasure.
2972 // Done correctly, the only time we'd need to cross to native could would be
2973 // to park() or unpark() threads. We'd also need a few more unsafe operators
2974 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2975 // (b) explicit barriers or fence operations.
2976 //
2977 // TODO:
2978 //
2979 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2980 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2981 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2982 // the lock operators would typically be faster than reifying Self.
2983 //
2984 // * Ideally I'd define the primitives as:
2985 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2986 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2987 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2988 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2989 // Furthermore the register assignments are overconstrained, possibly resulting in
2990 // sub-optimal code near the synchronization site.
2991 //
2992 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
2993 // Alternately, use a better sp-proximity test.
2994 //
2995 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
2996 // Either one is sufficient to uniquely identify a thread.
2997 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
2998 //
2999 // * Intrinsify notify() and notifyAll() for the common cases where the
3000 // object is locked by the calling thread but the waitlist is empty.
3001 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3002 //
3003 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3004 // But beware of excessive branch density on AMD Opterons.
3005 //
3006 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3007 // or failure of the fast-path. If the fast-path fails then we pass
3008 // control to the slow-path, typically in C. In Fast_Lock and
3009 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3010 // will emit a conditional branch immediately after the node.
3011 // So we have branches to branches and lots of ICC.ZF games.
3012 // Instead, it might be better to have C2 pass a "FailureLabel"
3013 // into Fast_Lock and Fast_Unlock. In the case of success, control
3014 // will drop through the node. ICC.ZF is undefined at exit.
3015 // In the case of failure, the node will branch directly to the
3016 // FailureLabel
3017
3018
3019 // obj: object to lock
3020 // box: on-stack box address (displaced header location) - KILLED
3021 // rax,: tmp -- KILLED
3022 // scr: tmp -- KILLED
3023 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3024
3025 Register objReg = as_Register($obj$$reg);
3026 Register boxReg = as_Register($box$$reg);
3027 Register tmpReg = as_Register($tmp$$reg);
3028 Register scrReg = as_Register($scr$$reg);
3029
3030 // Ensure the register assignents are disjoint
3031 guarantee (objReg != boxReg, "") ;
3032 guarantee (objReg != tmpReg, "") ;
3033 guarantee (objReg != scrReg, "") ;
3034 guarantee (boxReg != tmpReg, "") ;
3035 guarantee (boxReg != scrReg, "") ;
3036 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3037
3038 MacroAssembler masm(&cbuf);
3039
3040 if (_counters != NULL) {
3041 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3042 }
3043 if (EmitSync & 1) {
3044 // set box->dhw = unused_mark (3)
3045 // Force all sync thru slow-path: slow_enter() and slow_exit()
3046 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3047 masm.cmpptr (rsp, (int32_t)0) ;
3048 } else
3049 if (EmitSync & 2) {
3050 Label DONE_LABEL ;
3051 if (UseBiasedLocking) {
3052 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3053 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3054 }
3055
3056 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3057 masm.orptr (tmpReg, 0x1);
3058 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3059 if (os::is_MP()) { masm.lock(); }
3060 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3061 masm.jcc(Assembler::equal, DONE_LABEL);
3062 // Recursive locking
3063 masm.subptr(tmpReg, rsp);
3064 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3065 masm.movptr(Address(boxReg, 0), tmpReg);
3066 masm.bind(DONE_LABEL) ;
3067 } else {
3068 // Possible cases that we'll encounter in fast_lock
3069 // ------------------------------------------------
3070 // * Inflated
3071 // -- unlocked
3072 // -- Locked
3073 // = by self
3074 // = by other
3075 // * biased
3076 // -- by Self
3077 // -- by other
3078 // * neutral
3079 // * stack-locked
3080 // -- by self
3081 // = sp-proximity test hits
3082 // = sp-proximity test generates false-negative
3083 // -- by other
3084 //
3085
3086 Label IsInflated, DONE_LABEL, PopDone ;
3087
3088 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3089 // order to reduce the number of conditional branches in the most common cases.
3090 // Beware -- there's a subtle invariant that fetch of the markword
3091 // at [FETCH], below, will never observe a biased encoding (*101b).
3092 // If this invariant is not held we risk exclusion (safety) failure.
3093 if (UseBiasedLocking && !UseOptoBiasInlining) {
3094 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3095 }
3096
3097 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3098 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3099 masm.jccb (Assembler::notZero, IsInflated) ;
3100
3101 // Attempt stack-locking ...
3102 masm.orptr (tmpReg, 0x1);
3103 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3104 if (os::is_MP()) { masm.lock(); }
3105 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3106 if (_counters != NULL) {
3107 masm.cond_inc32(Assembler::equal,
3108 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3109 }
3110 masm.jccb (Assembler::equal, DONE_LABEL);
3111
3112 // Recursive locking
3113 masm.subptr(tmpReg, rsp);
3114 masm.andptr(tmpReg, 0xFFFFF003 );
3115 masm.movptr(Address(boxReg, 0), tmpReg);
3116 if (_counters != NULL) {
3117 masm.cond_inc32(Assembler::equal,
3118 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3119 }
3120 masm.jmp (DONE_LABEL) ;
3121
3122 masm.bind (IsInflated) ;
3123
3124 // The object is inflated.
3125 //
3126 // TODO-FIXME: eliminate the ugly use of manifest constants:
3127 // Use markOopDesc::monitor_value instead of "2".
3128 // use markOop::unused_mark() instead of "3".
3129 // The tmpReg value is an objectMonitor reference ORed with
3130 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3131 // objectmonitor pointer by masking off the "2" bit or we can just
3132 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3133 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3134 //
3135 // I use the latter as it avoids AGI stalls.
3136 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3137 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3138 //
3139 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3140
3141 // boxReg refers to the on-stack BasicLock in the current frame.
3142 // We'd like to write:
3143 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3144 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3145 // additional latency as we have another ST in the store buffer that must drain.
3146
3147 if (EmitSync & 8192) {
3148 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3149 masm.get_thread (scrReg) ;
3150 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3151 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3152 if (os::is_MP()) { masm.lock(); }
3153 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3154 } else
3155 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3156 masm.movptr(scrReg, boxReg) ;
3157 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3158
3159 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3160 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3161 // prefetchw [eax + Offset(_owner)-2]
3162 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3163 }
3164
3165 if ((EmitSync & 64) == 0) {
3166 // Optimistic form: consider XORL tmpReg,tmpReg
3167 masm.movptr(tmpReg, NULL_WORD) ;
3168 } else {
3169 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3170 // Test-And-CAS instead of CAS
3171 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3172 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3173 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3174 }
3175
3176 // Appears unlocked - try to swing _owner from null to non-null.
3177 // Ideally, I'd manifest "Self" with get_thread and then attempt
3178 // to CAS the register containing Self into m->Owner.
3179 // But we don't have enough registers, so instead we can either try to CAS
3180 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3181 // we later store "Self" into m->Owner. Transiently storing a stack address
3182 // (rsp or the address of the box) into m->owner is harmless.
3183 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3184 if (os::is_MP()) { masm.lock(); }
3185 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3186 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3187 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3188 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3189 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3190 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3191
3192 // If the CAS fails we can either retry or pass control to the slow-path.
3193 // We use the latter tactic.
3194 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3195 // If the CAS was successful ...
3196 // Self has acquired the lock
3197 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3198 // Intentional fall-through into DONE_LABEL ...
3199 } else {
3200 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3201 masm.movptr(boxReg, tmpReg) ;
3202
3203 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3204 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3205 // prefetchw [eax + Offset(_owner)-2]
3206 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3207 }
3208
3209 if ((EmitSync & 64) == 0) {
3210 // Optimistic form
3211 masm.xorptr (tmpReg, tmpReg) ;
3212 } else {
3213 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3214 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3215 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3216 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3217 }
3218
3219 // Appears unlocked - try to swing _owner from null to non-null.
3220 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3221 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3222 masm.get_thread (scrReg) ;
3223 if (os::is_MP()) { masm.lock(); }
3224 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3225
3226 // If the CAS fails we can either retry or pass control to the slow-path.
3227 // We use the latter tactic.
3228 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3229 // If the CAS was successful ...
3230 // Self has acquired the lock
3231 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3232 // Intentional fall-through into DONE_LABEL ...
3233 }
3234
3235 // DONE_LABEL is a hot target - we'd really like to place it at the
3236 // start of cache line by padding with NOPs.
3237 // See the AMD and Intel software optimization manuals for the
3238 // most efficient "long" NOP encodings.
3239 // Unfortunately none of our alignment mechanisms suffice.
3240 masm.bind(DONE_LABEL);
3241
3242 // Avoid branch-to-branch on AMD processors
3243 // This appears to be superstition.
3244 if (EmitSync & 32) masm.nop() ;
3245
3246
3247 // At DONE_LABEL the icc ZFlag is set as follows ...
3248 // Fast_Unlock uses the same protocol.
3249 // ZFlag == 1 -> Success
3250 // ZFlag == 0 -> Failure - force control through the slow-path
3251 }
3252 %}
3253
3254 // obj: object to unlock
3255 // box: box address (displaced header location), killed. Must be EAX.
3256 // rbx,: killed tmp; cannot be obj nor box.
3257 //
3258 // Some commentary on balanced locking:
3259 //
3260 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3261 // Methods that don't have provably balanced locking are forced to run in the
3262 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3263 // The interpreter provides two properties:
3264 // I1: At return-time the interpreter automatically and quietly unlocks any
3265 // objects acquired the current activation (frame). Recall that the
3266 // interpreter maintains an on-stack list of locks currently held by
3267 // a frame.
3268 // I2: If a method attempts to unlock an object that is not held by the
3269 // the frame the interpreter throws IMSX.
3270 //
3271 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3272 // B() doesn't have provably balanced locking so it runs in the interpreter.
3273 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3274 // is still locked by A().
3275 //
3276 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3277 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3278 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3279 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3280
3281 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3282
3283 Register objReg = as_Register($obj$$reg);
3284 Register boxReg = as_Register($box$$reg);
3285 Register tmpReg = as_Register($tmp$$reg);
3286
3287 guarantee (objReg != boxReg, "") ;
3288 guarantee (objReg != tmpReg, "") ;
3289 guarantee (boxReg != tmpReg, "") ;
3290 guarantee (boxReg == as_Register(EAX_enc), "") ;
3291 MacroAssembler masm(&cbuf);
3292
3293 if (EmitSync & 4) {
3294 // Disable - inhibit all inlining. Force control through the slow-path
3295 masm.cmpptr (rsp, 0) ;
3296 } else
3297 if (EmitSync & 8) {
3298 Label DONE_LABEL ;
3299 if (UseBiasedLocking) {
3300 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3301 }
3302 // classic stack-locking code ...
3303 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3304 masm.testptr(tmpReg, tmpReg) ;
3305 masm.jcc (Assembler::zero, DONE_LABEL) ;
3306 if (os::is_MP()) { masm.lock(); }
3307 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3308 masm.bind(DONE_LABEL);
3309 } else {
3310 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3311
3312 // Critically, the biased locking test must have precedence over
3313 // and appear before the (box->dhw == 0) recursive stack-lock test.
3314 if (UseBiasedLocking && !UseOptoBiasInlining) {
3315 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3316 }
3317
3318 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3319 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3320 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3321
3322 masm.testptr(tmpReg, 0x02) ; // Inflated?
3323 masm.jccb (Assembler::zero, Stacked) ;
3324
3325 masm.bind (Inflated) ;
3326 // It's inflated.
3327 // Despite our balanced locking property we still check that m->_owner == Self
3328 // as java routines or native JNI code called by this thread might
3329 // have released the lock.
3330 // Refer to the comments in synchronizer.cpp for how we might encode extra
3331 // state in _succ so we can avoid fetching EntryList|cxq.
3332 //
3333 // I'd like to add more cases in fast_lock() and fast_unlock() --
3334 // such as recursive enter and exit -- but we have to be wary of
3335 // I$ bloat, T$ effects and BP$ effects.
3336 //
3337 // If there's no contention try a 1-0 exit. That is, exit without
3338 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3339 // we detect and recover from the race that the 1-0 exit admits.
3340 //
3341 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3342 // before it STs null into _owner, releasing the lock. Updates
3343 // to data protected by the critical section must be visible before
3344 // we drop the lock (and thus before any other thread could acquire
3345 // the lock and observe the fields protected by the lock).
3346 // IA32's memory-model is SPO, so STs are ordered with respect to
3347 // each other and there's no need for an explicit barrier (fence).
3348 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3349
3350 masm.get_thread (boxReg) ;
3351 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3352 // prefetchw [ebx + Offset(_owner)-2]
3353 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3354 }
3355
3356 // Note that we could employ various encoding schemes to reduce
3357 // the number of loads below (currently 4) to just 2 or 3.
3358 // Refer to the comments in synchronizer.cpp.
3359 // In practice the chain of fetches doesn't seem to impact performance, however.
3360 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3361 // Attempt to reduce branch density - AMD's branch predictor.
3362 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3363 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3364 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3365 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3366 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3367 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3368 masm.jmpb (DONE_LABEL) ;
3369 } else {
3370 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3371 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3372 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3373 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3374 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3375 masm.jccb (Assembler::notZero, CheckSucc) ;
3376 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3377 masm.jmpb (DONE_LABEL) ;
3378 }
3379
3380 // The Following code fragment (EmitSync & 65536) improves the performance of
3381 // contended applications and contended synchronization microbenchmarks.
3382 // Unfortunately the emission of the code - even though not executed - causes regressions
3383 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3384 // with an equal number of never-executed NOPs results in the same regression.
3385 // We leave it off by default.
3386
3387 if ((EmitSync & 65536) != 0) {
3388 Label LSuccess, LGoSlowPath ;
3389
3390 masm.bind (CheckSucc) ;
3391
3392 // Optional pre-test ... it's safe to elide this
3393 if ((EmitSync & 16) == 0) {
3394 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3395 masm.jccb (Assembler::zero, LGoSlowPath) ;
3396 }
3397
3398 // We have a classic Dekker-style idiom:
3399 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3400 // There are a number of ways to implement the barrier:
3401 // (1) lock:andl &m->_owner, 0
3402 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3403 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3404 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3405 // (2) If supported, an explicit MFENCE is appealing.
3406 // In older IA32 processors MFENCE is slower than lock:add or xchg
3407 // particularly if the write-buffer is full as might be the case if
3408 // if stores closely precede the fence or fence-equivalent instruction.
3409 // In more modern implementations MFENCE appears faster, however.
3410 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3411 // The $lines underlying the top-of-stack should be in M-state.
3412 // The locked add instruction is serializing, of course.
3413 // (4) Use xchg, which is serializing
3414 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3415 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3416 // The integer condition codes will tell us if succ was 0.
3417 // Since _succ and _owner should reside in the same $line and
3418 // we just stored into _owner, it's likely that the $line
3419 // remains in M-state for the lock:orl.
3420 //
3421 // We currently use (3), although it's likely that switching to (2)
3422 // is correct for the future.
3423
3424 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3425 if (os::is_MP()) {
3426 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3427 masm.mfence();
3428 } else {
3429 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3430 }
3431 }
3432 // Ratify _succ remains non-null
3433 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3434 masm.jccb (Assembler::notZero, LSuccess) ;
3435
3436 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3437 if (os::is_MP()) { masm.lock(); }
3438 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3439 masm.jccb (Assembler::notEqual, LSuccess) ;
3440 // Since we're low on registers we installed rsp as a placeholding in _owner.
3441 // Now install Self over rsp. This is safe as we're transitioning from
3442 // non-null to non=null
3443 masm.get_thread (boxReg) ;
3444 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3445 // Intentional fall-through into LGoSlowPath ...
3446
3447 masm.bind (LGoSlowPath) ;
3448 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3449 masm.jmpb (DONE_LABEL) ;
3450
3451 masm.bind (LSuccess) ;
3452 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3453 masm.jmpb (DONE_LABEL) ;
3454 }
3455
3456 masm.bind (Stacked) ;
3457 // It's not inflated and it's not recursively stack-locked and it's not biased.
3458 // It must be stack-locked.
3459 // Try to reset the header to displaced header.
3460 // The "box" value on the stack is stable, so we can reload
3461 // and be assured we observe the same value as above.
3462 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3463 if (os::is_MP()) { masm.lock(); }
3464 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3465 // Intention fall-thru into DONE_LABEL
3466
3467
3468 // DONE_LABEL is a hot target - we'd really like to place it at the
3469 // start of cache line by padding with NOPs.
3470 // See the AMD and Intel software optimization manuals for the
3471 // most efficient "long" NOP encodings.
3472 // Unfortunately none of our alignment mechanisms suffice.
3473 if ((EmitSync & 65536) == 0) {
3474 masm.bind (CheckSucc) ;
3475 }
3476 masm.bind(DONE_LABEL);
3477
3478 // Avoid branch to branch on AMD processors
3479 if (EmitSync & 32768) { masm.nop() ; }
3480 }
3481 %}
3482
3483
3484 enc_class enc_pop_rdx() %{
3485 emit_opcode(cbuf,0x5A);
3486 %}
3487
3488 enc_class enc_rethrow() %{
3489 cbuf.set_insts_mark();
3490 emit_opcode(cbuf, 0xE9); // jmp entry
3491 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3492 runtime_call_Relocation::spec(), RELOC_IMM32 );
3493 %}
3494
3495
3496 // Convert a double to an int. Java semantics require we do complex
3497 // manglelations in the corner cases. So we set the rounding mode to
3498 // 'zero', store the darned double down as an int, and reset the
3499 // rounding mode to 'nearest'. The hardware throws an exception which
3500 // patches up the correct value directly to the stack.
3501 enc_class DPR2I_encoding( regDPR src ) %{
3502 // Flip to round-to-zero mode. We attempted to allow invalid-op
3503 // exceptions here, so that a NAN or other corner-case value will
3504 // thrown an exception (but normal values get converted at full speed).
3505 // However, I2C adapters and other float-stack manglers leave pending
3506 // invalid-op exceptions hanging. We would have to clear them before
3507 // enabling them and that is more expensive than just testing for the
3508 // invalid value Intel stores down in the corner cases.
3509 emit_opcode(cbuf,0xD9); // FLDCW trunc
3510 emit_opcode(cbuf,0x2D);
3511 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3512 // Allocate a word
3513 emit_opcode(cbuf,0x83); // SUB ESP,4
3514 emit_opcode(cbuf,0xEC);
3515 emit_d8(cbuf,0x04);
3516 // Encoding assumes a double has been pushed into FPR0.
3517 // Store down the double as an int, popping the FPU stack
3518 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3519 emit_opcode(cbuf,0x1C);
3520 emit_d8(cbuf,0x24);
3521 // Restore the rounding mode; mask the exception
3522 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3523 emit_opcode(cbuf,0x2D);
3524 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3525 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3526 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3527
3528 // Load the converted int; adjust CPU stack
3529 emit_opcode(cbuf,0x58); // POP EAX
3530 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3531 emit_d32 (cbuf,0x80000000); // 0x80000000
3532 emit_opcode(cbuf,0x75); // JNE around_slow_call
3533 emit_d8 (cbuf,0x07); // Size of slow_call
3534 // Push src onto stack slow-path
3535 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3536 emit_d8 (cbuf,0xC0-1+$src$$reg );
3537 // CALL directly to the runtime
3538 cbuf.set_insts_mark();
3539 emit_opcode(cbuf,0xE8); // Call into runtime
3540 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3541 // Carry on here...
3542 %}
3543
3544 enc_class DPR2L_encoding( regDPR src ) %{
3545 emit_opcode(cbuf,0xD9); // FLDCW trunc
3546 emit_opcode(cbuf,0x2D);
3547 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3548 // Allocate a word
3549 emit_opcode(cbuf,0x83); // SUB ESP,8
3550 emit_opcode(cbuf,0xEC);
3551 emit_d8(cbuf,0x08);
3552 // Encoding assumes a double has been pushed into FPR0.
3553 // Store down the double as a long, popping the FPU stack
3554 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3555 emit_opcode(cbuf,0x3C);
3556 emit_d8(cbuf,0x24);
3557 // Restore the rounding mode; mask the exception
3558 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3559 emit_opcode(cbuf,0x2D);
3560 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3561 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3562 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3563
3564 // Load the converted int; adjust CPU stack
3565 emit_opcode(cbuf,0x58); // POP EAX
3566 emit_opcode(cbuf,0x5A); // POP EDX
3567 emit_opcode(cbuf,0x81); // CMP EDX,imm
3568 emit_d8 (cbuf,0xFA); // rdx
3569 emit_d32 (cbuf,0x80000000); // 0x80000000
3570 emit_opcode(cbuf,0x75); // JNE around_slow_call
3571 emit_d8 (cbuf,0x07+4); // Size of slow_call
3572 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3573 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3574 emit_opcode(cbuf,0x75); // JNE around_slow_call
3575 emit_d8 (cbuf,0x07); // Size of slow_call
3576 // Push src onto stack slow-path
3577 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3578 emit_d8 (cbuf,0xC0-1+$src$$reg );
3579 // CALL directly to the runtime
3580 cbuf.set_insts_mark();
3581 emit_opcode(cbuf,0xE8); // Call into runtime
3582 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3583 // Carry on here...
3584 %}
3585
3586 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3587 // Operand was loaded from memory into fp ST (stack top)
3588 // FMUL ST,$src /* D8 C8+i */
3589 emit_opcode(cbuf, 0xD8);
3590 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3591 %}
3592
3593 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3594 // FADDP ST,src2 /* D8 C0+i */
3595 emit_opcode(cbuf, 0xD8);
3596 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3597 //could use FADDP src2,fpST /* DE C0+i */
3598 %}
3599
3600 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3601 // FADDP src2,ST /* DE C0+i */
3602 emit_opcode(cbuf, 0xDE);
3603 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3604 %}
3605
3606 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3607 // Operand has been loaded into fp ST (stack top)
3608 // FSUB ST,$src1
3609 emit_opcode(cbuf, 0xD8);
3610 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3611
3612 // FDIV
3613 emit_opcode(cbuf, 0xD8);
3614 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3615 %}
3616
3617 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3618 // Operand was loaded from memory into fp ST (stack top)
3619 // FADD ST,$src /* D8 C0+i */
3620 emit_opcode(cbuf, 0xD8);
3621 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3622
3623 // FMUL ST,src2 /* D8 C*+i */
3624 emit_opcode(cbuf, 0xD8);
3625 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3626 %}
3627
3628
3629 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3630 // Operand was loaded from memory into fp ST (stack top)
3631 // FADD ST,$src /* D8 C0+i */
3632 emit_opcode(cbuf, 0xD8);
3633 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3634
3635 // FMULP src2,ST /* DE C8+i */
3636 emit_opcode(cbuf, 0xDE);
3637 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3638 %}
3639
3640 // Atomically load the volatile long
3641 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3642 emit_opcode(cbuf,0xDF);
3643 int rm_byte_opcode = 0x05;
3644 int base = $mem$$base;
3645 int index = $mem$$index;
3646 int scale = $mem$$scale;
3647 int displace = $mem$$disp;
3648 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3649 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3650 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3651 %}
3652
3653 // Volatile Store Long. Must be atomic, so move it into
3654 // the FP TOS and then do a 64-bit FIST. Has to probe the
3655 // target address before the store (for null-ptr checks)
3656 // so the memory operand is used twice in the encoding.
3657 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3658 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3659 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3660 emit_opcode(cbuf,0xDF);
3661 int rm_byte_opcode = 0x07;
3662 int base = $mem$$base;
3663 int index = $mem$$index;
3664 int scale = $mem$$scale;
3665 int displace = $mem$$disp;
3666 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3667 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3668 %}
3669
3670 // Safepoint Poll. This polls the safepoint page, and causes an
3671 // exception if it is not readable. Unfortunately, it kills the condition code
3672 // in the process
3673 // We current use TESTL [spp],EDI
3674 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3675
3676 enc_class Safepoint_Poll() %{
3677 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3678 emit_opcode(cbuf,0x85);
3679 emit_rm (cbuf, 0x0, 0x7, 0x5);
3680 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3681 %}
3682 %}
3683
3684
3685 //----------FRAME--------------------------------------------------------------
3686 // Definition of frame structure and management information.
3687 //
3688 // S T A C K L A Y O U T Allocators stack-slot number
3689 // | (to get allocators register number
3690 // G Owned by | | v add OptoReg::stack0())
3691 // r CALLER | |
3692 // o | +--------+ pad to even-align allocators stack-slot
3693 // w V | pad0 | numbers; owned by CALLER
3694 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3695 // h ^ | in | 5
3696 // | | args | 4 Holes in incoming args owned by SELF
3697 // | | | | 3
3698 // | | +--------+
3699 // V | | old out| Empty on Intel, window on Sparc
3700 // | old |preserve| Must be even aligned.
3701 // | SP-+--------+----> Matcher::_old_SP, even aligned
3702 // | | in | 3 area for Intel ret address
3703 // Owned by |preserve| Empty on Sparc.
3704 // SELF +--------+
3705 // | | pad2 | 2 pad to align old SP
3706 // | +--------+ 1
3707 // | | locks | 0
3708 // | +--------+----> OptoReg::stack0(), even aligned
3709 // | | pad1 | 11 pad to align new SP
3710 // | +--------+
3711 // | | | 10
3712 // | | spills | 9 spills
3713 // V | | 8 (pad0 slot for callee)
3714 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3715 // ^ | out | 7
3716 // | | args | 6 Holes in outgoing args owned by CALLEE
3717 // Owned by +--------+
3718 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3719 // | new |preserve| Must be even-aligned.
3720 // | SP-+--------+----> Matcher::_new_SP, even aligned
3721 // | | |
3722 //
3723 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3724 // known from SELF's arguments and the Java calling convention.
3725 // Region 6-7 is determined per call site.
3726 // Note 2: If the calling convention leaves holes in the incoming argument
3727 // area, those holes are owned by SELF. Holes in the outgoing area
3728 // are owned by the CALLEE. Holes should not be nessecary in the
3729 // incoming area, as the Java calling convention is completely under
3730 // the control of the AD file. Doubles can be sorted and packed to
3731 // avoid holes. Holes in the outgoing arguments may be nessecary for
3732 // varargs C calling conventions.
3733 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3734 // even aligned with pad0 as needed.
3735 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3736 // region 6-11 is even aligned; it may be padded out more so that
3737 // the region from SP to FP meets the minimum stack alignment.
3738
3739 frame %{
3740 // What direction does stack grow in (assumed to be same for C & Java)
3741 stack_direction(TOWARDS_LOW);
3742
3743 // These three registers define part of the calling convention
3744 // between compiled code and the interpreter.
3745 inline_cache_reg(EAX); // Inline Cache Register
3746 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3747
3748 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3749 cisc_spilling_operand_name(indOffset32);
3750
3751 // Number of stack slots consumed by locking an object
3752 sync_stack_slots(1);
3753
3754 // Compiled code's Frame Pointer
3755 frame_pointer(ESP);
3756 // Interpreter stores its frame pointer in a register which is
3757 // stored to the stack by I2CAdaptors.
3758 // I2CAdaptors convert from interpreted java to compiled java.
3759 interpreter_frame_pointer(EBP);
3760
3761 // Stack alignment requirement
3762 // Alignment size in bytes (128-bit -> 16 bytes)
3763 stack_alignment(StackAlignmentInBytes);
3764
3765 // Number of stack slots between incoming argument block and the start of
3766 // a new frame. The PROLOG must add this many slots to the stack. The
3767 // EPILOG must remove this many slots. Intel needs one slot for
3768 // return address and one for rbp, (must save rbp)
3769 in_preserve_stack_slots(2+VerifyStackAtCalls);
3770
3771 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3772 // for calls to C. Supports the var-args backing area for register parms.
3773 varargs_C_out_slots_killed(0);
3774
3775 // The after-PROLOG location of the return address. Location of
3776 // return address specifies a type (REG or STACK) and a number
3777 // representing the register number (i.e. - use a register name) or
3778 // stack slot.
3779 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3780 // Otherwise, it is above the locks and verification slot and alignment word
3781 return_addr(STACK - 1 +
3782 round_to((Compile::current()->in_preserve_stack_slots() +
3783 Compile::current()->fixed_slots()),
3784 stack_alignment_in_slots()));
3785
3786 // Body of function which returns an integer array locating
3787 // arguments either in registers or in stack slots. Passed an array
3788 // of ideal registers called "sig" and a "length" count. Stack-slot
3789 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3790 // arguments for a CALLEE. Incoming stack arguments are
3791 // automatically biased by the preserve_stack_slots field above.
3792 calling_convention %{
3793 // No difference between ingoing/outgoing just pass false
3794 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3795 %}
3796
3797
3798 // Body of function which returns an integer array locating
3799 // arguments either in registers or in stack slots. Passed an array
3800 // of ideal registers called "sig" and a "length" count. Stack-slot
3801 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3802 // arguments for a CALLEE. Incoming stack arguments are
3803 // automatically biased by the preserve_stack_slots field above.
3804 c_calling_convention %{
3805 // This is obviously always outgoing
3806 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3807 %}
3808
3809 // Location of C & interpreter return values
3810 c_return_value %{
3811 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3812 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3813 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3814
3815 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3816 // that C functions return float and double results in XMM0.
3817 if( ideal_reg == Op_RegD && UseSSE>=2 )
3818 return OptoRegPair(XMM0b_num,XMM0_num);
3819 if( ideal_reg == Op_RegF && UseSSE>=2 )
3820 return OptoRegPair(OptoReg::Bad,XMM0_num);
3821
3822 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3823 %}
3824
3825 // Location of return values
3826 return_value %{
3827 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3828 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3829 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3830 if( ideal_reg == Op_RegD && UseSSE>=2 )
3831 return OptoRegPair(XMM0b_num,XMM0_num);
3832 if( ideal_reg == Op_RegF && UseSSE>=1 )
3833 return OptoRegPair(OptoReg::Bad,XMM0_num);
3834 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3835 %}
3836
3837 %}
3838
3839 //----------ATTRIBUTES---------------------------------------------------------
3840 //----------Operand Attributes-------------------------------------------------
3841 op_attrib op_cost(0); // Required cost attribute
3842
3843 //----------Instruction Attributes---------------------------------------------
3844 ins_attrib ins_cost(100); // Required cost attribute
3845 ins_attrib ins_size(8); // Required size attribute (in bits)
3846 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3847 // non-matching short branch variant of some
3848 // long branch?
3849 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3850 // specifies the alignment that some part of the instruction (not
3851 // necessarily the start) requires. If > 1, a compute_padding()
3852 // function must be provided for the instruction
3853
3854 //----------OPERANDS-----------------------------------------------------------
3855 // Operand definitions must precede instruction definitions for correct parsing
3856 // in the ADLC because operands constitute user defined types which are used in
3857 // instruction definitions.
3858
3859 //----------Simple Operands----------------------------------------------------
3860 // Immediate Operands
3861 // Integer Immediate
3862 operand immI() %{
3863 match(ConI);
3864
3865 op_cost(10);
3866 format %{ %}
3867 interface(CONST_INTER);
3868 %}
3869
3870 // Constant for test vs zero
3871 operand immI0() %{
3872 predicate(n->get_int() == 0);
3873 match(ConI);
3874
3875 op_cost(0);
3876 format %{ %}
3877 interface(CONST_INTER);
3878 %}
3879
3880 // Constant for increment
3881 operand immI1() %{
3882 predicate(n->get_int() == 1);
3883 match(ConI);
3884
3885 op_cost(0);
3886 format %{ %}
3887 interface(CONST_INTER);
3888 %}
3889
3890 // Constant for decrement
3891 operand immI_M1() %{
3892 predicate(n->get_int() == -1);
3893 match(ConI);
3894
3895 op_cost(0);
3896 format %{ %}
3897 interface(CONST_INTER);
3898 %}
3899
3900 // Valid scale values for addressing modes
3901 operand immI2() %{
3902 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3903 match(ConI);
3904
3905 format %{ %}
3906 interface(CONST_INTER);
3907 %}
3908
3909 operand immI8() %{
3910 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3911 match(ConI);
3912
3913 op_cost(5);
3914 format %{ %}
3915 interface(CONST_INTER);
3916 %}
3917
3918 operand immI16() %{
3919 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3920 match(ConI);
3921
3922 op_cost(10);
3923 format %{ %}
3924 interface(CONST_INTER);
3925 %}
3926
3927 // Constant for long shifts
3928 operand immI_32() %{
3929 predicate( n->get_int() == 32 );
3930 match(ConI);
3931
3932 op_cost(0);
3933 format %{ %}
3934 interface(CONST_INTER);
3935 %}
3936
3937 operand immI_1_31() %{
3938 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3939 match(ConI);
3940
3941 op_cost(0);
3942 format %{ %}
3943 interface(CONST_INTER);
3944 %}
3945
3946 operand immI_32_63() %{
3947 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3948 match(ConI);
3949 op_cost(0);
3950
3951 format %{ %}
3952 interface(CONST_INTER);
3953 %}
3954
3955 operand immI_1() %{
3956 predicate( n->get_int() == 1 );
3957 match(ConI);
3958
3959 op_cost(0);
3960 format %{ %}
3961 interface(CONST_INTER);
3962 %}
3963
3964 operand immI_2() %{
3965 predicate( n->get_int() == 2 );
3966 match(ConI);
3967
3968 op_cost(0);
3969 format %{ %}
3970 interface(CONST_INTER);
3971 %}
3972
3973 operand immI_3() %{
3974 predicate( n->get_int() == 3 );
3975 match(ConI);
3976
3977 op_cost(0);
3978 format %{ %}
3979 interface(CONST_INTER);
3980 %}
3981
3982 // Pointer Immediate
3983 operand immP() %{
3984 match(ConP);
3985
3986 op_cost(10);
3987 format %{ %}
3988 interface(CONST_INTER);
3989 %}
3990
3991 // NULL Pointer Immediate
3992 operand immP0() %{
3993 predicate( n->get_ptr() == 0 );
3994 match(ConP);
3995 op_cost(0);
3996
3997 format %{ %}
3998 interface(CONST_INTER);
3999 %}
4000
4001 // Long Immediate
4002 operand immL() %{
4003 match(ConL);
4004
4005 op_cost(20);
4006 format %{ %}
4007 interface(CONST_INTER);
4008 %}
4009
4010 // Long Immediate zero
4011 operand immL0() %{
4012 predicate( n->get_long() == 0L );
4013 match(ConL);
4014 op_cost(0);
4015
4016 format %{ %}
4017 interface(CONST_INTER);
4018 %}
4019
4020 // Long Immediate zero
4021 operand immL_M1() %{
4022 predicate( n->get_long() == -1L );
4023 match(ConL);
4024 op_cost(0);
4025
4026 format %{ %}
4027 interface(CONST_INTER);
4028 %}
4029
4030 // Long immediate from 0 to 127.
4031 // Used for a shorter form of long mul by 10.
4032 operand immL_127() %{
4033 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4034 match(ConL);
4035 op_cost(0);
4036
4037 format %{ %}
4038 interface(CONST_INTER);
4039 %}
4040
4041 // Long Immediate: low 32-bit mask
4042 operand immL_32bits() %{
4043 predicate(n->get_long() == 0xFFFFFFFFL);
4044 match(ConL);
4045 op_cost(0);
4046
4047 format %{ %}
4048 interface(CONST_INTER);
4049 %}
4050
4051 // Long Immediate: low 32-bit mask
4052 operand immL32() %{
4053 predicate(n->get_long() == (int)(n->get_long()));
4054 match(ConL);
4055 op_cost(20);
4056
4057 format %{ %}
4058 interface(CONST_INTER);
4059 %}
4060
4061 //Double Immediate zero
4062 operand immDPR0() %{
4063 // Do additional (and counter-intuitive) test against NaN to work around VC++
4064 // bug that generates code such that NaNs compare equal to 0.0
4065 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4066 match(ConD);
4067
4068 op_cost(5);
4069 format %{ %}
4070 interface(CONST_INTER);
4071 %}
4072
4073 // Double Immediate one
4074 operand immDPR1() %{
4075 predicate( UseSSE<=1 && n->getd() == 1.0 );
4076 match(ConD);
4077
4078 op_cost(5);
4079 format %{ %}
4080 interface(CONST_INTER);
4081 %}
4082
4083 // Double Immediate
4084 operand immDPR() %{
4085 predicate(UseSSE<=1);
4086 match(ConD);
4087
4088 op_cost(5);
4089 format %{ %}
4090 interface(CONST_INTER);
4091 %}
4092
4093 operand immD() %{
4094 predicate(UseSSE>=2);
4095 match(ConD);
4096
4097 op_cost(5);
4098 format %{ %}
4099 interface(CONST_INTER);
4100 %}
4101
4102 // Double Immediate zero
4103 operand immD0() %{
4104 // Do additional (and counter-intuitive) test against NaN to work around VC++
4105 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4106 // compare equal to -0.0.
4107 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4108 match(ConD);
4109
4110 format %{ %}
4111 interface(CONST_INTER);
4112 %}
4113
4114 // Float Immediate zero
4115 operand immFPR0() %{
4116 predicate(UseSSE == 0 && n->getf() == 0.0F);
4117 match(ConF);
4118
4119 op_cost(5);
4120 format %{ %}
4121 interface(CONST_INTER);
4122 %}
4123
4124 // Float Immediate one
4125 operand immFPR1() %{
4126 predicate(UseSSE == 0 && n->getf() == 1.0F);
4127 match(ConF);
4128
4129 op_cost(5);
4130 format %{ %}
4131 interface(CONST_INTER);
4132 %}
4133
4134 // Float Immediate
4135 operand immFPR() %{
4136 predicate( UseSSE == 0 );
4137 match(ConF);
4138
4139 op_cost(5);
4140 format %{ %}
4141 interface(CONST_INTER);
4142 %}
4143
4144 // Float Immediate
4145 operand immF() %{
4146 predicate(UseSSE >= 1);
4147 match(ConF);
4148
4149 op_cost(5);
4150 format %{ %}
4151 interface(CONST_INTER);
4152 %}
4153
4154 // Float Immediate zero. Zero and not -0.0
4155 operand immF0() %{
4156 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4157 match(ConF);
4158
4159 op_cost(5);
4160 format %{ %}
4161 interface(CONST_INTER);
4162 %}
4163
4164 // Immediates for special shifts (sign extend)
4165
4166 // Constants for increment
4167 operand immI_16() %{
4168 predicate( n->get_int() == 16 );
4169 match(ConI);
4170
4171 format %{ %}
4172 interface(CONST_INTER);
4173 %}
4174
4175 operand immI_24() %{
4176 predicate( n->get_int() == 24 );
4177 match(ConI);
4178
4179 format %{ %}
4180 interface(CONST_INTER);
4181 %}
4182
4183 // Constant for byte-wide masking
4184 operand immI_255() %{
4185 predicate( n->get_int() == 255 );
4186 match(ConI);
4187
4188 format %{ %}
4189 interface(CONST_INTER);
4190 %}
4191
4192 // Constant for short-wide masking
4193 operand immI_65535() %{
4194 predicate(n->get_int() == 65535);
4195 match(ConI);
4196
4197 format %{ %}
4198 interface(CONST_INTER);
4199 %}
4200
4201 // Register Operands
4202 // Integer Register
4203 operand rRegI() %{
4204 constraint(ALLOC_IN_RC(int_reg));
4205 match(RegI);
4206 match(xRegI);
4207 match(eAXRegI);
4208 match(eBXRegI);
4209 match(eCXRegI);
4210 match(eDXRegI);
4211 match(eDIRegI);
4212 match(eSIRegI);
4213
4214 format %{ %}
4215 interface(REG_INTER);
4216 %}
4217
4218 // Subset of Integer Register
4219 operand xRegI(rRegI reg) %{
4220 constraint(ALLOC_IN_RC(int_x_reg));
4221 match(reg);
4222 match(eAXRegI);
4223 match(eBXRegI);
4224 match(eCXRegI);
4225 match(eDXRegI);
4226
4227 format %{ %}
4228 interface(REG_INTER);
4229 %}
4230
4231 // Special Registers
4232 operand eAXRegI(xRegI reg) %{
4233 constraint(ALLOC_IN_RC(eax_reg));
4234 match(reg);
4235 match(rRegI);
4236
4237 format %{ "EAX" %}
4238 interface(REG_INTER);
4239 %}
4240
4241 // Special Registers
4242 operand eBXRegI(xRegI reg) %{
4243 constraint(ALLOC_IN_RC(ebx_reg));
4244 match(reg);
4245 match(rRegI);
4246
4247 format %{ "EBX" %}
4248 interface(REG_INTER);
4249 %}
4250
4251 operand eCXRegI(xRegI reg) %{
4252 constraint(ALLOC_IN_RC(ecx_reg));
4253 match(reg);
4254 match(rRegI);
4255
4256 format %{ "ECX" %}
4257 interface(REG_INTER);
4258 %}
4259
4260 operand eDXRegI(xRegI reg) %{
4261 constraint(ALLOC_IN_RC(edx_reg));
4262 match(reg);
4263 match(rRegI);
4264
4265 format %{ "EDX" %}
4266 interface(REG_INTER);
4267 %}
4268
4269 operand eDIRegI(xRegI reg) %{
4270 constraint(ALLOC_IN_RC(edi_reg));
4271 match(reg);
4272 match(rRegI);
4273
4274 format %{ "EDI" %}
4275 interface(REG_INTER);
4276 %}
4277
4278 operand naxRegI() %{
4279 constraint(ALLOC_IN_RC(nax_reg));
4280 match(RegI);
4281 match(eCXRegI);
4282 match(eDXRegI);
4283 match(eSIRegI);
4284 match(eDIRegI);
4285
4286 format %{ %}
4287 interface(REG_INTER);
4288 %}
4289
4290 operand nadxRegI() %{
4291 constraint(ALLOC_IN_RC(nadx_reg));
4292 match(RegI);
4293 match(eBXRegI);
4294 match(eCXRegI);
4295 match(eSIRegI);
4296 match(eDIRegI);
4297
4298 format %{ %}
4299 interface(REG_INTER);
4300 %}
4301
4302 operand ncxRegI() %{
4303 constraint(ALLOC_IN_RC(ncx_reg));
4304 match(RegI);
4305 match(eAXRegI);
4306 match(eDXRegI);
4307 match(eSIRegI);
4308 match(eDIRegI);
4309
4310 format %{ %}
4311 interface(REG_INTER);
4312 %}
4313
4314 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4315 // //
4316 operand eSIRegI(xRegI reg) %{
4317 constraint(ALLOC_IN_RC(esi_reg));
4318 match(reg);
4319 match(rRegI);
4320
4321 format %{ "ESI" %}
4322 interface(REG_INTER);
4323 %}
4324
4325 // Pointer Register
4326 operand anyRegP() %{
4327 constraint(ALLOC_IN_RC(any_reg));
4328 match(RegP);
4329 match(eAXRegP);
4330 match(eBXRegP);
4331 match(eCXRegP);
4332 match(eDIRegP);
4333 match(eRegP);
4334
4335 format %{ %}
4336 interface(REG_INTER);
4337 %}
4338
4339 operand eRegP() %{
4340 constraint(ALLOC_IN_RC(int_reg));
4341 match(RegP);
4342 match(eAXRegP);
4343 match(eBXRegP);
4344 match(eCXRegP);
4345 match(eDIRegP);
4346
4347 format %{ %}
4348 interface(REG_INTER);
4349 %}
4350
4351 // On windows95, EBP is not safe to use for implicit null tests.
4352 operand eRegP_no_EBP() %{
4353 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4354 match(RegP);
4355 match(eAXRegP);
4356 match(eBXRegP);
4357 match(eCXRegP);
4358 match(eDIRegP);
4359
4360 op_cost(100);
4361 format %{ %}
4362 interface(REG_INTER);
4363 %}
4364
4365 operand naxRegP() %{
4366 constraint(ALLOC_IN_RC(nax_reg));
4367 match(RegP);
4368 match(eBXRegP);
4369 match(eDXRegP);
4370 match(eCXRegP);
4371 match(eSIRegP);
4372 match(eDIRegP);
4373
4374 format %{ %}
4375 interface(REG_INTER);
4376 %}
4377
4378 operand nabxRegP() %{
4379 constraint(ALLOC_IN_RC(nabx_reg));
4380 match(RegP);
4381 match(eCXRegP);
4382 match(eDXRegP);
4383 match(eSIRegP);
4384 match(eDIRegP);
4385
4386 format %{ %}
4387 interface(REG_INTER);
4388 %}
4389
4390 operand pRegP() %{
4391 constraint(ALLOC_IN_RC(p_reg));
4392 match(RegP);
4393 match(eBXRegP);
4394 match(eDXRegP);
4395 match(eSIRegP);
4396 match(eDIRegP);
4397
4398 format %{ %}
4399 interface(REG_INTER);
4400 %}
4401
4402 // Special Registers
4403 // Return a pointer value
4404 operand eAXRegP(eRegP reg) %{
4405 constraint(ALLOC_IN_RC(eax_reg));
4406 match(reg);
4407 format %{ "EAX" %}
4408 interface(REG_INTER);
4409 %}
4410
4411 // Used in AtomicAdd
4412 operand eBXRegP(eRegP reg) %{
4413 constraint(ALLOC_IN_RC(ebx_reg));
4414 match(reg);
4415 format %{ "EBX" %}
4416 interface(REG_INTER);
4417 %}
4418
4419 // Tail-call (interprocedural jump) to interpreter
4420 operand eCXRegP(eRegP reg) %{
4421 constraint(ALLOC_IN_RC(ecx_reg));
4422 match(reg);
4423 format %{ "ECX" %}
4424 interface(REG_INTER);
4425 %}
4426
4427 operand eSIRegP(eRegP reg) %{
4428 constraint(ALLOC_IN_RC(esi_reg));
4429 match(reg);
4430 format %{ "ESI" %}
4431 interface(REG_INTER);
4432 %}
4433
4434 // Used in rep stosw
4435 operand eDIRegP(eRegP reg) %{
4436 constraint(ALLOC_IN_RC(edi_reg));
4437 match(reg);
4438 format %{ "EDI" %}
4439 interface(REG_INTER);
4440 %}
4441
4442 operand eBPRegP() %{
4443 constraint(ALLOC_IN_RC(ebp_reg));
4444 match(RegP);
4445 format %{ "EBP" %}
4446 interface(REG_INTER);
4447 %}
4448
4449 operand eRegL() %{
4450 constraint(ALLOC_IN_RC(long_reg));
4451 match(RegL);
4452 match(eADXRegL);
4453
4454 format %{ %}
4455 interface(REG_INTER);
4456 %}
4457
4458 operand eADXRegL( eRegL reg ) %{
4459 constraint(ALLOC_IN_RC(eadx_reg));
4460 match(reg);
4461
4462 format %{ "EDX:EAX" %}
4463 interface(REG_INTER);
4464 %}
4465
4466 operand eBCXRegL( eRegL reg ) %{
4467 constraint(ALLOC_IN_RC(ebcx_reg));
4468 match(reg);
4469
4470 format %{ "EBX:ECX" %}
4471 interface(REG_INTER);
4472 %}
4473
4474 // Special case for integer high multiply
4475 operand eADXRegL_low_only() %{
4476 constraint(ALLOC_IN_RC(eadx_reg));
4477 match(RegL);
4478
4479 format %{ "EAX" %}
4480 interface(REG_INTER);
4481 %}
4482
4483 // Flags register, used as output of compare instructions
4484 operand eFlagsReg() %{
4485 constraint(ALLOC_IN_RC(int_flags));
4486 match(RegFlags);
4487
4488 format %{ "EFLAGS" %}
4489 interface(REG_INTER);
4490 %}
4491
4492 // Flags register, used as output of FLOATING POINT compare instructions
4493 operand eFlagsRegU() %{
4494 constraint(ALLOC_IN_RC(int_flags));
4495 match(RegFlags);
4496
4497 format %{ "EFLAGS_U" %}
4498 interface(REG_INTER);
4499 %}
4500
4501 operand eFlagsRegUCF() %{
4502 constraint(ALLOC_IN_RC(int_flags));
4503 match(RegFlags);
4504 predicate(false);
4505
4506 format %{ "EFLAGS_U_CF" %}
4507 interface(REG_INTER);
4508 %}
4509
4510 // Condition Code Register used by long compare
4511 operand flagsReg_long_LTGE() %{
4512 constraint(ALLOC_IN_RC(int_flags));
4513 match(RegFlags);
4514 format %{ "FLAGS_LTGE" %}
4515 interface(REG_INTER);
4516 %}
4517 operand flagsReg_long_EQNE() %{
4518 constraint(ALLOC_IN_RC(int_flags));
4519 match(RegFlags);
4520 format %{ "FLAGS_EQNE" %}
4521 interface(REG_INTER);
4522 %}
4523 operand flagsReg_long_LEGT() %{
4524 constraint(ALLOC_IN_RC(int_flags));
4525 match(RegFlags);
4526 format %{ "FLAGS_LEGT" %}
4527 interface(REG_INTER);
4528 %}
4529
4530 // Float register operands
4531 operand regDPR() %{
4532 predicate( UseSSE < 2 );
4533 constraint(ALLOC_IN_RC(fp_dbl_reg));
4534 match(RegD);
4535 match(regDPR1);
4536 match(regDPR2);
4537 format %{ %}
4538 interface(REG_INTER);
4539 %}
4540
4541 operand regDPR1(regDPR reg) %{
4542 predicate( UseSSE < 2 );
4543 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4544 match(reg);
4545 format %{ "FPR1" %}
4546 interface(REG_INTER);
4547 %}
4548
4549 operand regDPR2(regDPR reg) %{
4550 predicate( UseSSE < 2 );
4551 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4552 match(reg);
4553 format %{ "FPR2" %}
4554 interface(REG_INTER);
4555 %}
4556
4557 operand regnotDPR1(regDPR reg) %{
4558 predicate( UseSSE < 2 );
4559 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4560 match(reg);
4561 format %{ %}
4562 interface(REG_INTER);
4563 %}
4564
4565 // Float register operands
4566 operand regFPR() %{
4567 predicate( UseSSE < 2 );
4568 constraint(ALLOC_IN_RC(fp_flt_reg));
4569 match(RegF);
4570 match(regFPR1);
4571 format %{ %}
4572 interface(REG_INTER);
4573 %}
4574
4575 // Float register operands
4576 operand regFPR1(regFPR reg) %{
4577 predicate( UseSSE < 2 );
4578 constraint(ALLOC_IN_RC(fp_flt_reg0));
4579 match(reg);
4580 format %{ "FPR1" %}
4581 interface(REG_INTER);
4582 %}
4583
4584 // XMM Float register operands
4585 operand regF() %{
4586 predicate( UseSSE>=1 );
4587 constraint(ALLOC_IN_RC(float_reg));
4588 match(RegF);
4589 format %{ %}
4590 interface(REG_INTER);
4591 %}
4592
4593 // XMM Double register operands
4594 operand regD() %{
4595 predicate( UseSSE>=2 );
4596 constraint(ALLOC_IN_RC(double_reg));
4597 match(RegD);
4598 format %{ %}
4599 interface(REG_INTER);
4600 %}
4601
4602
4603 //----------Memory Operands----------------------------------------------------
4604 // Direct Memory Operand
4605 operand direct(immP addr) %{
4606 match(addr);
4607
4608 format %{ "[$addr]" %}
4609 interface(MEMORY_INTER) %{
4610 base(0xFFFFFFFF);
4611 index(0x4);
4612 scale(0x0);
4613 disp($addr);
4614 %}
4615 %}
4616
4617 // Indirect Memory Operand
4618 operand indirect(eRegP reg) %{
4619 constraint(ALLOC_IN_RC(int_reg));
4620 match(reg);
4621
4622 format %{ "[$reg]" %}
4623 interface(MEMORY_INTER) %{
4624 base($reg);
4625 index(0x4);
4626 scale(0x0);
4627 disp(0x0);
4628 %}
4629 %}
4630
4631 // Indirect Memory Plus Short Offset Operand
4632 operand indOffset8(eRegP reg, immI8 off) %{
4633 match(AddP reg off);
4634
4635 format %{ "[$reg + $off]" %}
4636 interface(MEMORY_INTER) %{
4637 base($reg);
4638 index(0x4);
4639 scale(0x0);
4640 disp($off);
4641 %}
4642 %}
4643
4644 // Indirect Memory Plus Long Offset Operand
4645 operand indOffset32(eRegP reg, immI off) %{
4646 match(AddP reg off);
4647
4648 format %{ "[$reg + $off]" %}
4649 interface(MEMORY_INTER) %{
4650 base($reg);
4651 index(0x4);
4652 scale(0x0);
4653 disp($off);
4654 %}
4655 %}
4656
4657 // Indirect Memory Plus Long Offset Operand
4658 operand indOffset32X(rRegI reg, immP off) %{
4659 match(AddP off reg);
4660
4661 format %{ "[$reg + $off]" %}
4662 interface(MEMORY_INTER) %{
4663 base($reg);
4664 index(0x4);
4665 scale(0x0);
4666 disp($off);
4667 %}
4668 %}
4669
4670 // Indirect Memory Plus Index Register Plus Offset Operand
4671 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4672 match(AddP (AddP reg ireg) off);
4673
4674 op_cost(10);
4675 format %{"[$reg + $off + $ireg]" %}
4676 interface(MEMORY_INTER) %{
4677 base($reg);
4678 index($ireg);
4679 scale(0x0);
4680 disp($off);
4681 %}
4682 %}
4683
4684 // Indirect Memory Plus Index Register Plus Offset Operand
4685 operand indIndex(eRegP reg, rRegI ireg) %{
4686 match(AddP reg ireg);
4687
4688 op_cost(10);
4689 format %{"[$reg + $ireg]" %}
4690 interface(MEMORY_INTER) %{
4691 base($reg);
4692 index($ireg);
4693 scale(0x0);
4694 disp(0x0);
4695 %}
4696 %}
4697
4698 // // -------------------------------------------------------------------------
4699 // // 486 architecture doesn't support "scale * index + offset" with out a base
4700 // // -------------------------------------------------------------------------
4701 // // Scaled Memory Operands
4702 // // Indirect Memory Times Scale Plus Offset Operand
4703 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4704 // match(AddP off (LShiftI ireg scale));
4705 //
4706 // op_cost(10);
4707 // format %{"[$off + $ireg << $scale]" %}
4708 // interface(MEMORY_INTER) %{
4709 // base(0x4);
4710 // index($ireg);
4711 // scale($scale);
4712 // disp($off);
4713 // %}
4714 // %}
4715
4716 // Indirect Memory Times Scale Plus Index Register
4717 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4718 match(AddP reg (LShiftI ireg scale));
4719
4720 op_cost(10);
4721 format %{"[$reg + $ireg << $scale]" %}
4722 interface(MEMORY_INTER) %{
4723 base($reg);
4724 index($ireg);
4725 scale($scale);
4726 disp(0x0);
4727 %}
4728 %}
4729
4730 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4731 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4732 match(AddP (AddP reg (LShiftI ireg scale)) off);
4733
4734 op_cost(10);
4735 format %{"[$reg + $off + $ireg << $scale]" %}
4736 interface(MEMORY_INTER) %{
4737 base($reg);
4738 index($ireg);
4739 scale($scale);
4740 disp($off);
4741 %}
4742 %}
4743
4744 //----------Load Long Memory Operands------------------------------------------
4745 // The load-long idiom will use it's address expression again after loading
4746 // the first word of the long. If the load-long destination overlaps with
4747 // registers used in the addressing expression, the 2nd half will be loaded
4748 // from a clobbered address. Fix this by requiring that load-long use
4749 // address registers that do not overlap with the load-long target.
4750
4751 // load-long support
4752 operand load_long_RegP() %{
4753 constraint(ALLOC_IN_RC(esi_reg));
4754 match(RegP);
4755 match(eSIRegP);
4756 op_cost(100);
4757 format %{ %}
4758 interface(REG_INTER);
4759 %}
4760
4761 // Indirect Memory Operand Long
4762 operand load_long_indirect(load_long_RegP reg) %{
4763 constraint(ALLOC_IN_RC(esi_reg));
4764 match(reg);
4765
4766 format %{ "[$reg]" %}
4767 interface(MEMORY_INTER) %{
4768 base($reg);
4769 index(0x4);
4770 scale(0x0);
4771 disp(0x0);
4772 %}
4773 %}
4774
4775 // Indirect Memory Plus Long Offset Operand
4776 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4777 match(AddP reg off);
4778
4779 format %{ "[$reg + $off]" %}
4780 interface(MEMORY_INTER) %{
4781 base($reg);
4782 index(0x4);
4783 scale(0x0);
4784 disp($off);
4785 %}
4786 %}
4787
4788 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4789
4790
4791 //----------Special Memory Operands--------------------------------------------
4792 // Stack Slot Operand - This operand is used for loading and storing temporary
4793 // values on the stack where a match requires a value to
4794 // flow through memory.
4795 operand stackSlotP(sRegP reg) %{
4796 constraint(ALLOC_IN_RC(stack_slots));
4797 // No match rule because this operand is only generated in matching
4798 format %{ "[$reg]" %}
4799 interface(MEMORY_INTER) %{
4800 base(0x4); // ESP
4801 index(0x4); // No Index
4802 scale(0x0); // No Scale
4803 disp($reg); // Stack Offset
4804 %}
4805 %}
4806
4807 operand stackSlotI(sRegI reg) %{
4808 constraint(ALLOC_IN_RC(stack_slots));
4809 // No match rule because this operand is only generated in matching
4810 format %{ "[$reg]" %}
4811 interface(MEMORY_INTER) %{
4812 base(0x4); // ESP
4813 index(0x4); // No Index
4814 scale(0x0); // No Scale
4815 disp($reg); // Stack Offset
4816 %}
4817 %}
4818
4819 operand stackSlotF(sRegF reg) %{
4820 constraint(ALLOC_IN_RC(stack_slots));
4821 // No match rule because this operand is only generated in matching
4822 format %{ "[$reg]" %}
4823 interface(MEMORY_INTER) %{
4824 base(0x4); // ESP
4825 index(0x4); // No Index
4826 scale(0x0); // No Scale
4827 disp($reg); // Stack Offset
4828 %}
4829 %}
4830
4831 operand stackSlotD(sRegD reg) %{
4832 constraint(ALLOC_IN_RC(stack_slots));
4833 // No match rule because this operand is only generated in matching
4834 format %{ "[$reg]" %}
4835 interface(MEMORY_INTER) %{
4836 base(0x4); // ESP
4837 index(0x4); // No Index
4838 scale(0x0); // No Scale
4839 disp($reg); // Stack Offset
4840 %}
4841 %}
4842
4843 operand stackSlotL(sRegL reg) %{
4844 constraint(ALLOC_IN_RC(stack_slots));
4845 // No match rule because this operand is only generated in matching
4846 format %{ "[$reg]" %}
4847 interface(MEMORY_INTER) %{
4848 base(0x4); // ESP
4849 index(0x4); // No Index
4850 scale(0x0); // No Scale
4851 disp($reg); // Stack Offset
4852 %}
4853 %}
4854
4855 //----------Memory Operands - Win95 Implicit Null Variants----------------
4856 // Indirect Memory Operand
4857 operand indirect_win95_safe(eRegP_no_EBP reg)
4858 %{
4859 constraint(ALLOC_IN_RC(int_reg));
4860 match(reg);
4861
4862 op_cost(100);
4863 format %{ "[$reg]" %}
4864 interface(MEMORY_INTER) %{
4865 base($reg);
4866 index(0x4);
4867 scale(0x0);
4868 disp(0x0);
4869 %}
4870 %}
4871
4872 // Indirect Memory Plus Short Offset Operand
4873 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4874 %{
4875 match(AddP reg off);
4876
4877 op_cost(100);
4878 format %{ "[$reg + $off]" %}
4879 interface(MEMORY_INTER) %{
4880 base($reg);
4881 index(0x4);
4882 scale(0x0);
4883 disp($off);
4884 %}
4885 %}
4886
4887 // Indirect Memory Plus Long Offset Operand
4888 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4889 %{
4890 match(AddP reg off);
4891
4892 op_cost(100);
4893 format %{ "[$reg + $off]" %}
4894 interface(MEMORY_INTER) %{
4895 base($reg);
4896 index(0x4);
4897 scale(0x0);
4898 disp($off);
4899 %}
4900 %}
4901
4902 // Indirect Memory Plus Index Register Plus Offset Operand
4903 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4904 %{
4905 match(AddP (AddP reg ireg) off);
4906
4907 op_cost(100);
4908 format %{"[$reg + $off + $ireg]" %}
4909 interface(MEMORY_INTER) %{
4910 base($reg);
4911 index($ireg);
4912 scale(0x0);
4913 disp($off);
4914 %}
4915 %}
4916
4917 // Indirect Memory Times Scale Plus Index Register
4918 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4919 %{
4920 match(AddP reg (LShiftI ireg scale));
4921
4922 op_cost(100);
4923 format %{"[$reg + $ireg << $scale]" %}
4924 interface(MEMORY_INTER) %{
4925 base($reg);
4926 index($ireg);
4927 scale($scale);
4928 disp(0x0);
4929 %}
4930 %}
4931
4932 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4933 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4934 %{
4935 match(AddP (AddP reg (LShiftI ireg scale)) off);
4936
4937 op_cost(100);
4938 format %{"[$reg + $off + $ireg << $scale]" %}
4939 interface(MEMORY_INTER) %{
4940 base($reg);
4941 index($ireg);
4942 scale($scale);
4943 disp($off);
4944 %}
4945 %}
4946
4947 //----------Conditional Branch Operands----------------------------------------
4948 // Comparison Op - This is the operation of the comparison, and is limited to
4949 // the following set of codes:
4950 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4951 //
4952 // Other attributes of the comparison, such as unsignedness, are specified
4953 // by the comparison instruction that sets a condition code flags register.
4954 // That result is represented by a flags operand whose subtype is appropriate
4955 // to the unsignedness (etc.) of the comparison.
4956 //
4957 // Later, the instruction which matches both the Comparison Op (a Bool) and
4958 // the flags (produced by the Cmp) specifies the coding of the comparison op
4959 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4960
4961 // Comparision Code
4962 operand cmpOp() %{
4963 match(Bool);
4964
4965 format %{ "" %}
4966 interface(COND_INTER) %{
4967 equal(0x4, "e");
4968 not_equal(0x5, "ne");
4969 less(0xC, "l");
4970 greater_equal(0xD, "ge");
4971 less_equal(0xE, "le");
4972 greater(0xF, "g");
4973 %}
4974 %}
4975
4976 // Comparison Code, unsigned compare. Used by FP also, with
4977 // C2 (unordered) turned into GT or LT already. The other bits
4978 // C0 and C3 are turned into Carry & Zero flags.
4979 operand cmpOpU() %{
4980 match(Bool);
4981
4982 format %{ "" %}
4983 interface(COND_INTER) %{
4984 equal(0x4, "e");
4985 not_equal(0x5, "ne");
4986 less(0x2, "b");
4987 greater_equal(0x3, "nb");
4988 less_equal(0x6, "be");
4989 greater(0x7, "nbe");
4990 %}
4991 %}
4992
4993 // Floating comparisons that don't require any fixup for the unordered case
4994 operand cmpOpUCF() %{
4995 match(Bool);
4996 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4997 n->as_Bool()->_test._test == BoolTest::ge ||
4998 n->as_Bool()->_test._test == BoolTest::le ||
4999 n->as_Bool()->_test._test == BoolTest::gt);
5000 format %{ "" %}
5001 interface(COND_INTER) %{
5002 equal(0x4, "e");
5003 not_equal(0x5, "ne");
5004 less(0x2, "b");
5005 greater_equal(0x3, "nb");
5006 less_equal(0x6, "be");
5007 greater(0x7, "nbe");
5008 %}
5009 %}
5010
5011
5012 // Floating comparisons that can be fixed up with extra conditional jumps
5013 operand cmpOpUCF2() %{
5014 match(Bool);
5015 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5016 n->as_Bool()->_test._test == BoolTest::eq);
5017 format %{ "" %}
5018 interface(COND_INTER) %{
5019 equal(0x4, "e");
5020 not_equal(0x5, "ne");
5021 less(0x2, "b");
5022 greater_equal(0x3, "nb");
5023 less_equal(0x6, "be");
5024 greater(0x7, "nbe");
5025 %}
5026 %}
5027
5028 // Comparison Code for FP conditional move
5029 operand cmpOp_fcmov() %{
5030 match(Bool);
5031
5032 format %{ "" %}
5033 interface(COND_INTER) %{
5034 equal (0x0C8);
5035 not_equal (0x1C8);
5036 less (0x0C0);
5037 greater_equal(0x1C0);
5038 less_equal (0x0D0);
5039 greater (0x1D0);
5040 %}
5041 %}
5042
5043 // Comparision Code used in long compares
5044 operand cmpOp_commute() %{
5045 match(Bool);
5046
5047 format %{ "" %}
5048 interface(COND_INTER) %{
5049 equal(0x4, "e");
5050 not_equal(0x5, "ne");
5051 less(0xF, "g");
5052 greater_equal(0xE, "le");
5053 less_equal(0xD, "ge");
5054 greater(0xC, "l");
5055 %}
5056 %}
5057
5058 //----------OPERAND CLASSES----------------------------------------------------
5059 // Operand Classes are groups of operands that are used as to simplify
5060 // instruction definitions by not requiring the AD writer to specify separate
5061 // instructions for every form of operand when the instruction accepts
5062 // multiple operand types with the same basic encoding and format. The classic
5063 // case of this is memory operands.
5064
5065 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5066 indIndex, indIndexScale, indIndexScaleOffset);
5067
5068 // Long memory operations are encoded in 2 instructions and a +4 offset.
5069 // This means some kind of offset is always required and you cannot use
5070 // an oop as the offset (done when working on static globals).
5071 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5072 indIndex, indIndexScale, indIndexScaleOffset);
5073
5074
5075 //----------PIPELINE-----------------------------------------------------------
5076 // Rules which define the behavior of the target architectures pipeline.
5077 pipeline %{
5078
5079 //----------ATTRIBUTES---------------------------------------------------------
5080 attributes %{
5081 variable_size_instructions; // Fixed size instructions
5082 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5083 instruction_unit_size = 1; // An instruction is 1 bytes long
5084 instruction_fetch_unit_size = 16; // The processor fetches one line
5085 instruction_fetch_units = 1; // of 16 bytes
5086
5087 // List of nop instructions
5088 nops( MachNop );
5089 %}
5090
5091 //----------RESOURCES----------------------------------------------------------
5092 // Resources are the functional units available to the machine
5093
5094 // Generic P2/P3 pipeline
5095 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5096 // 3 instructions decoded per cycle.
5097 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5098 // 2 ALU op, only ALU0 handles mul/div instructions.
5099 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5100 MS0, MS1, MEM = MS0 | MS1,
5101 BR, FPU,
5102 ALU0, ALU1, ALU = ALU0 | ALU1 );
5103
5104 //----------PIPELINE DESCRIPTION-----------------------------------------------
5105 // Pipeline Description specifies the stages in the machine's pipeline
5106
5107 // Generic P2/P3 pipeline
5108 pipe_desc(S0, S1, S2, S3, S4, S5);
5109
5110 //----------PIPELINE CLASSES---------------------------------------------------
5111 // Pipeline Classes describe the stages in which input and output are
5112 // referenced by the hardware pipeline.
5113
5114 // Naming convention: ialu or fpu
5115 // Then: _reg
5116 // Then: _reg if there is a 2nd register
5117 // Then: _long if it's a pair of instructions implementing a long
5118 // Then: _fat if it requires the big decoder
5119 // Or: _mem if it requires the big decoder and a memory unit.
5120
5121 // Integer ALU reg operation
5122 pipe_class ialu_reg(rRegI dst) %{
5123 single_instruction;
5124 dst : S4(write);
5125 dst : S3(read);
5126 DECODE : S0; // any decoder
5127 ALU : S3; // any alu
5128 %}
5129
5130 // Long ALU reg operation
5131 pipe_class ialu_reg_long(eRegL dst) %{
5132 instruction_count(2);
5133 dst : S4(write);
5134 dst : S3(read);
5135 DECODE : S0(2); // any 2 decoders
5136 ALU : S3(2); // both alus
5137 %}
5138
5139 // Integer ALU reg operation using big decoder
5140 pipe_class ialu_reg_fat(rRegI dst) %{
5141 single_instruction;
5142 dst : S4(write);
5143 dst : S3(read);
5144 D0 : S0; // big decoder only
5145 ALU : S3; // any alu
5146 %}
5147
5148 // Long ALU reg operation using big decoder
5149 pipe_class ialu_reg_long_fat(eRegL dst) %{
5150 instruction_count(2);
5151 dst : S4(write);
5152 dst : S3(read);
5153 D0 : S0(2); // big decoder only; twice
5154 ALU : S3(2); // any 2 alus
5155 %}
5156
5157 // Integer ALU reg-reg operation
5158 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5159 single_instruction;
5160 dst : S4(write);
5161 src : S3(read);
5162 DECODE : S0; // any decoder
5163 ALU : S3; // any alu
5164 %}
5165
5166 // Long ALU reg-reg operation
5167 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5168 instruction_count(2);
5169 dst : S4(write);
5170 src : S3(read);
5171 DECODE : S0(2); // any 2 decoders
5172 ALU : S3(2); // both alus
5173 %}
5174
5175 // Integer ALU reg-reg operation
5176 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5177 single_instruction;
5178 dst : S4(write);
5179 src : S3(read);
5180 D0 : S0; // big decoder only
5181 ALU : S3; // any alu
5182 %}
5183
5184 // Long ALU reg-reg operation
5185 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5186 instruction_count(2);
5187 dst : S4(write);
5188 src : S3(read);
5189 D0 : S0(2); // big decoder only; twice
5190 ALU : S3(2); // both alus
5191 %}
5192
5193 // Integer ALU reg-mem operation
5194 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5195 single_instruction;
5196 dst : S5(write);
5197 mem : S3(read);
5198 D0 : S0; // big decoder only
5199 ALU : S4; // any alu
5200 MEM : S3; // any mem
5201 %}
5202
5203 // Long ALU reg-mem operation
5204 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5205 instruction_count(2);
5206 dst : S5(write);
5207 mem : S3(read);
5208 D0 : S0(2); // big decoder only; twice
5209 ALU : S4(2); // any 2 alus
5210 MEM : S3(2); // both mems
5211 %}
5212
5213 // Integer mem operation (prefetch)
5214 pipe_class ialu_mem(memory mem)
5215 %{
5216 single_instruction;
5217 mem : S3(read);
5218 D0 : S0; // big decoder only
5219 MEM : S3; // any mem
5220 %}
5221
5222 // Integer Store to Memory
5223 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5224 single_instruction;
5225 mem : S3(read);
5226 src : S5(read);
5227 D0 : S0; // big decoder only
5228 ALU : S4; // any alu
5229 MEM : S3;
5230 %}
5231
5232 // Long Store to Memory
5233 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5234 instruction_count(2);
5235 mem : S3(read);
5236 src : S5(read);
5237 D0 : S0(2); // big decoder only; twice
5238 ALU : S4(2); // any 2 alus
5239 MEM : S3(2); // Both mems
5240 %}
5241
5242 // Integer Store to Memory
5243 pipe_class ialu_mem_imm(memory mem) %{
5244 single_instruction;
5245 mem : S3(read);
5246 D0 : S0; // big decoder only
5247 ALU : S4; // any alu
5248 MEM : S3;
5249 %}
5250
5251 // Integer ALU0 reg-reg operation
5252 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5253 single_instruction;
5254 dst : S4(write);
5255 src : S3(read);
5256 D0 : S0; // Big decoder only
5257 ALU0 : S3; // only alu0
5258 %}
5259
5260 // Integer ALU0 reg-mem operation
5261 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5262 single_instruction;
5263 dst : S5(write);
5264 mem : S3(read);
5265 D0 : S0; // big decoder only
5266 ALU0 : S4; // ALU0 only
5267 MEM : S3; // any mem
5268 %}
5269
5270 // Integer ALU reg-reg operation
5271 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5272 single_instruction;
5273 cr : S4(write);
5274 src1 : S3(read);
5275 src2 : S3(read);
5276 DECODE : S0; // any decoder
5277 ALU : S3; // any alu
5278 %}
5279
5280 // Integer ALU reg-imm operation
5281 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5282 single_instruction;
5283 cr : S4(write);
5284 src1 : S3(read);
5285 DECODE : S0; // any decoder
5286 ALU : S3; // any alu
5287 %}
5288
5289 // Integer ALU reg-mem operation
5290 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5291 single_instruction;
5292 cr : S4(write);
5293 src1 : S3(read);
5294 src2 : S3(read);
5295 D0 : S0; // big decoder only
5296 ALU : S4; // any alu
5297 MEM : S3;
5298 %}
5299
5300 // Conditional move reg-reg
5301 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5302 instruction_count(4);
5303 y : S4(read);
5304 q : S3(read);
5305 p : S3(read);
5306 DECODE : S0(4); // any decoder
5307 %}
5308
5309 // Conditional move reg-reg
5310 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5311 single_instruction;
5312 dst : S4(write);
5313 src : S3(read);
5314 cr : S3(read);
5315 DECODE : S0; // any decoder
5316 %}
5317
5318 // Conditional move reg-mem
5319 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5320 single_instruction;
5321 dst : S4(write);
5322 src : S3(read);
5323 cr : S3(read);
5324 DECODE : S0; // any decoder
5325 MEM : S3;
5326 %}
5327
5328 // Conditional move reg-reg long
5329 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5330 single_instruction;
5331 dst : S4(write);
5332 src : S3(read);
5333 cr : S3(read);
5334 DECODE : S0(2); // any 2 decoders
5335 %}
5336
5337 // Conditional move double reg-reg
5338 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5339 single_instruction;
5340 dst : S4(write);
5341 src : S3(read);
5342 cr : S3(read);
5343 DECODE : S0; // any decoder
5344 %}
5345
5346 // Float reg-reg operation
5347 pipe_class fpu_reg(regDPR dst) %{
5348 instruction_count(2);
5349 dst : S3(read);
5350 DECODE : S0(2); // any 2 decoders
5351 FPU : S3;
5352 %}
5353
5354 // Float reg-reg operation
5355 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5356 instruction_count(2);
5357 dst : S4(write);
5358 src : S3(read);
5359 DECODE : S0(2); // any 2 decoders
5360 FPU : S3;
5361 %}
5362
5363 // Float reg-reg operation
5364 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5365 instruction_count(3);
5366 dst : S4(write);
5367 src1 : S3(read);
5368 src2 : S3(read);
5369 DECODE : S0(3); // any 3 decoders
5370 FPU : S3(2);
5371 %}
5372
5373 // Float reg-reg operation
5374 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5375 instruction_count(4);
5376 dst : S4(write);
5377 src1 : S3(read);
5378 src2 : S3(read);
5379 src3 : S3(read);
5380 DECODE : S0(4); // any 3 decoders
5381 FPU : S3(2);
5382 %}
5383
5384 // Float reg-reg operation
5385 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5386 instruction_count(4);
5387 dst : S4(write);
5388 src1 : S3(read);
5389 src2 : S3(read);
5390 src3 : S3(read);
5391 DECODE : S1(3); // any 3 decoders
5392 D0 : S0; // Big decoder only
5393 FPU : S3(2);
5394 MEM : S3;
5395 %}
5396
5397 // Float reg-mem operation
5398 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5399 instruction_count(2);
5400 dst : S5(write);
5401 mem : S3(read);
5402 D0 : S0; // big decoder only
5403 DECODE : S1; // any decoder for FPU POP
5404 FPU : S4;
5405 MEM : S3; // any mem
5406 %}
5407
5408 // Float reg-mem operation
5409 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5410 instruction_count(3);
5411 dst : S5(write);
5412 src1 : S3(read);
5413 mem : S3(read);
5414 D0 : S0; // big decoder only
5415 DECODE : S1(2); // any decoder for FPU POP
5416 FPU : S4;
5417 MEM : S3; // any mem
5418 %}
5419
5420 // Float mem-reg operation
5421 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5422 instruction_count(2);
5423 src : S5(read);
5424 mem : S3(read);
5425 DECODE : S0; // any decoder for FPU PUSH
5426 D0 : S1; // big decoder only
5427 FPU : S4;
5428 MEM : S3; // any mem
5429 %}
5430
5431 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5432 instruction_count(3);
5433 src1 : S3(read);
5434 src2 : S3(read);
5435 mem : S3(read);
5436 DECODE : S0(2); // any decoder for FPU PUSH
5437 D0 : S1; // big decoder only
5438 FPU : S4;
5439 MEM : S3; // any mem
5440 %}
5441
5442 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5443 instruction_count(3);
5444 src1 : S3(read);
5445 src2 : S3(read);
5446 mem : S4(read);
5447 DECODE : S0; // any decoder for FPU PUSH
5448 D0 : S0(2); // big decoder only
5449 FPU : S4;
5450 MEM : S3(2); // any mem
5451 %}
5452
5453 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5454 instruction_count(2);
5455 src1 : S3(read);
5456 dst : S4(read);
5457 D0 : S0(2); // big decoder only
5458 MEM : S3(2); // any mem
5459 %}
5460
5461 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5462 instruction_count(3);
5463 src1 : S3(read);
5464 src2 : S3(read);
5465 dst : S4(read);
5466 D0 : S0(3); // big decoder only
5467 FPU : S4;
5468 MEM : S3(3); // any mem
5469 %}
5470
5471 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5472 instruction_count(3);
5473 src1 : S4(read);
5474 mem : S4(read);
5475 DECODE : S0; // any decoder for FPU PUSH
5476 D0 : S0(2); // big decoder only
5477 FPU : S4;
5478 MEM : S3(2); // any mem
5479 %}
5480
5481 // Float load constant
5482 pipe_class fpu_reg_con(regDPR dst) %{
5483 instruction_count(2);
5484 dst : S5(write);
5485 D0 : S0; // big decoder only for the load
5486 DECODE : S1; // any decoder for FPU POP
5487 FPU : S4;
5488 MEM : S3; // any mem
5489 %}
5490
5491 // Float load constant
5492 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5493 instruction_count(3);
5494 dst : S5(write);
5495 src : S3(read);
5496 D0 : S0; // big decoder only for the load
5497 DECODE : S1(2); // any decoder for FPU POP
5498 FPU : S4;
5499 MEM : S3; // any mem
5500 %}
5501
5502 // UnConditional branch
5503 pipe_class pipe_jmp( label labl ) %{
5504 single_instruction;
5505 BR : S3;
5506 %}
5507
5508 // Conditional branch
5509 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5510 single_instruction;
5511 cr : S1(read);
5512 BR : S3;
5513 %}
5514
5515 // Allocation idiom
5516 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5517 instruction_count(1); force_serialization;
5518 fixed_latency(6);
5519 heap_ptr : S3(read);
5520 DECODE : S0(3);
5521 D0 : S2;
5522 MEM : S3;
5523 ALU : S3(2);
5524 dst : S5(write);
5525 BR : S5;
5526 %}
5527
5528 // Generic big/slow expanded idiom
5529 pipe_class pipe_slow( ) %{
5530 instruction_count(10); multiple_bundles; force_serialization;
5531 fixed_latency(100);
5532 D0 : S0(2);
5533 MEM : S3(2);
5534 %}
5535
5536 // The real do-nothing guy
5537 pipe_class empty( ) %{
5538 instruction_count(0);
5539 %}
5540
5541 // Define the class for the Nop node
5542 define %{
5543 MachNop = empty;
5544 %}
5545
5546 %}
5547
5548 //----------INSTRUCTIONS-------------------------------------------------------
5549 //
5550 // match -- States which machine-independent subtree may be replaced
5551 // by this instruction.
5552 // ins_cost -- The estimated cost of this instruction is used by instruction
5553 // selection to identify a minimum cost tree of machine
5554 // instructions that matches a tree of machine-independent
5555 // instructions.
5556 // format -- A string providing the disassembly for this instruction.
5557 // The value of an instruction's operand may be inserted
5558 // by referring to it with a '$' prefix.
5559 // opcode -- Three instruction opcodes may be provided. These are referred
5560 // to within an encode class as $primary, $secondary, and $tertiary
5561 // respectively. The primary opcode is commonly used to
5562 // indicate the type of machine instruction, while secondary
5563 // and tertiary are often used for prefix options or addressing
5564 // modes.
5565 // ins_encode -- A list of encode classes with parameters. The encode class
5566 // name must have been defined in an 'enc_class' specification
5567 // in the encode section of the architecture description.
5568
5569 //----------BSWAP-Instruction--------------------------------------------------
5570 instruct bytes_reverse_int(rRegI dst) %{
5571 match(Set dst (ReverseBytesI dst));
5572
5573 format %{ "BSWAP $dst" %}
5574 opcode(0x0F, 0xC8);
5575 ins_encode( OpcP, OpcSReg(dst) );
5576 ins_pipe( ialu_reg );
5577 %}
5578
5579 instruct bytes_reverse_long(eRegL dst) %{
5580 match(Set dst (ReverseBytesL dst));
5581
5582 format %{ "BSWAP $dst.lo\n\t"
5583 "BSWAP $dst.hi\n\t"
5584 "XCHG $dst.lo $dst.hi" %}
5585
5586 ins_cost(125);
5587 ins_encode( bswap_long_bytes(dst) );
5588 ins_pipe( ialu_reg_reg);
5589 %}
5590
5591 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5592 match(Set dst (ReverseBytesUS dst));
5593 effect(KILL cr);
5594
5595 format %{ "BSWAP $dst\n\t"
5596 "SHR $dst,16\n\t" %}
5597 ins_encode %{
5598 __ bswapl($dst$$Register);
5599 __ shrl($dst$$Register, 16);
5600 %}
5601 ins_pipe( ialu_reg );
5602 %}
5603
5604 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5605 match(Set dst (ReverseBytesS dst));
5606 effect(KILL cr);
5607
5608 format %{ "BSWAP $dst\n\t"
5609 "SAR $dst,16\n\t" %}
5610 ins_encode %{
5611 __ bswapl($dst$$Register);
5612 __ sarl($dst$$Register, 16);
5613 %}
5614 ins_pipe( ialu_reg );
5615 %}
5616
5617
5618 //---------- Zeros Count Instructions ------------------------------------------
5619
5620 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5621 predicate(UseCountLeadingZerosInstruction);
5622 match(Set dst (CountLeadingZerosI src));
5623 effect(KILL cr);
5624
5625 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5626 ins_encode %{
5627 __ lzcntl($dst$$Register, $src$$Register);
5628 %}
5629 ins_pipe(ialu_reg);
5630 %}
5631
5632 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5633 predicate(!UseCountLeadingZerosInstruction);
5634 match(Set dst (CountLeadingZerosI src));
5635 effect(KILL cr);
5636
5637 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5638 "JNZ skip\n\t"
5639 "MOV $dst, -1\n"
5640 "skip:\n\t"
5641 "NEG $dst\n\t"
5642 "ADD $dst, 31" %}
5643 ins_encode %{
5644 Register Rdst = $dst$$Register;
5645 Register Rsrc = $src$$Register;
5646 Label skip;
5647 __ bsrl(Rdst, Rsrc);
5648 __ jccb(Assembler::notZero, skip);
5649 __ movl(Rdst, -1);
5650 __ bind(skip);
5651 __ negl(Rdst);
5652 __ addl(Rdst, BitsPerInt - 1);
5653 %}
5654 ins_pipe(ialu_reg);
5655 %}
5656
5657 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5658 predicate(UseCountLeadingZerosInstruction);
5659 match(Set dst (CountLeadingZerosL src));
5660 effect(TEMP dst, KILL cr);
5661
5662 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5663 "JNC done\n\t"
5664 "LZCNT $dst, $src.lo\n\t"
5665 "ADD $dst, 32\n"
5666 "done:" %}
5667 ins_encode %{
5668 Register Rdst = $dst$$Register;
5669 Register Rsrc = $src$$Register;
5670 Label done;
5671 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5672 __ jccb(Assembler::carryClear, done);
5673 __ lzcntl(Rdst, Rsrc);
5674 __ addl(Rdst, BitsPerInt);
5675 __ bind(done);
5676 %}
5677 ins_pipe(ialu_reg);
5678 %}
5679
5680 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5681 predicate(!UseCountLeadingZerosInstruction);
5682 match(Set dst (CountLeadingZerosL src));
5683 effect(TEMP dst, KILL cr);
5684
5685 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5686 "JZ msw_is_zero\n\t"
5687 "ADD $dst, 32\n\t"
5688 "JMP not_zero\n"
5689 "msw_is_zero:\n\t"
5690 "BSR $dst, $src.lo\n\t"
5691 "JNZ not_zero\n\t"
5692 "MOV $dst, -1\n"
5693 "not_zero:\n\t"
5694 "NEG $dst\n\t"
5695 "ADD $dst, 63\n" %}
5696 ins_encode %{
5697 Register Rdst = $dst$$Register;
5698 Register Rsrc = $src$$Register;
5699 Label msw_is_zero;
5700 Label not_zero;
5701 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5702 __ jccb(Assembler::zero, msw_is_zero);
5703 __ addl(Rdst, BitsPerInt);
5704 __ jmpb(not_zero);
5705 __ bind(msw_is_zero);
5706 __ bsrl(Rdst, Rsrc);
5707 __ jccb(Assembler::notZero, not_zero);
5708 __ movl(Rdst, -1);
5709 __ bind(not_zero);
5710 __ negl(Rdst);
5711 __ addl(Rdst, BitsPerLong - 1);
5712 %}
5713 ins_pipe(ialu_reg);
5714 %}
5715
5716 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5717 match(Set dst (CountTrailingZerosI src));
5718 effect(KILL cr);
5719
5720 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5721 "JNZ done\n\t"
5722 "MOV $dst, 32\n"
5723 "done:" %}
5724 ins_encode %{
5725 Register Rdst = $dst$$Register;
5726 Label done;
5727 __ bsfl(Rdst, $src$$Register);
5728 __ jccb(Assembler::notZero, done);
5729 __ movl(Rdst, BitsPerInt);
5730 __ bind(done);
5731 %}
5732 ins_pipe(ialu_reg);
5733 %}
5734
5735 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5736 match(Set dst (CountTrailingZerosL src));
5737 effect(TEMP dst, KILL cr);
5738
5739 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5740 "JNZ done\n\t"
5741 "BSF $dst, $src.hi\n\t"
5742 "JNZ msw_not_zero\n\t"
5743 "MOV $dst, 32\n"
5744 "msw_not_zero:\n\t"
5745 "ADD $dst, 32\n"
5746 "done:" %}
5747 ins_encode %{
5748 Register Rdst = $dst$$Register;
5749 Register Rsrc = $src$$Register;
5750 Label msw_not_zero;
5751 Label done;
5752 __ bsfl(Rdst, Rsrc);
5753 __ jccb(Assembler::notZero, done);
5754 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5755 __ jccb(Assembler::notZero, msw_not_zero);
5756 __ movl(Rdst, BitsPerInt);
5757 __ bind(msw_not_zero);
5758 __ addl(Rdst, BitsPerInt);
5759 __ bind(done);
5760 %}
5761 ins_pipe(ialu_reg);
5762 %}
5763
5764
5765 //---------- Population Count Instructions -------------------------------------
5766
5767 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5768 predicate(UsePopCountInstruction);
5769 match(Set dst (PopCountI src));
5770 effect(KILL cr);
5771
5772 format %{ "POPCNT $dst, $src" %}
5773 ins_encode %{
5774 __ popcntl($dst$$Register, $src$$Register);
5775 %}
5776 ins_pipe(ialu_reg);
5777 %}
5778
5779 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5780 predicate(UsePopCountInstruction);
5781 match(Set dst (PopCountI (LoadI mem)));
5782 effect(KILL cr);
5783
5784 format %{ "POPCNT $dst, $mem" %}
5785 ins_encode %{
5786 __ popcntl($dst$$Register, $mem$$Address);
5787 %}
5788 ins_pipe(ialu_reg);
5789 %}
5790
5791 // Note: Long.bitCount(long) returns an int.
5792 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5793 predicate(UsePopCountInstruction);
5794 match(Set dst (PopCountL src));
5795 effect(KILL cr, TEMP tmp, TEMP dst);
5796
5797 format %{ "POPCNT $dst, $src.lo\n\t"
5798 "POPCNT $tmp, $src.hi\n\t"
5799 "ADD $dst, $tmp" %}
5800 ins_encode %{
5801 __ popcntl($dst$$Register, $src$$Register);
5802 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5803 __ addl($dst$$Register, $tmp$$Register);
5804 %}
5805 ins_pipe(ialu_reg);
5806 %}
5807
5808 // Note: Long.bitCount(long) returns an int.
5809 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5810 predicate(UsePopCountInstruction);
5811 match(Set dst (PopCountL (LoadL mem)));
5812 effect(KILL cr, TEMP tmp, TEMP dst);
5813
5814 format %{ "POPCNT $dst, $mem\n\t"
5815 "POPCNT $tmp, $mem+4\n\t"
5816 "ADD $dst, $tmp" %}
5817 ins_encode %{
5818 //__ popcntl($dst$$Register, $mem$$Address$$first);
5819 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5820 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
5821 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
5822 __ addl($dst$$Register, $tmp$$Register);
5823 %}
5824 ins_pipe(ialu_reg);
5825 %}
5826
5827
5828 //----------Load/Store/Move Instructions---------------------------------------
5829 //----------Load Instructions--------------------------------------------------
5830 // Load Byte (8bit signed)
5831 instruct loadB(xRegI dst, memory mem) %{
5832 match(Set dst (LoadB mem));
5833
5834 ins_cost(125);
5835 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5836
5837 ins_encode %{
5838 __ movsbl($dst$$Register, $mem$$Address);
5839 %}
5840
5841 ins_pipe(ialu_reg_mem);
5842 %}
5843
5844 // Load Byte (8bit signed) into Long Register
5845 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5846 match(Set dst (ConvI2L (LoadB mem)));
5847 effect(KILL cr);
5848
5849 ins_cost(375);
5850 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5851 "MOV $dst.hi,$dst.lo\n\t"
5852 "SAR $dst.hi,7" %}
5853
5854 ins_encode %{
5855 __ movsbl($dst$$Register, $mem$$Address);
5856 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5857 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5858 %}
5859
5860 ins_pipe(ialu_reg_mem);
5861 %}
5862
5863 // Load Unsigned Byte (8bit UNsigned)
5864 instruct loadUB(xRegI dst, memory mem) %{
5865 match(Set dst (LoadUB mem));
5866
5867 ins_cost(125);
5868 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5869
5870 ins_encode %{
5871 __ movzbl($dst$$Register, $mem$$Address);
5872 %}
5873
5874 ins_pipe(ialu_reg_mem);
5875 %}
5876
5877 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5878 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5879 match(Set dst (ConvI2L (LoadUB mem)));
5880 effect(KILL cr);
5881
5882 ins_cost(250);
5883 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5884 "XOR $dst.hi,$dst.hi" %}
5885
5886 ins_encode %{
5887 Register Rdst = $dst$$Register;
5888 __ movzbl(Rdst, $mem$$Address);
5889 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5890 %}
5891
5892 ins_pipe(ialu_reg_mem);
5893 %}
5894
5895 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5896 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5897 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5898 effect(KILL cr);
5899
5900 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5901 "XOR $dst.hi,$dst.hi\n\t"
5902 "AND $dst.lo,$mask" %}
5903 ins_encode %{
5904 Register Rdst = $dst$$Register;
5905 __ movzbl(Rdst, $mem$$Address);
5906 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5907 __ andl(Rdst, $mask$$constant);
5908 %}
5909 ins_pipe(ialu_reg_mem);
5910 %}
5911
5912 // Load Short (16bit signed)
5913 instruct loadS(rRegI dst, memory mem) %{
5914 match(Set dst (LoadS mem));
5915
5916 ins_cost(125);
5917 format %{ "MOVSX $dst,$mem\t# short" %}
5918
5919 ins_encode %{
5920 __ movswl($dst$$Register, $mem$$Address);
5921 %}
5922
5923 ins_pipe(ialu_reg_mem);
5924 %}
5925
5926 // Load Short (16 bit signed) to Byte (8 bit signed)
5927 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5928 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5929
5930 ins_cost(125);
5931 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5932 ins_encode %{
5933 __ movsbl($dst$$Register, $mem$$Address);
5934 %}
5935 ins_pipe(ialu_reg_mem);
5936 %}
5937
5938 // Load Short (16bit signed) into Long Register
5939 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5940 match(Set dst (ConvI2L (LoadS mem)));
5941 effect(KILL cr);
5942
5943 ins_cost(375);
5944 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5945 "MOV $dst.hi,$dst.lo\n\t"
5946 "SAR $dst.hi,15" %}
5947
5948 ins_encode %{
5949 __ movswl($dst$$Register, $mem$$Address);
5950 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5951 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
5952 %}
5953
5954 ins_pipe(ialu_reg_mem);
5955 %}
5956
5957 // Load Unsigned Short/Char (16bit unsigned)
5958 instruct loadUS(rRegI dst, memory mem) %{
5959 match(Set dst (LoadUS mem));
5960
5961 ins_cost(125);
5962 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
5963
5964 ins_encode %{
5965 __ movzwl($dst$$Register, $mem$$Address);
5966 %}
5967
5968 ins_pipe(ialu_reg_mem);
5969 %}
5970
5971 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5972 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5973 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5974
5975 ins_cost(125);
5976 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
5977 ins_encode %{
5978 __ movsbl($dst$$Register, $mem$$Address);
5979 %}
5980 ins_pipe(ialu_reg_mem);
5981 %}
5982
5983 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5984 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5985 match(Set dst (ConvI2L (LoadUS mem)));
5986 effect(KILL cr);
5987
5988 ins_cost(250);
5989 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
5990 "XOR $dst.hi,$dst.hi" %}
5991
5992 ins_encode %{
5993 __ movzwl($dst$$Register, $mem$$Address);
5994 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
5995 %}
5996
5997 ins_pipe(ialu_reg_mem);
5998 %}
5999
6000 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6001 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6002 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6003 effect(KILL cr);
6004
6005 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6006 "XOR $dst.hi,$dst.hi" %}
6007 ins_encode %{
6008 Register Rdst = $dst$$Register;
6009 __ movzbl(Rdst, $mem$$Address);
6010 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6011 %}
6012 ins_pipe(ialu_reg_mem);
6013 %}
6014
6015 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6016 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6017 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6018 effect(KILL cr);
6019
6020 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6021 "XOR $dst.hi,$dst.hi\n\t"
6022 "AND $dst.lo,$mask" %}
6023 ins_encode %{
6024 Register Rdst = $dst$$Register;
6025 __ movzwl(Rdst, $mem$$Address);
6026 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6027 __ andl(Rdst, $mask$$constant);
6028 %}
6029 ins_pipe(ialu_reg_mem);
6030 %}
6031
6032 // Load Integer
6033 instruct loadI(rRegI dst, memory mem) %{
6034 match(Set dst (LoadI mem));
6035
6036 ins_cost(125);
6037 format %{ "MOV $dst,$mem\t# int" %}
6038
6039 ins_encode %{
6040 __ movl($dst$$Register, $mem$$Address);
6041 %}
6042
6043 ins_pipe(ialu_reg_mem);
6044 %}
6045
6046 // Load Integer (32 bit signed) to Byte (8 bit signed)
6047 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6048 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6049
6050 ins_cost(125);
6051 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6052 ins_encode %{
6053 __ movsbl($dst$$Register, $mem$$Address);
6054 %}
6055 ins_pipe(ialu_reg_mem);
6056 %}
6057
6058 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6059 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6060 match(Set dst (AndI (LoadI mem) mask));
6061
6062 ins_cost(125);
6063 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6064 ins_encode %{
6065 __ movzbl($dst$$Register, $mem$$Address);
6066 %}
6067 ins_pipe(ialu_reg_mem);
6068 %}
6069
6070 // Load Integer (32 bit signed) to Short (16 bit signed)
6071 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6072 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6073
6074 ins_cost(125);
6075 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6076 ins_encode %{
6077 __ movswl($dst$$Register, $mem$$Address);
6078 %}
6079 ins_pipe(ialu_reg_mem);
6080 %}
6081
6082 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6083 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6084 match(Set dst (AndI (LoadI mem) mask));
6085
6086 ins_cost(125);
6087 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6088 ins_encode %{
6089 __ movzwl($dst$$Register, $mem$$Address);
6090 %}
6091 ins_pipe(ialu_reg_mem);
6092 %}
6093
6094 // Load Integer into Long Register
6095 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6096 match(Set dst (ConvI2L (LoadI mem)));
6097 effect(KILL cr);
6098
6099 ins_cost(375);
6100 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6101 "MOV $dst.hi,$dst.lo\n\t"
6102 "SAR $dst.hi,31" %}
6103
6104 ins_encode %{
6105 __ movl($dst$$Register, $mem$$Address);
6106 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6107 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6108 %}
6109
6110 ins_pipe(ialu_reg_mem);
6111 %}
6112
6113 // Load Integer with mask 0xFF into Long Register
6114 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6115 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6116 effect(KILL cr);
6117
6118 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6119 "XOR $dst.hi,$dst.hi" %}
6120 ins_encode %{
6121 Register Rdst = $dst$$Register;
6122 __ movzbl(Rdst, $mem$$Address);
6123 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6124 %}
6125 ins_pipe(ialu_reg_mem);
6126 %}
6127
6128 // Load Integer with mask 0xFFFF into Long Register
6129 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6130 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6131 effect(KILL cr);
6132
6133 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6134 "XOR $dst.hi,$dst.hi" %}
6135 ins_encode %{
6136 Register Rdst = $dst$$Register;
6137 __ movzwl(Rdst, $mem$$Address);
6138 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6139 %}
6140 ins_pipe(ialu_reg_mem);
6141 %}
6142
6143 // Load Integer with 32-bit mask into Long Register
6144 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{
6145 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6146 effect(KILL cr);
6147
6148 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t"
6149 "XOR $dst.hi,$dst.hi\n\t"
6150 "AND $dst.lo,$mask" %}
6151 ins_encode %{
6152 Register Rdst = $dst$$Register;
6153 __ movl(Rdst, $mem$$Address);
6154 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6155 __ andl(Rdst, $mask$$constant);
6156 %}
6157 ins_pipe(ialu_reg_mem);
6158 %}
6159
6160 // Load Unsigned Integer into Long Register
6161 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6162 match(Set dst (LoadUI2L mem));
6163 effect(KILL cr);
6164
6165 ins_cost(250);
6166 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6167 "XOR $dst.hi,$dst.hi" %}
6168
6169 ins_encode %{
6170 __ movl($dst$$Register, $mem$$Address);
6171 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6172 %}
6173
6174 ins_pipe(ialu_reg_mem);
6175 %}
6176
6177 // Load Long. Cannot clobber address while loading, so restrict address
6178 // register to ESI
6179 instruct loadL(eRegL dst, load_long_memory mem) %{
6180 predicate(!((LoadLNode*)n)->require_atomic_access());
6181 match(Set dst (LoadL mem));
6182
6183 ins_cost(250);
6184 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6185 "MOV $dst.hi,$mem+4" %}
6186
6187 ins_encode %{
6188 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6189 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6190 __ movl($dst$$Register, Amemlo);
6191 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6192 %}
6193
6194 ins_pipe(ialu_reg_long_mem);
6195 %}
6196
6197 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6198 // then store it down to the stack and reload on the int
6199 // side.
6200 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6201 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6202 match(Set dst (LoadL mem));
6203
6204 ins_cost(200);
6205 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6206 "FISTp $dst" %}
6207 ins_encode(enc_loadL_volatile(mem,dst));
6208 ins_pipe( fpu_reg_mem );
6209 %}
6210
6211 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6212 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6213 match(Set dst (LoadL mem));
6214 effect(TEMP tmp);
6215 ins_cost(180);
6216 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6217 "MOVSD $dst,$tmp" %}
6218 ins_encode %{
6219 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6220 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6221 %}
6222 ins_pipe( pipe_slow );
6223 %}
6224
6225 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6226 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6227 match(Set dst (LoadL mem));
6228 effect(TEMP tmp);
6229 ins_cost(160);
6230 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6231 "MOVD $dst.lo,$tmp\n\t"
6232 "PSRLQ $tmp,32\n\t"
6233 "MOVD $dst.hi,$tmp" %}
6234 ins_encode %{
6235 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6236 __ movdl($dst$$Register, $tmp$$XMMRegister);
6237 __ psrlq($tmp$$XMMRegister, 32);
6238 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6239 %}
6240 ins_pipe( pipe_slow );
6241 %}
6242
6243 // Load Range
6244 instruct loadRange(rRegI dst, memory mem) %{
6245 match(Set dst (LoadRange mem));
6246
6247 ins_cost(125);
6248 format %{ "MOV $dst,$mem" %}
6249 opcode(0x8B);
6250 ins_encode( OpcP, RegMem(dst,mem));
6251 ins_pipe( ialu_reg_mem );
6252 %}
6253
6254
6255 // Load Pointer
6256 instruct loadP(eRegP dst, memory mem) %{
6257 match(Set dst (LoadP mem));
6258
6259 ins_cost(125);
6260 format %{ "MOV $dst,$mem" %}
6261 opcode(0x8B);
6262 ins_encode( OpcP, RegMem(dst,mem));
6263 ins_pipe( ialu_reg_mem );
6264 %}
6265
6266 // Load Klass Pointer
6267 instruct loadKlass(eRegP dst, memory mem) %{
6268 match(Set dst (LoadKlass mem));
6269
6270 ins_cost(125);
6271 format %{ "MOV $dst,$mem" %}
6272 opcode(0x8B);
6273 ins_encode( OpcP, RegMem(dst,mem));
6274 ins_pipe( ialu_reg_mem );
6275 %}
6276
6277 // Load Double
6278 instruct loadDPR(regDPR dst, memory mem) %{
6279 predicate(UseSSE<=1);
6280 match(Set dst (LoadD mem));
6281
6282 ins_cost(150);
6283 format %{ "FLD_D ST,$mem\n\t"
6284 "FSTP $dst" %}
6285 opcode(0xDD); /* DD /0 */
6286 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6287 Pop_Reg_DPR(dst) );
6288 ins_pipe( fpu_reg_mem );
6289 %}
6290
6291 // Load Double to XMM
6292 instruct loadD(regD dst, memory mem) %{
6293 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6294 match(Set dst (LoadD mem));
6295 ins_cost(145);
6296 format %{ "MOVSD $dst,$mem" %}
6297 ins_encode %{
6298 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6299 %}
6300 ins_pipe( pipe_slow );
6301 %}
6302
6303 instruct loadD_partial(regD dst, memory mem) %{
6304 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6305 match(Set dst (LoadD mem));
6306 ins_cost(145);
6307 format %{ "MOVLPD $dst,$mem" %}
6308 ins_encode %{
6309 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6310 %}
6311 ins_pipe( pipe_slow );
6312 %}
6313
6314 // Load to XMM register (single-precision floating point)
6315 // MOVSS instruction
6316 instruct loadF(regF dst, memory mem) %{
6317 predicate(UseSSE>=1);
6318 match(Set dst (LoadF mem));
6319 ins_cost(145);
6320 format %{ "MOVSS $dst,$mem" %}
6321 ins_encode %{
6322 __ movflt ($dst$$XMMRegister, $mem$$Address);
6323 %}
6324 ins_pipe( pipe_slow );
6325 %}
6326
6327 // Load Float
6328 instruct loadFPR(regFPR dst, memory mem) %{
6329 predicate(UseSSE==0);
6330 match(Set dst (LoadF mem));
6331
6332 ins_cost(150);
6333 format %{ "FLD_S ST,$mem\n\t"
6334 "FSTP $dst" %}
6335 opcode(0xD9); /* D9 /0 */
6336 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6337 Pop_Reg_FPR(dst) );
6338 ins_pipe( fpu_reg_mem );
6339 %}
6340
6341 // Load Effective Address
6342 instruct leaP8(eRegP dst, indOffset8 mem) %{
6343 match(Set dst mem);
6344
6345 ins_cost(110);
6346 format %{ "LEA $dst,$mem" %}
6347 opcode(0x8D);
6348 ins_encode( OpcP, RegMem(dst,mem));
6349 ins_pipe( ialu_reg_reg_fat );
6350 %}
6351
6352 instruct leaP32(eRegP dst, indOffset32 mem) %{
6353 match(Set dst mem);
6354
6355 ins_cost(110);
6356 format %{ "LEA $dst,$mem" %}
6357 opcode(0x8D);
6358 ins_encode( OpcP, RegMem(dst,mem));
6359 ins_pipe( ialu_reg_reg_fat );
6360 %}
6361
6362 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6363 match(Set dst mem);
6364
6365 ins_cost(110);
6366 format %{ "LEA $dst,$mem" %}
6367 opcode(0x8D);
6368 ins_encode( OpcP, RegMem(dst,mem));
6369 ins_pipe( ialu_reg_reg_fat );
6370 %}
6371
6372 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6373 match(Set dst mem);
6374
6375 ins_cost(110);
6376 format %{ "LEA $dst,$mem" %}
6377 opcode(0x8D);
6378 ins_encode( OpcP, RegMem(dst,mem));
6379 ins_pipe( ialu_reg_reg_fat );
6380 %}
6381
6382 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6383 match(Set dst mem);
6384
6385 ins_cost(110);
6386 format %{ "LEA $dst,$mem" %}
6387 opcode(0x8D);
6388 ins_encode( OpcP, RegMem(dst,mem));
6389 ins_pipe( ialu_reg_reg_fat );
6390 %}
6391
6392 // Load Constant
6393 instruct loadConI(rRegI dst, immI src) %{
6394 match(Set dst src);
6395
6396 format %{ "MOV $dst,$src" %}
6397 ins_encode( LdImmI(dst, src) );
6398 ins_pipe( ialu_reg_fat );
6399 %}
6400
6401 // Load Constant zero
6402 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6403 match(Set dst src);
6404 effect(KILL cr);
6405
6406 ins_cost(50);
6407 format %{ "XOR $dst,$dst" %}
6408 opcode(0x33); /* + rd */
6409 ins_encode( OpcP, RegReg( dst, dst ) );
6410 ins_pipe( ialu_reg );
6411 %}
6412
6413 instruct loadConP(eRegP dst, immP src) %{
6414 match(Set dst src);
6415
6416 format %{ "MOV $dst,$src" %}
6417 opcode(0xB8); /* + rd */
6418 ins_encode( LdImmP(dst, src) );
6419 ins_pipe( ialu_reg_fat );
6420 %}
6421
6422 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6423 match(Set dst src);
6424 effect(KILL cr);
6425 ins_cost(200);
6426 format %{ "MOV $dst.lo,$src.lo\n\t"
6427 "MOV $dst.hi,$src.hi" %}
6428 opcode(0xB8);
6429 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6430 ins_pipe( ialu_reg_long_fat );
6431 %}
6432
6433 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6434 match(Set dst src);
6435 effect(KILL cr);
6436 ins_cost(150);
6437 format %{ "XOR $dst.lo,$dst.lo\n\t"
6438 "XOR $dst.hi,$dst.hi" %}
6439 opcode(0x33,0x33);
6440 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6441 ins_pipe( ialu_reg_long );
6442 %}
6443
6444 // The instruction usage is guarded by predicate in operand immFPR().
6445 instruct loadConFPR(regFPR dst, immFPR con) %{
6446 match(Set dst con);
6447 ins_cost(125);
6448 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6449 "FSTP $dst" %}
6450 ins_encode %{
6451 __ fld_s($constantaddress($con));
6452 __ fstp_d($dst$$reg);
6453 %}
6454 ins_pipe(fpu_reg_con);
6455 %}
6456
6457 // The instruction usage is guarded by predicate in operand immFPR0().
6458 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6459 match(Set dst con);
6460 ins_cost(125);
6461 format %{ "FLDZ ST\n\t"
6462 "FSTP $dst" %}
6463 ins_encode %{
6464 __ fldz();
6465 __ fstp_d($dst$$reg);
6466 %}
6467 ins_pipe(fpu_reg_con);
6468 %}
6469
6470 // The instruction usage is guarded by predicate in operand immFPR1().
6471 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6472 match(Set dst con);
6473 ins_cost(125);
6474 format %{ "FLD1 ST\n\t"
6475 "FSTP $dst" %}
6476 ins_encode %{
6477 __ fld1();
6478 __ fstp_d($dst$$reg);
6479 %}
6480 ins_pipe(fpu_reg_con);
6481 %}
6482
6483 // The instruction usage is guarded by predicate in operand immF().
6484 instruct loadConF(regF dst, immF con) %{
6485 match(Set dst con);
6486 ins_cost(125);
6487 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6488 ins_encode %{
6489 __ movflt($dst$$XMMRegister, $constantaddress($con));
6490 %}
6491 ins_pipe(pipe_slow);
6492 %}
6493
6494 // The instruction usage is guarded by predicate in operand immF0().
6495 instruct loadConF0(regF dst, immF0 src) %{
6496 match(Set dst src);
6497 ins_cost(100);
6498 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6499 ins_encode %{
6500 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6501 %}
6502 ins_pipe(pipe_slow);
6503 %}
6504
6505 // The instruction usage is guarded by predicate in operand immDPR().
6506 instruct loadConDPR(regDPR dst, immDPR con) %{
6507 match(Set dst con);
6508 ins_cost(125);
6509
6510 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6511 "FSTP $dst" %}
6512 ins_encode %{
6513 __ fld_d($constantaddress($con));
6514 __ fstp_d($dst$$reg);
6515 %}
6516 ins_pipe(fpu_reg_con);
6517 %}
6518
6519 // The instruction usage is guarded by predicate in operand immDPR0().
6520 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6521 match(Set dst con);
6522 ins_cost(125);
6523
6524 format %{ "FLDZ ST\n\t"
6525 "FSTP $dst" %}
6526 ins_encode %{
6527 __ fldz();
6528 __ fstp_d($dst$$reg);
6529 %}
6530 ins_pipe(fpu_reg_con);
6531 %}
6532
6533 // The instruction usage is guarded by predicate in operand immDPR1().
6534 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6535 match(Set dst con);
6536 ins_cost(125);
6537
6538 format %{ "FLD1 ST\n\t"
6539 "FSTP $dst" %}
6540 ins_encode %{
6541 __ fld1();
6542 __ fstp_d($dst$$reg);
6543 %}
6544 ins_pipe(fpu_reg_con);
6545 %}
6546
6547 // The instruction usage is guarded by predicate in operand immD().
6548 instruct loadConD(regD dst, immD con) %{
6549 match(Set dst con);
6550 ins_cost(125);
6551 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6552 ins_encode %{
6553 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6554 %}
6555 ins_pipe(pipe_slow);
6556 %}
6557
6558 // The instruction usage is guarded by predicate in operand immD0().
6559 instruct loadConD0(regD dst, immD0 src) %{
6560 match(Set dst src);
6561 ins_cost(100);
6562 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6563 ins_encode %{
6564 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6565 %}
6566 ins_pipe( pipe_slow );
6567 %}
6568
6569 // Load Stack Slot
6570 instruct loadSSI(rRegI dst, stackSlotI src) %{
6571 match(Set dst src);
6572 ins_cost(125);
6573
6574 format %{ "MOV $dst,$src" %}
6575 opcode(0x8B);
6576 ins_encode( OpcP, RegMem(dst,src));
6577 ins_pipe( ialu_reg_mem );
6578 %}
6579
6580 instruct loadSSL(eRegL dst, stackSlotL src) %{
6581 match(Set dst src);
6582
6583 ins_cost(200);
6584 format %{ "MOV $dst,$src.lo\n\t"
6585 "MOV $dst+4,$src.hi" %}
6586 opcode(0x8B, 0x8B);
6587 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6588 ins_pipe( ialu_mem_long_reg );
6589 %}
6590
6591 // Load Stack Slot
6592 instruct loadSSP(eRegP dst, stackSlotP src) %{
6593 match(Set dst src);
6594 ins_cost(125);
6595
6596 format %{ "MOV $dst,$src" %}
6597 opcode(0x8B);
6598 ins_encode( OpcP, RegMem(dst,src));
6599 ins_pipe( ialu_reg_mem );
6600 %}
6601
6602 // Load Stack Slot
6603 instruct loadSSF(regFPR dst, stackSlotF src) %{
6604 match(Set dst src);
6605 ins_cost(125);
6606
6607 format %{ "FLD_S $src\n\t"
6608 "FSTP $dst" %}
6609 opcode(0xD9); /* D9 /0, FLD m32real */
6610 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6611 Pop_Reg_FPR(dst) );
6612 ins_pipe( fpu_reg_mem );
6613 %}
6614
6615 // Load Stack Slot
6616 instruct loadSSD(regDPR dst, stackSlotD src) %{
6617 match(Set dst src);
6618 ins_cost(125);
6619
6620 format %{ "FLD_D $src\n\t"
6621 "FSTP $dst" %}
6622 opcode(0xDD); /* DD /0, FLD m64real */
6623 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6624 Pop_Reg_DPR(dst) );
6625 ins_pipe( fpu_reg_mem );
6626 %}
6627
6628 // Prefetch instructions.
6629 // Must be safe to execute with invalid address (cannot fault).
6630
6631 instruct prefetchr0( memory mem ) %{
6632 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6633 match(PrefetchRead mem);
6634 ins_cost(0);
6635 size(0);
6636 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6637 ins_encode();
6638 ins_pipe(empty);
6639 %}
6640
6641 instruct prefetchr( memory mem ) %{
6642 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6643 match(PrefetchRead mem);
6644 ins_cost(100);
6645
6646 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6647 ins_encode %{
6648 __ prefetchr($mem$$Address);
6649 %}
6650 ins_pipe(ialu_mem);
6651 %}
6652
6653 instruct prefetchrNTA( memory mem ) %{
6654 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6655 match(PrefetchRead mem);
6656 ins_cost(100);
6657
6658 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6659 ins_encode %{
6660 __ prefetchnta($mem$$Address);
6661 %}
6662 ins_pipe(ialu_mem);
6663 %}
6664
6665 instruct prefetchrT0( memory mem ) %{
6666 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6667 match(PrefetchRead mem);
6668 ins_cost(100);
6669
6670 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6671 ins_encode %{
6672 __ prefetcht0($mem$$Address);
6673 %}
6674 ins_pipe(ialu_mem);
6675 %}
6676
6677 instruct prefetchrT2( memory mem ) %{
6678 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6679 match(PrefetchRead mem);
6680 ins_cost(100);
6681
6682 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6683 ins_encode %{
6684 __ prefetcht2($mem$$Address);
6685 %}
6686 ins_pipe(ialu_mem);
6687 %}
6688
6689 instruct prefetchw0( memory mem ) %{
6690 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6691 match(PrefetchWrite mem);
6692 ins_cost(0);
6693 size(0);
6694 format %{ "Prefetch (non-SSE is empty encoding)" %}
6695 ins_encode();
6696 ins_pipe(empty);
6697 %}
6698
6699 instruct prefetchw( memory mem ) %{
6700 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6701 match( PrefetchWrite mem );
6702 ins_cost(100);
6703
6704 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6705 ins_encode %{
6706 __ prefetchw($mem$$Address);
6707 %}
6708 ins_pipe(ialu_mem);
6709 %}
6710
6711 instruct prefetchwNTA( memory mem ) %{
6712 predicate(UseSSE>=1);
6713 match(PrefetchWrite mem);
6714 ins_cost(100);
6715
6716 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6717 ins_encode %{
6718 __ prefetchnta($mem$$Address);
6719 %}
6720 ins_pipe(ialu_mem);
6721 %}
6722
6723 // Prefetch instructions for allocation.
6724
6725 instruct prefetchAlloc0( memory mem ) %{
6726 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6727 match(PrefetchAllocation mem);
6728 ins_cost(0);
6729 size(0);
6730 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6731 ins_encode();
6732 ins_pipe(empty);
6733 %}
6734
6735 instruct prefetchAlloc( memory mem ) %{
6736 predicate(AllocatePrefetchInstr==3);
6737 match( PrefetchAllocation mem );
6738 ins_cost(100);
6739
6740 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6741 ins_encode %{
6742 __ prefetchw($mem$$Address);
6743 %}
6744 ins_pipe(ialu_mem);
6745 %}
6746
6747 instruct prefetchAllocNTA( memory mem ) %{
6748 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6749 match(PrefetchAllocation mem);
6750 ins_cost(100);
6751
6752 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6753 ins_encode %{
6754 __ prefetchnta($mem$$Address);
6755 %}
6756 ins_pipe(ialu_mem);
6757 %}
6758
6759 instruct prefetchAllocT0( memory mem ) %{
6760 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6761 match(PrefetchAllocation mem);
6762 ins_cost(100);
6763
6764 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6765 ins_encode %{
6766 __ prefetcht0($mem$$Address);
6767 %}
6768 ins_pipe(ialu_mem);
6769 %}
6770
6771 instruct prefetchAllocT2( memory mem ) %{
6772 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6773 match(PrefetchAllocation mem);
6774 ins_cost(100);
6775
6776 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6777 ins_encode %{
6778 __ prefetcht2($mem$$Address);
6779 %}
6780 ins_pipe(ialu_mem);
6781 %}
6782
6783 //----------Store Instructions-------------------------------------------------
6784
6785 // Store Byte
6786 instruct storeB(memory mem, xRegI src) %{
6787 match(Set mem (StoreB mem src));
6788
6789 ins_cost(125);
6790 format %{ "MOV8 $mem,$src" %}
6791 opcode(0x88);
6792 ins_encode( OpcP, RegMem( src, mem ) );
6793 ins_pipe( ialu_mem_reg );
6794 %}
6795
6796 // Store Char/Short
6797 instruct storeC(memory mem, rRegI src) %{
6798 match(Set mem (StoreC mem src));
6799
6800 ins_cost(125);
6801 format %{ "MOV16 $mem,$src" %}
6802 opcode(0x89, 0x66);
6803 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6804 ins_pipe( ialu_mem_reg );
6805 %}
6806
6807 // Store Integer
6808 instruct storeI(memory mem, rRegI src) %{
6809 match(Set mem (StoreI mem src));
6810
6811 ins_cost(125);
6812 format %{ "MOV $mem,$src" %}
6813 opcode(0x89);
6814 ins_encode( OpcP, RegMem( src, mem ) );
6815 ins_pipe( ialu_mem_reg );
6816 %}
6817
6818 // Store Long
6819 instruct storeL(long_memory mem, eRegL src) %{
6820 predicate(!((StoreLNode*)n)->require_atomic_access());
6821 match(Set mem (StoreL mem src));
6822
6823 ins_cost(200);
6824 format %{ "MOV $mem,$src.lo\n\t"
6825 "MOV $mem+4,$src.hi" %}
6826 opcode(0x89, 0x89);
6827 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6828 ins_pipe( ialu_mem_long_reg );
6829 %}
6830
6831 // Store Long to Integer
6832 instruct storeL2I(memory mem, eRegL src) %{
6833 match(Set mem (StoreI mem (ConvL2I src)));
6834
6835 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6836 ins_encode %{
6837 __ movl($mem$$Address, $src$$Register);
6838 %}
6839 ins_pipe(ialu_mem_reg);
6840 %}
6841
6842 // Volatile Store Long. Must be atomic, so move it into
6843 // the FP TOS and then do a 64-bit FIST. Has to probe the
6844 // target address before the store (for null-ptr checks)
6845 // so the memory operand is used twice in the encoding.
6846 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6847 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6848 match(Set mem (StoreL mem src));
6849 effect( KILL cr );
6850 ins_cost(400);
6851 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6852 "FILD $src\n\t"
6853 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6854 opcode(0x3B);
6855 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6856 ins_pipe( fpu_reg_mem );
6857 %}
6858
6859 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6860 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6861 match(Set mem (StoreL mem src));
6862 effect( TEMP tmp, KILL cr );
6863 ins_cost(380);
6864 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6865 "MOVSD $tmp,$src\n\t"
6866 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6867 ins_encode %{
6868 __ cmpl(rax, $mem$$Address);
6869 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6870 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6871 %}
6872 ins_pipe( pipe_slow );
6873 %}
6874
6875 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6876 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6877 match(Set mem (StoreL mem src));
6878 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6879 ins_cost(360);
6880 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6881 "MOVD $tmp,$src.lo\n\t"
6882 "MOVD $tmp2,$src.hi\n\t"
6883 "PUNPCKLDQ $tmp,$tmp2\n\t"
6884 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6885 ins_encode %{
6886 __ cmpl(rax, $mem$$Address);
6887 __ movdl($tmp$$XMMRegister, $src$$Register);
6888 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6889 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6890 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6891 %}
6892 ins_pipe( pipe_slow );
6893 %}
6894
6895 // Store Pointer; for storing unknown oops and raw pointers
6896 instruct storeP(memory mem, anyRegP src) %{
6897 match(Set mem (StoreP mem src));
6898
6899 ins_cost(125);
6900 format %{ "MOV $mem,$src" %}
6901 opcode(0x89);
6902 ins_encode( OpcP, RegMem( src, mem ) );
6903 ins_pipe( ialu_mem_reg );
6904 %}
6905
6906 // Store Integer Immediate
6907 instruct storeImmI(memory mem, immI src) %{
6908 match(Set mem (StoreI mem src));
6909
6910 ins_cost(150);
6911 format %{ "MOV $mem,$src" %}
6912 opcode(0xC7); /* C7 /0 */
6913 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6914 ins_pipe( ialu_mem_imm );
6915 %}
6916
6917 // Store Short/Char Immediate
6918 instruct storeImmI16(memory mem, immI16 src) %{
6919 predicate(UseStoreImmI16);
6920 match(Set mem (StoreC mem src));
6921
6922 ins_cost(150);
6923 format %{ "MOV16 $mem,$src" %}
6924 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6925 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6926 ins_pipe( ialu_mem_imm );
6927 %}
6928
6929 // Store Pointer Immediate; null pointers or constant oops that do not
6930 // need card-mark barriers.
6931 instruct storeImmP(memory mem, immP src) %{
6932 match(Set mem (StoreP mem src));
6933
6934 ins_cost(150);
6935 format %{ "MOV $mem,$src" %}
6936 opcode(0xC7); /* C7 /0 */
6937 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6938 ins_pipe( ialu_mem_imm );
6939 %}
6940
6941 // Store Byte Immediate
6942 instruct storeImmB(memory mem, immI8 src) %{
6943 match(Set mem (StoreB mem src));
6944
6945 ins_cost(150);
6946 format %{ "MOV8 $mem,$src" %}
6947 opcode(0xC6); /* C6 /0 */
6948 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6949 ins_pipe( ialu_mem_imm );
6950 %}
6951
6952 // Store CMS card-mark Immediate
6953 instruct storeImmCM(memory mem, immI8 src) %{
6954 match(Set mem (StoreCM mem src));
6955
6956 ins_cost(150);
6957 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
6958 opcode(0xC6); /* C6 /0 */
6959 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
6960 ins_pipe( ialu_mem_imm );
6961 %}
6962
6963 // Store Double
6964 instruct storeDPR( memory mem, regDPR1 src) %{
6965 predicate(UseSSE<=1);
6966 match(Set mem (StoreD mem src));
6967
6968 ins_cost(100);
6969 format %{ "FST_D $mem,$src" %}
6970 opcode(0xDD); /* DD /2 */
6971 ins_encode( enc_FPR_store(mem,src) );
6972 ins_pipe( fpu_mem_reg );
6973 %}
6974
6975 // Store double does rounding on x86
6976 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
6977 predicate(UseSSE<=1);
6978 match(Set mem (StoreD mem (RoundDouble src)));
6979
6980 ins_cost(100);
6981 format %{ "FST_D $mem,$src\t# round" %}
6982 opcode(0xDD); /* DD /2 */
6983 ins_encode( enc_FPR_store(mem,src) );
6984 ins_pipe( fpu_mem_reg );
6985 %}
6986
6987 // Store XMM register to memory (double-precision floating points)
6988 // MOVSD instruction
6989 instruct storeD(memory mem, regD src) %{
6990 predicate(UseSSE>=2);
6991 match(Set mem (StoreD mem src));
6992 ins_cost(95);
6993 format %{ "MOVSD $mem,$src" %}
6994 ins_encode %{
6995 __ movdbl($mem$$Address, $src$$XMMRegister);
6996 %}
6997 ins_pipe( pipe_slow );
6998 %}
6999
7000 // Store XMM register to memory (single-precision floating point)
7001 // MOVSS instruction
7002 instruct storeF(memory mem, regF src) %{
7003 predicate(UseSSE>=1);
7004 match(Set mem (StoreF mem src));
7005 ins_cost(95);
7006 format %{ "MOVSS $mem,$src" %}
7007 ins_encode %{
7008 __ movflt($mem$$Address, $src$$XMMRegister);
7009 %}
7010 ins_pipe( pipe_slow );
7011 %}
7012
7013 // Store Float
7014 instruct storeFPR( memory mem, regFPR1 src) %{
7015 predicate(UseSSE==0);
7016 match(Set mem (StoreF mem src));
7017
7018 ins_cost(100);
7019 format %{ "FST_S $mem,$src" %}
7020 opcode(0xD9); /* D9 /2 */
7021 ins_encode( enc_FPR_store(mem,src) );
7022 ins_pipe( fpu_mem_reg );
7023 %}
7024
7025 // Store Float does rounding on x86
7026 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7027 predicate(UseSSE==0);
7028 match(Set mem (StoreF mem (RoundFloat src)));
7029
7030 ins_cost(100);
7031 format %{ "FST_S $mem,$src\t# round" %}
7032 opcode(0xD9); /* D9 /2 */
7033 ins_encode( enc_FPR_store(mem,src) );
7034 ins_pipe( fpu_mem_reg );
7035 %}
7036
7037 // Store Float does rounding on x86
7038 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7039 predicate(UseSSE<=1);
7040 match(Set mem (StoreF mem (ConvD2F src)));
7041
7042 ins_cost(100);
7043 format %{ "FST_S $mem,$src\t# D-round" %}
7044 opcode(0xD9); /* D9 /2 */
7045 ins_encode( enc_FPR_store(mem,src) );
7046 ins_pipe( fpu_mem_reg );
7047 %}
7048
7049 // Store immediate Float value (it is faster than store from FPU register)
7050 // The instruction usage is guarded by predicate in operand immFPR().
7051 instruct storeFPR_imm( memory mem, immFPR src) %{
7052 match(Set mem (StoreF mem src));
7053
7054 ins_cost(50);
7055 format %{ "MOV $mem,$src\t# store float" %}
7056 opcode(0xC7); /* C7 /0 */
7057 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7058 ins_pipe( ialu_mem_imm );
7059 %}
7060
7061 // Store immediate Float value (it is faster than store from XMM register)
7062 // The instruction usage is guarded by predicate in operand immF().
7063 instruct storeF_imm( memory mem, immF src) %{
7064 match(Set mem (StoreF mem src));
7065
7066 ins_cost(50);
7067 format %{ "MOV $mem,$src\t# store float" %}
7068 opcode(0xC7); /* C7 /0 */
7069 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7070 ins_pipe( ialu_mem_imm );
7071 %}
7072
7073 // Store Integer to stack slot
7074 instruct storeSSI(stackSlotI dst, rRegI src) %{
7075 match(Set dst src);
7076
7077 ins_cost(100);
7078 format %{ "MOV $dst,$src" %}
7079 opcode(0x89);
7080 ins_encode( OpcPRegSS( dst, src ) );
7081 ins_pipe( ialu_mem_reg );
7082 %}
7083
7084 // Store Integer to stack slot
7085 instruct storeSSP(stackSlotP dst, eRegP src) %{
7086 match(Set dst src);
7087
7088 ins_cost(100);
7089 format %{ "MOV $dst,$src" %}
7090 opcode(0x89);
7091 ins_encode( OpcPRegSS( dst, src ) );
7092 ins_pipe( ialu_mem_reg );
7093 %}
7094
7095 // Store Long to stack slot
7096 instruct storeSSL(stackSlotL dst, eRegL src) %{
7097 match(Set dst src);
7098
7099 ins_cost(200);
7100 format %{ "MOV $dst,$src.lo\n\t"
7101 "MOV $dst+4,$src.hi" %}
7102 opcode(0x89, 0x89);
7103 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7104 ins_pipe( ialu_mem_long_reg );
7105 %}
7106
7107 //----------MemBar Instructions-----------------------------------------------
7108 // Memory barrier flavors
7109
7110 instruct membar_acquire() %{
7111 match(MemBarAcquire);
7112 ins_cost(400);
7113
7114 size(0);
7115 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7116 ins_encode();
7117 ins_pipe(empty);
7118 %}
7119
7120 instruct membar_acquire_lock() %{
7121 match(MemBarAcquireLock);
7122 ins_cost(0);
7123
7124 size(0);
7125 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7126 ins_encode( );
7127 ins_pipe(empty);
7128 %}
7129
7130 instruct membar_release() %{
7131 match(MemBarRelease);
7132 ins_cost(400);
7133
7134 size(0);
7135 format %{ "MEMBAR-release ! (empty encoding)" %}
7136 ins_encode( );
7137 ins_pipe(empty);
7138 %}
7139
7140 instruct membar_release_lock() %{
7141 match(MemBarReleaseLock);
7142 ins_cost(0);
7143
7144 size(0);
7145 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7146 ins_encode( );
7147 ins_pipe(empty);
7148 %}
7149
7150 instruct membar_volatile(eFlagsReg cr) %{
7151 match(MemBarVolatile);
7152 effect(KILL cr);
7153 ins_cost(400);
7154
7155 format %{
7156 $$template
7157 if (os::is_MP()) {
7158 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7159 } else {
7160 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7161 }
7162 %}
7163 ins_encode %{
7164 __ membar(Assembler::StoreLoad);
7165 %}
7166 ins_pipe(pipe_slow);
7167 %}
7168
7169 instruct unnecessary_membar_volatile() %{
7170 match(MemBarVolatile);
7171 predicate(Matcher::post_store_load_barrier(n));
7172 ins_cost(0);
7173
7174 size(0);
7175 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7176 ins_encode( );
7177 ins_pipe(empty);
7178 %}
7179
7180 instruct membar_storestore() %{
7181 match(MemBarStoreStore);
7182 ins_cost(0);
7183
7184 size(0);
7185 format %{ "MEMBAR-storestore (empty encoding)" %}
7186 ins_encode( );
7187 ins_pipe(empty);
7188 %}
7189
7190 //----------Move Instructions--------------------------------------------------
7191 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7192 match(Set dst (CastX2P src));
7193 format %{ "# X2P $dst, $src" %}
7194 ins_encode( /*empty encoding*/ );
7195 ins_cost(0);
7196 ins_pipe(empty);
7197 %}
7198
7199 instruct castP2X(rRegI dst, eRegP src ) %{
7200 match(Set dst (CastP2X src));
7201 ins_cost(50);
7202 format %{ "MOV $dst, $src\t# CastP2X" %}
7203 ins_encode( enc_Copy( dst, src) );
7204 ins_pipe( ialu_reg_reg );
7205 %}
7206
7207 //----------Conditional Move---------------------------------------------------
7208 // Conditional move
7209 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7210 predicate(!VM_Version::supports_cmov() );
7211 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7212 ins_cost(200);
7213 format %{ "J$cop,us skip\t# signed cmove\n\t"
7214 "MOV $dst,$src\n"
7215 "skip:" %}
7216 ins_encode %{
7217 Label Lskip;
7218 // Invert sense of branch from sense of CMOV
7219 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7220 __ movl($dst$$Register, $src$$Register);
7221 __ bind(Lskip);
7222 %}
7223 ins_pipe( pipe_cmov_reg );
7224 %}
7225
7226 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7227 predicate(!VM_Version::supports_cmov() );
7228 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7229 ins_cost(200);
7230 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7231 "MOV $dst,$src\n"
7232 "skip:" %}
7233 ins_encode %{
7234 Label Lskip;
7235 // Invert sense of branch from sense of CMOV
7236 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7237 __ movl($dst$$Register, $src$$Register);
7238 __ bind(Lskip);
7239 %}
7240 ins_pipe( pipe_cmov_reg );
7241 %}
7242
7243 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7244 predicate(VM_Version::supports_cmov() );
7245 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7246 ins_cost(200);
7247 format %{ "CMOV$cop $dst,$src" %}
7248 opcode(0x0F,0x40);
7249 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7250 ins_pipe( pipe_cmov_reg );
7251 %}
7252
7253 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7254 predicate(VM_Version::supports_cmov() );
7255 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7256 ins_cost(200);
7257 format %{ "CMOV$cop $dst,$src" %}
7258 opcode(0x0F,0x40);
7259 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7260 ins_pipe( pipe_cmov_reg );
7261 %}
7262
7263 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7264 predicate(VM_Version::supports_cmov() );
7265 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7266 ins_cost(200);
7267 expand %{
7268 cmovI_regU(cop, cr, dst, src);
7269 %}
7270 %}
7271
7272 // Conditional move
7273 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7274 predicate(VM_Version::supports_cmov() );
7275 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7276 ins_cost(250);
7277 format %{ "CMOV$cop $dst,$src" %}
7278 opcode(0x0F,0x40);
7279 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7280 ins_pipe( pipe_cmov_mem );
7281 %}
7282
7283 // Conditional move
7284 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7285 predicate(VM_Version::supports_cmov() );
7286 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7287 ins_cost(250);
7288 format %{ "CMOV$cop $dst,$src" %}
7289 opcode(0x0F,0x40);
7290 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7291 ins_pipe( pipe_cmov_mem );
7292 %}
7293
7294 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7295 predicate(VM_Version::supports_cmov() );
7296 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7297 ins_cost(250);
7298 expand %{
7299 cmovI_memU(cop, cr, dst, src);
7300 %}
7301 %}
7302
7303 // Conditional move
7304 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7305 predicate(VM_Version::supports_cmov() );
7306 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7307 ins_cost(200);
7308 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7309 opcode(0x0F,0x40);
7310 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7311 ins_pipe( pipe_cmov_reg );
7312 %}
7313
7314 // Conditional move (non-P6 version)
7315 // Note: a CMoveP is generated for stubs and native wrappers
7316 // regardless of whether we are on a P6, so we
7317 // emulate a cmov here
7318 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7319 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7320 ins_cost(300);
7321 format %{ "Jn$cop skip\n\t"
7322 "MOV $dst,$src\t# pointer\n"
7323 "skip:" %}
7324 opcode(0x8b);
7325 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7326 ins_pipe( pipe_cmov_reg );
7327 %}
7328
7329 // Conditional move
7330 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7331 predicate(VM_Version::supports_cmov() );
7332 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7333 ins_cost(200);
7334 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7335 opcode(0x0F,0x40);
7336 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7337 ins_pipe( pipe_cmov_reg );
7338 %}
7339
7340 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7341 predicate(VM_Version::supports_cmov() );
7342 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7343 ins_cost(200);
7344 expand %{
7345 cmovP_regU(cop, cr, dst, src);
7346 %}
7347 %}
7348
7349 // DISABLED: Requires the ADLC to emit a bottom_type call that
7350 // correctly meets the two pointer arguments; one is an incoming
7351 // register but the other is a memory operand. ALSO appears to
7352 // be buggy with implicit null checks.
7353 //
7354 //// Conditional move
7355 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7356 // predicate(VM_Version::supports_cmov() );
7357 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7358 // ins_cost(250);
7359 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7360 // opcode(0x0F,0x40);
7361 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7362 // ins_pipe( pipe_cmov_mem );
7363 //%}
7364 //
7365 //// Conditional move
7366 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7367 // predicate(VM_Version::supports_cmov() );
7368 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7369 // ins_cost(250);
7370 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7371 // opcode(0x0F,0x40);
7372 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7373 // ins_pipe( pipe_cmov_mem );
7374 //%}
7375
7376 // Conditional move
7377 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7378 predicate(UseSSE<=1);
7379 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7380 ins_cost(200);
7381 format %{ "FCMOV$cop $dst,$src\t# double" %}
7382 opcode(0xDA);
7383 ins_encode( enc_cmov_dpr(cop,src) );
7384 ins_pipe( pipe_cmovDPR_reg );
7385 %}
7386
7387 // Conditional move
7388 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7389 predicate(UseSSE==0);
7390 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7391 ins_cost(200);
7392 format %{ "FCMOV$cop $dst,$src\t# float" %}
7393 opcode(0xDA);
7394 ins_encode( enc_cmov_dpr(cop,src) );
7395 ins_pipe( pipe_cmovDPR_reg );
7396 %}
7397
7398 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7399 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7400 predicate(UseSSE<=1);
7401 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7402 ins_cost(200);
7403 format %{ "Jn$cop skip\n\t"
7404 "MOV $dst,$src\t# double\n"
7405 "skip:" %}
7406 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7407 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7408 ins_pipe( pipe_cmovDPR_reg );
7409 %}
7410
7411 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7412 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7413 predicate(UseSSE==0);
7414 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7415 ins_cost(200);
7416 format %{ "Jn$cop skip\n\t"
7417 "MOV $dst,$src\t# float\n"
7418 "skip:" %}
7419 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7420 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7421 ins_pipe( pipe_cmovDPR_reg );
7422 %}
7423
7424 // No CMOVE with SSE/SSE2
7425 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7426 predicate (UseSSE>=1);
7427 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7428 ins_cost(200);
7429 format %{ "Jn$cop skip\n\t"
7430 "MOVSS $dst,$src\t# float\n"
7431 "skip:" %}
7432 ins_encode %{
7433 Label skip;
7434 // Invert sense of branch from sense of CMOV
7435 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7436 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7437 __ bind(skip);
7438 %}
7439 ins_pipe( pipe_slow );
7440 %}
7441
7442 // No CMOVE with SSE/SSE2
7443 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7444 predicate (UseSSE>=2);
7445 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7446 ins_cost(200);
7447 format %{ "Jn$cop skip\n\t"
7448 "MOVSD $dst,$src\t# float\n"
7449 "skip:" %}
7450 ins_encode %{
7451 Label skip;
7452 // Invert sense of branch from sense of CMOV
7453 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7454 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7455 __ bind(skip);
7456 %}
7457 ins_pipe( pipe_slow );
7458 %}
7459
7460 // unsigned version
7461 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7462 predicate (UseSSE>=1);
7463 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7464 ins_cost(200);
7465 format %{ "Jn$cop skip\n\t"
7466 "MOVSS $dst,$src\t# float\n"
7467 "skip:" %}
7468 ins_encode %{
7469 Label skip;
7470 // Invert sense of branch from sense of CMOV
7471 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7472 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7473 __ bind(skip);
7474 %}
7475 ins_pipe( pipe_slow );
7476 %}
7477
7478 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7479 predicate (UseSSE>=1);
7480 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7481 ins_cost(200);
7482 expand %{
7483 fcmovF_regU(cop, cr, dst, src);
7484 %}
7485 %}
7486
7487 // unsigned version
7488 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7489 predicate (UseSSE>=2);
7490 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7491 ins_cost(200);
7492 format %{ "Jn$cop skip\n\t"
7493 "MOVSD $dst,$src\t# float\n"
7494 "skip:" %}
7495 ins_encode %{
7496 Label skip;
7497 // Invert sense of branch from sense of CMOV
7498 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7499 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7500 __ bind(skip);
7501 %}
7502 ins_pipe( pipe_slow );
7503 %}
7504
7505 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7506 predicate (UseSSE>=2);
7507 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7508 ins_cost(200);
7509 expand %{
7510 fcmovD_regU(cop, cr, dst, src);
7511 %}
7512 %}
7513
7514 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7515 predicate(VM_Version::supports_cmov() );
7516 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7517 ins_cost(200);
7518 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7519 "CMOV$cop $dst.hi,$src.hi" %}
7520 opcode(0x0F,0x40);
7521 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7522 ins_pipe( pipe_cmov_reg_long );
7523 %}
7524
7525 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7526 predicate(VM_Version::supports_cmov() );
7527 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7528 ins_cost(200);
7529 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7530 "CMOV$cop $dst.hi,$src.hi" %}
7531 opcode(0x0F,0x40);
7532 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7533 ins_pipe( pipe_cmov_reg_long );
7534 %}
7535
7536 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7537 predicate(VM_Version::supports_cmov() );
7538 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7539 ins_cost(200);
7540 expand %{
7541 cmovL_regU(cop, cr, dst, src);
7542 %}
7543 %}
7544
7545 //----------Arithmetic Instructions--------------------------------------------
7546 //----------Addition Instructions----------------------------------------------
7547 // Integer Addition Instructions
7548 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7549 match(Set dst (AddI dst src));
7550 effect(KILL cr);
7551
7552 size(2);
7553 format %{ "ADD $dst,$src" %}
7554 opcode(0x03);
7555 ins_encode( OpcP, RegReg( dst, src) );
7556 ins_pipe( ialu_reg_reg );
7557 %}
7558
7559 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7560 match(Set dst (AddI dst src));
7561 effect(KILL cr);
7562
7563 format %{ "ADD $dst,$src" %}
7564 opcode(0x81, 0x00); /* /0 id */
7565 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7566 ins_pipe( ialu_reg );
7567 %}
7568
7569 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7570 predicate(UseIncDec);
7571 match(Set dst (AddI dst src));
7572 effect(KILL cr);
7573
7574 size(1);
7575 format %{ "INC $dst" %}
7576 opcode(0x40); /* */
7577 ins_encode( Opc_plus( primary, dst ) );
7578 ins_pipe( ialu_reg );
7579 %}
7580
7581 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7582 match(Set dst (AddI src0 src1));
7583 ins_cost(110);
7584
7585 format %{ "LEA $dst,[$src0 + $src1]" %}
7586 opcode(0x8D); /* 0x8D /r */
7587 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7588 ins_pipe( ialu_reg_reg );
7589 %}
7590
7591 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7592 match(Set dst (AddP src0 src1));
7593 ins_cost(110);
7594
7595 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7596 opcode(0x8D); /* 0x8D /r */
7597 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7598 ins_pipe( ialu_reg_reg );
7599 %}
7600
7601 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7602 predicate(UseIncDec);
7603 match(Set dst (AddI dst src));
7604 effect(KILL cr);
7605
7606 size(1);
7607 format %{ "DEC $dst" %}
7608 opcode(0x48); /* */
7609 ins_encode( Opc_plus( primary, dst ) );
7610 ins_pipe( ialu_reg );
7611 %}
7612
7613 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7614 match(Set dst (AddP dst src));
7615 effect(KILL cr);
7616
7617 size(2);
7618 format %{ "ADD $dst,$src" %}
7619 opcode(0x03);
7620 ins_encode( OpcP, RegReg( dst, src) );
7621 ins_pipe( ialu_reg_reg );
7622 %}
7623
7624 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7625 match(Set dst (AddP dst src));
7626 effect(KILL cr);
7627
7628 format %{ "ADD $dst,$src" %}
7629 opcode(0x81,0x00); /* Opcode 81 /0 id */
7630 // ins_encode( RegImm( dst, src) );
7631 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7632 ins_pipe( ialu_reg );
7633 %}
7634
7635 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7636 match(Set dst (AddI dst (LoadI src)));
7637 effect(KILL cr);
7638
7639 ins_cost(125);
7640 format %{ "ADD $dst,$src" %}
7641 opcode(0x03);
7642 ins_encode( OpcP, RegMem( dst, src) );
7643 ins_pipe( ialu_reg_mem );
7644 %}
7645
7646 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7647 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7648 effect(KILL cr);
7649
7650 ins_cost(150);
7651 format %{ "ADD $dst,$src" %}
7652 opcode(0x01); /* Opcode 01 /r */
7653 ins_encode( OpcP, RegMem( src, dst ) );
7654 ins_pipe( ialu_mem_reg );
7655 %}
7656
7657 // Add Memory with Immediate
7658 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7659 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7660 effect(KILL cr);
7661
7662 ins_cost(125);
7663 format %{ "ADD $dst,$src" %}
7664 opcode(0x81); /* Opcode 81 /0 id */
7665 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7666 ins_pipe( ialu_mem_imm );
7667 %}
7668
7669 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7670 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7671 effect(KILL cr);
7672
7673 ins_cost(125);
7674 format %{ "INC $dst" %}
7675 opcode(0xFF); /* Opcode FF /0 */
7676 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7677 ins_pipe( ialu_mem_imm );
7678 %}
7679
7680 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7681 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7682 effect(KILL cr);
7683
7684 ins_cost(125);
7685 format %{ "DEC $dst" %}
7686 opcode(0xFF); /* Opcode FF /1 */
7687 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7688 ins_pipe( ialu_mem_imm );
7689 %}
7690
7691
7692 instruct checkCastPP( eRegP dst ) %{
7693 match(Set dst (CheckCastPP dst));
7694
7695 size(0);
7696 format %{ "#checkcastPP of $dst" %}
7697 ins_encode( /*empty encoding*/ );
7698 ins_pipe( empty );
7699 %}
7700
7701 instruct castPP( eRegP dst ) %{
7702 match(Set dst (CastPP dst));
7703 format %{ "#castPP of $dst" %}
7704 ins_encode( /*empty encoding*/ );
7705 ins_pipe( empty );
7706 %}
7707
7708 instruct castII( rRegI dst ) %{
7709 match(Set dst (CastII dst));
7710 format %{ "#castII of $dst" %}
7711 ins_encode( /*empty encoding*/ );
7712 ins_cost(0);
7713 ins_pipe( empty );
7714 %}
7715
7716
7717 // Load-locked - same as a regular pointer load when used with compare-swap
7718 instruct loadPLocked(eRegP dst, memory mem) %{
7719 match(Set dst (LoadPLocked mem));
7720
7721 ins_cost(125);
7722 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7723 opcode(0x8B);
7724 ins_encode( OpcP, RegMem(dst,mem));
7725 ins_pipe( ialu_reg_mem );
7726 %}
7727
7728 // Conditional-store of the updated heap-top.
7729 // Used during allocation of the shared heap.
7730 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7731 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7732 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7733 // EAX is killed if there is contention, but then it's also unused.
7734 // In the common case of no contention, EAX holds the new oop address.
7735 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7736 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7737 ins_pipe( pipe_cmpxchg );
7738 %}
7739
7740 // Conditional-store of an int value.
7741 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7742 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7743 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7744 effect(KILL oldval);
7745 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7746 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7747 ins_pipe( pipe_cmpxchg );
7748 %}
7749
7750 // Conditional-store of a long value.
7751 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7752 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7753 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7754 effect(KILL oldval);
7755 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7756 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7757 "XCHG EBX,ECX"
7758 %}
7759 ins_encode %{
7760 // Note: we need to swap rbx, and rcx before and after the
7761 // cmpxchg8 instruction because the instruction uses
7762 // rcx as the high order word of the new value to store but
7763 // our register encoding uses rbx.
7764 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7765 if( os::is_MP() )
7766 __ lock();
7767 __ cmpxchg8($mem$$Address);
7768 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7769 %}
7770 ins_pipe( pipe_cmpxchg );
7771 %}
7772
7773 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7774
7775 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7776 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7777 effect(KILL cr, KILL oldval);
7778 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7779 "MOV $res,0\n\t"
7780 "JNE,s fail\n\t"
7781 "MOV $res,1\n"
7782 "fail:" %}
7783 ins_encode( enc_cmpxchg8(mem_ptr),
7784 enc_flags_ne_to_boolean(res) );
7785 ins_pipe( pipe_cmpxchg );
7786 %}
7787
7788 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7789 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7790 effect(KILL cr, KILL oldval);
7791 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7792 "MOV $res,0\n\t"
7793 "JNE,s fail\n\t"
7794 "MOV $res,1\n"
7795 "fail:" %}
7796 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7797 ins_pipe( pipe_cmpxchg );
7798 %}
7799
7800 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7801 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7802 effect(KILL cr, KILL oldval);
7803 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7804 "MOV $res,0\n\t"
7805 "JNE,s fail\n\t"
7806 "MOV $res,1\n"
7807 "fail:" %}
7808 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7809 ins_pipe( pipe_cmpxchg );
7810 %}
7811
7812 //----------Subtraction Instructions-------------------------------------------
7813 // Integer Subtraction Instructions
7814 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7815 match(Set dst (SubI dst src));
7816 effect(KILL cr);
7817
7818 size(2);
7819 format %{ "SUB $dst,$src" %}
7820 opcode(0x2B);
7821 ins_encode( OpcP, RegReg( dst, src) );
7822 ins_pipe( ialu_reg_reg );
7823 %}
7824
7825 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7826 match(Set dst (SubI dst src));
7827 effect(KILL cr);
7828
7829 format %{ "SUB $dst,$src" %}
7830 opcode(0x81,0x05); /* Opcode 81 /5 */
7831 // ins_encode( RegImm( dst, src) );
7832 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7833 ins_pipe( ialu_reg );
7834 %}
7835
7836 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7837 match(Set dst (SubI dst (LoadI src)));
7838 effect(KILL cr);
7839
7840 ins_cost(125);
7841 format %{ "SUB $dst,$src" %}
7842 opcode(0x2B);
7843 ins_encode( OpcP, RegMem( dst, src) );
7844 ins_pipe( ialu_reg_mem );
7845 %}
7846
7847 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7848 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7849 effect(KILL cr);
7850
7851 ins_cost(150);
7852 format %{ "SUB $dst,$src" %}
7853 opcode(0x29); /* Opcode 29 /r */
7854 ins_encode( OpcP, RegMem( src, dst ) );
7855 ins_pipe( ialu_mem_reg );
7856 %}
7857
7858 // Subtract from a pointer
7859 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7860 match(Set dst (AddP dst (SubI zero src)));
7861 effect(KILL cr);
7862
7863 size(2);
7864 format %{ "SUB $dst,$src" %}
7865 opcode(0x2B);
7866 ins_encode( OpcP, RegReg( dst, src) );
7867 ins_pipe( ialu_reg_reg );
7868 %}
7869
7870 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7871 match(Set dst (SubI zero dst));
7872 effect(KILL cr);
7873
7874 size(2);
7875 format %{ "NEG $dst" %}
7876 opcode(0xF7,0x03); // Opcode F7 /3
7877 ins_encode( OpcP, RegOpc( dst ) );
7878 ins_pipe( ialu_reg );
7879 %}
7880
7881
7882 //----------Multiplication/Division Instructions-------------------------------
7883 // Integer Multiplication Instructions
7884 // Multiply Register
7885 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7886 match(Set dst (MulI dst src));
7887 effect(KILL cr);
7888
7889 size(3);
7890 ins_cost(300);
7891 format %{ "IMUL $dst,$src" %}
7892 opcode(0xAF, 0x0F);
7893 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7894 ins_pipe( ialu_reg_reg_alu0 );
7895 %}
7896
7897 // Multiply 32-bit Immediate
7898 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7899 match(Set dst (MulI src imm));
7900 effect(KILL cr);
7901
7902 ins_cost(300);
7903 format %{ "IMUL $dst,$src,$imm" %}
7904 opcode(0x69); /* 69 /r id */
7905 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7906 ins_pipe( ialu_reg_reg_alu0 );
7907 %}
7908
7909 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7910 match(Set dst src);
7911 effect(KILL cr);
7912
7913 // Note that this is artificially increased to make it more expensive than loadConL
7914 ins_cost(250);
7915 format %{ "MOV EAX,$src\t// low word only" %}
7916 opcode(0xB8);
7917 ins_encode( LdImmL_Lo(dst, src) );
7918 ins_pipe( ialu_reg_fat );
7919 %}
7920
7921 // Multiply by 32-bit Immediate, taking the shifted high order results
7922 // (special case for shift by 32)
7923 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
7924 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7925 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7926 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7927 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7928 effect(USE src1, KILL cr);
7929
7930 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7931 ins_cost(0*100 + 1*400 - 150);
7932 format %{ "IMUL EDX:EAX,$src1" %}
7933 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7934 ins_pipe( pipe_slow );
7935 %}
7936
7937 // Multiply by 32-bit Immediate, taking the shifted high order results
7938 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
7939 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
7940 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
7941 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
7942 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
7943 effect(USE src1, KILL cr);
7944
7945 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
7946 ins_cost(1*100 + 1*400 - 150);
7947 format %{ "IMUL EDX:EAX,$src1\n\t"
7948 "SAR EDX,$cnt-32" %}
7949 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
7950 ins_pipe( pipe_slow );
7951 %}
7952
7953 // Multiply Memory 32-bit Immediate
7954 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
7955 match(Set dst (MulI (LoadI src) imm));
7956 effect(KILL cr);
7957
7958 ins_cost(300);
7959 format %{ "IMUL $dst,$src,$imm" %}
7960 opcode(0x69); /* 69 /r id */
7961 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
7962 ins_pipe( ialu_reg_mem_alu0 );
7963 %}
7964
7965 // Multiply Memory
7966 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
7967 match(Set dst (MulI dst (LoadI src)));
7968 effect(KILL cr);
7969
7970 ins_cost(350);
7971 format %{ "IMUL $dst,$src" %}
7972 opcode(0xAF, 0x0F);
7973 ins_encode( OpcS, OpcP, RegMem( dst, src) );
7974 ins_pipe( ialu_reg_mem_alu0 );
7975 %}
7976
7977 // Multiply Register Int to Long
7978 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
7979 // Basic Idea: long = (long)int * (long)int
7980 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
7981 effect(DEF dst, USE src, USE src1, KILL flags);
7982
7983 ins_cost(300);
7984 format %{ "IMUL $dst,$src1" %}
7985
7986 ins_encode( long_int_multiply( dst, src1 ) );
7987 ins_pipe( ialu_reg_reg_alu0 );
7988 %}
7989
7990 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
7991 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
7992 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
7993 effect(KILL flags);
7994
7995 ins_cost(300);
7996 format %{ "MUL $dst,$src1" %}
7997
7998 ins_encode( long_uint_multiply(dst, src1) );
7999 ins_pipe( ialu_reg_reg_alu0 );
8000 %}
8001
8002 // Multiply Register Long
8003 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8004 match(Set dst (MulL dst src));
8005 effect(KILL cr, TEMP tmp);
8006 ins_cost(4*100+3*400);
8007 // Basic idea: lo(result) = lo(x_lo * y_lo)
8008 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8009 format %{ "MOV $tmp,$src.lo\n\t"
8010 "IMUL $tmp,EDX\n\t"
8011 "MOV EDX,$src.hi\n\t"
8012 "IMUL EDX,EAX\n\t"
8013 "ADD $tmp,EDX\n\t"
8014 "MUL EDX:EAX,$src.lo\n\t"
8015 "ADD EDX,$tmp" %}
8016 ins_encode( long_multiply( dst, src, tmp ) );
8017 ins_pipe( pipe_slow );
8018 %}
8019
8020 // Multiply Register Long where the left operand's high 32 bits are zero
8021 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8022 predicate(is_operand_hi32_zero(n->in(1)));
8023 match(Set dst (MulL dst src));
8024 effect(KILL cr, TEMP tmp);
8025 ins_cost(2*100+2*400);
8026 // Basic idea: lo(result) = lo(x_lo * y_lo)
8027 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8028 format %{ "MOV $tmp,$src.hi\n\t"
8029 "IMUL $tmp,EAX\n\t"
8030 "MUL EDX:EAX,$src.lo\n\t"
8031 "ADD EDX,$tmp" %}
8032 ins_encode %{
8033 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8034 __ imull($tmp$$Register, rax);
8035 __ mull($src$$Register);
8036 __ addl(rdx, $tmp$$Register);
8037 %}
8038 ins_pipe( pipe_slow );
8039 %}
8040
8041 // Multiply Register Long where the right operand's high 32 bits are zero
8042 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8043 predicate(is_operand_hi32_zero(n->in(2)));
8044 match(Set dst (MulL dst src));
8045 effect(KILL cr, TEMP tmp);
8046 ins_cost(2*100+2*400);
8047 // Basic idea: lo(result) = lo(x_lo * y_lo)
8048 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8049 format %{ "MOV $tmp,$src.lo\n\t"
8050 "IMUL $tmp,EDX\n\t"
8051 "MUL EDX:EAX,$src.lo\n\t"
8052 "ADD EDX,$tmp" %}
8053 ins_encode %{
8054 __ movl($tmp$$Register, $src$$Register);
8055 __ imull($tmp$$Register, rdx);
8056 __ mull($src$$Register);
8057 __ addl(rdx, $tmp$$Register);
8058 %}
8059 ins_pipe( pipe_slow );
8060 %}
8061
8062 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8063 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8064 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8065 match(Set dst (MulL dst src));
8066 effect(KILL cr);
8067 ins_cost(1*400);
8068 // Basic idea: lo(result) = lo(x_lo * y_lo)
8069 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8070 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8071 ins_encode %{
8072 __ mull($src$$Register);
8073 %}
8074 ins_pipe( pipe_slow );
8075 %}
8076
8077 // Multiply Register Long by small constant
8078 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8079 match(Set dst (MulL dst src));
8080 effect(KILL cr, TEMP tmp);
8081 ins_cost(2*100+2*400);
8082 size(12);
8083 // Basic idea: lo(result) = lo(src * EAX)
8084 // hi(result) = hi(src * EAX) + lo(src * EDX)
8085 format %{ "IMUL $tmp,EDX,$src\n\t"
8086 "MOV EDX,$src\n\t"
8087 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8088 "ADD EDX,$tmp" %}
8089 ins_encode( long_multiply_con( dst, src, tmp ) );
8090 ins_pipe( pipe_slow );
8091 %}
8092
8093 // Integer DIV with Register
8094 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8095 match(Set rax (DivI rax div));
8096 effect(KILL rdx, KILL cr);
8097 size(26);
8098 ins_cost(30*100+10*100);
8099 format %{ "CMP EAX,0x80000000\n\t"
8100 "JNE,s normal\n\t"
8101 "XOR EDX,EDX\n\t"
8102 "CMP ECX,-1\n\t"
8103 "JE,s done\n"
8104 "normal: CDQ\n\t"
8105 "IDIV $div\n\t"
8106 "done:" %}
8107 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8108 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8109 ins_pipe( ialu_reg_reg_alu0 );
8110 %}
8111
8112 // Divide Register Long
8113 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8114 match(Set dst (DivL src1 src2));
8115 effect( KILL cr, KILL cx, KILL bx );
8116 ins_cost(10000);
8117 format %{ "PUSH $src1.hi\n\t"
8118 "PUSH $src1.lo\n\t"
8119 "PUSH $src2.hi\n\t"
8120 "PUSH $src2.lo\n\t"
8121 "CALL SharedRuntime::ldiv\n\t"
8122 "ADD ESP,16" %}
8123 ins_encode( long_div(src1,src2) );
8124 ins_pipe( pipe_slow );
8125 %}
8126
8127 // Integer DIVMOD with Register, both quotient and mod results
8128 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8129 match(DivModI rax div);
8130 effect(KILL cr);
8131 size(26);
8132 ins_cost(30*100+10*100);
8133 format %{ "CMP EAX,0x80000000\n\t"
8134 "JNE,s normal\n\t"
8135 "XOR EDX,EDX\n\t"
8136 "CMP ECX,-1\n\t"
8137 "JE,s done\n"
8138 "normal: CDQ\n\t"
8139 "IDIV $div\n\t"
8140 "done:" %}
8141 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8142 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8143 ins_pipe( pipe_slow );
8144 %}
8145
8146 // Integer MOD with Register
8147 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8148 match(Set rdx (ModI rax div));
8149 effect(KILL rax, KILL cr);
8150
8151 size(26);
8152 ins_cost(300);
8153 format %{ "CDQ\n\t"
8154 "IDIV $div" %}
8155 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8156 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8157 ins_pipe( ialu_reg_reg_alu0 );
8158 %}
8159
8160 // Remainder Register Long
8161 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8162 match(Set dst (ModL src1 src2));
8163 effect( KILL cr, KILL cx, KILL bx );
8164 ins_cost(10000);
8165 format %{ "PUSH $src1.hi\n\t"
8166 "PUSH $src1.lo\n\t"
8167 "PUSH $src2.hi\n\t"
8168 "PUSH $src2.lo\n\t"
8169 "CALL SharedRuntime::lrem\n\t"
8170 "ADD ESP,16" %}
8171 ins_encode( long_mod(src1,src2) );
8172 ins_pipe( pipe_slow );
8173 %}
8174
8175 // Divide Register Long (no special case since divisor != -1)
8176 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8177 match(Set dst (DivL dst imm));
8178 effect( TEMP tmp, TEMP tmp2, KILL cr );
8179 ins_cost(1000);
8180 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8181 "XOR $tmp2,$tmp2\n\t"
8182 "CMP $tmp,EDX\n\t"
8183 "JA,s fast\n\t"
8184 "MOV $tmp2,EAX\n\t"
8185 "MOV EAX,EDX\n\t"
8186 "MOV EDX,0\n\t"
8187 "JLE,s pos\n\t"
8188 "LNEG EAX : $tmp2\n\t"
8189 "DIV $tmp # unsigned division\n\t"
8190 "XCHG EAX,$tmp2\n\t"
8191 "DIV $tmp\n\t"
8192 "LNEG $tmp2 : EAX\n\t"
8193 "JMP,s done\n"
8194 "pos:\n\t"
8195 "DIV $tmp\n\t"
8196 "XCHG EAX,$tmp2\n"
8197 "fast:\n\t"
8198 "DIV $tmp\n"
8199 "done:\n\t"
8200 "MOV EDX,$tmp2\n\t"
8201 "NEG EDX:EAX # if $imm < 0" %}
8202 ins_encode %{
8203 int con = (int)$imm$$constant;
8204 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8205 int pcon = (con > 0) ? con : -con;
8206 Label Lfast, Lpos, Ldone;
8207
8208 __ movl($tmp$$Register, pcon);
8209 __ xorl($tmp2$$Register,$tmp2$$Register);
8210 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8211 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8212
8213 __ movl($tmp2$$Register, $dst$$Register); // save
8214 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8215 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8216 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8217
8218 // Negative dividend.
8219 // convert value to positive to use unsigned division
8220 __ lneg($dst$$Register, $tmp2$$Register);
8221 __ divl($tmp$$Register);
8222 __ xchgl($dst$$Register, $tmp2$$Register);
8223 __ divl($tmp$$Register);
8224 // revert result back to negative
8225 __ lneg($tmp2$$Register, $dst$$Register);
8226 __ jmpb(Ldone);
8227
8228 __ bind(Lpos);
8229 __ divl($tmp$$Register); // Use unsigned division
8230 __ xchgl($dst$$Register, $tmp2$$Register);
8231 // Fallthrow for final divide, tmp2 has 32 bit hi result
8232
8233 __ bind(Lfast);
8234 // fast path: src is positive
8235 __ divl($tmp$$Register); // Use unsigned division
8236
8237 __ bind(Ldone);
8238 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8239 if (con < 0) {
8240 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8241 }
8242 %}
8243 ins_pipe( pipe_slow );
8244 %}
8245
8246 // Remainder Register Long (remainder fit into 32 bits)
8247 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8248 match(Set dst (ModL dst imm));
8249 effect( TEMP tmp, TEMP tmp2, KILL cr );
8250 ins_cost(1000);
8251 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8252 "CMP $tmp,EDX\n\t"
8253 "JA,s fast\n\t"
8254 "MOV $tmp2,EAX\n\t"
8255 "MOV EAX,EDX\n\t"
8256 "MOV EDX,0\n\t"
8257 "JLE,s pos\n\t"
8258 "LNEG EAX : $tmp2\n\t"
8259 "DIV $tmp # unsigned division\n\t"
8260 "MOV EAX,$tmp2\n\t"
8261 "DIV $tmp\n\t"
8262 "NEG EDX\n\t"
8263 "JMP,s done\n"
8264 "pos:\n\t"
8265 "DIV $tmp\n\t"
8266 "MOV EAX,$tmp2\n"
8267 "fast:\n\t"
8268 "DIV $tmp\n"
8269 "done:\n\t"
8270 "MOV EAX,EDX\n\t"
8271 "SAR EDX,31\n\t" %}
8272 ins_encode %{
8273 int con = (int)$imm$$constant;
8274 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8275 int pcon = (con > 0) ? con : -con;
8276 Label Lfast, Lpos, Ldone;
8277
8278 __ movl($tmp$$Register, pcon);
8279 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8280 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8281
8282 __ movl($tmp2$$Register, $dst$$Register); // save
8283 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8284 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8285 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8286
8287 // Negative dividend.
8288 // convert value to positive to use unsigned division
8289 __ lneg($dst$$Register, $tmp2$$Register);
8290 __ divl($tmp$$Register);
8291 __ movl($dst$$Register, $tmp2$$Register);
8292 __ divl($tmp$$Register);
8293 // revert remainder back to negative
8294 __ negl(HIGH_FROM_LOW($dst$$Register));
8295 __ jmpb(Ldone);
8296
8297 __ bind(Lpos);
8298 __ divl($tmp$$Register);
8299 __ movl($dst$$Register, $tmp2$$Register);
8300
8301 __ bind(Lfast);
8302 // fast path: src is positive
8303 __ divl($tmp$$Register);
8304
8305 __ bind(Ldone);
8306 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8307 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8308
8309 %}
8310 ins_pipe( pipe_slow );
8311 %}
8312
8313 // Integer Shift Instructions
8314 // Shift Left by one
8315 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8316 match(Set dst (LShiftI dst shift));
8317 effect(KILL cr);
8318
8319 size(2);
8320 format %{ "SHL $dst,$shift" %}
8321 opcode(0xD1, 0x4); /* D1 /4 */
8322 ins_encode( OpcP, RegOpc( dst ) );
8323 ins_pipe( ialu_reg );
8324 %}
8325
8326 // Shift Left by 8-bit immediate
8327 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8328 match(Set dst (LShiftI dst shift));
8329 effect(KILL cr);
8330
8331 size(3);
8332 format %{ "SHL $dst,$shift" %}
8333 opcode(0xC1, 0x4); /* C1 /4 ib */
8334 ins_encode( RegOpcImm( dst, shift) );
8335 ins_pipe( ialu_reg );
8336 %}
8337
8338 // Shift Left by variable
8339 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8340 match(Set dst (LShiftI dst shift));
8341 effect(KILL cr);
8342
8343 size(2);
8344 format %{ "SHL $dst,$shift" %}
8345 opcode(0xD3, 0x4); /* D3 /4 */
8346 ins_encode( OpcP, RegOpc( dst ) );
8347 ins_pipe( ialu_reg_reg );
8348 %}
8349
8350 // Arithmetic shift right by one
8351 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8352 match(Set dst (RShiftI dst shift));
8353 effect(KILL cr);
8354
8355 size(2);
8356 format %{ "SAR $dst,$shift" %}
8357 opcode(0xD1, 0x7); /* D1 /7 */
8358 ins_encode( OpcP, RegOpc( dst ) );
8359 ins_pipe( ialu_reg );
8360 %}
8361
8362 // Arithmetic shift right by one
8363 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8364 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8365 effect(KILL cr);
8366 format %{ "SAR $dst,$shift" %}
8367 opcode(0xD1, 0x7); /* D1 /7 */
8368 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8369 ins_pipe( ialu_mem_imm );
8370 %}
8371
8372 // Arithmetic Shift Right by 8-bit immediate
8373 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8374 match(Set dst (RShiftI dst shift));
8375 effect(KILL cr);
8376
8377 size(3);
8378 format %{ "SAR $dst,$shift" %}
8379 opcode(0xC1, 0x7); /* C1 /7 ib */
8380 ins_encode( RegOpcImm( dst, shift ) );
8381 ins_pipe( ialu_mem_imm );
8382 %}
8383
8384 // Arithmetic Shift Right by 8-bit immediate
8385 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8386 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8387 effect(KILL cr);
8388
8389 format %{ "SAR $dst,$shift" %}
8390 opcode(0xC1, 0x7); /* C1 /7 ib */
8391 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8392 ins_pipe( ialu_mem_imm );
8393 %}
8394
8395 // Arithmetic Shift Right by variable
8396 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8397 match(Set dst (RShiftI dst shift));
8398 effect(KILL cr);
8399
8400 size(2);
8401 format %{ "SAR $dst,$shift" %}
8402 opcode(0xD3, 0x7); /* D3 /7 */
8403 ins_encode( OpcP, RegOpc( dst ) );
8404 ins_pipe( ialu_reg_reg );
8405 %}
8406
8407 // Logical shift right by one
8408 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8409 match(Set dst (URShiftI dst shift));
8410 effect(KILL cr);
8411
8412 size(2);
8413 format %{ "SHR $dst,$shift" %}
8414 opcode(0xD1, 0x5); /* D1 /5 */
8415 ins_encode( OpcP, RegOpc( dst ) );
8416 ins_pipe( ialu_reg );
8417 %}
8418
8419 // Logical Shift Right by 8-bit immediate
8420 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8421 match(Set dst (URShiftI dst shift));
8422 effect(KILL cr);
8423
8424 size(3);
8425 format %{ "SHR $dst,$shift" %}
8426 opcode(0xC1, 0x5); /* C1 /5 ib */
8427 ins_encode( RegOpcImm( dst, shift) );
8428 ins_pipe( ialu_reg );
8429 %}
8430
8431
8432 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8433 // This idiom is used by the compiler for the i2b bytecode.
8434 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8435 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8436
8437 size(3);
8438 format %{ "MOVSX $dst,$src :8" %}
8439 ins_encode %{
8440 __ movsbl($dst$$Register, $src$$Register);
8441 %}
8442 ins_pipe(ialu_reg_reg);
8443 %}
8444
8445 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8446 // This idiom is used by the compiler the i2s bytecode.
8447 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8448 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8449
8450 size(3);
8451 format %{ "MOVSX $dst,$src :16" %}
8452 ins_encode %{
8453 __ movswl($dst$$Register, $src$$Register);
8454 %}
8455 ins_pipe(ialu_reg_reg);
8456 %}
8457
8458
8459 // Logical Shift Right by variable
8460 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8461 match(Set dst (URShiftI dst shift));
8462 effect(KILL cr);
8463
8464 size(2);
8465 format %{ "SHR $dst,$shift" %}
8466 opcode(0xD3, 0x5); /* D3 /5 */
8467 ins_encode( OpcP, RegOpc( dst ) );
8468 ins_pipe( ialu_reg_reg );
8469 %}
8470
8471
8472 //----------Logical Instructions-----------------------------------------------
8473 //----------Integer Logical Instructions---------------------------------------
8474 // And Instructions
8475 // And Register with Register
8476 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8477 match(Set dst (AndI dst src));
8478 effect(KILL cr);
8479
8480 size(2);
8481 format %{ "AND $dst,$src" %}
8482 opcode(0x23);
8483 ins_encode( OpcP, RegReg( dst, src) );
8484 ins_pipe( ialu_reg_reg );
8485 %}
8486
8487 // And Register with Immediate
8488 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8489 match(Set dst (AndI dst src));
8490 effect(KILL cr);
8491
8492 format %{ "AND $dst,$src" %}
8493 opcode(0x81,0x04); /* Opcode 81 /4 */
8494 // ins_encode( RegImm( dst, src) );
8495 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8496 ins_pipe( ialu_reg );
8497 %}
8498
8499 // And Register with Memory
8500 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8501 match(Set dst (AndI dst (LoadI src)));
8502 effect(KILL cr);
8503
8504 ins_cost(125);
8505 format %{ "AND $dst,$src" %}
8506 opcode(0x23);
8507 ins_encode( OpcP, RegMem( dst, src) );
8508 ins_pipe( ialu_reg_mem );
8509 %}
8510
8511 // And Memory with Register
8512 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8513 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8514 effect(KILL cr);
8515
8516 ins_cost(150);
8517 format %{ "AND $dst,$src" %}
8518 opcode(0x21); /* Opcode 21 /r */
8519 ins_encode( OpcP, RegMem( src, dst ) );
8520 ins_pipe( ialu_mem_reg );
8521 %}
8522
8523 // And Memory with Immediate
8524 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8525 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8526 effect(KILL cr);
8527
8528 ins_cost(125);
8529 format %{ "AND $dst,$src" %}
8530 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8531 // ins_encode( MemImm( dst, src) );
8532 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8533 ins_pipe( ialu_mem_imm );
8534 %}
8535
8536 // Or Instructions
8537 // Or Register with Register
8538 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8539 match(Set dst (OrI dst src));
8540 effect(KILL cr);
8541
8542 size(2);
8543 format %{ "OR $dst,$src" %}
8544 opcode(0x0B);
8545 ins_encode( OpcP, RegReg( dst, src) );
8546 ins_pipe( ialu_reg_reg );
8547 %}
8548
8549 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8550 match(Set dst (OrI dst (CastP2X src)));
8551 effect(KILL cr);
8552
8553 size(2);
8554 format %{ "OR $dst,$src" %}
8555 opcode(0x0B);
8556 ins_encode( OpcP, RegReg( dst, src) );
8557 ins_pipe( ialu_reg_reg );
8558 %}
8559
8560
8561 // Or Register with Immediate
8562 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8563 match(Set dst (OrI dst src));
8564 effect(KILL cr);
8565
8566 format %{ "OR $dst,$src" %}
8567 opcode(0x81,0x01); /* Opcode 81 /1 id */
8568 // ins_encode( RegImm( dst, src) );
8569 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8570 ins_pipe( ialu_reg );
8571 %}
8572
8573 // Or Register with Memory
8574 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8575 match(Set dst (OrI dst (LoadI src)));
8576 effect(KILL cr);
8577
8578 ins_cost(125);
8579 format %{ "OR $dst,$src" %}
8580 opcode(0x0B);
8581 ins_encode( OpcP, RegMem( dst, src) );
8582 ins_pipe( ialu_reg_mem );
8583 %}
8584
8585 // Or Memory with Register
8586 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8587 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8588 effect(KILL cr);
8589
8590 ins_cost(150);
8591 format %{ "OR $dst,$src" %}
8592 opcode(0x09); /* Opcode 09 /r */
8593 ins_encode( OpcP, RegMem( src, dst ) );
8594 ins_pipe( ialu_mem_reg );
8595 %}
8596
8597 // Or Memory with Immediate
8598 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8599 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8600 effect(KILL cr);
8601
8602 ins_cost(125);
8603 format %{ "OR $dst,$src" %}
8604 opcode(0x81,0x1); /* Opcode 81 /1 id */
8605 // ins_encode( MemImm( dst, src) );
8606 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8607 ins_pipe( ialu_mem_imm );
8608 %}
8609
8610 // ROL/ROR
8611 // ROL expand
8612 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8613 effect(USE_DEF dst, USE shift, KILL cr);
8614
8615 format %{ "ROL $dst, $shift" %}
8616 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8617 ins_encode( OpcP, RegOpc( dst ));
8618 ins_pipe( ialu_reg );
8619 %}
8620
8621 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8622 effect(USE_DEF dst, USE shift, KILL cr);
8623
8624 format %{ "ROL $dst, $shift" %}
8625 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8626 ins_encode( RegOpcImm(dst, shift) );
8627 ins_pipe(ialu_reg);
8628 %}
8629
8630 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8631 effect(USE_DEF dst, USE shift, KILL cr);
8632
8633 format %{ "ROL $dst, $shift" %}
8634 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8635 ins_encode(OpcP, RegOpc(dst));
8636 ins_pipe( ialu_reg_reg );
8637 %}
8638 // end of ROL expand
8639
8640 // ROL 32bit by one once
8641 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8642 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8643
8644 expand %{
8645 rolI_eReg_imm1(dst, lshift, cr);
8646 %}
8647 %}
8648
8649 // ROL 32bit var by imm8 once
8650 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8651 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8652 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8653
8654 expand %{
8655 rolI_eReg_imm8(dst, lshift, cr);
8656 %}
8657 %}
8658
8659 // ROL 32bit var by var once
8660 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8661 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8662
8663 expand %{
8664 rolI_eReg_CL(dst, shift, cr);
8665 %}
8666 %}
8667
8668 // ROL 32bit var by var once
8669 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8670 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8671
8672 expand %{
8673 rolI_eReg_CL(dst, shift, cr);
8674 %}
8675 %}
8676
8677 // ROR expand
8678 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8679 effect(USE_DEF dst, USE shift, KILL cr);
8680
8681 format %{ "ROR $dst, $shift" %}
8682 opcode(0xD1,0x1); /* Opcode D1 /1 */
8683 ins_encode( OpcP, RegOpc( dst ) );
8684 ins_pipe( ialu_reg );
8685 %}
8686
8687 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8688 effect (USE_DEF dst, USE shift, KILL cr);
8689
8690 format %{ "ROR $dst, $shift" %}
8691 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8692 ins_encode( RegOpcImm(dst, shift) );
8693 ins_pipe( ialu_reg );
8694 %}
8695
8696 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8697 effect(USE_DEF dst, USE shift, KILL cr);
8698
8699 format %{ "ROR $dst, $shift" %}
8700 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8701 ins_encode(OpcP, RegOpc(dst));
8702 ins_pipe( ialu_reg_reg );
8703 %}
8704 // end of ROR expand
8705
8706 // ROR right once
8707 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8708 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8709
8710 expand %{
8711 rorI_eReg_imm1(dst, rshift, cr);
8712 %}
8713 %}
8714
8715 // ROR 32bit by immI8 once
8716 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8717 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8718 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8719
8720 expand %{
8721 rorI_eReg_imm8(dst, rshift, cr);
8722 %}
8723 %}
8724
8725 // ROR 32bit var by var once
8726 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8727 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8728
8729 expand %{
8730 rorI_eReg_CL(dst, shift, cr);
8731 %}
8732 %}
8733
8734 // ROR 32bit var by var once
8735 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8736 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8737
8738 expand %{
8739 rorI_eReg_CL(dst, shift, cr);
8740 %}
8741 %}
8742
8743 // Xor Instructions
8744 // Xor Register with Register
8745 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8746 match(Set dst (XorI dst src));
8747 effect(KILL cr);
8748
8749 size(2);
8750 format %{ "XOR $dst,$src" %}
8751 opcode(0x33);
8752 ins_encode( OpcP, RegReg( dst, src) );
8753 ins_pipe( ialu_reg_reg );
8754 %}
8755
8756 // Xor Register with Immediate -1
8757 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8758 match(Set dst (XorI dst imm));
8759
8760 size(2);
8761 format %{ "NOT $dst" %}
8762 ins_encode %{
8763 __ notl($dst$$Register);
8764 %}
8765 ins_pipe( ialu_reg );
8766 %}
8767
8768 // Xor Register with Immediate
8769 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8770 match(Set dst (XorI dst src));
8771 effect(KILL cr);
8772
8773 format %{ "XOR $dst,$src" %}
8774 opcode(0x81,0x06); /* Opcode 81 /6 id */
8775 // ins_encode( RegImm( dst, src) );
8776 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8777 ins_pipe( ialu_reg );
8778 %}
8779
8780 // Xor Register with Memory
8781 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8782 match(Set dst (XorI dst (LoadI src)));
8783 effect(KILL cr);
8784
8785 ins_cost(125);
8786 format %{ "XOR $dst,$src" %}
8787 opcode(0x33);
8788 ins_encode( OpcP, RegMem(dst, src) );
8789 ins_pipe( ialu_reg_mem );
8790 %}
8791
8792 // Xor Memory with Register
8793 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8794 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8795 effect(KILL cr);
8796
8797 ins_cost(150);
8798 format %{ "XOR $dst,$src" %}
8799 opcode(0x31); /* Opcode 31 /r */
8800 ins_encode( OpcP, RegMem( src, dst ) );
8801 ins_pipe( ialu_mem_reg );
8802 %}
8803
8804 // Xor Memory with Immediate
8805 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8806 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8807 effect(KILL cr);
8808
8809 ins_cost(125);
8810 format %{ "XOR $dst,$src" %}
8811 opcode(0x81,0x6); /* Opcode 81 /6 id */
8812 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8813 ins_pipe( ialu_mem_imm );
8814 %}
8815
8816 //----------Convert Int to Boolean---------------------------------------------
8817
8818 instruct movI_nocopy(rRegI dst, rRegI src) %{
8819 effect( DEF dst, USE src );
8820 format %{ "MOV $dst,$src" %}
8821 ins_encode( enc_Copy( dst, src) );
8822 ins_pipe( ialu_reg_reg );
8823 %}
8824
8825 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8826 effect( USE_DEF dst, USE src, KILL cr );
8827
8828 size(4);
8829 format %{ "NEG $dst\n\t"
8830 "ADC $dst,$src" %}
8831 ins_encode( neg_reg(dst),
8832 OpcRegReg(0x13,dst,src) );
8833 ins_pipe( ialu_reg_reg_long );
8834 %}
8835
8836 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8837 match(Set dst (Conv2B src));
8838
8839 expand %{
8840 movI_nocopy(dst,src);
8841 ci2b(dst,src,cr);
8842 %}
8843 %}
8844
8845 instruct movP_nocopy(rRegI dst, eRegP src) %{
8846 effect( DEF dst, USE src );
8847 format %{ "MOV $dst,$src" %}
8848 ins_encode( enc_Copy( dst, src) );
8849 ins_pipe( ialu_reg_reg );
8850 %}
8851
8852 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8853 effect( USE_DEF dst, USE src, KILL cr );
8854 format %{ "NEG $dst\n\t"
8855 "ADC $dst,$src" %}
8856 ins_encode( neg_reg(dst),
8857 OpcRegReg(0x13,dst,src) );
8858 ins_pipe( ialu_reg_reg_long );
8859 %}
8860
8861 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8862 match(Set dst (Conv2B src));
8863
8864 expand %{
8865 movP_nocopy(dst,src);
8866 cp2b(dst,src,cr);
8867 %}
8868 %}
8869
8870 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
8871 match(Set dst (CmpLTMask p q));
8872 effect( KILL cr );
8873 ins_cost(400);
8874
8875 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8876 format %{ "XOR $dst,$dst\n\t"
8877 "CMP $p,$q\n\t"
8878 "SETlt $dst\n\t"
8879 "NEG $dst" %}
8880 ins_encode( OpcRegReg(0x33,dst,dst),
8881 OpcRegReg(0x3B,p,q),
8882 setLT_reg(dst), neg_reg(dst) );
8883 ins_pipe( pipe_slow );
8884 %}
8885
8886 instruct cmpLTMask0( rRegI dst, immI0 zero, eFlagsReg cr ) %{
8887 match(Set dst (CmpLTMask dst zero));
8888 effect( DEF dst, KILL cr );
8889 ins_cost(100);
8890
8891 format %{ "SAR $dst,31" %}
8892 opcode(0xC1, 0x7); /* C1 /7 ib */
8893 ins_encode( RegOpcImm( dst, 0x1F ) );
8894 ins_pipe( ialu_reg );
8895 %}
8896
8897
8898 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
8899 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8900 effect( KILL tmp, KILL cr );
8901 ins_cost(400);
8902 // annoyingly, $tmp has no edges so you cant ask for it in
8903 // any format or encoding
8904 format %{ "SUB $p,$q\n\t"
8905 "SBB ECX,ECX\n\t"
8906 "AND ECX,$y\n\t"
8907 "ADD $p,ECX" %}
8908 ins_encode( enc_cmpLTP(p,q,y,tmp) );
8909 ins_pipe( pipe_cmplt );
8910 %}
8911
8912 /* If I enable this, I encourage spilling in the inner loop of compress.
8913 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
8914 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8915 effect( USE_KILL tmp, KILL cr );
8916 ins_cost(400);
8917
8918 format %{ "SUB $p,$q\n\t"
8919 "SBB ECX,ECX\n\t"
8920 "AND ECX,$y\n\t"
8921 "ADD $p,ECX" %}
8922 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
8923 %}
8924 */
8925
8926 //----------Long Instructions------------------------------------------------
8927 // Add Long Register with Register
8928 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8929 match(Set dst (AddL dst src));
8930 effect(KILL cr);
8931 ins_cost(200);
8932 format %{ "ADD $dst.lo,$src.lo\n\t"
8933 "ADC $dst.hi,$src.hi" %}
8934 opcode(0x03, 0x13);
8935 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8936 ins_pipe( ialu_reg_reg_long );
8937 %}
8938
8939 // Add Long Register with Immediate
8940 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8941 match(Set dst (AddL dst src));
8942 effect(KILL cr);
8943 format %{ "ADD $dst.lo,$src.lo\n\t"
8944 "ADC $dst.hi,$src.hi" %}
8945 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
8946 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8947 ins_pipe( ialu_reg_long );
8948 %}
8949
8950 // Add Long Register with Memory
8951 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8952 match(Set dst (AddL dst (LoadL mem)));
8953 effect(KILL cr);
8954 ins_cost(125);
8955 format %{ "ADD $dst.lo,$mem\n\t"
8956 "ADC $dst.hi,$mem+4" %}
8957 opcode(0x03, 0x13);
8958 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8959 ins_pipe( ialu_reg_long_mem );
8960 %}
8961
8962 // Subtract Long Register with Register.
8963 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8964 match(Set dst (SubL dst src));
8965 effect(KILL cr);
8966 ins_cost(200);
8967 format %{ "SUB $dst.lo,$src.lo\n\t"
8968 "SBB $dst.hi,$src.hi" %}
8969 opcode(0x2B, 0x1B);
8970 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8971 ins_pipe( ialu_reg_reg_long );
8972 %}
8973
8974 // Subtract Long Register with Immediate
8975 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8976 match(Set dst (SubL dst src));
8977 effect(KILL cr);
8978 format %{ "SUB $dst.lo,$src.lo\n\t"
8979 "SBB $dst.hi,$src.hi" %}
8980 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
8981 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8982 ins_pipe( ialu_reg_long );
8983 %}
8984
8985 // Subtract Long Register with Memory
8986 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8987 match(Set dst (SubL dst (LoadL mem)));
8988 effect(KILL cr);
8989 ins_cost(125);
8990 format %{ "SUB $dst.lo,$mem\n\t"
8991 "SBB $dst.hi,$mem+4" %}
8992 opcode(0x2B, 0x1B);
8993 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8994 ins_pipe( ialu_reg_long_mem );
8995 %}
8996
8997 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
8998 match(Set dst (SubL zero dst));
8999 effect(KILL cr);
9000 ins_cost(300);
9001 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9002 ins_encode( neg_long(dst) );
9003 ins_pipe( ialu_reg_reg_long );
9004 %}
9005
9006 // And Long Register with Register
9007 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9008 match(Set dst (AndL dst src));
9009 effect(KILL cr);
9010 format %{ "AND $dst.lo,$src.lo\n\t"
9011 "AND $dst.hi,$src.hi" %}
9012 opcode(0x23,0x23);
9013 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9014 ins_pipe( ialu_reg_reg_long );
9015 %}
9016
9017 // And Long Register with Immediate
9018 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9019 match(Set dst (AndL dst src));
9020 effect(KILL cr);
9021 format %{ "AND $dst.lo,$src.lo\n\t"
9022 "AND $dst.hi,$src.hi" %}
9023 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9024 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9025 ins_pipe( ialu_reg_long );
9026 %}
9027
9028 // And Long Register with Memory
9029 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9030 match(Set dst (AndL dst (LoadL mem)));
9031 effect(KILL cr);
9032 ins_cost(125);
9033 format %{ "AND $dst.lo,$mem\n\t"
9034 "AND $dst.hi,$mem+4" %}
9035 opcode(0x23, 0x23);
9036 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9037 ins_pipe( ialu_reg_long_mem );
9038 %}
9039
9040 // Or Long Register with Register
9041 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9042 match(Set dst (OrL dst src));
9043 effect(KILL cr);
9044 format %{ "OR $dst.lo,$src.lo\n\t"
9045 "OR $dst.hi,$src.hi" %}
9046 opcode(0x0B,0x0B);
9047 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9048 ins_pipe( ialu_reg_reg_long );
9049 %}
9050
9051 // Or Long Register with Immediate
9052 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9053 match(Set dst (OrL dst src));
9054 effect(KILL cr);
9055 format %{ "OR $dst.lo,$src.lo\n\t"
9056 "OR $dst.hi,$src.hi" %}
9057 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9058 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9059 ins_pipe( ialu_reg_long );
9060 %}
9061
9062 // Or Long Register with Memory
9063 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9064 match(Set dst (OrL dst (LoadL mem)));
9065 effect(KILL cr);
9066 ins_cost(125);
9067 format %{ "OR $dst.lo,$mem\n\t"
9068 "OR $dst.hi,$mem+4" %}
9069 opcode(0x0B,0x0B);
9070 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9071 ins_pipe( ialu_reg_long_mem );
9072 %}
9073
9074 // Xor Long Register with Register
9075 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9076 match(Set dst (XorL dst src));
9077 effect(KILL cr);
9078 format %{ "XOR $dst.lo,$src.lo\n\t"
9079 "XOR $dst.hi,$src.hi" %}
9080 opcode(0x33,0x33);
9081 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9082 ins_pipe( ialu_reg_reg_long );
9083 %}
9084
9085 // Xor Long Register with Immediate -1
9086 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9087 match(Set dst (XorL dst imm));
9088 format %{ "NOT $dst.lo\n\t"
9089 "NOT $dst.hi" %}
9090 ins_encode %{
9091 __ notl($dst$$Register);
9092 __ notl(HIGH_FROM_LOW($dst$$Register));
9093 %}
9094 ins_pipe( ialu_reg_long );
9095 %}
9096
9097 // Xor Long Register with Immediate
9098 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9099 match(Set dst (XorL dst src));
9100 effect(KILL cr);
9101 format %{ "XOR $dst.lo,$src.lo\n\t"
9102 "XOR $dst.hi,$src.hi" %}
9103 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9104 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9105 ins_pipe( ialu_reg_long );
9106 %}
9107
9108 // Xor Long Register with Memory
9109 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9110 match(Set dst (XorL dst (LoadL mem)));
9111 effect(KILL cr);
9112 ins_cost(125);
9113 format %{ "XOR $dst.lo,$mem\n\t"
9114 "XOR $dst.hi,$mem+4" %}
9115 opcode(0x33,0x33);
9116 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9117 ins_pipe( ialu_reg_long_mem );
9118 %}
9119
9120 // Shift Left Long by 1
9121 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9122 predicate(UseNewLongLShift);
9123 match(Set dst (LShiftL dst cnt));
9124 effect(KILL cr);
9125 ins_cost(100);
9126 format %{ "ADD $dst.lo,$dst.lo\n\t"
9127 "ADC $dst.hi,$dst.hi" %}
9128 ins_encode %{
9129 __ addl($dst$$Register,$dst$$Register);
9130 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9131 %}
9132 ins_pipe( ialu_reg_long );
9133 %}
9134
9135 // Shift Left Long by 2
9136 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9137 predicate(UseNewLongLShift);
9138 match(Set dst (LShiftL dst cnt));
9139 effect(KILL cr);
9140 ins_cost(100);
9141 format %{ "ADD $dst.lo,$dst.lo\n\t"
9142 "ADC $dst.hi,$dst.hi\n\t"
9143 "ADD $dst.lo,$dst.lo\n\t"
9144 "ADC $dst.hi,$dst.hi" %}
9145 ins_encode %{
9146 __ addl($dst$$Register,$dst$$Register);
9147 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9148 __ addl($dst$$Register,$dst$$Register);
9149 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9150 %}
9151 ins_pipe( ialu_reg_long );
9152 %}
9153
9154 // Shift Left Long by 3
9155 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9156 predicate(UseNewLongLShift);
9157 match(Set dst (LShiftL dst cnt));
9158 effect(KILL cr);
9159 ins_cost(100);
9160 format %{ "ADD $dst.lo,$dst.lo\n\t"
9161 "ADC $dst.hi,$dst.hi\n\t"
9162 "ADD $dst.lo,$dst.lo\n\t"
9163 "ADC $dst.hi,$dst.hi\n\t"
9164 "ADD $dst.lo,$dst.lo\n\t"
9165 "ADC $dst.hi,$dst.hi" %}
9166 ins_encode %{
9167 __ addl($dst$$Register,$dst$$Register);
9168 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9169 __ addl($dst$$Register,$dst$$Register);
9170 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9171 __ addl($dst$$Register,$dst$$Register);
9172 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9173 %}
9174 ins_pipe( ialu_reg_long );
9175 %}
9176
9177 // Shift Left Long by 1-31
9178 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9179 match(Set dst (LShiftL dst cnt));
9180 effect(KILL cr);
9181 ins_cost(200);
9182 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9183 "SHL $dst.lo,$cnt" %}
9184 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9185 ins_encode( move_long_small_shift(dst,cnt) );
9186 ins_pipe( ialu_reg_long );
9187 %}
9188
9189 // Shift Left Long by 32-63
9190 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9191 match(Set dst (LShiftL dst cnt));
9192 effect(KILL cr);
9193 ins_cost(300);
9194 format %{ "MOV $dst.hi,$dst.lo\n"
9195 "\tSHL $dst.hi,$cnt-32\n"
9196 "\tXOR $dst.lo,$dst.lo" %}
9197 opcode(0xC1, 0x4); /* C1 /4 ib */
9198 ins_encode( move_long_big_shift_clr(dst,cnt) );
9199 ins_pipe( ialu_reg_long );
9200 %}
9201
9202 // Shift Left Long by variable
9203 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9204 match(Set dst (LShiftL dst shift));
9205 effect(KILL cr);
9206 ins_cost(500+200);
9207 size(17);
9208 format %{ "TEST $shift,32\n\t"
9209 "JEQ,s small\n\t"
9210 "MOV $dst.hi,$dst.lo\n\t"
9211 "XOR $dst.lo,$dst.lo\n"
9212 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9213 "SHL $dst.lo,$shift" %}
9214 ins_encode( shift_left_long( dst, shift ) );
9215 ins_pipe( pipe_slow );
9216 %}
9217
9218 // Shift Right Long by 1-31
9219 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9220 match(Set dst (URShiftL dst cnt));
9221 effect(KILL cr);
9222 ins_cost(200);
9223 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9224 "SHR $dst.hi,$cnt" %}
9225 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9226 ins_encode( move_long_small_shift(dst,cnt) );
9227 ins_pipe( ialu_reg_long );
9228 %}
9229
9230 // Shift Right Long by 32-63
9231 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9232 match(Set dst (URShiftL dst cnt));
9233 effect(KILL cr);
9234 ins_cost(300);
9235 format %{ "MOV $dst.lo,$dst.hi\n"
9236 "\tSHR $dst.lo,$cnt-32\n"
9237 "\tXOR $dst.hi,$dst.hi" %}
9238 opcode(0xC1, 0x5); /* C1 /5 ib */
9239 ins_encode( move_long_big_shift_clr(dst,cnt) );
9240 ins_pipe( ialu_reg_long );
9241 %}
9242
9243 // Shift Right Long by variable
9244 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9245 match(Set dst (URShiftL dst shift));
9246 effect(KILL cr);
9247 ins_cost(600);
9248 size(17);
9249 format %{ "TEST $shift,32\n\t"
9250 "JEQ,s small\n\t"
9251 "MOV $dst.lo,$dst.hi\n\t"
9252 "XOR $dst.hi,$dst.hi\n"
9253 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9254 "SHR $dst.hi,$shift" %}
9255 ins_encode( shift_right_long( dst, shift ) );
9256 ins_pipe( pipe_slow );
9257 %}
9258
9259 // Shift Right Long by 1-31
9260 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9261 match(Set dst (RShiftL dst cnt));
9262 effect(KILL cr);
9263 ins_cost(200);
9264 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9265 "SAR $dst.hi,$cnt" %}
9266 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9267 ins_encode( move_long_small_shift(dst,cnt) );
9268 ins_pipe( ialu_reg_long );
9269 %}
9270
9271 // Shift Right Long by 32-63
9272 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9273 match(Set dst (RShiftL dst cnt));
9274 effect(KILL cr);
9275 ins_cost(300);
9276 format %{ "MOV $dst.lo,$dst.hi\n"
9277 "\tSAR $dst.lo,$cnt-32\n"
9278 "\tSAR $dst.hi,31" %}
9279 opcode(0xC1, 0x7); /* C1 /7 ib */
9280 ins_encode( move_long_big_shift_sign(dst,cnt) );
9281 ins_pipe( ialu_reg_long );
9282 %}
9283
9284 // Shift Right arithmetic Long by variable
9285 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9286 match(Set dst (RShiftL dst shift));
9287 effect(KILL cr);
9288 ins_cost(600);
9289 size(18);
9290 format %{ "TEST $shift,32\n\t"
9291 "JEQ,s small\n\t"
9292 "MOV $dst.lo,$dst.hi\n\t"
9293 "SAR $dst.hi,31\n"
9294 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9295 "SAR $dst.hi,$shift" %}
9296 ins_encode( shift_right_arith_long( dst, shift ) );
9297 ins_pipe( pipe_slow );
9298 %}
9299
9300
9301 //----------Double Instructions------------------------------------------------
9302 // Double Math
9303
9304 // Compare & branch
9305
9306 // P6 version of float compare, sets condition codes in EFLAGS
9307 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9308 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9309 match(Set cr (CmpD src1 src2));
9310 effect(KILL rax);
9311 ins_cost(150);
9312 format %{ "FLD $src1\n\t"
9313 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9314 "JNP exit\n\t"
9315 "MOV ah,1 // saw a NaN, set CF\n\t"
9316 "SAHF\n"
9317 "exit:\tNOP // avoid branch to branch" %}
9318 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9319 ins_encode( Push_Reg_DPR(src1),
9320 OpcP, RegOpc(src2),
9321 cmpF_P6_fixup );
9322 ins_pipe( pipe_slow );
9323 %}
9324
9325 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9326 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9327 match(Set cr (CmpD src1 src2));
9328 ins_cost(150);
9329 format %{ "FLD $src1\n\t"
9330 "FUCOMIP ST,$src2 // P6 instruction" %}
9331 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9332 ins_encode( Push_Reg_DPR(src1),
9333 OpcP, RegOpc(src2));
9334 ins_pipe( pipe_slow );
9335 %}
9336
9337 // Compare & branch
9338 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9339 predicate(UseSSE<=1);
9340 match(Set cr (CmpD src1 src2));
9341 effect(KILL rax);
9342 ins_cost(200);
9343 format %{ "FLD $src1\n\t"
9344 "FCOMp $src2\n\t"
9345 "FNSTSW AX\n\t"
9346 "TEST AX,0x400\n\t"
9347 "JZ,s flags\n\t"
9348 "MOV AH,1\t# unordered treat as LT\n"
9349 "flags:\tSAHF" %}
9350 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9351 ins_encode( Push_Reg_DPR(src1),
9352 OpcP, RegOpc(src2),
9353 fpu_flags);
9354 ins_pipe( pipe_slow );
9355 %}
9356
9357 // Compare vs zero into -1,0,1
9358 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9359 predicate(UseSSE<=1);
9360 match(Set dst (CmpD3 src1 zero));
9361 effect(KILL cr, KILL rax);
9362 ins_cost(280);
9363 format %{ "FTSTD $dst,$src1" %}
9364 opcode(0xE4, 0xD9);
9365 ins_encode( Push_Reg_DPR(src1),
9366 OpcS, OpcP, PopFPU,
9367 CmpF_Result(dst));
9368 ins_pipe( pipe_slow );
9369 %}
9370
9371 // Compare into -1,0,1
9372 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9373 predicate(UseSSE<=1);
9374 match(Set dst (CmpD3 src1 src2));
9375 effect(KILL cr, KILL rax);
9376 ins_cost(300);
9377 format %{ "FCMPD $dst,$src1,$src2" %}
9378 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9379 ins_encode( Push_Reg_DPR(src1),
9380 OpcP, RegOpc(src2),
9381 CmpF_Result(dst));
9382 ins_pipe( pipe_slow );
9383 %}
9384
9385 // float compare and set condition codes in EFLAGS by XMM regs
9386 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9387 predicate(UseSSE>=2);
9388 match(Set cr (CmpD src1 src2));
9389 ins_cost(145);
9390 format %{ "UCOMISD $src1,$src2\n\t"
9391 "JNP,s exit\n\t"
9392 "PUSHF\t# saw NaN, set CF\n\t"
9393 "AND [rsp], #0xffffff2b\n\t"
9394 "POPF\n"
9395 "exit:" %}
9396 ins_encode %{
9397 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9398 emit_cmpfp_fixup(_masm);
9399 %}
9400 ins_pipe( pipe_slow );
9401 %}
9402
9403 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9404 predicate(UseSSE>=2);
9405 match(Set cr (CmpD src1 src2));
9406 ins_cost(100);
9407 format %{ "UCOMISD $src1,$src2" %}
9408 ins_encode %{
9409 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9410 %}
9411 ins_pipe( pipe_slow );
9412 %}
9413
9414 // float compare and set condition codes in EFLAGS by XMM regs
9415 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9416 predicate(UseSSE>=2);
9417 match(Set cr (CmpD src1 (LoadD src2)));
9418 ins_cost(145);
9419 format %{ "UCOMISD $src1,$src2\n\t"
9420 "JNP,s exit\n\t"
9421 "PUSHF\t# saw NaN, set CF\n\t"
9422 "AND [rsp], #0xffffff2b\n\t"
9423 "POPF\n"
9424 "exit:" %}
9425 ins_encode %{
9426 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9427 emit_cmpfp_fixup(_masm);
9428 %}
9429 ins_pipe( pipe_slow );
9430 %}
9431
9432 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9433 predicate(UseSSE>=2);
9434 match(Set cr (CmpD src1 (LoadD src2)));
9435 ins_cost(100);
9436 format %{ "UCOMISD $src1,$src2" %}
9437 ins_encode %{
9438 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9439 %}
9440 ins_pipe( pipe_slow );
9441 %}
9442
9443 // Compare into -1,0,1 in XMM
9444 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9445 predicate(UseSSE>=2);
9446 match(Set dst (CmpD3 src1 src2));
9447 effect(KILL cr);
9448 ins_cost(255);
9449 format %{ "UCOMISD $src1, $src2\n\t"
9450 "MOV $dst, #-1\n\t"
9451 "JP,s done\n\t"
9452 "JB,s done\n\t"
9453 "SETNE $dst\n\t"
9454 "MOVZB $dst, $dst\n"
9455 "done:" %}
9456 ins_encode %{
9457 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9458 emit_cmpfp3(_masm, $dst$$Register);
9459 %}
9460 ins_pipe( pipe_slow );
9461 %}
9462
9463 // Compare into -1,0,1 in XMM and memory
9464 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9465 predicate(UseSSE>=2);
9466 match(Set dst (CmpD3 src1 (LoadD src2)));
9467 effect(KILL cr);
9468 ins_cost(275);
9469 format %{ "UCOMISD $src1, $src2\n\t"
9470 "MOV $dst, #-1\n\t"
9471 "JP,s done\n\t"
9472 "JB,s done\n\t"
9473 "SETNE $dst\n\t"
9474 "MOVZB $dst, $dst\n"
9475 "done:" %}
9476 ins_encode %{
9477 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9478 emit_cmpfp3(_masm, $dst$$Register);
9479 %}
9480 ins_pipe( pipe_slow );
9481 %}
9482
9483
9484 instruct subDPR_reg(regDPR dst, regDPR src) %{
9485 predicate (UseSSE <=1);
9486 match(Set dst (SubD dst src));
9487
9488 format %{ "FLD $src\n\t"
9489 "DSUBp $dst,ST" %}
9490 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9491 ins_cost(150);
9492 ins_encode( Push_Reg_DPR(src),
9493 OpcP, RegOpc(dst) );
9494 ins_pipe( fpu_reg_reg );
9495 %}
9496
9497 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9498 predicate (UseSSE <=1);
9499 match(Set dst (RoundDouble (SubD src1 src2)));
9500 ins_cost(250);
9501
9502 format %{ "FLD $src2\n\t"
9503 "DSUB ST,$src1\n\t"
9504 "FSTP_D $dst\t# D-round" %}
9505 opcode(0xD8, 0x5);
9506 ins_encode( Push_Reg_DPR(src2),
9507 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9508 ins_pipe( fpu_mem_reg_reg );
9509 %}
9510
9511
9512 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9513 predicate (UseSSE <=1);
9514 match(Set dst (SubD dst (LoadD src)));
9515 ins_cost(150);
9516
9517 format %{ "FLD $src\n\t"
9518 "DSUBp $dst,ST" %}
9519 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9520 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9521 OpcP, RegOpc(dst) );
9522 ins_pipe( fpu_reg_mem );
9523 %}
9524
9525 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9526 predicate (UseSSE<=1);
9527 match(Set dst (AbsD src));
9528 ins_cost(100);
9529 format %{ "FABS" %}
9530 opcode(0xE1, 0xD9);
9531 ins_encode( OpcS, OpcP );
9532 ins_pipe( fpu_reg_reg );
9533 %}
9534
9535 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9536 predicate(UseSSE<=1);
9537 match(Set dst (NegD src));
9538 ins_cost(100);
9539 format %{ "FCHS" %}
9540 opcode(0xE0, 0xD9);
9541 ins_encode( OpcS, OpcP );
9542 ins_pipe( fpu_reg_reg );
9543 %}
9544
9545 instruct addDPR_reg(regDPR dst, regDPR src) %{
9546 predicate(UseSSE<=1);
9547 match(Set dst (AddD dst src));
9548 format %{ "FLD $src\n\t"
9549 "DADD $dst,ST" %}
9550 size(4);
9551 ins_cost(150);
9552 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9553 ins_encode( Push_Reg_DPR(src),
9554 OpcP, RegOpc(dst) );
9555 ins_pipe( fpu_reg_reg );
9556 %}
9557
9558
9559 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9560 predicate(UseSSE<=1);
9561 match(Set dst (RoundDouble (AddD src1 src2)));
9562 ins_cost(250);
9563
9564 format %{ "FLD $src2\n\t"
9565 "DADD ST,$src1\n\t"
9566 "FSTP_D $dst\t# D-round" %}
9567 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9568 ins_encode( Push_Reg_DPR(src2),
9569 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9570 ins_pipe( fpu_mem_reg_reg );
9571 %}
9572
9573
9574 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9575 predicate(UseSSE<=1);
9576 match(Set dst (AddD dst (LoadD src)));
9577 ins_cost(150);
9578
9579 format %{ "FLD $src\n\t"
9580 "DADDp $dst,ST" %}
9581 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9582 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9583 OpcP, RegOpc(dst) );
9584 ins_pipe( fpu_reg_mem );
9585 %}
9586
9587 // add-to-memory
9588 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9589 predicate(UseSSE<=1);
9590 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9591 ins_cost(150);
9592
9593 format %{ "FLD_D $dst\n\t"
9594 "DADD ST,$src\n\t"
9595 "FST_D $dst" %}
9596 opcode(0xDD, 0x0);
9597 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9598 Opcode(0xD8), RegOpc(src),
9599 set_instruction_start,
9600 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9601 ins_pipe( fpu_reg_mem );
9602 %}
9603
9604 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9605 predicate(UseSSE<=1);
9606 match(Set dst (AddD dst con));
9607 ins_cost(125);
9608 format %{ "FLD1\n\t"
9609 "DADDp $dst,ST" %}
9610 ins_encode %{
9611 __ fld1();
9612 __ faddp($dst$$reg);
9613 %}
9614 ins_pipe(fpu_reg);
9615 %}
9616
9617 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9618 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9619 match(Set dst (AddD dst con));
9620 ins_cost(200);
9621 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9622 "DADDp $dst,ST" %}
9623 ins_encode %{
9624 __ fld_d($constantaddress($con));
9625 __ faddp($dst$$reg);
9626 %}
9627 ins_pipe(fpu_reg_mem);
9628 %}
9629
9630 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9631 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9632 match(Set dst (RoundDouble (AddD src con)));
9633 ins_cost(200);
9634 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9635 "DADD ST,$src\n\t"
9636 "FSTP_D $dst\t# D-round" %}
9637 ins_encode %{
9638 __ fld_d($constantaddress($con));
9639 __ fadd($src$$reg);
9640 __ fstp_d(Address(rsp, $dst$$disp));
9641 %}
9642 ins_pipe(fpu_mem_reg_con);
9643 %}
9644
9645 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9646 predicate(UseSSE<=1);
9647 match(Set dst (MulD dst src));
9648 format %{ "FLD $src\n\t"
9649 "DMULp $dst,ST" %}
9650 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9651 ins_cost(150);
9652 ins_encode( Push_Reg_DPR(src),
9653 OpcP, RegOpc(dst) );
9654 ins_pipe( fpu_reg_reg );
9655 %}
9656
9657 // Strict FP instruction biases argument before multiply then
9658 // biases result to avoid double rounding of subnormals.
9659 //
9660 // scale arg1 by multiplying arg1 by 2^(-15360)
9661 // load arg2
9662 // multiply scaled arg1 by arg2
9663 // rescale product by 2^(15360)
9664 //
9665 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9666 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9667 match(Set dst (MulD dst src));
9668 ins_cost(1); // Select this instruction for all strict FP double multiplies
9669
9670 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9671 "DMULp $dst,ST\n\t"
9672 "FLD $src\n\t"
9673 "DMULp $dst,ST\n\t"
9674 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9675 "DMULp $dst,ST\n\t" %}
9676 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9677 ins_encode( strictfp_bias1(dst),
9678 Push_Reg_DPR(src),
9679 OpcP, RegOpc(dst),
9680 strictfp_bias2(dst) );
9681 ins_pipe( fpu_reg_reg );
9682 %}
9683
9684 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9685 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9686 match(Set dst (MulD dst con));
9687 ins_cost(200);
9688 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9689 "DMULp $dst,ST" %}
9690 ins_encode %{
9691 __ fld_d($constantaddress($con));
9692 __ fmulp($dst$$reg);
9693 %}
9694 ins_pipe(fpu_reg_mem);
9695 %}
9696
9697
9698 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9699 predicate( UseSSE<=1 );
9700 match(Set dst (MulD dst (LoadD src)));
9701 ins_cost(200);
9702 format %{ "FLD_D $src\n\t"
9703 "DMULp $dst,ST" %}
9704 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9705 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9706 OpcP, RegOpc(dst) );
9707 ins_pipe( fpu_reg_mem );
9708 %}
9709
9710 //
9711 // Cisc-alternate to reg-reg multiply
9712 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9713 predicate( UseSSE<=1 );
9714 match(Set dst (MulD src (LoadD mem)));
9715 ins_cost(250);
9716 format %{ "FLD_D $mem\n\t"
9717 "DMUL ST,$src\n\t"
9718 "FSTP_D $dst" %}
9719 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9720 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9721 OpcReg_FPR(src),
9722 Pop_Reg_DPR(dst) );
9723 ins_pipe( fpu_reg_reg_mem );
9724 %}
9725
9726
9727 // MACRO3 -- addDPR a mulDPR
9728 // This instruction is a '2-address' instruction in that the result goes
9729 // back to src2. This eliminates a move from the macro; possibly the
9730 // register allocator will have to add it back (and maybe not).
9731 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9732 predicate( UseSSE<=1 );
9733 match(Set src2 (AddD (MulD src0 src1) src2));
9734 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9735 "DMUL ST,$src1\n\t"
9736 "DADDp $src2,ST" %}
9737 ins_cost(250);
9738 opcode(0xDD); /* LoadD DD /0 */
9739 ins_encode( Push_Reg_FPR(src0),
9740 FMul_ST_reg(src1),
9741 FAddP_reg_ST(src2) );
9742 ins_pipe( fpu_reg_reg_reg );
9743 %}
9744
9745
9746 // MACRO3 -- subDPR a mulDPR
9747 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9748 predicate( UseSSE<=1 );
9749 match(Set src2 (SubD (MulD src0 src1) src2));
9750 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9751 "DMUL ST,$src1\n\t"
9752 "DSUBRp $src2,ST" %}
9753 ins_cost(250);
9754 ins_encode( Push_Reg_FPR(src0),
9755 FMul_ST_reg(src1),
9756 Opcode(0xDE), Opc_plus(0xE0,src2));
9757 ins_pipe( fpu_reg_reg_reg );
9758 %}
9759
9760
9761 instruct divDPR_reg(regDPR dst, regDPR src) %{
9762 predicate( UseSSE<=1 );
9763 match(Set dst (DivD dst src));
9764
9765 format %{ "FLD $src\n\t"
9766 "FDIVp $dst,ST" %}
9767 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9768 ins_cost(150);
9769 ins_encode( Push_Reg_DPR(src),
9770 OpcP, RegOpc(dst) );
9771 ins_pipe( fpu_reg_reg );
9772 %}
9773
9774 // Strict FP instruction biases argument before division then
9775 // biases result, to avoid double rounding of subnormals.
9776 //
9777 // scale dividend by multiplying dividend by 2^(-15360)
9778 // load divisor
9779 // divide scaled dividend by divisor
9780 // rescale quotient by 2^(15360)
9781 //
9782 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9783 predicate (UseSSE<=1);
9784 match(Set dst (DivD dst src));
9785 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9786 ins_cost(01);
9787
9788 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9789 "DMULp $dst,ST\n\t"
9790 "FLD $src\n\t"
9791 "FDIVp $dst,ST\n\t"
9792 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9793 "DMULp $dst,ST\n\t" %}
9794 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9795 ins_encode( strictfp_bias1(dst),
9796 Push_Reg_DPR(src),
9797 OpcP, RegOpc(dst),
9798 strictfp_bias2(dst) );
9799 ins_pipe( fpu_reg_reg );
9800 %}
9801
9802 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9803 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9804 match(Set dst (RoundDouble (DivD src1 src2)));
9805
9806 format %{ "FLD $src1\n\t"
9807 "FDIV ST,$src2\n\t"
9808 "FSTP_D $dst\t# D-round" %}
9809 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9810 ins_encode( Push_Reg_DPR(src1),
9811 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9812 ins_pipe( fpu_mem_reg_reg );
9813 %}
9814
9815
9816 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9817 predicate(UseSSE<=1);
9818 match(Set dst (ModD dst src));
9819 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9820
9821 format %{ "DMOD $dst,$src" %}
9822 ins_cost(250);
9823 ins_encode(Push_Reg_Mod_DPR(dst, src),
9824 emitModDPR(),
9825 Push_Result_Mod_DPR(src),
9826 Pop_Reg_DPR(dst));
9827 ins_pipe( pipe_slow );
9828 %}
9829
9830 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9831 predicate(UseSSE>=2);
9832 match(Set dst (ModD src0 src1));
9833 effect(KILL rax, KILL cr);
9834
9835 format %{ "SUB ESP,8\t # DMOD\n"
9836 "\tMOVSD [ESP+0],$src1\n"
9837 "\tFLD_D [ESP+0]\n"
9838 "\tMOVSD [ESP+0],$src0\n"
9839 "\tFLD_D [ESP+0]\n"
9840 "loop:\tFPREM\n"
9841 "\tFWAIT\n"
9842 "\tFNSTSW AX\n"
9843 "\tSAHF\n"
9844 "\tJP loop\n"
9845 "\tFSTP_D [ESP+0]\n"
9846 "\tMOVSD $dst,[ESP+0]\n"
9847 "\tADD ESP,8\n"
9848 "\tFSTP ST0\t # Restore FPU Stack"
9849 %}
9850 ins_cost(250);
9851 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9852 ins_pipe( pipe_slow );
9853 %}
9854
9855 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9856 predicate (UseSSE<=1);
9857 match(Set dst (SinD src));
9858 ins_cost(1800);
9859 format %{ "DSIN $dst" %}
9860 opcode(0xD9, 0xFE);
9861 ins_encode( OpcP, OpcS );
9862 ins_pipe( pipe_slow );
9863 %}
9864
9865 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9866 predicate (UseSSE>=2);
9867 match(Set dst (SinD dst));
9868 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9869 ins_cost(1800);
9870 format %{ "DSIN $dst" %}
9871 opcode(0xD9, 0xFE);
9872 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9873 ins_pipe( pipe_slow );
9874 %}
9875
9876 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9877 predicate (UseSSE<=1);
9878 match(Set dst (CosD src));
9879 ins_cost(1800);
9880 format %{ "DCOS $dst" %}
9881 opcode(0xD9, 0xFF);
9882 ins_encode( OpcP, OpcS );
9883 ins_pipe( pipe_slow );
9884 %}
9885
9886 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9887 predicate (UseSSE>=2);
9888 match(Set dst (CosD dst));
9889 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9890 ins_cost(1800);
9891 format %{ "DCOS $dst" %}
9892 opcode(0xD9, 0xFF);
9893 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9894 ins_pipe( pipe_slow );
9895 %}
9896
9897 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9898 predicate (UseSSE<=1);
9899 match(Set dst(TanD src));
9900 format %{ "DTAN $dst" %}
9901 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9902 Opcode(0xDD), Opcode(0xD8)); // fstp st
9903 ins_pipe( pipe_slow );
9904 %}
9905
9906 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9907 predicate (UseSSE>=2);
9908 match(Set dst(TanD dst));
9909 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9910 format %{ "DTAN $dst" %}
9911 ins_encode( Push_SrcD(dst),
9912 Opcode(0xD9), Opcode(0xF2), // fptan
9913 Opcode(0xDD), Opcode(0xD8), // fstp st
9914 Push_ResultD(dst) );
9915 ins_pipe( pipe_slow );
9916 %}
9917
9918 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9919 predicate (UseSSE<=1);
9920 match(Set dst(AtanD dst src));
9921 format %{ "DATA $dst,$src" %}
9922 opcode(0xD9, 0xF3);
9923 ins_encode( Push_Reg_DPR(src),
9924 OpcP, OpcS, RegOpc(dst) );
9925 ins_pipe( pipe_slow );
9926 %}
9927
9928 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9929 predicate (UseSSE>=2);
9930 match(Set dst(AtanD dst src));
9931 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9932 format %{ "DATA $dst,$src" %}
9933 opcode(0xD9, 0xF3);
9934 ins_encode( Push_SrcD(src),
9935 OpcP, OpcS, Push_ResultD(dst) );
9936 ins_pipe( pipe_slow );
9937 %}
9938
9939 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9940 predicate (UseSSE<=1);
9941 match(Set dst (SqrtD src));
9942 format %{ "DSQRT $dst,$src" %}
9943 opcode(0xFA, 0xD9);
9944 ins_encode( Push_Reg_DPR(src),
9945 OpcS, OpcP, Pop_Reg_DPR(dst) );
9946 ins_pipe( pipe_slow );
9947 %}
9948
9949 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9950 predicate (UseSSE<=1);
9951 match(Set Y (PowD X Y)); // Raise X to the Yth power
9952 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9953 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
9954 ins_encode %{
9955 __ subptr(rsp, 8);
9956 __ fld_s($X$$reg - 1);
9957 __ fast_pow();
9958 __ addptr(rsp, 8);
9959 %}
9960 ins_pipe( pipe_slow );
9961 %}
9962
9963 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9964 predicate (UseSSE>=2);
9965 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9966 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9967 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9968 ins_encode %{
9969 __ subptr(rsp, 8);
9970 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9971 __ fld_d(Address(rsp, 0));
9972 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9973 __ fld_d(Address(rsp, 0));
9974 __ fast_pow();
9975 __ fstp_d(Address(rsp, 0));
9976 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9977 __ addptr(rsp, 8);
9978 %}
9979 ins_pipe( pipe_slow );
9980 %}
9981
9982
9983 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9984 predicate (UseSSE<=1);
9985 match(Set dpr1 (ExpD dpr1));
9986 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9987 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
9988 ins_encode %{
9989 __ fast_exp();
9990 %}
9991 ins_pipe( pipe_slow );
9992 %}
9993
9994 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
9995 predicate (UseSSE>=2);
9996 match(Set dst (ExpD src));
9997 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9998 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9999 ins_encode %{
10000 __ subptr(rsp, 8);
10001 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10002 __ fld_d(Address(rsp, 0));
10003 __ fast_exp();
10004 __ fstp_d(Address(rsp, 0));
10005 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10006 __ addptr(rsp, 8);
10007 %}
10008 ins_pipe( pipe_slow );
10009 %}
10010
10011 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10012 predicate (UseSSE<=1);
10013 // The source Double operand on FPU stack
10014 match(Set dst (Log10D src));
10015 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10016 // fxch ; swap ST(0) with ST(1)
10017 // fyl2x ; compute log_10(2) * log_2(x)
10018 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10019 "FXCH \n\t"
10020 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10021 %}
10022 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10023 Opcode(0xD9), Opcode(0xC9), // fxch
10024 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10025
10026 ins_pipe( pipe_slow );
10027 %}
10028
10029 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10030 predicate (UseSSE>=2);
10031 effect(KILL cr);
10032 match(Set dst (Log10D src));
10033 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10034 // fyl2x ; compute log_10(2) * log_2(x)
10035 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10036 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10037 %}
10038 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10039 Push_SrcD(src),
10040 Opcode(0xD9), Opcode(0xF1), // fyl2x
10041 Push_ResultD(dst));
10042
10043 ins_pipe( pipe_slow );
10044 %}
10045
10046 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10047 predicate (UseSSE<=1);
10048 // The source Double operand on FPU stack
10049 match(Set dst (LogD src));
10050 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10051 // fxch ; swap ST(0) with ST(1)
10052 // fyl2x ; compute log_e(2) * log_2(x)
10053 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10054 "FXCH \n\t"
10055 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10056 %}
10057 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10058 Opcode(0xD9), Opcode(0xC9), // fxch
10059 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10060
10061 ins_pipe( pipe_slow );
10062 %}
10063
10064 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10065 predicate (UseSSE>=2);
10066 effect(KILL cr);
10067 // The source and result Double operands in XMM registers
10068 match(Set dst (LogD src));
10069 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10070 // fyl2x ; compute log_e(2) * log_2(x)
10071 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10072 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10073 %}
10074 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10075 Push_SrcD(src),
10076 Opcode(0xD9), Opcode(0xF1), // fyl2x
10077 Push_ResultD(dst));
10078 ins_pipe( pipe_slow );
10079 %}
10080
10081 //-------------Float Instructions-------------------------------
10082 // Float Math
10083
10084 // Code for float compare:
10085 // fcompp();
10086 // fwait(); fnstsw_ax();
10087 // sahf();
10088 // movl(dst, unordered_result);
10089 // jcc(Assembler::parity, exit);
10090 // movl(dst, less_result);
10091 // jcc(Assembler::below, exit);
10092 // movl(dst, equal_result);
10093 // jcc(Assembler::equal, exit);
10094 // movl(dst, greater_result);
10095 // exit:
10096
10097 // P6 version of float compare, sets condition codes in EFLAGS
10098 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10099 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10100 match(Set cr (CmpF src1 src2));
10101 effect(KILL rax);
10102 ins_cost(150);
10103 format %{ "FLD $src1\n\t"
10104 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10105 "JNP exit\n\t"
10106 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10107 "SAHF\n"
10108 "exit:\tNOP // avoid branch to branch" %}
10109 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10110 ins_encode( Push_Reg_DPR(src1),
10111 OpcP, RegOpc(src2),
10112 cmpF_P6_fixup );
10113 ins_pipe( pipe_slow );
10114 %}
10115
10116 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10117 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10118 match(Set cr (CmpF src1 src2));
10119 ins_cost(100);
10120 format %{ "FLD $src1\n\t"
10121 "FUCOMIP ST,$src2 // P6 instruction" %}
10122 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10123 ins_encode( Push_Reg_DPR(src1),
10124 OpcP, RegOpc(src2));
10125 ins_pipe( pipe_slow );
10126 %}
10127
10128
10129 // Compare & branch
10130 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10131 predicate(UseSSE == 0);
10132 match(Set cr (CmpF src1 src2));
10133 effect(KILL rax);
10134 ins_cost(200);
10135 format %{ "FLD $src1\n\t"
10136 "FCOMp $src2\n\t"
10137 "FNSTSW AX\n\t"
10138 "TEST AX,0x400\n\t"
10139 "JZ,s flags\n\t"
10140 "MOV AH,1\t# unordered treat as LT\n"
10141 "flags:\tSAHF" %}
10142 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10143 ins_encode( Push_Reg_DPR(src1),
10144 OpcP, RegOpc(src2),
10145 fpu_flags);
10146 ins_pipe( pipe_slow );
10147 %}
10148
10149 // Compare vs zero into -1,0,1
10150 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10151 predicate(UseSSE == 0);
10152 match(Set dst (CmpF3 src1 zero));
10153 effect(KILL cr, KILL rax);
10154 ins_cost(280);
10155 format %{ "FTSTF $dst,$src1" %}
10156 opcode(0xE4, 0xD9);
10157 ins_encode( Push_Reg_DPR(src1),
10158 OpcS, OpcP, PopFPU,
10159 CmpF_Result(dst));
10160 ins_pipe( pipe_slow );
10161 %}
10162
10163 // Compare into -1,0,1
10164 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10165 predicate(UseSSE == 0);
10166 match(Set dst (CmpF3 src1 src2));
10167 effect(KILL cr, KILL rax);
10168 ins_cost(300);
10169 format %{ "FCMPF $dst,$src1,$src2" %}
10170 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10171 ins_encode( Push_Reg_DPR(src1),
10172 OpcP, RegOpc(src2),
10173 CmpF_Result(dst));
10174 ins_pipe( pipe_slow );
10175 %}
10176
10177 // float compare and set condition codes in EFLAGS by XMM regs
10178 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10179 predicate(UseSSE>=1);
10180 match(Set cr (CmpF src1 src2));
10181 ins_cost(145);
10182 format %{ "UCOMISS $src1,$src2\n\t"
10183 "JNP,s exit\n\t"
10184 "PUSHF\t# saw NaN, set CF\n\t"
10185 "AND [rsp], #0xffffff2b\n\t"
10186 "POPF\n"
10187 "exit:" %}
10188 ins_encode %{
10189 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10190 emit_cmpfp_fixup(_masm);
10191 %}
10192 ins_pipe( pipe_slow );
10193 %}
10194
10195 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10196 predicate(UseSSE>=1);
10197 match(Set cr (CmpF src1 src2));
10198 ins_cost(100);
10199 format %{ "UCOMISS $src1,$src2" %}
10200 ins_encode %{
10201 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10202 %}
10203 ins_pipe( pipe_slow );
10204 %}
10205
10206 // float compare and set condition codes in EFLAGS by XMM regs
10207 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10208 predicate(UseSSE>=1);
10209 match(Set cr (CmpF src1 (LoadF src2)));
10210 ins_cost(165);
10211 format %{ "UCOMISS $src1,$src2\n\t"
10212 "JNP,s exit\n\t"
10213 "PUSHF\t# saw NaN, set CF\n\t"
10214 "AND [rsp], #0xffffff2b\n\t"
10215 "POPF\n"
10216 "exit:" %}
10217 ins_encode %{
10218 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10219 emit_cmpfp_fixup(_masm);
10220 %}
10221 ins_pipe( pipe_slow );
10222 %}
10223
10224 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10225 predicate(UseSSE>=1);
10226 match(Set cr (CmpF src1 (LoadF src2)));
10227 ins_cost(100);
10228 format %{ "UCOMISS $src1,$src2" %}
10229 ins_encode %{
10230 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10231 %}
10232 ins_pipe( pipe_slow );
10233 %}
10234
10235 // Compare into -1,0,1 in XMM
10236 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10237 predicate(UseSSE>=1);
10238 match(Set dst (CmpF3 src1 src2));
10239 effect(KILL cr);
10240 ins_cost(255);
10241 format %{ "UCOMISS $src1, $src2\n\t"
10242 "MOV $dst, #-1\n\t"
10243 "JP,s done\n\t"
10244 "JB,s done\n\t"
10245 "SETNE $dst\n\t"
10246 "MOVZB $dst, $dst\n"
10247 "done:" %}
10248 ins_encode %{
10249 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10250 emit_cmpfp3(_masm, $dst$$Register);
10251 %}
10252 ins_pipe( pipe_slow );
10253 %}
10254
10255 // Compare into -1,0,1 in XMM and memory
10256 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10257 predicate(UseSSE>=1);
10258 match(Set dst (CmpF3 src1 (LoadF src2)));
10259 effect(KILL cr);
10260 ins_cost(275);
10261 format %{ "UCOMISS $src1, $src2\n\t"
10262 "MOV $dst, #-1\n\t"
10263 "JP,s done\n\t"
10264 "JB,s done\n\t"
10265 "SETNE $dst\n\t"
10266 "MOVZB $dst, $dst\n"
10267 "done:" %}
10268 ins_encode %{
10269 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10270 emit_cmpfp3(_masm, $dst$$Register);
10271 %}
10272 ins_pipe( pipe_slow );
10273 %}
10274
10275 // Spill to obtain 24-bit precision
10276 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10277 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10278 match(Set dst (SubF src1 src2));
10279
10280 format %{ "FSUB $dst,$src1 - $src2" %}
10281 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10282 ins_encode( Push_Reg_FPR(src1),
10283 OpcReg_FPR(src2),
10284 Pop_Mem_FPR(dst) );
10285 ins_pipe( fpu_mem_reg_reg );
10286 %}
10287 //
10288 // This instruction does not round to 24-bits
10289 instruct subFPR_reg(regFPR dst, regFPR src) %{
10290 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10291 match(Set dst (SubF dst src));
10292
10293 format %{ "FSUB $dst,$src" %}
10294 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10295 ins_encode( Push_Reg_FPR(src),
10296 OpcP, RegOpc(dst) );
10297 ins_pipe( fpu_reg_reg );
10298 %}
10299
10300 // Spill to obtain 24-bit precision
10301 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10302 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10303 match(Set dst (AddF src1 src2));
10304
10305 format %{ "FADD $dst,$src1,$src2" %}
10306 opcode(0xD8, 0x0); /* D8 C0+i */
10307 ins_encode( Push_Reg_FPR(src2),
10308 OpcReg_FPR(src1),
10309 Pop_Mem_FPR(dst) );
10310 ins_pipe( fpu_mem_reg_reg );
10311 %}
10312 //
10313 // This instruction does not round to 24-bits
10314 instruct addFPR_reg(regFPR dst, regFPR src) %{
10315 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10316 match(Set dst (AddF dst src));
10317
10318 format %{ "FLD $src\n\t"
10319 "FADDp $dst,ST" %}
10320 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10321 ins_encode( Push_Reg_FPR(src),
10322 OpcP, RegOpc(dst) );
10323 ins_pipe( fpu_reg_reg );
10324 %}
10325
10326 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10327 predicate(UseSSE==0);
10328 match(Set dst (AbsF src));
10329 ins_cost(100);
10330 format %{ "FABS" %}
10331 opcode(0xE1, 0xD9);
10332 ins_encode( OpcS, OpcP );
10333 ins_pipe( fpu_reg_reg );
10334 %}
10335
10336 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10337 predicate(UseSSE==0);
10338 match(Set dst (NegF src));
10339 ins_cost(100);
10340 format %{ "FCHS" %}
10341 opcode(0xE0, 0xD9);
10342 ins_encode( OpcS, OpcP );
10343 ins_pipe( fpu_reg_reg );
10344 %}
10345
10346 // Cisc-alternate to addFPR_reg
10347 // Spill to obtain 24-bit precision
10348 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10349 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10350 match(Set dst (AddF src1 (LoadF src2)));
10351
10352 format %{ "FLD $src2\n\t"
10353 "FADD ST,$src1\n\t"
10354 "FSTP_S $dst" %}
10355 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10356 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10357 OpcReg_FPR(src1),
10358 Pop_Mem_FPR(dst) );
10359 ins_pipe( fpu_mem_reg_mem );
10360 %}
10361 //
10362 // Cisc-alternate to addFPR_reg
10363 // This instruction does not round to 24-bits
10364 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10365 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10366 match(Set dst (AddF dst (LoadF src)));
10367
10368 format %{ "FADD $dst,$src" %}
10369 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10370 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10371 OpcP, RegOpc(dst) );
10372 ins_pipe( fpu_reg_mem );
10373 %}
10374
10375 // // Following two instructions for _222_mpegaudio
10376 // Spill to obtain 24-bit precision
10377 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10378 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10379 match(Set dst (AddF src1 src2));
10380
10381 format %{ "FADD $dst,$src1,$src2" %}
10382 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10383 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10384 OpcReg_FPR(src2),
10385 Pop_Mem_FPR(dst) );
10386 ins_pipe( fpu_mem_reg_mem );
10387 %}
10388
10389 // Cisc-spill variant
10390 // Spill to obtain 24-bit precision
10391 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10392 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10393 match(Set dst (AddF src1 (LoadF src2)));
10394
10395 format %{ "FADD $dst,$src1,$src2 cisc" %}
10396 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10397 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10398 set_instruction_start,
10399 OpcP, RMopc_Mem(secondary,src1),
10400 Pop_Mem_FPR(dst) );
10401 ins_pipe( fpu_mem_mem_mem );
10402 %}
10403
10404 // Spill to obtain 24-bit precision
10405 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10406 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10407 match(Set dst (AddF src1 src2));
10408
10409 format %{ "FADD $dst,$src1,$src2" %}
10410 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10411 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10412 set_instruction_start,
10413 OpcP, RMopc_Mem(secondary,src1),
10414 Pop_Mem_FPR(dst) );
10415 ins_pipe( fpu_mem_mem_mem );
10416 %}
10417
10418
10419 // Spill to obtain 24-bit precision
10420 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10421 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10422 match(Set dst (AddF src con));
10423 format %{ "FLD $src\n\t"
10424 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10425 "FSTP_S $dst" %}
10426 ins_encode %{
10427 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10428 __ fadd_s($constantaddress($con));
10429 __ fstp_s(Address(rsp, $dst$$disp));
10430 %}
10431 ins_pipe(fpu_mem_reg_con);
10432 %}
10433 //
10434 // This instruction does not round to 24-bits
10435 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10436 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10437 match(Set dst (AddF src con));
10438 format %{ "FLD $src\n\t"
10439 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10440 "FSTP $dst" %}
10441 ins_encode %{
10442 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10443 __ fadd_s($constantaddress($con));
10444 __ fstp_d($dst$$reg);
10445 %}
10446 ins_pipe(fpu_reg_reg_con);
10447 %}
10448
10449 // Spill to obtain 24-bit precision
10450 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10451 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10452 match(Set dst (MulF src1 src2));
10453
10454 format %{ "FLD $src1\n\t"
10455 "FMUL $src2\n\t"
10456 "FSTP_S $dst" %}
10457 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10458 ins_encode( Push_Reg_FPR(src1),
10459 OpcReg_FPR(src2),
10460 Pop_Mem_FPR(dst) );
10461 ins_pipe( fpu_mem_reg_reg );
10462 %}
10463 //
10464 // This instruction does not round to 24-bits
10465 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10466 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10467 match(Set dst (MulF src1 src2));
10468
10469 format %{ "FLD $src1\n\t"
10470 "FMUL $src2\n\t"
10471 "FSTP_S $dst" %}
10472 opcode(0xD8, 0x1); /* D8 C8+i */
10473 ins_encode( Push_Reg_FPR(src2),
10474 OpcReg_FPR(src1),
10475 Pop_Reg_FPR(dst) );
10476 ins_pipe( fpu_reg_reg_reg );
10477 %}
10478
10479
10480 // Spill to obtain 24-bit precision
10481 // Cisc-alternate to reg-reg multiply
10482 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10483 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10484 match(Set dst (MulF src1 (LoadF src2)));
10485
10486 format %{ "FLD_S $src2\n\t"
10487 "FMUL $src1\n\t"
10488 "FSTP_S $dst" %}
10489 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10490 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10491 OpcReg_FPR(src1),
10492 Pop_Mem_FPR(dst) );
10493 ins_pipe( fpu_mem_reg_mem );
10494 %}
10495 //
10496 // This instruction does not round to 24-bits
10497 // Cisc-alternate to reg-reg multiply
10498 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10499 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10500 match(Set dst (MulF src1 (LoadF src2)));
10501
10502 format %{ "FMUL $dst,$src1,$src2" %}
10503 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10504 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10505 OpcReg_FPR(src1),
10506 Pop_Reg_FPR(dst) );
10507 ins_pipe( fpu_reg_reg_mem );
10508 %}
10509
10510 // Spill to obtain 24-bit precision
10511 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10512 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10513 match(Set dst (MulF src1 src2));
10514
10515 format %{ "FMUL $dst,$src1,$src2" %}
10516 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10517 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10518 set_instruction_start,
10519 OpcP, RMopc_Mem(secondary,src1),
10520 Pop_Mem_FPR(dst) );
10521 ins_pipe( fpu_mem_mem_mem );
10522 %}
10523
10524 // Spill to obtain 24-bit precision
10525 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10526 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10527 match(Set dst (MulF src con));
10528
10529 format %{ "FLD $src\n\t"
10530 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10531 "FSTP_S $dst" %}
10532 ins_encode %{
10533 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10534 __ fmul_s($constantaddress($con));
10535 __ fstp_s(Address(rsp, $dst$$disp));
10536 %}
10537 ins_pipe(fpu_mem_reg_con);
10538 %}
10539 //
10540 // This instruction does not round to 24-bits
10541 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10542 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10543 match(Set dst (MulF src con));
10544
10545 format %{ "FLD $src\n\t"
10546 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10547 "FSTP $dst" %}
10548 ins_encode %{
10549 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10550 __ fmul_s($constantaddress($con));
10551 __ fstp_d($dst$$reg);
10552 %}
10553 ins_pipe(fpu_reg_reg_con);
10554 %}
10555
10556
10557 //
10558 // MACRO1 -- subsume unshared load into mulFPR
10559 // This instruction does not round to 24-bits
10560 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10561 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10562 match(Set dst (MulF (LoadF mem1) src));
10563
10564 format %{ "FLD $mem1 ===MACRO1===\n\t"
10565 "FMUL ST,$src\n\t"
10566 "FSTP $dst" %}
10567 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10568 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10569 OpcReg_FPR(src),
10570 Pop_Reg_FPR(dst) );
10571 ins_pipe( fpu_reg_reg_mem );
10572 %}
10573 //
10574 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10575 // This instruction does not round to 24-bits
10576 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10577 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10578 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10579 ins_cost(95);
10580
10581 format %{ "FLD $mem1 ===MACRO2===\n\t"
10582 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10583 "FADD ST,$src2\n\t"
10584 "FSTP $dst" %}
10585 opcode(0xD9); /* LoadF D9 /0 */
10586 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10587 FMul_ST_reg(src1),
10588 FAdd_ST_reg(src2),
10589 Pop_Reg_FPR(dst) );
10590 ins_pipe( fpu_reg_mem_reg_reg );
10591 %}
10592
10593 // MACRO3 -- addFPR a mulFPR
10594 // This instruction does not round to 24-bits. It is a '2-address'
10595 // instruction in that the result goes back to src2. This eliminates
10596 // a move from the macro; possibly the register allocator will have
10597 // to add it back (and maybe not).
10598 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10599 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10600 match(Set src2 (AddF (MulF src0 src1) src2));
10601
10602 format %{ "FLD $src0 ===MACRO3===\n\t"
10603 "FMUL ST,$src1\n\t"
10604 "FADDP $src2,ST" %}
10605 opcode(0xD9); /* LoadF D9 /0 */
10606 ins_encode( Push_Reg_FPR(src0),
10607 FMul_ST_reg(src1),
10608 FAddP_reg_ST(src2) );
10609 ins_pipe( fpu_reg_reg_reg );
10610 %}
10611
10612 // MACRO4 -- divFPR subFPR
10613 // This instruction does not round to 24-bits
10614 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10615 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10616 match(Set dst (DivF (SubF src2 src1) src3));
10617
10618 format %{ "FLD $src2 ===MACRO4===\n\t"
10619 "FSUB ST,$src1\n\t"
10620 "FDIV ST,$src3\n\t"
10621 "FSTP $dst" %}
10622 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10623 ins_encode( Push_Reg_FPR(src2),
10624 subFPR_divFPR_encode(src1,src3),
10625 Pop_Reg_FPR(dst) );
10626 ins_pipe( fpu_reg_reg_reg_reg );
10627 %}
10628
10629 // Spill to obtain 24-bit precision
10630 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10631 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10632 match(Set dst (DivF src1 src2));
10633
10634 format %{ "FDIV $dst,$src1,$src2" %}
10635 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10636 ins_encode( Push_Reg_FPR(src1),
10637 OpcReg_FPR(src2),
10638 Pop_Mem_FPR(dst) );
10639 ins_pipe( fpu_mem_reg_reg );
10640 %}
10641 //
10642 // This instruction does not round to 24-bits
10643 instruct divFPR_reg(regFPR dst, regFPR src) %{
10644 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10645 match(Set dst (DivF dst src));
10646
10647 format %{ "FDIV $dst,$src" %}
10648 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10649 ins_encode( Push_Reg_FPR(src),
10650 OpcP, RegOpc(dst) );
10651 ins_pipe( fpu_reg_reg );
10652 %}
10653
10654
10655 // Spill to obtain 24-bit precision
10656 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10657 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10658 match(Set dst (ModF src1 src2));
10659 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10660
10661 format %{ "FMOD $dst,$src1,$src2" %}
10662 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10663 emitModDPR(),
10664 Push_Result_Mod_DPR(src2),
10665 Pop_Mem_FPR(dst));
10666 ins_pipe( pipe_slow );
10667 %}
10668 //
10669 // This instruction does not round to 24-bits
10670 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10671 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10672 match(Set dst (ModF dst src));
10673 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10674
10675 format %{ "FMOD $dst,$src" %}
10676 ins_encode(Push_Reg_Mod_DPR(dst, src),
10677 emitModDPR(),
10678 Push_Result_Mod_DPR(src),
10679 Pop_Reg_FPR(dst));
10680 ins_pipe( pipe_slow );
10681 %}
10682
10683 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10684 predicate(UseSSE>=1);
10685 match(Set dst (ModF src0 src1));
10686 effect(KILL rax, KILL cr);
10687 format %{ "SUB ESP,4\t # FMOD\n"
10688 "\tMOVSS [ESP+0],$src1\n"
10689 "\tFLD_S [ESP+0]\n"
10690 "\tMOVSS [ESP+0],$src0\n"
10691 "\tFLD_S [ESP+0]\n"
10692 "loop:\tFPREM\n"
10693 "\tFWAIT\n"
10694 "\tFNSTSW AX\n"
10695 "\tSAHF\n"
10696 "\tJP loop\n"
10697 "\tFSTP_S [ESP+0]\n"
10698 "\tMOVSS $dst,[ESP+0]\n"
10699 "\tADD ESP,4\n"
10700 "\tFSTP ST0\t # Restore FPU Stack"
10701 %}
10702 ins_cost(250);
10703 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10704 ins_pipe( pipe_slow );
10705 %}
10706
10707
10708 //----------Arithmetic Conversion Instructions---------------------------------
10709 // The conversions operations are all Alpha sorted. Please keep it that way!
10710
10711 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10712 predicate(UseSSE==0);
10713 match(Set dst (RoundFloat src));
10714 ins_cost(125);
10715 format %{ "FST_S $dst,$src\t# F-round" %}
10716 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10717 ins_pipe( fpu_mem_reg );
10718 %}
10719
10720 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10721 predicate(UseSSE<=1);
10722 match(Set dst (RoundDouble src));
10723 ins_cost(125);
10724 format %{ "FST_D $dst,$src\t# D-round" %}
10725 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10726 ins_pipe( fpu_mem_reg );
10727 %}
10728
10729 // Force rounding to 24-bit precision and 6-bit exponent
10730 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10731 predicate(UseSSE==0);
10732 match(Set dst (ConvD2F src));
10733 format %{ "FST_S $dst,$src\t# F-round" %}
10734 expand %{
10735 roundFloat_mem_reg(dst,src);
10736 %}
10737 %}
10738
10739 // Force rounding to 24-bit precision and 6-bit exponent
10740 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10741 predicate(UseSSE==1);
10742 match(Set dst (ConvD2F src));
10743 effect( KILL cr );
10744 format %{ "SUB ESP,4\n\t"
10745 "FST_S [ESP],$src\t# F-round\n\t"
10746 "MOVSS $dst,[ESP]\n\t"
10747 "ADD ESP,4" %}
10748 ins_encode %{
10749 __ subptr(rsp, 4);
10750 if ($src$$reg != FPR1L_enc) {
10751 __ fld_s($src$$reg-1);
10752 __ fstp_s(Address(rsp, 0));
10753 } else {
10754 __ fst_s(Address(rsp, 0));
10755 }
10756 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10757 __ addptr(rsp, 4);
10758 %}
10759 ins_pipe( pipe_slow );
10760 %}
10761
10762 // Force rounding double precision to single precision
10763 instruct convD2F_reg(regF dst, regD src) %{
10764 predicate(UseSSE>=2);
10765 match(Set dst (ConvD2F src));
10766 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10767 ins_encode %{
10768 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10769 %}
10770 ins_pipe( pipe_slow );
10771 %}
10772
10773 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10774 predicate(UseSSE==0);
10775 match(Set dst (ConvF2D src));
10776 format %{ "FST_S $dst,$src\t# D-round" %}
10777 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10778 ins_pipe( fpu_reg_reg );
10779 %}
10780
10781 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10782 predicate(UseSSE==1);
10783 match(Set dst (ConvF2D src));
10784 format %{ "FST_D $dst,$src\t# D-round" %}
10785 expand %{
10786 roundDouble_mem_reg(dst,src);
10787 %}
10788 %}
10789
10790 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10791 predicate(UseSSE==1);
10792 match(Set dst (ConvF2D src));
10793 effect( KILL cr );
10794 format %{ "SUB ESP,4\n\t"
10795 "MOVSS [ESP] $src\n\t"
10796 "FLD_S [ESP]\n\t"
10797 "ADD ESP,4\n\t"
10798 "FSTP $dst\t# D-round" %}
10799 ins_encode %{
10800 __ subptr(rsp, 4);
10801 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10802 __ fld_s(Address(rsp, 0));
10803 __ addptr(rsp, 4);
10804 __ fstp_d($dst$$reg);
10805 %}
10806 ins_pipe( pipe_slow );
10807 %}
10808
10809 instruct convF2D_reg(regD dst, regF src) %{
10810 predicate(UseSSE>=2);
10811 match(Set dst (ConvF2D src));
10812 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10813 ins_encode %{
10814 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10815 %}
10816 ins_pipe( pipe_slow );
10817 %}
10818
10819 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10820 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10821 predicate(UseSSE<=1);
10822 match(Set dst (ConvD2I src));
10823 effect( KILL tmp, KILL cr );
10824 format %{ "FLD $src\t# Convert double to int \n\t"
10825 "FLDCW trunc mode\n\t"
10826 "SUB ESP,4\n\t"
10827 "FISTp [ESP + #0]\n\t"
10828 "FLDCW std/24-bit mode\n\t"
10829 "POP EAX\n\t"
10830 "CMP EAX,0x80000000\n\t"
10831 "JNE,s fast\n\t"
10832 "FLD_D $src\n\t"
10833 "CALL d2i_wrapper\n"
10834 "fast:" %}
10835 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10836 ins_pipe( pipe_slow );
10837 %}
10838
10839 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10840 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10841 predicate(UseSSE>=2);
10842 match(Set dst (ConvD2I src));
10843 effect( KILL tmp, KILL cr );
10844 format %{ "CVTTSD2SI $dst, $src\n\t"
10845 "CMP $dst,0x80000000\n\t"
10846 "JNE,s fast\n\t"
10847 "SUB ESP, 8\n\t"
10848 "MOVSD [ESP], $src\n\t"
10849 "FLD_D [ESP]\n\t"
10850 "ADD ESP, 8\n\t"
10851 "CALL d2i_wrapper\n"
10852 "fast:" %}
10853 ins_encode %{
10854 Label fast;
10855 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10856 __ cmpl($dst$$Register, 0x80000000);
10857 __ jccb(Assembler::notEqual, fast);
10858 __ subptr(rsp, 8);
10859 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10860 __ fld_d(Address(rsp, 0));
10861 __ addptr(rsp, 8);
10862 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10863 __ bind(fast);
10864 %}
10865 ins_pipe( pipe_slow );
10866 %}
10867
10868 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10869 predicate(UseSSE<=1);
10870 match(Set dst (ConvD2L src));
10871 effect( KILL cr );
10872 format %{ "FLD $src\t# Convert double to long\n\t"
10873 "FLDCW trunc mode\n\t"
10874 "SUB ESP,8\n\t"
10875 "FISTp [ESP + #0]\n\t"
10876 "FLDCW std/24-bit mode\n\t"
10877 "POP EAX\n\t"
10878 "POP EDX\n\t"
10879 "CMP EDX,0x80000000\n\t"
10880 "JNE,s fast\n\t"
10881 "TEST EAX,EAX\n\t"
10882 "JNE,s fast\n\t"
10883 "FLD $src\n\t"
10884 "CALL d2l_wrapper\n"
10885 "fast:" %}
10886 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
10887 ins_pipe( pipe_slow );
10888 %}
10889
10890 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10891 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10892 predicate (UseSSE>=2);
10893 match(Set dst (ConvD2L src));
10894 effect( KILL cr );
10895 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10896 "MOVSD [ESP],$src\n\t"
10897 "FLD_D [ESP]\n\t"
10898 "FLDCW trunc mode\n\t"
10899 "FISTp [ESP + #0]\n\t"
10900 "FLDCW std/24-bit mode\n\t"
10901 "POP EAX\n\t"
10902 "POP EDX\n\t"
10903 "CMP EDX,0x80000000\n\t"
10904 "JNE,s fast\n\t"
10905 "TEST EAX,EAX\n\t"
10906 "JNE,s fast\n\t"
10907 "SUB ESP,8\n\t"
10908 "MOVSD [ESP],$src\n\t"
10909 "FLD_D [ESP]\n\t"
10910 "ADD ESP,8\n\t"
10911 "CALL d2l_wrapper\n"
10912 "fast:" %}
10913 ins_encode %{
10914 Label fast;
10915 __ subptr(rsp, 8);
10916 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10917 __ fld_d(Address(rsp, 0));
10918 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
10919 __ fistp_d(Address(rsp, 0));
10920 // Restore the rounding mode, mask the exception
10921 if (Compile::current()->in_24_bit_fp_mode()) {
10922 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
10923 } else {
10924 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
10925 }
10926 // Load the converted long, adjust CPU stack
10927 __ pop(rax);
10928 __ pop(rdx);
10929 __ cmpl(rdx, 0x80000000);
10930 __ jccb(Assembler::notEqual, fast);
10931 __ testl(rax, rax);
10932 __ jccb(Assembler::notEqual, fast);
10933 __ subptr(rsp, 8);
10934 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10935 __ fld_d(Address(rsp, 0));
10936 __ addptr(rsp, 8);
10937 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
10938 __ bind(fast);
10939 %}
10940 ins_pipe( pipe_slow );
10941 %}
10942
10943 // Convert a double to an int. Java semantics require we do complex
10944 // manglations in the corner cases. So we set the rounding mode to
10945 // 'zero', store the darned double down as an int, and reset the
10946 // rounding mode to 'nearest'. The hardware stores a flag value down
10947 // if we would overflow or converted a NAN; we check for this and
10948 // and go the slow path if needed.
10949 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
10950 predicate(UseSSE==0);
10951 match(Set dst (ConvF2I src));
10952 effect( KILL tmp, KILL cr );
10953 format %{ "FLD $src\t# Convert float to int \n\t"
10954 "FLDCW trunc mode\n\t"
10955 "SUB ESP,4\n\t"
10956 "FISTp [ESP + #0]\n\t"
10957 "FLDCW std/24-bit mode\n\t"
10958 "POP EAX\n\t"
10959 "CMP EAX,0x80000000\n\t"
10960 "JNE,s fast\n\t"
10961 "FLD $src\n\t"
10962 "CALL d2i_wrapper\n"
10963 "fast:" %}
10964 // DPR2I_encoding works for FPR2I
10965 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
10966 ins_pipe( pipe_slow );
10967 %}
10968
10969 // Convert a float in xmm to an int reg.
10970 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
10971 predicate(UseSSE>=1);
10972 match(Set dst (ConvF2I src));
10973 effect( KILL tmp, KILL cr );
10974 format %{ "CVTTSS2SI $dst, $src\n\t"
10975 "CMP $dst,0x80000000\n\t"
10976 "JNE,s fast\n\t"
10977 "SUB ESP, 4\n\t"
10978 "MOVSS [ESP], $src\n\t"
10979 "FLD [ESP]\n\t"
10980 "ADD ESP, 4\n\t"
10981 "CALL d2i_wrapper\n"
10982 "fast:" %}
10983 ins_encode %{
10984 Label fast;
10985 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10986 __ cmpl($dst$$Register, 0x80000000);
10987 __ jccb(Assembler::notEqual, fast);
10988 __ subptr(rsp, 4);
10989 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10990 __ fld_s(Address(rsp, 0));
10991 __ addptr(rsp, 4);
10992 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10993 __ bind(fast);
10994 %}
10995 ins_pipe( pipe_slow );
10996 %}
10997
10998 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
10999 predicate(UseSSE==0);
11000 match(Set dst (ConvF2L src));
11001 effect( KILL cr );
11002 format %{ "FLD $src\t# Convert float to long\n\t"
11003 "FLDCW trunc mode\n\t"
11004 "SUB ESP,8\n\t"
11005 "FISTp [ESP + #0]\n\t"
11006 "FLDCW std/24-bit mode\n\t"
11007 "POP EAX\n\t"
11008 "POP EDX\n\t"
11009 "CMP EDX,0x80000000\n\t"
11010 "JNE,s fast\n\t"
11011 "TEST EAX,EAX\n\t"
11012 "JNE,s fast\n\t"
11013 "FLD $src\n\t"
11014 "CALL d2l_wrapper\n"
11015 "fast:" %}
11016 // DPR2L_encoding works for FPR2L
11017 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11018 ins_pipe( pipe_slow );
11019 %}
11020
11021 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11022 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11023 predicate (UseSSE>=1);
11024 match(Set dst (ConvF2L src));
11025 effect( KILL cr );
11026 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11027 "MOVSS [ESP],$src\n\t"
11028 "FLD_S [ESP]\n\t"
11029 "FLDCW trunc mode\n\t"
11030 "FISTp [ESP + #0]\n\t"
11031 "FLDCW std/24-bit mode\n\t"
11032 "POP EAX\n\t"
11033 "POP EDX\n\t"
11034 "CMP EDX,0x80000000\n\t"
11035 "JNE,s fast\n\t"
11036 "TEST EAX,EAX\n\t"
11037 "JNE,s fast\n\t"
11038 "SUB ESP,4\t# Convert float to long\n\t"
11039 "MOVSS [ESP],$src\n\t"
11040 "FLD_S [ESP]\n\t"
11041 "ADD ESP,4\n\t"
11042 "CALL d2l_wrapper\n"
11043 "fast:" %}
11044 ins_encode %{
11045 Label fast;
11046 __ subptr(rsp, 8);
11047 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11048 __ fld_s(Address(rsp, 0));
11049 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11050 __ fistp_d(Address(rsp, 0));
11051 // Restore the rounding mode, mask the exception
11052 if (Compile::current()->in_24_bit_fp_mode()) {
11053 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11054 } else {
11055 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11056 }
11057 // Load the converted long, adjust CPU stack
11058 __ pop(rax);
11059 __ pop(rdx);
11060 __ cmpl(rdx, 0x80000000);
11061 __ jccb(Assembler::notEqual, fast);
11062 __ testl(rax, rax);
11063 __ jccb(Assembler::notEqual, fast);
11064 __ subptr(rsp, 4);
11065 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11066 __ fld_s(Address(rsp, 0));
11067 __ addptr(rsp, 4);
11068 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11069 __ bind(fast);
11070 %}
11071 ins_pipe( pipe_slow );
11072 %}
11073
11074 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11075 predicate( UseSSE<=1 );
11076 match(Set dst (ConvI2D src));
11077 format %{ "FILD $src\n\t"
11078 "FSTP $dst" %}
11079 opcode(0xDB, 0x0); /* DB /0 */
11080 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11081 ins_pipe( fpu_reg_mem );
11082 %}
11083
11084 instruct convI2D_reg(regD dst, rRegI src) %{
11085 predicate( UseSSE>=2 && !UseXmmI2D );
11086 match(Set dst (ConvI2D src));
11087 format %{ "CVTSI2SD $dst,$src" %}
11088 ins_encode %{
11089 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11090 %}
11091 ins_pipe( pipe_slow );
11092 %}
11093
11094 instruct convI2D_mem(regD dst, memory mem) %{
11095 predicate( UseSSE>=2 );
11096 match(Set dst (ConvI2D (LoadI mem)));
11097 format %{ "CVTSI2SD $dst,$mem" %}
11098 ins_encode %{
11099 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11100 %}
11101 ins_pipe( pipe_slow );
11102 %}
11103
11104 instruct convXI2D_reg(regD dst, rRegI src)
11105 %{
11106 predicate( UseSSE>=2 && UseXmmI2D );
11107 match(Set dst (ConvI2D src));
11108
11109 format %{ "MOVD $dst,$src\n\t"
11110 "CVTDQ2PD $dst,$dst\t# i2d" %}
11111 ins_encode %{
11112 __ movdl($dst$$XMMRegister, $src$$Register);
11113 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11114 %}
11115 ins_pipe(pipe_slow); // XXX
11116 %}
11117
11118 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11119 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11120 match(Set dst (ConvI2D (LoadI mem)));
11121 format %{ "FILD $mem\n\t"
11122 "FSTP $dst" %}
11123 opcode(0xDB); /* DB /0 */
11124 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11125 Pop_Reg_DPR(dst));
11126 ins_pipe( fpu_reg_mem );
11127 %}
11128
11129 // Convert a byte to a float; no rounding step needed.
11130 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11131 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11132 match(Set dst (ConvI2F src));
11133 format %{ "FILD $src\n\t"
11134 "FSTP $dst" %}
11135
11136 opcode(0xDB, 0x0); /* DB /0 */
11137 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11138 ins_pipe( fpu_reg_mem );
11139 %}
11140
11141 // In 24-bit mode, force exponent rounding by storing back out
11142 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11143 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11144 match(Set dst (ConvI2F src));
11145 ins_cost(200);
11146 format %{ "FILD $src\n\t"
11147 "FSTP_S $dst" %}
11148 opcode(0xDB, 0x0); /* DB /0 */
11149 ins_encode( Push_Mem_I(src),
11150 Pop_Mem_FPR(dst));
11151 ins_pipe( fpu_mem_mem );
11152 %}
11153
11154 // In 24-bit mode, force exponent rounding by storing back out
11155 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11156 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11157 match(Set dst (ConvI2F (LoadI mem)));
11158 ins_cost(200);
11159 format %{ "FILD $mem\n\t"
11160 "FSTP_S $dst" %}
11161 opcode(0xDB); /* DB /0 */
11162 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11163 Pop_Mem_FPR(dst));
11164 ins_pipe( fpu_mem_mem );
11165 %}
11166
11167 // This instruction does not round to 24-bits
11168 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11169 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11170 match(Set dst (ConvI2F src));
11171 format %{ "FILD $src\n\t"
11172 "FSTP $dst" %}
11173 opcode(0xDB, 0x0); /* DB /0 */
11174 ins_encode( Push_Mem_I(src),
11175 Pop_Reg_FPR(dst));
11176 ins_pipe( fpu_reg_mem );
11177 %}
11178
11179 // This instruction does not round to 24-bits
11180 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11181 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11182 match(Set dst (ConvI2F (LoadI mem)));
11183 format %{ "FILD $mem\n\t"
11184 "FSTP $dst" %}
11185 opcode(0xDB); /* DB /0 */
11186 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11187 Pop_Reg_FPR(dst));
11188 ins_pipe( fpu_reg_mem );
11189 %}
11190
11191 // Convert an int to a float in xmm; no rounding step needed.
11192 instruct convI2F_reg(regF dst, rRegI src) %{
11193 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11194 match(Set dst (ConvI2F src));
11195 format %{ "CVTSI2SS $dst, $src" %}
11196 ins_encode %{
11197 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11198 %}
11199 ins_pipe( pipe_slow );
11200 %}
11201
11202 instruct convXI2F_reg(regF dst, rRegI src)
11203 %{
11204 predicate( UseSSE>=2 && UseXmmI2F );
11205 match(Set dst (ConvI2F src));
11206
11207 format %{ "MOVD $dst,$src\n\t"
11208 "CVTDQ2PS $dst,$dst\t# i2f" %}
11209 ins_encode %{
11210 __ movdl($dst$$XMMRegister, $src$$Register);
11211 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11212 %}
11213 ins_pipe(pipe_slow); // XXX
11214 %}
11215
11216 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11217 match(Set dst (ConvI2L src));
11218 effect(KILL cr);
11219 ins_cost(375);
11220 format %{ "MOV $dst.lo,$src\n\t"
11221 "MOV $dst.hi,$src\n\t"
11222 "SAR $dst.hi,31" %}
11223 ins_encode(convert_int_long(dst,src));
11224 ins_pipe( ialu_reg_reg_long );
11225 %}
11226
11227 // Zero-extend convert int to long
11228 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11229 match(Set dst (AndL (ConvI2L src) mask) );
11230 effect( KILL flags );
11231 ins_cost(250);
11232 format %{ "MOV $dst.lo,$src\n\t"
11233 "XOR $dst.hi,$dst.hi" %}
11234 opcode(0x33); // XOR
11235 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11236 ins_pipe( ialu_reg_reg_long );
11237 %}
11238
11239 // Zero-extend long
11240 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11241 match(Set dst (AndL src mask) );
11242 effect( KILL flags );
11243 ins_cost(250);
11244 format %{ "MOV $dst.lo,$src.lo\n\t"
11245 "XOR $dst.hi,$dst.hi\n\t" %}
11246 opcode(0x33); // XOR
11247 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11248 ins_pipe( ialu_reg_reg_long );
11249 %}
11250
11251 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11252 predicate (UseSSE<=1);
11253 match(Set dst (ConvL2D src));
11254 effect( KILL cr );
11255 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11256 "PUSH $src.lo\n\t"
11257 "FILD ST,[ESP + #0]\n\t"
11258 "ADD ESP,8\n\t"
11259 "FSTP_D $dst\t# D-round" %}
11260 opcode(0xDF, 0x5); /* DF /5 */
11261 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11262 ins_pipe( pipe_slow );
11263 %}
11264
11265 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11266 predicate (UseSSE>=2);
11267 match(Set dst (ConvL2D src));
11268 effect( KILL cr );
11269 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11270 "PUSH $src.lo\n\t"
11271 "FILD_D [ESP]\n\t"
11272 "FSTP_D [ESP]\n\t"
11273 "MOVSD $dst,[ESP]\n\t"
11274 "ADD ESP,8" %}
11275 opcode(0xDF, 0x5); /* DF /5 */
11276 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11277 ins_pipe( pipe_slow );
11278 %}
11279
11280 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11281 predicate (UseSSE>=1);
11282 match(Set dst (ConvL2F src));
11283 effect( KILL cr );
11284 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11285 "PUSH $src.lo\n\t"
11286 "FILD_D [ESP]\n\t"
11287 "FSTP_S [ESP]\n\t"
11288 "MOVSS $dst,[ESP]\n\t"
11289 "ADD ESP,8" %}
11290 opcode(0xDF, 0x5); /* DF /5 */
11291 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11292 ins_pipe( pipe_slow );
11293 %}
11294
11295 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11296 match(Set dst (ConvL2F src));
11297 effect( KILL cr );
11298 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11299 "PUSH $src.lo\n\t"
11300 "FILD ST,[ESP + #0]\n\t"
11301 "ADD ESP,8\n\t"
11302 "FSTP_S $dst\t# F-round" %}
11303 opcode(0xDF, 0x5); /* DF /5 */
11304 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11305 ins_pipe( pipe_slow );
11306 %}
11307
11308 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11309 match(Set dst (ConvL2I src));
11310 effect( DEF dst, USE src );
11311 format %{ "MOV $dst,$src.lo" %}
11312 ins_encode(enc_CopyL_Lo(dst,src));
11313 ins_pipe( ialu_reg_reg );
11314 %}
11315
11316
11317 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11318 match(Set dst (MoveF2I src));
11319 effect( DEF dst, USE src );
11320 ins_cost(100);
11321 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11322 ins_encode %{
11323 __ movl($dst$$Register, Address(rsp, $src$$disp));
11324 %}
11325 ins_pipe( ialu_reg_mem );
11326 %}
11327
11328 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11329 predicate(UseSSE==0);
11330 match(Set dst (MoveF2I src));
11331 effect( DEF dst, USE src );
11332
11333 ins_cost(125);
11334 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11335 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11336 ins_pipe( fpu_mem_reg );
11337 %}
11338
11339 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11340 predicate(UseSSE>=1);
11341 match(Set dst (MoveF2I src));
11342 effect( DEF dst, USE src );
11343
11344 ins_cost(95);
11345 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11346 ins_encode %{
11347 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11348 %}
11349 ins_pipe( pipe_slow );
11350 %}
11351
11352 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11353 predicate(UseSSE>=2);
11354 match(Set dst (MoveF2I src));
11355 effect( DEF dst, USE src );
11356 ins_cost(85);
11357 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11358 ins_encode %{
11359 __ movdl($dst$$Register, $src$$XMMRegister);
11360 %}
11361 ins_pipe( pipe_slow );
11362 %}
11363
11364 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11365 match(Set dst (MoveI2F src));
11366 effect( DEF dst, USE src );
11367
11368 ins_cost(100);
11369 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11370 ins_encode %{
11371 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11372 %}
11373 ins_pipe( ialu_mem_reg );
11374 %}
11375
11376
11377 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11378 predicate(UseSSE==0);
11379 match(Set dst (MoveI2F src));
11380 effect(DEF dst, USE src);
11381
11382 ins_cost(125);
11383 format %{ "FLD_S $src\n\t"
11384 "FSTP $dst\t# MoveI2F_stack_reg" %}
11385 opcode(0xD9); /* D9 /0, FLD m32real */
11386 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11387 Pop_Reg_FPR(dst) );
11388 ins_pipe( fpu_reg_mem );
11389 %}
11390
11391 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11392 predicate(UseSSE>=1);
11393 match(Set dst (MoveI2F src));
11394 effect( DEF dst, USE src );
11395
11396 ins_cost(95);
11397 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11398 ins_encode %{
11399 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11400 %}
11401 ins_pipe( pipe_slow );
11402 %}
11403
11404 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11405 predicate(UseSSE>=2);
11406 match(Set dst (MoveI2F src));
11407 effect( DEF dst, USE src );
11408
11409 ins_cost(85);
11410 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11411 ins_encode %{
11412 __ movdl($dst$$XMMRegister, $src$$Register);
11413 %}
11414 ins_pipe( pipe_slow );
11415 %}
11416
11417 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11418 match(Set dst (MoveD2L src));
11419 effect(DEF dst, USE src);
11420
11421 ins_cost(250);
11422 format %{ "MOV $dst.lo,$src\n\t"
11423 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11424 opcode(0x8B, 0x8B);
11425 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11426 ins_pipe( ialu_mem_long_reg );
11427 %}
11428
11429 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11430 predicate(UseSSE<=1);
11431 match(Set dst (MoveD2L src));
11432 effect(DEF dst, USE src);
11433
11434 ins_cost(125);
11435 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11436 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11437 ins_pipe( fpu_mem_reg );
11438 %}
11439
11440 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11441 predicate(UseSSE>=2);
11442 match(Set dst (MoveD2L src));
11443 effect(DEF dst, USE src);
11444 ins_cost(95);
11445 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11446 ins_encode %{
11447 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11448 %}
11449 ins_pipe( pipe_slow );
11450 %}
11451
11452 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11453 predicate(UseSSE>=2);
11454 match(Set dst (MoveD2L src));
11455 effect(DEF dst, USE src, TEMP tmp);
11456 ins_cost(85);
11457 format %{ "MOVD $dst.lo,$src\n\t"
11458 "PSHUFLW $tmp,$src,0x4E\n\t"
11459 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11460 ins_encode %{
11461 __ movdl($dst$$Register, $src$$XMMRegister);
11462 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11463 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11464 %}
11465 ins_pipe( pipe_slow );
11466 %}
11467
11468 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11469 match(Set dst (MoveL2D src));
11470 effect(DEF dst, USE src);
11471
11472 ins_cost(200);
11473 format %{ "MOV $dst,$src.lo\n\t"
11474 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11475 opcode(0x89, 0x89);
11476 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11477 ins_pipe( ialu_mem_long_reg );
11478 %}
11479
11480
11481 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11482 predicate(UseSSE<=1);
11483 match(Set dst (MoveL2D src));
11484 effect(DEF dst, USE src);
11485 ins_cost(125);
11486
11487 format %{ "FLD_D $src\n\t"
11488 "FSTP $dst\t# MoveL2D_stack_reg" %}
11489 opcode(0xDD); /* DD /0, FLD m64real */
11490 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11491 Pop_Reg_DPR(dst) );
11492 ins_pipe( fpu_reg_mem );
11493 %}
11494
11495
11496 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11497 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11498 match(Set dst (MoveL2D src));
11499 effect(DEF dst, USE src);
11500
11501 ins_cost(95);
11502 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11503 ins_encode %{
11504 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11505 %}
11506 ins_pipe( pipe_slow );
11507 %}
11508
11509 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11510 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11511 match(Set dst (MoveL2D src));
11512 effect(DEF dst, USE src);
11513
11514 ins_cost(95);
11515 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11516 ins_encode %{
11517 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11518 %}
11519 ins_pipe( pipe_slow );
11520 %}
11521
11522 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11523 predicate(UseSSE>=2);
11524 match(Set dst (MoveL2D src));
11525 effect(TEMP dst, USE src, TEMP tmp);
11526 ins_cost(85);
11527 format %{ "MOVD $dst,$src.lo\n\t"
11528 "MOVD $tmp,$src.hi\n\t"
11529 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11530 ins_encode %{
11531 __ movdl($dst$$XMMRegister, $src$$Register);
11532 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11533 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11534 %}
11535 ins_pipe( pipe_slow );
11536 %}
11537
11538
11539 // =======================================================================
11540 // fast clearing of an array
11541 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11542 match(Set dummy (ClearArray cnt base));
11543 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11544 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
11545 "XOR EAX,EAX\n\t"
11546 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11547 opcode(0,0x4);
11548 ins_encode( Opcode(0xD1), RegOpc(ECX),
11549 OpcRegReg(0x33,EAX,EAX),
11550 Opcode(0xF3), Opcode(0xAB) );
11551 ins_pipe( pipe_slow );
11552 %}
11553
11554 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11555 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11556 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11557 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11558
11559 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11560 ins_encode %{
11561 __ string_compare($str1$$Register, $str2$$Register,
11562 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11563 $tmp1$$XMMRegister);
11564 %}
11565 ins_pipe( pipe_slow );
11566 %}
11567
11568 // fast string equals
11569 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11570 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11571 match(Set result (StrEquals (Binary str1 str2) cnt));
11572 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11573
11574 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11575 ins_encode %{
11576 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11577 $cnt$$Register, $result$$Register, $tmp3$$Register,
11578 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11579 %}
11580 ins_pipe( pipe_slow );
11581 %}
11582
11583 // fast search of substring with known size.
11584 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11585 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11586 predicate(UseSSE42Intrinsics);
11587 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11588 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11589
11590 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11591 ins_encode %{
11592 int icnt2 = (int)$int_cnt2$$constant;
11593 if (icnt2 >= 8) {
11594 // IndexOf for constant substrings with size >= 8 elements
11595 // which don't need to be loaded through stack.
11596 __ string_indexofC8($str1$$Register, $str2$$Register,
11597 $cnt1$$Register, $cnt2$$Register,
11598 icnt2, $result$$Register,
11599 $vec$$XMMRegister, $tmp$$Register);
11600 } else {
11601 // Small strings are loaded through stack if they cross page boundary.
11602 __ string_indexof($str1$$Register, $str2$$Register,
11603 $cnt1$$Register, $cnt2$$Register,
11604 icnt2, $result$$Register,
11605 $vec$$XMMRegister, $tmp$$Register);
11606 }
11607 %}
11608 ins_pipe( pipe_slow );
11609 %}
11610
11611 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11612 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11613 predicate(UseSSE42Intrinsics);
11614 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11615 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11616
11617 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11618 ins_encode %{
11619 __ string_indexof($str1$$Register, $str2$$Register,
11620 $cnt1$$Register, $cnt2$$Register,
11621 (-1), $result$$Register,
11622 $vec$$XMMRegister, $tmp$$Register);
11623 %}
11624 ins_pipe( pipe_slow );
11625 %}
11626
11627 // fast array equals
11628 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11629 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11630 %{
11631 match(Set result (AryEq ary1 ary2));
11632 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11633 //ins_cost(300);
11634
11635 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11636 ins_encode %{
11637 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11638 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11639 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11640 %}
11641 ins_pipe( pipe_slow );
11642 %}
11643
11644 //----------Control Flow Instructions------------------------------------------
11645 // Signed compare Instructions
11646 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11647 match(Set cr (CmpI op1 op2));
11648 effect( DEF cr, USE op1, USE op2 );
11649 format %{ "CMP $op1,$op2" %}
11650 opcode(0x3B); /* Opcode 3B /r */
11651 ins_encode( OpcP, RegReg( op1, op2) );
11652 ins_pipe( ialu_cr_reg_reg );
11653 %}
11654
11655 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11656 match(Set cr (CmpI op1 op2));
11657 effect( DEF cr, USE op1 );
11658 format %{ "CMP $op1,$op2" %}
11659 opcode(0x81,0x07); /* Opcode 81 /7 */
11660 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11661 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11662 ins_pipe( ialu_cr_reg_imm );
11663 %}
11664
11665 // Cisc-spilled version of cmpI_eReg
11666 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11667 match(Set cr (CmpI op1 (LoadI op2)));
11668
11669 format %{ "CMP $op1,$op2" %}
11670 ins_cost(500);
11671 opcode(0x3B); /* Opcode 3B /r */
11672 ins_encode( OpcP, RegMem( op1, op2) );
11673 ins_pipe( ialu_cr_reg_mem );
11674 %}
11675
11676 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11677 match(Set cr (CmpI src zero));
11678 effect( DEF cr, USE src );
11679
11680 format %{ "TEST $src,$src" %}
11681 opcode(0x85);
11682 ins_encode( OpcP, RegReg( src, src ) );
11683 ins_pipe( ialu_cr_reg_imm );
11684 %}
11685
11686 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11687 match(Set cr (CmpI (AndI src con) zero));
11688
11689 format %{ "TEST $src,$con" %}
11690 opcode(0xF7,0x00);
11691 ins_encode( OpcP, RegOpc(src), Con32(con) );
11692 ins_pipe( ialu_cr_reg_imm );
11693 %}
11694
11695 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11696 match(Set cr (CmpI (AndI src mem) zero));
11697
11698 format %{ "TEST $src,$mem" %}
11699 opcode(0x85);
11700 ins_encode( OpcP, RegMem( src, mem ) );
11701 ins_pipe( ialu_cr_reg_mem );
11702 %}
11703
11704 // Unsigned compare Instructions; really, same as signed except they
11705 // produce an eFlagsRegU instead of eFlagsReg.
11706 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11707 match(Set cr (CmpU op1 op2));
11708
11709 format %{ "CMPu $op1,$op2" %}
11710 opcode(0x3B); /* Opcode 3B /r */
11711 ins_encode( OpcP, RegReg( op1, op2) );
11712 ins_pipe( ialu_cr_reg_reg );
11713 %}
11714
11715 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11716 match(Set cr (CmpU op1 op2));
11717
11718 format %{ "CMPu $op1,$op2" %}
11719 opcode(0x81,0x07); /* Opcode 81 /7 */
11720 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11721 ins_pipe( ialu_cr_reg_imm );
11722 %}
11723
11724 // // Cisc-spilled version of cmpU_eReg
11725 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11726 match(Set cr (CmpU op1 (LoadI op2)));
11727
11728 format %{ "CMPu $op1,$op2" %}
11729 ins_cost(500);
11730 opcode(0x3B); /* Opcode 3B /r */
11731 ins_encode( OpcP, RegMem( op1, op2) );
11732 ins_pipe( ialu_cr_reg_mem );
11733 %}
11734
11735 // // Cisc-spilled version of cmpU_eReg
11736 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11737 // match(Set cr (CmpU (LoadI op1) op2));
11738 //
11739 // format %{ "CMPu $op1,$op2" %}
11740 // ins_cost(500);
11741 // opcode(0x39); /* Opcode 39 /r */
11742 // ins_encode( OpcP, RegMem( op1, op2) );
11743 //%}
11744
11745 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11746 match(Set cr (CmpU src zero));
11747
11748 format %{ "TESTu $src,$src" %}
11749 opcode(0x85);
11750 ins_encode( OpcP, RegReg( src, src ) );
11751 ins_pipe( ialu_cr_reg_imm );
11752 %}
11753
11754 // Unsigned pointer compare Instructions
11755 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11756 match(Set cr (CmpP op1 op2));
11757
11758 format %{ "CMPu $op1,$op2" %}
11759 opcode(0x3B); /* Opcode 3B /r */
11760 ins_encode( OpcP, RegReg( op1, op2) );
11761 ins_pipe( ialu_cr_reg_reg );
11762 %}
11763
11764 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11765 match(Set cr (CmpP op1 op2));
11766
11767 format %{ "CMPu $op1,$op2" %}
11768 opcode(0x81,0x07); /* Opcode 81 /7 */
11769 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11770 ins_pipe( ialu_cr_reg_imm );
11771 %}
11772
11773 // // Cisc-spilled version of cmpP_eReg
11774 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11775 match(Set cr (CmpP op1 (LoadP op2)));
11776
11777 format %{ "CMPu $op1,$op2" %}
11778 ins_cost(500);
11779 opcode(0x3B); /* Opcode 3B /r */
11780 ins_encode( OpcP, RegMem( op1, op2) );
11781 ins_pipe( ialu_cr_reg_mem );
11782 %}
11783
11784 // // Cisc-spilled version of cmpP_eReg
11785 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11786 // match(Set cr (CmpP (LoadP op1) op2));
11787 //
11788 // format %{ "CMPu $op1,$op2" %}
11789 // ins_cost(500);
11790 // opcode(0x39); /* Opcode 39 /r */
11791 // ins_encode( OpcP, RegMem( op1, op2) );
11792 //%}
11793
11794 // Compare raw pointer (used in out-of-heap check).
11795 // Only works because non-oop pointers must be raw pointers
11796 // and raw pointers have no anti-dependencies.
11797 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11798 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
11799 match(Set cr (CmpP op1 (LoadP op2)));
11800
11801 format %{ "CMPu $op1,$op2" %}
11802 opcode(0x3B); /* Opcode 3B /r */
11803 ins_encode( OpcP, RegMem( op1, op2) );
11804 ins_pipe( ialu_cr_reg_mem );
11805 %}
11806
11807 //
11808 // This will generate a signed flags result. This should be ok
11809 // since any compare to a zero should be eq/neq.
11810 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11811 match(Set cr (CmpP src zero));
11812
11813 format %{ "TEST $src,$src" %}
11814 opcode(0x85);
11815 ins_encode( OpcP, RegReg( src, src ) );
11816 ins_pipe( ialu_cr_reg_imm );
11817 %}
11818
11819 // Cisc-spilled version of testP_reg
11820 // This will generate a signed flags result. This should be ok
11821 // since any compare to a zero should be eq/neq.
11822 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11823 match(Set cr (CmpP (LoadP op) zero));
11824
11825 format %{ "TEST $op,0xFFFFFFFF" %}
11826 ins_cost(500);
11827 opcode(0xF7); /* Opcode F7 /0 */
11828 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11829 ins_pipe( ialu_cr_reg_imm );
11830 %}
11831
11832 // Yanked all unsigned pointer compare operations.
11833 // Pointer compares are done with CmpP which is already unsigned.
11834
11835 //----------Max and Min--------------------------------------------------------
11836 // Min Instructions
11837 ////
11838 // *** Min and Max using the conditional move are slower than the
11839 // *** branch version on a Pentium III.
11840 // // Conditional move for min
11841 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11842 // effect( USE_DEF op2, USE op1, USE cr );
11843 // format %{ "CMOVlt $op2,$op1\t! min" %}
11844 // opcode(0x4C,0x0F);
11845 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11846 // ins_pipe( pipe_cmov_reg );
11847 //%}
11848 //
11849 //// Min Register with Register (P6 version)
11850 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11851 // predicate(VM_Version::supports_cmov() );
11852 // match(Set op2 (MinI op1 op2));
11853 // ins_cost(200);
11854 // expand %{
11855 // eFlagsReg cr;
11856 // compI_eReg(cr,op1,op2);
11857 // cmovI_reg_lt(op2,op1,cr);
11858 // %}
11859 //%}
11860
11861 // Min Register with Register (generic version)
11862 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11863 match(Set dst (MinI dst src));
11864 effect(KILL flags);
11865 ins_cost(300);
11866
11867 format %{ "MIN $dst,$src" %}
11868 opcode(0xCC);
11869 ins_encode( min_enc(dst,src) );
11870 ins_pipe( pipe_slow );
11871 %}
11872
11873 // Max Register with Register
11874 // *** Min and Max using the conditional move are slower than the
11875 // *** branch version on a Pentium III.
11876 // // Conditional move for max
11877 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11878 // effect( USE_DEF op2, USE op1, USE cr );
11879 // format %{ "CMOVgt $op2,$op1\t! max" %}
11880 // opcode(0x4F,0x0F);
11881 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11882 // ins_pipe( pipe_cmov_reg );
11883 //%}
11884 //
11885 // // Max Register with Register (P6 version)
11886 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
11887 // predicate(VM_Version::supports_cmov() );
11888 // match(Set op2 (MaxI op1 op2));
11889 // ins_cost(200);
11890 // expand %{
11891 // eFlagsReg cr;
11892 // compI_eReg(cr,op1,op2);
11893 // cmovI_reg_gt(op2,op1,cr);
11894 // %}
11895 //%}
11896
11897 // Max Register with Register (generic version)
11898 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
11899 match(Set dst (MaxI dst src));
11900 effect(KILL flags);
11901 ins_cost(300);
11902
11903 format %{ "MAX $dst,$src" %}
11904 opcode(0xCC);
11905 ins_encode( max_enc(dst,src) );
11906 ins_pipe( pipe_slow );
11907 %}
11908
11909 // ============================================================================
11910 // Counted Loop limit node which represents exact final iterator value.
11911 // Note: the resulting value should fit into integer range since
11912 // counted loops have limit check on overflow.
11913 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
11914 match(Set limit (LoopLimit (Binary init limit) stride));
11915 effect(TEMP limit_hi, TEMP tmp, KILL flags);
11916 ins_cost(300);
11917
11918 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
11919 ins_encode %{
11920 int strd = (int)$stride$$constant;
11921 assert(strd != 1 && strd != -1, "sanity");
11922 int m1 = (strd > 0) ? 1 : -1;
11923 // Convert limit to long (EAX:EDX)
11924 __ cdql();
11925 // Convert init to long (init:tmp)
11926 __ movl($tmp$$Register, $init$$Register);
11927 __ sarl($tmp$$Register, 31);
11928 // $limit - $init
11929 __ subl($limit$$Register, $init$$Register);
11930 __ sbbl($limit_hi$$Register, $tmp$$Register);
11931 // + ($stride - 1)
11932 if (strd > 0) {
11933 __ addl($limit$$Register, (strd - 1));
11934 __ adcl($limit_hi$$Register, 0);
11935 __ movl($tmp$$Register, strd);
11936 } else {
11937 __ addl($limit$$Register, (strd + 1));
11938 __ adcl($limit_hi$$Register, -1);
11939 __ lneg($limit_hi$$Register, $limit$$Register);
11940 __ movl($tmp$$Register, -strd);
11941 }
11942 // signed devision: (EAX:EDX) / pos_stride
11943 __ idivl($tmp$$Register);
11944 if (strd < 0) {
11945 // restore sign
11946 __ negl($tmp$$Register);
11947 }
11948 // (EAX) * stride
11949 __ mull($tmp$$Register);
11950 // + init (ignore upper bits)
11951 __ addl($limit$$Register, $init$$Register);
11952 %}
11953 ins_pipe( pipe_slow );
11954 %}
11955
11956 // ============================================================================
11957 // Branch Instructions
11958 // Jump Table
11959 instruct jumpXtnd(rRegI switch_val) %{
11960 match(Jump switch_val);
11961 ins_cost(350);
11962 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
11963 ins_encode %{
11964 // Jump to Address(table_base + switch_reg)
11965 Address index(noreg, $switch_val$$Register, Address::times_1);
11966 __ jump(ArrayAddress($constantaddress, index));
11967 %}
11968 ins_pipe(pipe_jmp);
11969 %}
11970
11971 // Jump Direct - Label defines a relative address from JMP+1
11972 instruct jmpDir(label labl) %{
11973 match(Goto);
11974 effect(USE labl);
11975
11976 ins_cost(300);
11977 format %{ "JMP $labl" %}
11978 size(5);
11979 ins_encode %{
11980 Label* L = $labl$$label;
11981 __ jmp(*L, false); // Always long jump
11982 %}
11983 ins_pipe( pipe_jmp );
11984 %}
11985
11986 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11987 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
11988 match(If cop cr);
11989 effect(USE labl);
11990
11991 ins_cost(300);
11992 format %{ "J$cop $labl" %}
11993 size(6);
11994 ins_encode %{
11995 Label* L = $labl$$label;
11996 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11997 %}
11998 ins_pipe( pipe_jcc );
11999 %}
12000
12001 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12002 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12003 match(CountedLoopEnd cop cr);
12004 effect(USE labl);
12005
12006 ins_cost(300);
12007 format %{ "J$cop $labl\t# Loop end" %}
12008 size(6);
12009 ins_encode %{
12010 Label* L = $labl$$label;
12011 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12012 %}
12013 ins_pipe( pipe_jcc );
12014 %}
12015
12016 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12017 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12018 match(CountedLoopEnd cop cmp);
12019 effect(USE labl);
12020
12021 ins_cost(300);
12022 format %{ "J$cop,u $labl\t# Loop end" %}
12023 size(6);
12024 ins_encode %{
12025 Label* L = $labl$$label;
12026 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12027 %}
12028 ins_pipe( pipe_jcc );
12029 %}
12030
12031 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12032 match(CountedLoopEnd cop cmp);
12033 effect(USE labl);
12034
12035 ins_cost(200);
12036 format %{ "J$cop,u $labl\t# Loop end" %}
12037 size(6);
12038 ins_encode %{
12039 Label* L = $labl$$label;
12040 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12041 %}
12042 ins_pipe( pipe_jcc );
12043 %}
12044
12045 // Jump Direct Conditional - using unsigned comparison
12046 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12047 match(If cop cmp);
12048 effect(USE labl);
12049
12050 ins_cost(300);
12051 format %{ "J$cop,u $labl" %}
12052 size(6);
12053 ins_encode %{
12054 Label* L = $labl$$label;
12055 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12056 %}
12057 ins_pipe(pipe_jcc);
12058 %}
12059
12060 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12061 match(If cop cmp);
12062 effect(USE labl);
12063
12064 ins_cost(200);
12065 format %{ "J$cop,u $labl" %}
12066 size(6);
12067 ins_encode %{
12068 Label* L = $labl$$label;
12069 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12070 %}
12071 ins_pipe(pipe_jcc);
12072 %}
12073
12074 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12075 match(If cop cmp);
12076 effect(USE labl);
12077
12078 ins_cost(200);
12079 format %{ $$template
12080 if ($cop$$cmpcode == Assembler::notEqual) {
12081 $$emit$$"JP,u $labl\n\t"
12082 $$emit$$"J$cop,u $labl"
12083 } else {
12084 $$emit$$"JP,u done\n\t"
12085 $$emit$$"J$cop,u $labl\n\t"
12086 $$emit$$"done:"
12087 }
12088 %}
12089 ins_encode %{
12090 Label* l = $labl$$label;
12091 if ($cop$$cmpcode == Assembler::notEqual) {
12092 __ jcc(Assembler::parity, *l, false);
12093 __ jcc(Assembler::notEqual, *l, false);
12094 } else if ($cop$$cmpcode == Assembler::equal) {
12095 Label done;
12096 __ jccb(Assembler::parity, done);
12097 __ jcc(Assembler::equal, *l, false);
12098 __ bind(done);
12099 } else {
12100 ShouldNotReachHere();
12101 }
12102 %}
12103 ins_pipe(pipe_jcc);
12104 %}
12105
12106 // ============================================================================
12107 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12108 // array for an instance of the superklass. Set a hidden internal cache on a
12109 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12110 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12111 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12112 match(Set result (PartialSubtypeCheck sub super));
12113 effect( KILL rcx, KILL cr );
12114
12115 ins_cost(1100); // slightly larger than the next version
12116 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12117 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12118 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12119 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12120 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12121 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12122 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12123 "miss:\t" %}
12124
12125 opcode(0x1); // Force a XOR of EDI
12126 ins_encode( enc_PartialSubtypeCheck() );
12127 ins_pipe( pipe_slow );
12128 %}
12129
12130 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12131 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12132 effect( KILL rcx, KILL result );
12133
12134 ins_cost(1000);
12135 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12136 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12137 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12138 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12139 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12140 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12141 "miss:\t" %}
12142
12143 opcode(0x0); // No need to XOR EDI
12144 ins_encode( enc_PartialSubtypeCheck() );
12145 ins_pipe( pipe_slow );
12146 %}
12147
12148 // ============================================================================
12149 // Branch Instructions -- short offset versions
12150 //
12151 // These instructions are used to replace jumps of a long offset (the default
12152 // match) with jumps of a shorter offset. These instructions are all tagged
12153 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12154 // match rules in general matching. Instead, the ADLC generates a conversion
12155 // method in the MachNode which can be used to do in-place replacement of the
12156 // long variant with the shorter variant. The compiler will determine if a
12157 // branch can be taken by the is_short_branch_offset() predicate in the machine
12158 // specific code section of the file.
12159
12160 // Jump Direct - Label defines a relative address from JMP+1
12161 instruct jmpDir_short(label labl) %{
12162 match(Goto);
12163 effect(USE labl);
12164
12165 ins_cost(300);
12166 format %{ "JMP,s $labl" %}
12167 size(2);
12168 ins_encode %{
12169 Label* L = $labl$$label;
12170 __ jmpb(*L);
12171 %}
12172 ins_pipe( pipe_jmp );
12173 ins_short_branch(1);
12174 %}
12175
12176 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12177 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12178 match(If cop cr);
12179 effect(USE labl);
12180
12181 ins_cost(300);
12182 format %{ "J$cop,s $labl" %}
12183 size(2);
12184 ins_encode %{
12185 Label* L = $labl$$label;
12186 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12187 %}
12188 ins_pipe( pipe_jcc );
12189 ins_short_branch(1);
12190 %}
12191
12192 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12193 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12194 match(CountedLoopEnd cop cr);
12195 effect(USE labl);
12196
12197 ins_cost(300);
12198 format %{ "J$cop,s $labl\t# Loop end" %}
12199 size(2);
12200 ins_encode %{
12201 Label* L = $labl$$label;
12202 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12203 %}
12204 ins_pipe( pipe_jcc );
12205 ins_short_branch(1);
12206 %}
12207
12208 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12209 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12210 match(CountedLoopEnd cop cmp);
12211 effect(USE labl);
12212
12213 ins_cost(300);
12214 format %{ "J$cop,us $labl\t# Loop end" %}
12215 size(2);
12216 ins_encode %{
12217 Label* L = $labl$$label;
12218 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12219 %}
12220 ins_pipe( pipe_jcc );
12221 ins_short_branch(1);
12222 %}
12223
12224 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12225 match(CountedLoopEnd cop cmp);
12226 effect(USE labl);
12227
12228 ins_cost(300);
12229 format %{ "J$cop,us $labl\t# Loop end" %}
12230 size(2);
12231 ins_encode %{
12232 Label* L = $labl$$label;
12233 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12234 %}
12235 ins_pipe( pipe_jcc );
12236 ins_short_branch(1);
12237 %}
12238
12239 // Jump Direct Conditional - using unsigned comparison
12240 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12241 match(If cop cmp);
12242 effect(USE labl);
12243
12244 ins_cost(300);
12245 format %{ "J$cop,us $labl" %}
12246 size(2);
12247 ins_encode %{
12248 Label* L = $labl$$label;
12249 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12250 %}
12251 ins_pipe( pipe_jcc );
12252 ins_short_branch(1);
12253 %}
12254
12255 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12256 match(If cop cmp);
12257 effect(USE labl);
12258
12259 ins_cost(300);
12260 format %{ "J$cop,us $labl" %}
12261 size(2);
12262 ins_encode %{
12263 Label* L = $labl$$label;
12264 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12265 %}
12266 ins_pipe( pipe_jcc );
12267 ins_short_branch(1);
12268 %}
12269
12270 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12271 match(If cop cmp);
12272 effect(USE labl);
12273
12274 ins_cost(300);
12275 format %{ $$template
12276 if ($cop$$cmpcode == Assembler::notEqual) {
12277 $$emit$$"JP,u,s $labl\n\t"
12278 $$emit$$"J$cop,u,s $labl"
12279 } else {
12280 $$emit$$"JP,u,s done\n\t"
12281 $$emit$$"J$cop,u,s $labl\n\t"
12282 $$emit$$"done:"
12283 }
12284 %}
12285 size(4);
12286 ins_encode %{
12287 Label* l = $labl$$label;
12288 if ($cop$$cmpcode == Assembler::notEqual) {
12289 __ jccb(Assembler::parity, *l);
12290 __ jccb(Assembler::notEqual, *l);
12291 } else if ($cop$$cmpcode == Assembler::equal) {
12292 Label done;
12293 __ jccb(Assembler::parity, done);
12294 __ jccb(Assembler::equal, *l);
12295 __ bind(done);
12296 } else {
12297 ShouldNotReachHere();
12298 }
12299 %}
12300 ins_pipe(pipe_jcc);
12301 ins_short_branch(1);
12302 %}
12303
12304 // ============================================================================
12305 // Long Compare
12306 //
12307 // Currently we hold longs in 2 registers. Comparing such values efficiently
12308 // is tricky. The flavor of compare used depends on whether we are testing
12309 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12310 // The GE test is the negated LT test. The LE test can be had by commuting
12311 // the operands (yielding a GE test) and then negating; negate again for the
12312 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12313 // NE test is negated from that.
12314
12315 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12316 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12317 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12318 // are collapsed internally in the ADLC's dfa-gen code. The match for
12319 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12320 // foo match ends up with the wrong leaf. One fix is to not match both
12321 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12322 // both forms beat the trinary form of long-compare and both are very useful
12323 // on Intel which has so few registers.
12324
12325 // Manifest a CmpL result in an integer register. Very painful.
12326 // This is the test to avoid.
12327 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12328 match(Set dst (CmpL3 src1 src2));
12329 effect( KILL flags );
12330 ins_cost(1000);
12331 format %{ "XOR $dst,$dst\n\t"
12332 "CMP $src1.hi,$src2.hi\n\t"
12333 "JLT,s m_one\n\t"
12334 "JGT,s p_one\n\t"
12335 "CMP $src1.lo,$src2.lo\n\t"
12336 "JB,s m_one\n\t"
12337 "JEQ,s done\n"
12338 "p_one:\tINC $dst\n\t"
12339 "JMP,s done\n"
12340 "m_one:\tDEC $dst\n"
12341 "done:" %}
12342 ins_encode %{
12343 Label p_one, m_one, done;
12344 __ xorptr($dst$$Register, $dst$$Register);
12345 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12346 __ jccb(Assembler::less, m_one);
12347 __ jccb(Assembler::greater, p_one);
12348 __ cmpl($src1$$Register, $src2$$Register);
12349 __ jccb(Assembler::below, m_one);
12350 __ jccb(Assembler::equal, done);
12351 __ bind(p_one);
12352 __ incrementl($dst$$Register);
12353 __ jmpb(done);
12354 __ bind(m_one);
12355 __ decrementl($dst$$Register);
12356 __ bind(done);
12357 %}
12358 ins_pipe( pipe_slow );
12359 %}
12360
12361 //======
12362 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12363 // compares. Can be used for LE or GT compares by reversing arguments.
12364 // NOT GOOD FOR EQ/NE tests.
12365 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12366 match( Set flags (CmpL src zero ));
12367 ins_cost(100);
12368 format %{ "TEST $src.hi,$src.hi" %}
12369 opcode(0x85);
12370 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12371 ins_pipe( ialu_cr_reg_reg );
12372 %}
12373
12374 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12375 // compares. Can be used for LE or GT compares by reversing arguments.
12376 // NOT GOOD FOR EQ/NE tests.
12377 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12378 match( Set flags (CmpL src1 src2 ));
12379 effect( TEMP tmp );
12380 ins_cost(300);
12381 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12382 "MOV $tmp,$src1.hi\n\t"
12383 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12384 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12385 ins_pipe( ialu_cr_reg_reg );
12386 %}
12387
12388 // Long compares reg < zero/req OR reg >= zero/req.
12389 // Just a wrapper for a normal branch, plus the predicate test.
12390 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12391 match(If cmp flags);
12392 effect(USE labl);
12393 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12394 expand %{
12395 jmpCon(cmp,flags,labl); // JLT or JGE...
12396 %}
12397 %}
12398
12399 // Compare 2 longs and CMOVE longs.
12400 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12401 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12402 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12403 ins_cost(400);
12404 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12405 "CMOV$cmp $dst.hi,$src.hi" %}
12406 opcode(0x0F,0x40);
12407 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12408 ins_pipe( pipe_cmov_reg_long );
12409 %}
12410
12411 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12412 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12413 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12414 ins_cost(500);
12415 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12416 "CMOV$cmp $dst.hi,$src.hi" %}
12417 opcode(0x0F,0x40);
12418 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12419 ins_pipe( pipe_cmov_reg_long );
12420 %}
12421
12422 // Compare 2 longs and CMOVE ints.
12423 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12424 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12425 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12426 ins_cost(200);
12427 format %{ "CMOV$cmp $dst,$src" %}
12428 opcode(0x0F,0x40);
12429 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12430 ins_pipe( pipe_cmov_reg );
12431 %}
12432
12433 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12434 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12435 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12436 ins_cost(250);
12437 format %{ "CMOV$cmp $dst,$src" %}
12438 opcode(0x0F,0x40);
12439 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12440 ins_pipe( pipe_cmov_mem );
12441 %}
12442
12443 // Compare 2 longs and CMOVE ints.
12444 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12445 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12446 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12447 ins_cost(200);
12448 format %{ "CMOV$cmp $dst,$src" %}
12449 opcode(0x0F,0x40);
12450 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12451 ins_pipe( pipe_cmov_reg );
12452 %}
12453
12454 // Compare 2 longs and CMOVE doubles
12455 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12456 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12457 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12458 ins_cost(200);
12459 expand %{
12460 fcmovDPR_regS(cmp,flags,dst,src);
12461 %}
12462 %}
12463
12464 // Compare 2 longs and CMOVE doubles
12465 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12466 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12467 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12468 ins_cost(200);
12469 expand %{
12470 fcmovD_regS(cmp,flags,dst,src);
12471 %}
12472 %}
12473
12474 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12475 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12476 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12477 ins_cost(200);
12478 expand %{
12479 fcmovFPR_regS(cmp,flags,dst,src);
12480 %}
12481 %}
12482
12483 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12484 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12485 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12486 ins_cost(200);
12487 expand %{
12488 fcmovF_regS(cmp,flags,dst,src);
12489 %}
12490 %}
12491
12492 //======
12493 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12494 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12495 match( Set flags (CmpL src zero ));
12496 effect(TEMP tmp);
12497 ins_cost(200);
12498 format %{ "MOV $tmp,$src.lo\n\t"
12499 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12500 ins_encode( long_cmp_flags0( src, tmp ) );
12501 ins_pipe( ialu_reg_reg_long );
12502 %}
12503
12504 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12505 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12506 match( Set flags (CmpL src1 src2 ));
12507 ins_cost(200+300);
12508 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12509 "JNE,s skip\n\t"
12510 "CMP $src1.hi,$src2.hi\n\t"
12511 "skip:\t" %}
12512 ins_encode( long_cmp_flags1( src1, src2 ) );
12513 ins_pipe( ialu_cr_reg_reg );
12514 %}
12515
12516 // Long compare reg == zero/reg OR reg != zero/reg
12517 // Just a wrapper for a normal branch, plus the predicate test.
12518 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12519 match(If cmp flags);
12520 effect(USE labl);
12521 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12522 expand %{
12523 jmpCon(cmp,flags,labl); // JEQ or JNE...
12524 %}
12525 %}
12526
12527 // Compare 2 longs and CMOVE longs.
12528 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12529 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12530 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12531 ins_cost(400);
12532 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12533 "CMOV$cmp $dst.hi,$src.hi" %}
12534 opcode(0x0F,0x40);
12535 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12536 ins_pipe( pipe_cmov_reg_long );
12537 %}
12538
12539 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12540 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12541 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12542 ins_cost(500);
12543 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12544 "CMOV$cmp $dst.hi,$src.hi" %}
12545 opcode(0x0F,0x40);
12546 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12547 ins_pipe( pipe_cmov_reg_long );
12548 %}
12549
12550 // Compare 2 longs and CMOVE ints.
12551 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12552 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12553 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12554 ins_cost(200);
12555 format %{ "CMOV$cmp $dst,$src" %}
12556 opcode(0x0F,0x40);
12557 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12558 ins_pipe( pipe_cmov_reg );
12559 %}
12560
12561 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12562 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12563 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12564 ins_cost(250);
12565 format %{ "CMOV$cmp $dst,$src" %}
12566 opcode(0x0F,0x40);
12567 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12568 ins_pipe( pipe_cmov_mem );
12569 %}
12570
12571 // Compare 2 longs and CMOVE ints.
12572 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12573 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12574 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12575 ins_cost(200);
12576 format %{ "CMOV$cmp $dst,$src" %}
12577 opcode(0x0F,0x40);
12578 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12579 ins_pipe( pipe_cmov_reg );
12580 %}
12581
12582 // Compare 2 longs and CMOVE doubles
12583 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12584 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12585 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12586 ins_cost(200);
12587 expand %{
12588 fcmovDPR_regS(cmp,flags,dst,src);
12589 %}
12590 %}
12591
12592 // Compare 2 longs and CMOVE doubles
12593 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12594 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12595 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12596 ins_cost(200);
12597 expand %{
12598 fcmovD_regS(cmp,flags,dst,src);
12599 %}
12600 %}
12601
12602 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12603 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12604 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12605 ins_cost(200);
12606 expand %{
12607 fcmovFPR_regS(cmp,flags,dst,src);
12608 %}
12609 %}
12610
12611 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12612 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12613 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12614 ins_cost(200);
12615 expand %{
12616 fcmovF_regS(cmp,flags,dst,src);
12617 %}
12618 %}
12619
12620 //======
12621 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12622 // Same as cmpL_reg_flags_LEGT except must negate src
12623 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12624 match( Set flags (CmpL src zero ));
12625 effect( TEMP tmp );
12626 ins_cost(300);
12627 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12628 "CMP $tmp,$src.lo\n\t"
12629 "SBB $tmp,$src.hi\n\t" %}
12630 ins_encode( long_cmp_flags3(src, tmp) );
12631 ins_pipe( ialu_reg_reg_long );
12632 %}
12633
12634 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12635 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12636 // requires a commuted test to get the same result.
12637 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12638 match( Set flags (CmpL src1 src2 ));
12639 effect( TEMP tmp );
12640 ins_cost(300);
12641 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12642 "MOV $tmp,$src2.hi\n\t"
12643 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12644 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12645 ins_pipe( ialu_cr_reg_reg );
12646 %}
12647
12648 // Long compares reg < zero/req OR reg >= zero/req.
12649 // Just a wrapper for a normal branch, plus the predicate test
12650 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12651 match(If cmp flags);
12652 effect(USE labl);
12653 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12654 ins_cost(300);
12655 expand %{
12656 jmpCon(cmp,flags,labl); // JGT or JLE...
12657 %}
12658 %}
12659
12660 // Compare 2 longs and CMOVE longs.
12661 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12662 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12663 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12664 ins_cost(400);
12665 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12666 "CMOV$cmp $dst.hi,$src.hi" %}
12667 opcode(0x0F,0x40);
12668 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12669 ins_pipe( pipe_cmov_reg_long );
12670 %}
12671
12672 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12673 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12674 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12675 ins_cost(500);
12676 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12677 "CMOV$cmp $dst.hi,$src.hi+4" %}
12678 opcode(0x0F,0x40);
12679 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12680 ins_pipe( pipe_cmov_reg_long );
12681 %}
12682
12683 // Compare 2 longs and CMOVE ints.
12684 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12685 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12686 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12687 ins_cost(200);
12688 format %{ "CMOV$cmp $dst,$src" %}
12689 opcode(0x0F,0x40);
12690 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12691 ins_pipe( pipe_cmov_reg );
12692 %}
12693
12694 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12695 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12696 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12697 ins_cost(250);
12698 format %{ "CMOV$cmp $dst,$src" %}
12699 opcode(0x0F,0x40);
12700 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12701 ins_pipe( pipe_cmov_mem );
12702 %}
12703
12704 // Compare 2 longs and CMOVE ptrs.
12705 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12706 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12707 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12708 ins_cost(200);
12709 format %{ "CMOV$cmp $dst,$src" %}
12710 opcode(0x0F,0x40);
12711 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12712 ins_pipe( pipe_cmov_reg );
12713 %}
12714
12715 // Compare 2 longs and CMOVE doubles
12716 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12717 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12718 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12719 ins_cost(200);
12720 expand %{
12721 fcmovDPR_regS(cmp,flags,dst,src);
12722 %}
12723 %}
12724
12725 // Compare 2 longs and CMOVE doubles
12726 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12727 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12728 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12729 ins_cost(200);
12730 expand %{
12731 fcmovD_regS(cmp,flags,dst,src);
12732 %}
12733 %}
12734
12735 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12736 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12737 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12738 ins_cost(200);
12739 expand %{
12740 fcmovFPR_regS(cmp,flags,dst,src);
12741 %}
12742 %}
12743
12744
12745 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12746 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12747 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12748 ins_cost(200);
12749 expand %{
12750 fcmovF_regS(cmp,flags,dst,src);
12751 %}
12752 %}
12753
12754
12755 // ============================================================================
12756 // Procedure Call/Return Instructions
12757 // Call Java Static Instruction
12758 // Note: If this code changes, the corresponding ret_addr_offset() and
12759 // compute_padding() functions will have to be adjusted.
12760 instruct CallStaticJavaDirect(method meth) %{
12761 match(CallStaticJava);
12762 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
12763 effect(USE meth);
12764
12765 ins_cost(300);
12766 format %{ "CALL,static " %}
12767 opcode(0xE8); /* E8 cd */
12768 ins_encode( pre_call_FPU,
12769 Java_Static_Call( meth ),
12770 call_epilog,
12771 post_call_FPU );
12772 ins_pipe( pipe_slow );
12773 ins_alignment(4);
12774 %}
12775
12776 // Call Java Static Instruction (method handle version)
12777 // Note: If this code changes, the corresponding ret_addr_offset() and
12778 // compute_padding() functions will have to be adjusted.
12779 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
12780 match(CallStaticJava);
12781 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
12782 effect(USE meth);
12783 // EBP is saved by all callees (for interpreter stack correction).
12784 // We use it here for a similar purpose, in {preserve,restore}_SP.
12785
12786 ins_cost(300);
12787 format %{ "CALL,static/MethodHandle " %}
12788 opcode(0xE8); /* E8 cd */
12789 ins_encode( pre_call_FPU,
12790 preserve_SP,
12791 Java_Static_Call( meth ),
12792 restore_SP,
12793 call_epilog,
12794 post_call_FPU );
12795 ins_pipe( pipe_slow );
12796 ins_alignment(4);
12797 %}
12798
12799 // Call Java Dynamic Instruction
12800 // Note: If this code changes, the corresponding ret_addr_offset() and
12801 // compute_padding() functions will have to be adjusted.
12802 instruct CallDynamicJavaDirect(method meth) %{
12803 match(CallDynamicJava);
12804 effect(USE meth);
12805
12806 ins_cost(300);
12807 format %{ "MOV EAX,(oop)-1\n\t"
12808 "CALL,dynamic" %}
12809 opcode(0xE8); /* E8 cd */
12810 ins_encode( pre_call_FPU,
12811 Java_Dynamic_Call( meth ),
12812 call_epilog,
12813 post_call_FPU );
12814 ins_pipe( pipe_slow );
12815 ins_alignment(4);
12816 %}
12817
12818 // Call Runtime Instruction
12819 instruct CallRuntimeDirect(method meth) %{
12820 match(CallRuntime );
12821 effect(USE meth);
12822
12823 ins_cost(300);
12824 format %{ "CALL,runtime " %}
12825 opcode(0xE8); /* E8 cd */
12826 // Use FFREEs to clear entries in float stack
12827 ins_encode( pre_call_FPU,
12828 FFree_Float_Stack_All,
12829 Java_To_Runtime( meth ),
12830 post_call_FPU );
12831 ins_pipe( pipe_slow );
12832 %}
12833
12834 // Call runtime without safepoint
12835 instruct CallLeafDirect(method meth) %{
12836 match(CallLeaf);
12837 effect(USE meth);
12838
12839 ins_cost(300);
12840 format %{ "CALL_LEAF,runtime " %}
12841 opcode(0xE8); /* E8 cd */
12842 ins_encode( pre_call_FPU,
12843 FFree_Float_Stack_All,
12844 Java_To_Runtime( meth ),
12845 Verify_FPU_For_Leaf, post_call_FPU );
12846 ins_pipe( pipe_slow );
12847 %}
12848
12849 instruct CallLeafNoFPDirect(method meth) %{
12850 match(CallLeafNoFP);
12851 effect(USE meth);
12852
12853 ins_cost(300);
12854 format %{ "CALL_LEAF_NOFP,runtime " %}
12855 opcode(0xE8); /* E8 cd */
12856 ins_encode(Java_To_Runtime(meth));
12857 ins_pipe( pipe_slow );
12858 %}
12859
12860
12861 // Return Instruction
12862 // Remove the return address & jump to it.
12863 instruct Ret() %{
12864 match(Return);
12865 format %{ "RET" %}
12866 opcode(0xC3);
12867 ins_encode(OpcP);
12868 ins_pipe( pipe_jmp );
12869 %}
12870
12871 // Tail Call; Jump from runtime stub to Java code.
12872 // Also known as an 'interprocedural jump'.
12873 // Target of jump will eventually return to caller.
12874 // TailJump below removes the return address.
12875 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12876 match(TailCall jump_target method_oop );
12877 ins_cost(300);
12878 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12879 opcode(0xFF, 0x4); /* Opcode FF /4 */
12880 ins_encode( OpcP, RegOpc(jump_target) );
12881 ins_pipe( pipe_jmp );
12882 %}
12883
12884
12885 // Tail Jump; remove the return address; jump to target.
12886 // TailCall above leaves the return address around.
12887 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12888 match( TailJump jump_target ex_oop );
12889 ins_cost(300);
12890 format %{ "POP EDX\t# pop return address into dummy\n\t"
12891 "JMP $jump_target " %}
12892 opcode(0xFF, 0x4); /* Opcode FF /4 */
12893 ins_encode( enc_pop_rdx,
12894 OpcP, RegOpc(jump_target) );
12895 ins_pipe( pipe_jmp );
12896 %}
12897
12898 // Create exception oop: created by stack-crawling runtime code.
12899 // Created exception is now available to this handler, and is setup
12900 // just prior to jumping to this handler. No code emitted.
12901 instruct CreateException( eAXRegP ex_oop )
12902 %{
12903 match(Set ex_oop (CreateEx));
12904
12905 size(0);
12906 // use the following format syntax
12907 format %{ "# exception oop is in EAX; no code emitted" %}
12908 ins_encode();
12909 ins_pipe( empty );
12910 %}
12911
12912
12913 // Rethrow exception:
12914 // The exception oop will come in the first argument position.
12915 // Then JUMP (not call) to the rethrow stub code.
12916 instruct RethrowException()
12917 %{
12918 match(Rethrow);
12919
12920 // use the following format syntax
12921 format %{ "JMP rethrow_stub" %}
12922 ins_encode(enc_rethrow);
12923 ins_pipe( pipe_jmp );
12924 %}
12925
12926 // inlined locking and unlocking
12927
12928
12929 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
12930 match( Set cr (FastLock object box) );
12931 effect( TEMP tmp, TEMP scr, USE_KILL box );
12932 ins_cost(300);
12933 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
12934 ins_encode( Fast_Lock(object,box,tmp,scr) );
12935 ins_pipe( pipe_slow );
12936 %}
12937
12938 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12939 match( Set cr (FastUnlock object box) );
12940 effect( TEMP tmp, USE_KILL box );
12941 ins_cost(300);
12942 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
12943 ins_encode( Fast_Unlock(object,box,tmp) );
12944 ins_pipe( pipe_slow );
12945 %}
12946
12947
12948
12949 // ============================================================================
12950 // Safepoint Instruction
12951 instruct safePoint_poll(eFlagsReg cr) %{
12952 match(SafePoint);
12953 effect(KILL cr);
12954
12955 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
12956 // On SPARC that might be acceptable as we can generate the address with
12957 // just a sethi, saving an or. By polling at offset 0 we can end up
12958 // putting additional pressure on the index-0 in the D$. Because of
12959 // alignment (just like the situation at hand) the lower indices tend
12960 // to see more traffic. It'd be better to change the polling address
12961 // to offset 0 of the last $line in the polling page.
12962
12963 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
12964 ins_cost(125);
12965 size(6) ;
12966 ins_encode( Safepoint_Poll() );
12967 ins_pipe( ialu_reg_mem );
12968 %}
12969
12970
12971 // ============================================================================
12972 // This name is KNOWN by the ADLC and cannot be changed.
12973 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12974 // for this guy.
12975 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
12976 match(Set dst (ThreadLocal));
12977 effect(DEF dst, KILL cr);
12978
12979 format %{ "MOV $dst, Thread::current()" %}
12980 ins_encode %{
12981 Register dstReg = as_Register($dst$$reg);
12982 __ get_thread(dstReg);
12983 %}
12984 ins_pipe( ialu_reg_fat );
12985 %}
12986
12987
12988
12989 //----------PEEPHOLE RULES-----------------------------------------------------
12990 // These must follow all instruction definitions as they use the names
12991 // defined in the instructions definitions.
12992 //
12993 // peepmatch ( root_instr_name [preceding_instruction]* );
12994 //
12995 // peepconstraint %{
12996 // (instruction_number.operand_name relational_op instruction_number.operand_name
12997 // [, ...] );
12998 // // instruction numbers are zero-based using left to right order in peepmatch
12999 //
13000 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13001 // // provide an instruction_number.operand_name for each operand that appears
13002 // // in the replacement instruction's match rule
13003 //
13004 // ---------VM FLAGS---------------------------------------------------------
13005 //
13006 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13007 //
13008 // Each peephole rule is given an identifying number starting with zero and
13009 // increasing by one in the order seen by the parser. An individual peephole
13010 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13011 // on the command-line.
13012 //
13013 // ---------CURRENT LIMITATIONS----------------------------------------------
13014 //
13015 // Only match adjacent instructions in same basic block
13016 // Only equality constraints
13017 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13018 // Only one replacement instruction
13019 //
13020 // ---------EXAMPLE----------------------------------------------------------
13021 //
13022 // // pertinent parts of existing instructions in architecture description
13023 // instruct movI(rRegI dst, rRegI src) %{
13024 // match(Set dst (CopyI src));
13025 // %}
13026 //
13027 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13028 // match(Set dst (AddI dst src));
13029 // effect(KILL cr);
13030 // %}
13031 //
13032 // // Change (inc mov) to lea
13033 // peephole %{
13034 // // increment preceeded by register-register move
13035 // peepmatch ( incI_eReg movI );
13036 // // require that the destination register of the increment
13037 // // match the destination register of the move
13038 // peepconstraint ( 0.dst == 1.dst );
13039 // // construct a replacement instruction that sets
13040 // // the destination to ( move's source register + one )
13041 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13042 // %}
13043 //
13044 // Implementation no longer uses movX instructions since
13045 // machine-independent system no longer uses CopyX nodes.
13046 //
13047 // peephole %{
13048 // peepmatch ( incI_eReg movI );
13049 // peepconstraint ( 0.dst == 1.dst );
13050 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13051 // %}
13052 //
13053 // peephole %{
13054 // peepmatch ( decI_eReg movI );
13055 // peepconstraint ( 0.dst == 1.dst );
13056 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13057 // %}
13058 //
13059 // peephole %{
13060 // peepmatch ( addI_eReg_imm movI );
13061 // peepconstraint ( 0.dst == 1.dst );
13062 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13063 // %}
13064 //
13065 // peephole %{
13066 // peepmatch ( addP_eReg_imm movP );
13067 // peepconstraint ( 0.dst == 1.dst );
13068 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13069 // %}
13070
13071 // // Change load of spilled value to only a spill
13072 // instruct storeI(memory mem, rRegI src) %{
13073 // match(Set mem (StoreI mem src));
13074 // %}
13075 //
13076 // instruct loadI(rRegI dst, memory mem) %{
13077 // match(Set dst (LoadI mem));
13078 // %}
13079 //
13080 peephole %{
13081 peepmatch ( loadI storeI );
13082 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13083 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13084 %}
13085
13086 //----------SMARTSPILL RULES---------------------------------------------------
13087 // These must follow all instruction definitions as they use the names
13088 // defined in the instructions definitions.