*** old/src/cpu/x86/vm/x86_64.ad	Thu Jul 26 18:06:25 2012
--- new/src/cpu/x86/vm/x86_64.ad	Thu Jul 26 18:06:25 2012

*** 1511,1536 ****
--- 1511,1520 ----
    assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
    __ end_a_stub();
    return offset;
  }
  
  
  const bool Matcher::match_rule_supported(int opcode) {
    if (!has_match_rule(opcode))
      return false;
  
    switch (opcode) {
      case Op_PopCountI:
      case Op_PopCountL:
        if (!UsePopCountInstruction)
          return false;
      break;
    }
  
    return true;  // Per default match rules are supported.
  }
  
  int Matcher::regnum_to_fpu_offset(int regnum)
  {
    return regnum - 32; // The FP registers are in the second chunk
  }
  

*** 10047,10061 ****
--- 10031,10044 ----
      __ movdq($dst$$Register, $src$$XMMRegister);
    %}
    ins_pipe( pipe_slow );
  %}
  
  // The next instructions have long latency and use Int unit. Set high cost.
  instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
    match(Set dst (MoveI2F src));
    effect(DEF dst, USE src);
!   ins_cost(300);
!   ins_cost(100);
    format %{ "movd    $dst,$src\t# MoveI2F" %}
    ins_encode %{
      __ movdl($dst$$XMMRegister, $src$$Register);
    %}
    ins_pipe( pipe_slow );

*** 10062,10072 ****
--- 10045,10055 ----
  %}
  
  instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
    match(Set dst (MoveL2D src));
    effect(DEF dst, USE src);
!   ins_cost(300);
!   ins_cost(100);
    format %{ "movd    $dst,$src\t# MoveL2D" %}
    ins_encode %{
       __ movdq($dst$$XMMRegister, $src$$Register);
    %}
    ins_pipe( pipe_slow );