1 /*
2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 #include "incls/_precompiled.incl"
26 #include "incls/_matcher.cpp.incl"
27
28 OptoReg::Name OptoReg::c_frame_pointer;
29
30
31
32 const int Matcher::base2reg[Type::lastype] = {
33 Node::NotAMachineReg,0,0, Op_RegI, Op_RegL, 0, Op_RegN,
34 Node::NotAMachineReg, Node::NotAMachineReg, /* tuple, array */
35 Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, /* the pointers */
36 0, 0/*abio*/,
37 Op_RegP /* Return address */, 0, /* the memories */
38 Op_RegF, Op_RegF, Op_RegF, Op_RegD, Op_RegD, Op_RegD,
39 0 /*bottom*/
40 };
41
42 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
43 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
44 RegMask Matcher::STACK_ONLY_mask;
45 RegMask Matcher::c_frame_ptr_mask;
46 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
47 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
48
49 //---------------------------Matcher-------------------------------------------
50 Matcher::Matcher( Node_List &proj_list ) :
51 PhaseTransform( Phase::Ins_Select ),
52 #ifdef ASSERT
53 _old2new_map(C->comp_arena()),
54 _new2old_map(C->comp_arena()),
55 #endif
56 _shared_nodes(C->comp_arena()),
57 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
58 _swallowed(swallowed),
59 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
60 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
61 _must_clone(must_clone), _proj_list(proj_list),
62 _register_save_policy(register_save_policy),
63 _c_reg_save_policy(c_reg_save_policy),
64 _register_save_type(register_save_type),
65 _ruleName(ruleName),
66 _allocation_started(false),
67 _states_arena(Chunk::medium_size),
68 _visited(&_states_arena),
69 _shared(&_states_arena),
70 _dontcare(&_states_arena) {
71 C->set_matcher(this);
72
73 idealreg2spillmask[Op_RegI] = NULL;
74 idealreg2spillmask[Op_RegN] = NULL;
75 idealreg2spillmask[Op_RegL] = NULL;
76 idealreg2spillmask[Op_RegF] = NULL;
77 idealreg2spillmask[Op_RegD] = NULL;
78 idealreg2spillmask[Op_RegP] = NULL;
79
80 idealreg2debugmask[Op_RegI] = NULL;
81 idealreg2debugmask[Op_RegN] = NULL;
82 idealreg2debugmask[Op_RegL] = NULL;
83 idealreg2debugmask[Op_RegF] = NULL;
84 idealreg2debugmask[Op_RegD] = NULL;
85 idealreg2debugmask[Op_RegP] = NULL;
86 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
87 }
88
89 //------------------------------warp_incoming_stk_arg------------------------
90 // This warps a VMReg into an OptoReg::Name
91 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
92 OptoReg::Name warped;
93 if( reg->is_stack() ) { // Stack slot argument?
94 warped = OptoReg::add(_old_SP, reg->reg2stack() );
95 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
96 if( warped >= _in_arg_limit )
97 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
98 if (!RegMask::can_represent(warped)) {
99 // the compiler cannot represent this method's calling sequence
100 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
101 return OptoReg::Bad;
102 }
103 return warped;
104 }
105 return OptoReg::as_OptoReg(reg);
106 }
107
108 //---------------------------compute_old_SP------------------------------------
109 OptoReg::Name Compile::compute_old_SP() {
110 int fixed = fixed_slots();
111 int preserve = in_preserve_stack_slots();
112 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
113 }
114
115
116
117 #ifdef ASSERT
118 void Matcher::verify_new_nodes_only(Node* xroot) {
119 // Make sure that the new graph only references new nodes
120 ResourceMark rm;
121 Unique_Node_List worklist;
122 VectorSet visited(Thread::current()->resource_area());
123 worklist.push(xroot);
124 while (worklist.size() > 0) {
125 Node* n = worklist.pop();
126 visited <<= n->_idx;
127 assert(C->node_arena()->contains(n), "dead node");
128 for (uint j = 0; j < n->req(); j++) {
129 Node* in = n->in(j);
130 if (in != NULL) {
131 assert(C->node_arena()->contains(in), "dead node");
132 if (!visited.test(in->_idx)) {
133 worklist.push(in);
134 }
135 }
136 }
137 }
138 }
139 #endif
140
141
142 //---------------------------match---------------------------------------------
143 void Matcher::match( ) {
144 // One-time initialization of some register masks.
145 init_spill_mask( C->root()->in(1) );
146 _return_addr_mask = return_addr();
147 #ifdef _LP64
148 // Pointers take 2 slots in 64-bit land
149 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
150 #endif
151
152 // Map a Java-signature return type into return register-value
153 // machine registers for 0, 1 and 2 returned values.
154 const TypeTuple *range = C->tf()->range();
155 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
156 // Get ideal-register return type
157 int ireg = base2reg[range->field_at(TypeFunc::Parms)->base()];
158 // Get machine return register
159 uint sop = C->start()->Opcode();
160 OptoRegPair regs = return_value(ireg, false);
161
162 // And mask for same
163 _return_value_mask = RegMask(regs.first());
164 if( OptoReg::is_valid(regs.second()) )
165 _return_value_mask.Insert(regs.second());
166 }
167
168 // ---------------
169 // Frame Layout
170
171 // Need the method signature to determine the incoming argument types,
172 // because the types determine which registers the incoming arguments are
173 // in, and this affects the matched code.
174 const TypeTuple *domain = C->tf()->domain();
175 uint argcnt = domain->cnt() - TypeFunc::Parms;
176 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
177 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
178 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
179 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
180 uint i;
181 for( i = 0; i<argcnt; i++ ) {
182 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
183 }
184
185 // Pass array of ideal registers and length to USER code (from the AD file)
186 // that will convert this to an array of register numbers.
187 const StartNode *start = C->start();
188 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
189 #ifdef ASSERT
190 // Sanity check users' calling convention. Real handy while trying to
191 // get the initial port correct.
192 { for (uint i = 0; i<argcnt; i++) {
193 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
194 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
195 _parm_regs[i].set_bad();
196 continue;
197 }
198 VMReg parm_reg = vm_parm_regs[i].first();
199 assert(parm_reg->is_valid(), "invalid arg?");
200 if (parm_reg->is_reg()) {
201 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
202 assert(can_be_java_arg(opto_parm_reg) ||
203 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
204 opto_parm_reg == inline_cache_reg(),
205 "parameters in register must be preserved by runtime stubs");
206 }
207 for (uint j = 0; j < i; j++) {
208 assert(parm_reg != vm_parm_regs[j].first(),
209 "calling conv. must produce distinct regs");
210 }
211 }
212 }
213 #endif
214
215 // Do some initial frame layout.
216
217 // Compute the old incoming SP (may be called FP) as
218 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
219 _old_SP = C->compute_old_SP();
220 assert( is_even(_old_SP), "must be even" );
221
222 // Compute highest incoming stack argument as
223 // _old_SP + out_preserve_stack_slots + incoming argument size.
224 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
225 assert( is_even(_in_arg_limit), "out_preserve must be even" );
226 for( i = 0; i < argcnt; i++ ) {
227 // Permit args to have no register
228 _calling_convention_mask[i].Clear();
229 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
230 continue;
231 }
232 // calling_convention returns stack arguments as a count of
233 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
234 // the allocators point of view, taking into account all the
235 // preserve area, locks & pad2.
236
237 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
238 if( OptoReg::is_valid(reg1))
239 _calling_convention_mask[i].Insert(reg1);
240
241 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
242 if( OptoReg::is_valid(reg2))
243 _calling_convention_mask[i].Insert(reg2);
244
245 // Saved biased stack-slot register number
246 _parm_regs[i].set_pair(reg2, reg1);
247 }
248
249 // Finally, make sure the incoming arguments take up an even number of
250 // words, in case the arguments or locals need to contain doubleword stack
251 // slots. The rest of the system assumes that stack slot pairs (in
252 // particular, in the spill area) which look aligned will in fact be
253 // aligned relative to the stack pointer in the target machine. Double
254 // stack slots will always be allocated aligned.
255 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
256
257 // Compute highest outgoing stack argument as
258 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
259 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
260 assert( is_even(_out_arg_limit), "out_preserve must be even" );
261
262 if (!RegMask::can_represent(OptoReg::add(_out_arg_limit,-1))) {
263 // the compiler cannot represent this method's calling sequence
264 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
265 }
266
267 if (C->failing()) return; // bailed out on incoming arg failure
268
269 // ---------------
270 // Collect roots of matcher trees. Every node for which
271 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
272 // can be a valid interior of some tree.
273 find_shared( C->root() );
274 find_shared( C->top() );
275
276 C->print_method("Before Matching");
277
278 // Swap out to old-space; emptying new-space
279 Arena *old = C->node_arena()->move_contents(C->old_arena());
280
281 // Save debug and profile information for nodes in old space:
282 _old_node_note_array = C->node_note_array();
283 if (_old_node_note_array != NULL) {
284 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
285 (C->comp_arena(), _old_node_note_array->length(),
286 0, NULL));
287 }
288
289 // Pre-size the new_node table to avoid the need for range checks.
290 grow_new_node_array(C->unique());
291
292 // Reset node counter so MachNodes start with _idx at 0
293 int nodes = C->unique(); // save value
294 C->set_unique(0);
295
296 // Recursively match trees from old space into new space.
297 // Correct leaves of new-space Nodes; they point to old-space.
298 _visited.Clear(); // Clear visit bits for xform call
299 C->set_cached_top_node(xform( C->top(), nodes ));
300 if (!C->failing()) {
301 Node* xroot = xform( C->root(), 1 );
302 if (xroot == NULL) {
303 Matcher::soft_match_failure(); // recursive matching process failed
304 C->record_method_not_compilable("instruction match failed");
305 } else {
306 // During matching shared constants were attached to C->root()
307 // because xroot wasn't available yet, so transfer the uses to
308 // the xroot.
309 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
310 Node* n = C->root()->fast_out(j);
311 if (C->node_arena()->contains(n)) {
312 assert(n->in(0) == C->root(), "should be control user");
313 n->set_req(0, xroot);
314 --j;
315 --jmax;
316 }
317 }
318
319 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
320 #ifdef ASSERT
321 verify_new_nodes_only(xroot);
322 #endif
323 }
324 }
325 if (C->top() == NULL || C->root() == NULL) {
326 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
327 }
328 if (C->failing()) {
329 // delete old;
330 old->destruct_contents();
331 return;
332 }
333 assert( C->top(), "" );
334 assert( C->root(), "" );
335 validate_null_checks();
336
337 // Now smoke old-space
338 NOT_DEBUG( old->destruct_contents() );
339
340 // ------------------------
341 // Set up save-on-entry registers
342 Fixup_Save_On_Entry( );
343 }
344
345
346 //------------------------------Fixup_Save_On_Entry----------------------------
347 // The stated purpose of this routine is to take care of save-on-entry
348 // registers. However, the overall goal of the Match phase is to convert into
349 // machine-specific instructions which have RegMasks to guide allocation.
350 // So what this procedure really does is put a valid RegMask on each input
351 // to the machine-specific variations of all Return, TailCall and Halt
352 // instructions. It also adds edgs to define the save-on-entry values (and of
353 // course gives them a mask).
354
355 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
356 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
357 // Do all the pre-defined register masks
358 rms[TypeFunc::Control ] = RegMask::Empty;
359 rms[TypeFunc::I_O ] = RegMask::Empty;
360 rms[TypeFunc::Memory ] = RegMask::Empty;
361 rms[TypeFunc::ReturnAdr] = ret_adr;
362 rms[TypeFunc::FramePtr ] = fp;
363 return rms;
364 }
365
366 //---------------------------init_first_stack_mask-----------------------------
367 // Create the initial stack mask used by values spilling to the stack.
368 // Disallow any debug info in outgoing argument areas by setting the
369 // initial mask accordingly.
370 void Matcher::init_first_stack_mask() {
371
372 // Allocate storage for spill masks as masks for the appropriate load type.
373 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask)*12);
374 idealreg2spillmask[Op_RegN] = &rms[0];
375 idealreg2spillmask[Op_RegI] = &rms[1];
376 idealreg2spillmask[Op_RegL] = &rms[2];
377 idealreg2spillmask[Op_RegF] = &rms[3];
378 idealreg2spillmask[Op_RegD] = &rms[4];
379 idealreg2spillmask[Op_RegP] = &rms[5];
380 idealreg2debugmask[Op_RegN] = &rms[6];
381 idealreg2debugmask[Op_RegI] = &rms[7];
382 idealreg2debugmask[Op_RegL] = &rms[8];
383 idealreg2debugmask[Op_RegF] = &rms[9];
384 idealreg2debugmask[Op_RegD] = &rms[10];
385 idealreg2debugmask[Op_RegP] = &rms[11];
386
387 OptoReg::Name i;
388
389 // At first, start with the empty mask
390 C->FIRST_STACK_mask().Clear();
391
392 // Add in the incoming argument area
393 OptoReg::Name init = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
394 for (i = init; i < _in_arg_limit; i = OptoReg::add(i,1))
395 C->FIRST_STACK_mask().Insert(i);
396
397 // Add in all bits past the outgoing argument area
398 guarantee(RegMask::can_represent(OptoReg::add(_out_arg_limit,-1)),
399 "must be able to represent all call arguments in reg mask");
400 init = _out_arg_limit;
401 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
402 C->FIRST_STACK_mask().Insert(i);
403
404 // Finally, set the "infinite stack" bit.
405 C->FIRST_STACK_mask().set_AllStack();
406
407 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
408 #ifdef _LP64
409 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
410 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
411 #endif
412 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
413 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
414 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
415 idealreg2spillmask[Op_RegL]->OR(C->FIRST_STACK_mask());
416 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
417 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
418 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
419 idealreg2spillmask[Op_RegD]->OR(C->FIRST_STACK_mask());
420 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
421 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
422
423 // Make up debug masks. Any spill slot plus callee-save registers.
424 // Caller-save registers are assumed to be trashable by the various
425 // inline-cache fixup routines.
426 *idealreg2debugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
427 *idealreg2debugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
428 *idealreg2debugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
429 *idealreg2debugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
430 *idealreg2debugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
431 *idealreg2debugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
432
433 // Prevent stub compilations from attempting to reference
434 // callee-saved registers from debug info
435 bool exclude_soe = !Compile::current()->is_method_compilation();
436
437 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
438 // registers the caller has to save do not work
439 if( _register_save_policy[i] == 'C' ||
440 _register_save_policy[i] == 'A' ||
441 (_register_save_policy[i] == 'E' && exclude_soe) ) {
442 idealreg2debugmask[Op_RegN]->Remove(i);
443 idealreg2debugmask[Op_RegI]->Remove(i); // Exclude save-on-call
444 idealreg2debugmask[Op_RegL]->Remove(i); // registers from debug
445 idealreg2debugmask[Op_RegF]->Remove(i); // masks
446 idealreg2debugmask[Op_RegD]->Remove(i);
447 idealreg2debugmask[Op_RegP]->Remove(i);
448 }
449 }
450 }
451
452 //---------------------------is_save_on_entry----------------------------------
453 bool Matcher::is_save_on_entry( int reg ) {
454 return
455 _register_save_policy[reg] == 'E' ||
456 _register_save_policy[reg] == 'A' || // Save-on-entry register?
457 // Also save argument registers in the trampolining stubs
458 (C->save_argument_registers() && is_spillable_arg(reg));
459 }
460
461 //---------------------------Fixup_Save_On_Entry-------------------------------
462 void Matcher::Fixup_Save_On_Entry( ) {
463 init_first_stack_mask();
464
465 Node *root = C->root(); // Short name for root
466 // Count number of save-on-entry registers.
467 uint soe_cnt = number_of_saved_registers();
468 uint i;
469
470 // Find the procedure Start Node
471 StartNode *start = C->start();
472 assert( start, "Expect a start node" );
473
474 // Save argument registers in the trampolining stubs
475 if( C->save_argument_registers() )
476 for( i = 0; i < _last_Mach_Reg; i++ )
477 if( is_spillable_arg(i) )
478 soe_cnt++;
479
480 // Input RegMask array shared by all Returns.
481 // The type for doubles and longs has a count of 2, but
482 // there is only 1 returned value
483 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
484 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
485 // Returns have 0 or 1 returned values depending on call signature.
486 // Return register is specified by return_value in the AD file.
487 if (ret_edge_cnt > TypeFunc::Parms)
488 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
489
490 // Input RegMask array shared by all Rethrows.
491 uint reth_edge_cnt = TypeFunc::Parms+1;
492 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
493 // Rethrow takes exception oop only, but in the argument 0 slot.
494 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
495 #ifdef _LP64
496 // Need two slots for ptrs in 64-bit land
497 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
498 #endif
499
500 // Input RegMask array shared by all TailCalls
501 uint tail_call_edge_cnt = TypeFunc::Parms+2;
502 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
503
504 // Input RegMask array shared by all TailJumps
505 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
506 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
507
508 // TailCalls have 2 returned values (target & moop), whose masks come
509 // from the usual MachNode/MachOper mechanism. Find a sample
510 // TailCall to extract these masks and put the correct masks into
511 // the tail_call_rms array.
512 for( i=1; i < root->req(); i++ ) {
513 MachReturnNode *m = root->in(i)->as_MachReturn();
514 if( m->ideal_Opcode() == Op_TailCall ) {
515 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
516 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
517 break;
518 }
519 }
520
521 // TailJumps have 2 returned values (target & ex_oop), whose masks come
522 // from the usual MachNode/MachOper mechanism. Find a sample
523 // TailJump to extract these masks and put the correct masks into
524 // the tail_jump_rms array.
525 for( i=1; i < root->req(); i++ ) {
526 MachReturnNode *m = root->in(i)->as_MachReturn();
527 if( m->ideal_Opcode() == Op_TailJump ) {
528 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
529 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
530 break;
531 }
532 }
533
534 // Input RegMask array shared by all Halts
535 uint halt_edge_cnt = TypeFunc::Parms;
536 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
537
538 // Capture the return input masks into each exit flavor
539 for( i=1; i < root->req(); i++ ) {
540 MachReturnNode *exit = root->in(i)->as_MachReturn();
541 switch( exit->ideal_Opcode() ) {
542 case Op_Return : exit->_in_rms = ret_rms; break;
543 case Op_Rethrow : exit->_in_rms = reth_rms; break;
544 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
545 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
546 case Op_Halt : exit->_in_rms = halt_rms; break;
547 default : ShouldNotReachHere();
548 }
549 }
550
551 // Next unused projection number from Start.
552 int proj_cnt = C->tf()->domain()->cnt();
553
554 // Do all the save-on-entry registers. Make projections from Start for
555 // them, and give them a use at the exit points. To the allocator, they
556 // look like incoming register arguments.
557 for( i = 0; i < _last_Mach_Reg; i++ ) {
558 if( is_save_on_entry(i) ) {
559
560 // Add the save-on-entry to the mask array
561 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
562 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
563 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
564 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
565 // Halts need the SOE registers, but only in the stack as debug info.
566 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
567 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
568
569 Node *mproj;
570
571 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
572 // into a single RegD.
573 if( (i&1) == 0 &&
574 _register_save_type[i ] == Op_RegF &&
575 _register_save_type[i+1] == Op_RegF &&
576 is_save_on_entry(i+1) ) {
577 // Add other bit for double
578 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
579 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
580 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
581 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
582 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
583 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
584 proj_cnt += 2; // Skip 2 for doubles
585 }
586 else if( (i&1) == 1 && // Else check for high half of double
587 _register_save_type[i-1] == Op_RegF &&
588 _register_save_type[i ] == Op_RegF &&
589 is_save_on_entry(i-1) ) {
590 ret_rms [ ret_edge_cnt] = RegMask::Empty;
591 reth_rms [ reth_edge_cnt] = RegMask::Empty;
592 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
593 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
594 halt_rms [ halt_edge_cnt] = RegMask::Empty;
595 mproj = C->top();
596 }
597 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
598 // into a single RegL.
599 else if( (i&1) == 0 &&
600 _register_save_type[i ] == Op_RegI &&
601 _register_save_type[i+1] == Op_RegI &&
602 is_save_on_entry(i+1) ) {
603 // Add other bit for long
604 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
605 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
606 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
607 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
608 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
609 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
610 proj_cnt += 2; // Skip 2 for longs
611 }
612 else if( (i&1) == 1 && // Else check for high half of long
613 _register_save_type[i-1] == Op_RegI &&
614 _register_save_type[i ] == Op_RegI &&
615 is_save_on_entry(i-1) ) {
616 ret_rms [ ret_edge_cnt] = RegMask::Empty;
617 reth_rms [ reth_edge_cnt] = RegMask::Empty;
618 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
619 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
620 halt_rms [ halt_edge_cnt] = RegMask::Empty;
621 mproj = C->top();
622 } else {
623 // Make a projection for it off the Start
624 mproj = new (C, 1) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
625 }
626
627 ret_edge_cnt ++;
628 reth_edge_cnt ++;
629 tail_call_edge_cnt ++;
630 tail_jump_edge_cnt ++;
631 halt_edge_cnt ++;
632
633 // Add a use of the SOE register to all exit paths
634 for( uint j=1; j < root->req(); j++ )
635 root->in(j)->add_req(mproj);
636 } // End of if a save-on-entry register
637 } // End of for all machine registers
638 }
639
640 //------------------------------init_spill_mask--------------------------------
641 void Matcher::init_spill_mask( Node *ret ) {
642 if( idealreg2regmask[Op_RegI] ) return; // One time only init
643
644 OptoReg::c_frame_pointer = c_frame_pointer();
645 c_frame_ptr_mask = c_frame_pointer();
646 #ifdef _LP64
647 // pointers are twice as big
648 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
649 #endif
650
651 // Start at OptoReg::stack0()
652 STACK_ONLY_mask.Clear();
653 OptoReg::Name init = OptoReg::stack2reg(0);
654 // STACK_ONLY_mask is all stack bits
655 OptoReg::Name i;
656 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
657 STACK_ONLY_mask.Insert(i);
658 // Also set the "infinite stack" bit.
659 STACK_ONLY_mask.set_AllStack();
660
661 // Copy the register names over into the shared world
662 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
663 // SharedInfo::regName[i] = regName[i];
664 // Handy RegMasks per machine register
665 mreg2regmask[i].Insert(i);
666 }
667
668 // Grab the Frame Pointer
669 Node *fp = ret->in(TypeFunc::FramePtr);
670 Node *mem = ret->in(TypeFunc::Memory);
671 const TypePtr* atp = TypePtr::BOTTOM;
672 // Share frame pointer while making spill ops
673 set_shared(fp);
674
675 // Compute generic short-offset Loads
676 #ifdef _LP64
677 MachNode *spillCP = match_tree(new (C, 3) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
678 #endif
679 MachNode *spillI = match_tree(new (C, 3) LoadINode(NULL,mem,fp,atp));
680 MachNode *spillL = match_tree(new (C, 3) LoadLNode(NULL,mem,fp,atp));
681 MachNode *spillF = match_tree(new (C, 3) LoadFNode(NULL,mem,fp,atp));
682 MachNode *spillD = match_tree(new (C, 3) LoadDNode(NULL,mem,fp,atp));
683 MachNode *spillP = match_tree(new (C, 3) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
684 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
685 spillD != NULL && spillP != NULL, "");
686
687 // Get the ADLC notion of the right regmask, for each basic type.
688 #ifdef _LP64
689 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
690 #endif
691 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
692 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
693 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
694 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
695 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
696 }
697
698 #ifdef ASSERT
699 static void match_alias_type(Compile* C, Node* n, Node* m) {
700 if (!VerifyAliases) return; // do not go looking for trouble by default
701 const TypePtr* nat = n->adr_type();
702 const TypePtr* mat = m->adr_type();
703 int nidx = C->get_alias_index(nat);
704 int midx = C->get_alias_index(mat);
705 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
706 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
707 for (uint i = 1; i < n->req(); i++) {
708 Node* n1 = n->in(i);
709 const TypePtr* n1at = n1->adr_type();
710 if (n1at != NULL) {
711 nat = n1at;
712 nidx = C->get_alias_index(n1at);
713 }
714 }
715 }
716 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
717 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
718 switch (n->Opcode()) {
719 case Op_PrefetchRead:
720 case Op_PrefetchWrite:
721 nidx = Compile::AliasIdxRaw;
722 nat = TypeRawPtr::BOTTOM;
723 break;
724 }
725 }
726 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
727 switch (n->Opcode()) {
728 case Op_ClearArray:
729 midx = Compile::AliasIdxRaw;
730 mat = TypeRawPtr::BOTTOM;
731 break;
732 }
733 }
734 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
735 switch (n->Opcode()) {
736 case Op_Return:
737 case Op_Rethrow:
738 case Op_Halt:
739 case Op_TailCall:
740 case Op_TailJump:
741 nidx = Compile::AliasIdxBot;
742 nat = TypePtr::BOTTOM;
743 break;
744 }
745 }
746 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
747 switch (n->Opcode()) {
748 case Op_StrComp:
749 case Op_StrEquals:
750 case Op_StrIndexOf:
751 case Op_AryEq:
752 case Op_MemBarVolatile:
753 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
754 nidx = Compile::AliasIdxTop;
755 nat = NULL;
756 break;
757 }
758 }
759 if (nidx != midx) {
760 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
761 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
762 n->dump();
763 m->dump();
764 }
765 assert(C->subsume_loads() && C->must_alias(nat, midx),
766 "must not lose alias info when matching");
767 }
768 }
769 #endif
770
771
772 //------------------------------MStack-----------------------------------------
773 // State and MStack class used in xform() and find_shared() iterative methods.
774 enum Node_State { Pre_Visit, // node has to be pre-visited
775 Visit, // visit node
776 Post_Visit, // post-visit node
777 Alt_Post_Visit // alternative post-visit path
778 };
779
780 class MStack: public Node_Stack {
781 public:
782 MStack(int size) : Node_Stack(size) { }
783
784 void push(Node *n, Node_State ns) {
785 Node_Stack::push(n, (uint)ns);
786 }
787 void push(Node *n, Node_State ns, Node *parent, int indx) {
788 ++_inode_top;
789 if ((_inode_top + 1) >= _inode_max) grow();
790 _inode_top->node = parent;
791 _inode_top->indx = (uint)indx;
792 ++_inode_top;
793 _inode_top->node = n;
794 _inode_top->indx = (uint)ns;
795 }
796 Node *parent() {
797 pop();
798 return node();
799 }
800 Node_State state() const {
801 return (Node_State)index();
802 }
803 void set_state(Node_State ns) {
804 set_index((uint)ns);
805 }
806 };
807
808
809 //------------------------------xform------------------------------------------
810 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
811 // Node in new-space. Given a new-space Node, recursively walk his children.
812 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
813 Node *Matcher::xform( Node *n, int max_stack ) {
814 // Use one stack to keep both: child's node/state and parent's node/index
815 MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2
816 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
817
818 while (mstack.is_nonempty()) {
819 n = mstack.node(); // Leave node on stack
820 Node_State nstate = mstack.state();
821 if (nstate == Visit) {
822 mstack.set_state(Post_Visit);
823 Node *oldn = n;
824 // Old-space or new-space check
825 if (!C->node_arena()->contains(n)) {
826 // Old space!
827 Node* m;
828 if (has_new_node(n)) { // Not yet Label/Reduced
829 m = new_node(n);
830 } else {
831 if (!is_dontcare(n)) { // Matcher can match this guy
832 // Calls match special. They match alone with no children.
833 // Their children, the incoming arguments, match normally.
834 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
835 if (C->failing()) return NULL;
836 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
837 } else { // Nothing the matcher cares about
838 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
839 // Convert to machine-dependent projection
840 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
841 #ifdef ASSERT
842 _new2old_map.map(m->_idx, n);
843 #endif
844 if (m->in(0) != NULL) // m might be top
845 collect_null_checks(m, n);
846 } else { // Else just a regular 'ol guy
847 m = n->clone(); // So just clone into new-space
848 #ifdef ASSERT
849 _new2old_map.map(m->_idx, n);
850 #endif
851 // Def-Use edges will be added incrementally as Uses
852 // of this node are matched.
853 assert(m->outcnt() == 0, "no Uses of this clone yet");
854 }
855 }
856
857 set_new_node(n, m); // Map old to new
858 if (_old_node_note_array != NULL) {
859 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
860 n->_idx);
861 C->set_node_notes_at(m->_idx, nn);
862 }
863 debug_only(match_alias_type(C, n, m));
864 }
865 n = m; // n is now a new-space node
866 mstack.set_node(n);
867 }
868
869 // New space!
870 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
871
872 int i;
873 // Put precedence edges on stack first (match them last).
874 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
875 Node *m = oldn->in(i);
876 if (m == NULL) break;
877 // set -1 to call add_prec() instead of set_req() during Step1
878 mstack.push(m, Visit, n, -1);
879 }
880
881 // For constant debug info, I'd rather have unmatched constants.
882 int cnt = n->req();
883 JVMState* jvms = n->jvms();
884 int debug_cnt = jvms ? jvms->debug_start() : cnt;
885
886 // Now do only debug info. Clone constants rather than matching.
887 // Constants are represented directly in the debug info without
888 // the need for executable machine instructions.
889 // Monitor boxes are also represented directly.
890 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
891 Node *m = n->in(i); // Get input
892 int op = m->Opcode();
893 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
894 if( op == Op_ConI || op == Op_ConP || op == Op_ConN ||
895 op == Op_ConF || op == Op_ConD || op == Op_ConL
896 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
897 ) {
898 m = m->clone();
899 #ifdef ASSERT
900 _new2old_map.map(m->_idx, n);
901 #endif
902 mstack.push(m, Post_Visit, n, i); // Don't need to visit
903 mstack.push(m->in(0), Visit, m, 0);
904 } else {
905 mstack.push(m, Visit, n, i);
906 }
907 }
908
909 // And now walk his children, and convert his inputs to new-space.
910 for( ; i >= 0; --i ) { // For all normal inputs do
911 Node *m = n->in(i); // Get input
912 if(m != NULL)
913 mstack.push(m, Visit, n, i);
914 }
915
916 }
917 else if (nstate == Post_Visit) {
918 // Set xformed input
919 Node *p = mstack.parent();
920 if (p != NULL) { // root doesn't have parent
921 int i = (int)mstack.index();
922 if (i >= 0)
923 p->set_req(i, n); // required input
924 else if (i == -1)
925 p->add_prec(n); // precedence input
926 else
927 ShouldNotReachHere();
928 }
929 mstack.pop(); // remove processed node from stack
930 }
931 else {
932 ShouldNotReachHere();
933 }
934 } // while (mstack.is_nonempty())
935 return n; // Return new-space Node
936 }
937
938 //------------------------------warp_outgoing_stk_arg------------------------
939 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
940 // Convert outgoing argument location to a pre-biased stack offset
941 if (reg->is_stack()) {
942 OptoReg::Name warped = reg->reg2stack();
943 // Adjust the stack slot offset to be the register number used
944 // by the allocator.
945 warped = OptoReg::add(begin_out_arg_area, warped);
946 // Keep track of the largest numbered stack slot used for an arg.
947 // Largest used slot per call-site indicates the amount of stack
948 // that is killed by the call.
949 if( warped >= out_arg_limit_per_call )
950 out_arg_limit_per_call = OptoReg::add(warped,1);
951 if (!RegMask::can_represent(warped)) {
952 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
953 return OptoReg::Bad;
954 }
955 return warped;
956 }
957 return OptoReg::as_OptoReg(reg);
958 }
959
960
961 //------------------------------match_sfpt-------------------------------------
962 // Helper function to match call instructions. Calls match special.
963 // They match alone with no children. Their children, the incoming
964 // arguments, match normally.
965 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
966 MachSafePointNode *msfpt = NULL;
967 MachCallNode *mcall = NULL;
968 uint cnt;
969 // Split out case for SafePoint vs Call
970 CallNode *call;
971 const TypeTuple *domain;
972 ciMethod* method = NULL;
973 if( sfpt->is_Call() ) {
974 call = sfpt->as_Call();
975 domain = call->tf()->domain();
976 cnt = domain->cnt();
977
978 // Match just the call, nothing else
979 MachNode *m = match_tree(call);
980 if (C->failing()) return NULL;
981 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
982
983 // Copy data from the Ideal SafePoint to the machine version
984 mcall = m->as_MachCall();
985
986 mcall->set_tf( call->tf());
987 mcall->set_entry_point(call->entry_point());
988 mcall->set_cnt( call->cnt());
989
990 if( mcall->is_MachCallJava() ) {
991 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
992 const CallJavaNode *call_java = call->as_CallJava();
993 method = call_java->method();
994 mcall_java->_method = method;
995 mcall_java->_bci = call_java->_bci;
996 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
997 if( mcall_java->is_MachCallStaticJava() )
998 mcall_java->as_MachCallStaticJava()->_name =
999 call_java->as_CallStaticJava()->_name;
1000 if( mcall_java->is_MachCallDynamicJava() )
1001 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1002 call_java->as_CallDynamicJava()->_vtable_index;
1003 }
1004 else if( mcall->is_MachCallRuntime() ) {
1005 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1006 }
1007 msfpt = mcall;
1008 }
1009 // This is a non-call safepoint
1010 else {
1011 call = NULL;
1012 domain = NULL;
1013 MachNode *mn = match_tree(sfpt);
1014 if (C->failing()) return NULL;
1015 msfpt = mn->as_MachSafePoint();
1016 cnt = TypeFunc::Parms;
1017 }
1018
1019 // Advertise the correct memory effects (for anti-dependence computation).
1020 msfpt->set_adr_type(sfpt->adr_type());
1021
1022 // Allocate a private array of RegMasks. These RegMasks are not shared.
1023 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1024 // Empty them all.
1025 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1026
1027 // Do all the pre-defined non-Empty register masks
1028 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1029 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1030
1031 // Place first outgoing argument can possibly be put.
1032 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1033 assert( is_even(begin_out_arg_area), "" );
1034 // Compute max outgoing register number per call site.
1035 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1036 // Calls to C may hammer extra stack slots above and beyond any arguments.
1037 // These are usually backing store for register arguments for varargs.
1038 if( call != NULL && call->is_CallRuntime() )
1039 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1040
1041
1042 // Do the normal argument list (parameters) register masks
1043 int argcnt = cnt - TypeFunc::Parms;
1044 if( argcnt > 0 ) { // Skip it all if we have no args
1045 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1046 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1047 int i;
1048 for( i = 0; i < argcnt; i++ ) {
1049 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1050 }
1051 // V-call to pick proper calling convention
1052 call->calling_convention( sig_bt, parm_regs, argcnt );
1053
1054 #ifdef ASSERT
1055 // Sanity check users' calling convention. Really handy during
1056 // the initial porting effort. Fairly expensive otherwise.
1057 { for (int i = 0; i<argcnt; i++) {
1058 if( !parm_regs[i].first()->is_valid() &&
1059 !parm_regs[i].second()->is_valid() ) continue;
1060 VMReg reg1 = parm_regs[i].first();
1061 VMReg reg2 = parm_regs[i].second();
1062 for (int j = 0; j < i; j++) {
1063 if( !parm_regs[j].first()->is_valid() &&
1064 !parm_regs[j].second()->is_valid() ) continue;
1065 VMReg reg3 = parm_regs[j].first();
1066 VMReg reg4 = parm_regs[j].second();
1067 if( !reg1->is_valid() ) {
1068 assert( !reg2->is_valid(), "valid halvsies" );
1069 } else if( !reg3->is_valid() ) {
1070 assert( !reg4->is_valid(), "valid halvsies" );
1071 } else {
1072 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1073 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1074 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1075 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1076 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1077 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1078 }
1079 }
1080 }
1081 }
1082 #endif
1083
1084 // Visit each argument. Compute its outgoing register mask.
1085 // Return results now can have 2 bits returned.
1086 // Compute max over all outgoing arguments both per call-site
1087 // and over the entire method.
1088 for( i = 0; i < argcnt; i++ ) {
1089 // Address of incoming argument mask to fill in
1090 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1091 if( !parm_regs[i].first()->is_valid() &&
1092 !parm_regs[i].second()->is_valid() ) {
1093 continue; // Avoid Halves
1094 }
1095 // Grab first register, adjust stack slots and insert in mask.
1096 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1097 if (OptoReg::is_valid(reg1))
1098 rm->Insert( reg1 );
1099 // Grab second register (if any), adjust stack slots and insert in mask.
1100 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1101 if (OptoReg::is_valid(reg2))
1102 rm->Insert( reg2 );
1103 } // End of for all arguments
1104
1105 // Compute number of stack slots needed to restore stack in case of
1106 // Pascal-style argument popping.
1107 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1108 }
1109
1110 // Compute the max stack slot killed by any call. These will not be
1111 // available for debug info, and will be used to adjust FIRST_STACK_mask
1112 // after all call sites have been visited.
1113 if( _out_arg_limit < out_arg_limit_per_call)
1114 _out_arg_limit = out_arg_limit_per_call;
1115
1116 if (mcall) {
1117 // Kill the outgoing argument area, including any non-argument holes and
1118 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1119 // Since the max-per-method covers the max-per-call-site and debug info
1120 // is excluded on the max-per-method basis, debug info cannot land in
1121 // this killed area.
1122 uint r_cnt = mcall->tf()->range()->cnt();
1123 MachProjNode *proj = new (C, 1) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1124 if (!RegMask::can_represent(OptoReg::Name(out_arg_limit_per_call-1))) {
1125 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1126 } else {
1127 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1128 proj->_rout.Insert(OptoReg::Name(i));
1129 }
1130 if( proj->_rout.is_NotEmpty() )
1131 _proj_list.push(proj);
1132 }
1133 // Transfer the safepoint information from the call to the mcall
1134 // Move the JVMState list
1135 msfpt->set_jvms(sfpt->jvms());
1136 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1137 jvms->set_map(sfpt);
1138 }
1139
1140 // Debug inputs begin just after the last incoming parameter
1141 assert( (mcall == NULL) || (mcall->jvms() == NULL) ||
1142 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "" );
1143
1144 // Move the OopMap
1145 msfpt->_oop_map = sfpt->_oop_map;
1146
1147 // Registers killed by the call are set in the local scheduling pass
1148 // of Global Code Motion.
1149 return msfpt;
1150 }
1151
1152 //---------------------------match_tree----------------------------------------
1153 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1154 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1155 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1156 // a Load's result RegMask for memoization in idealreg2regmask[]
1157 MachNode *Matcher::match_tree( const Node *n ) {
1158 assert( n->Opcode() != Op_Phi, "cannot match" );
1159 assert( !n->is_block_start(), "cannot match" );
1160 // Set the mark for all locally allocated State objects.
1161 // When this call returns, the _states_arena arena will be reset
1162 // freeing all State objects.
1163 ResourceMark rm( &_states_arena );
1164
1165 LabelRootDepth = 0;
1166
1167 // StoreNodes require their Memory input to match any LoadNodes
1168 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1169 #ifdef ASSERT
1170 Node* save_mem_node = _mem_node;
1171 _mem_node = n->is_Store() ? (Node*)n : NULL;
1172 #endif
1173 // State object for root node of match tree
1174 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1175 State *s = new (&_states_arena) State;
1176 s->_kids[0] = NULL;
1177 s->_kids[1] = NULL;
1178 s->_leaf = (Node*)n;
1179 // Label the input tree, allocating labels from top-level arena
1180 Label_Root( n, s, n->in(0), mem );
1181 if (C->failing()) return NULL;
1182
1183 // The minimum cost match for the whole tree is found at the root State
1184 uint mincost = max_juint;
1185 uint cost = max_juint;
1186 uint i;
1187 for( i = 0; i < NUM_OPERANDS; i++ ) {
1188 if( s->valid(i) && // valid entry and
1189 s->_cost[i] < cost && // low cost and
1190 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1191 cost = s->_cost[mincost=i];
1192 }
1193 if (mincost == max_juint) {
1194 #ifndef PRODUCT
1195 tty->print("No matching rule for:");
1196 s->dump();
1197 #endif
1198 Matcher::soft_match_failure();
1199 return NULL;
1200 }
1201 // Reduce input tree based upon the state labels to machine Nodes
1202 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1203 #ifdef ASSERT
1204 _old2new_map.map(n->_idx, m);
1205 _new2old_map.map(m->_idx, (Node*)n);
1206 #endif
1207
1208 // Add any Matcher-ignored edges
1209 uint cnt = n->req();
1210 uint start = 1;
1211 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1212 if( n->is_AddP() ) {
1213 assert( mem == (Node*)1, "" );
1214 start = AddPNode::Base+1;
1215 }
1216 for( i = start; i < cnt; i++ ) {
1217 if( !n->match_edge(i) ) {
1218 if( i < m->req() )
1219 m->ins_req( i, n->in(i) );
1220 else
1221 m->add_req( n->in(i) );
1222 }
1223 }
1224
1225 debug_only( _mem_node = save_mem_node; )
1226 return m;
1227 }
1228
1229
1230 //------------------------------match_into_reg---------------------------------
1231 // Choose to either match this Node in a register or part of the current
1232 // match tree. Return true for requiring a register and false for matching
1233 // as part of the current match tree.
1234 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1235
1236 const Type *t = m->bottom_type();
1237
1238 if( t->singleton() ) {
1239 // Never force constants into registers. Allow them to match as
1240 // constants or registers. Copies of the same value will share
1241 // the same register. See find_shared_node.
1242 return false;
1243 } else { // Not a constant
1244 // Stop recursion if they have different Controls.
1245 // Slot 0 of constants is not really a Control.
1246 if( control && m->in(0) && control != m->in(0) ) {
1247
1248 // Actually, we can live with the most conservative control we
1249 // find, if it post-dominates the others. This allows us to
1250 // pick up load/op/store trees where the load can float a little
1251 // above the store.
1252 Node *x = control;
1253 const uint max_scan = 6; // Arbitrary scan cutoff
1254 uint j;
1255 for( j=0; j<max_scan; j++ ) {
1256 if( x->is_Region() ) // Bail out at merge points
1257 return true;
1258 x = x->in(0);
1259 if( x == m->in(0) ) // Does 'control' post-dominate
1260 break; // m->in(0)? If so, we can use it
1261 }
1262 if( j == max_scan ) // No post-domination before scan end?
1263 return true; // Then break the match tree up
1264 }
1265 if (m->is_DecodeN() && Matcher::clone_shift_expressions) {
1266 // These are commonly used in address expressions and can
1267 // efficiently fold into them on X64 in some cases.
1268 return false;
1269 }
1270 }
1271
1272 // Not forceable cloning. If shared, put it into a register.
1273 return shared;
1274 }
1275
1276
1277 //------------------------------Instruction Selection--------------------------
1278 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1279 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1280 // things the Matcher does not match (e.g., Memory), and things with different
1281 // Controls (hence forced into different blocks). We pass in the Control
1282 // selected for this entire State tree.
1283
1284 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1285 // Store and the Load must have identical Memories (as well as identical
1286 // pointers). Since the Matcher does not have anything for Memory (and
1287 // does not handle DAGs), I have to match the Memory input myself. If the
1288 // Tree root is a Store, I require all Loads to have the identical memory.
1289 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1290 // Since Label_Root is a recursive function, its possible that we might run
1291 // out of stack space. See bugs 6272980 & 6227033 for more info.
1292 LabelRootDepth++;
1293 if (LabelRootDepth > MaxLabelRootDepth) {
1294 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1295 return NULL;
1296 }
1297 uint care = 0; // Edges matcher cares about
1298 uint cnt = n->req();
1299 uint i = 0;
1300
1301 // Examine children for memory state
1302 // Can only subsume a child into your match-tree if that child's memory state
1303 // is not modified along the path to another input.
1304 // It is unsafe even if the other inputs are separate roots.
1305 Node *input_mem = NULL;
1306 for( i = 1; i < cnt; i++ ) {
1307 if( !n->match_edge(i) ) continue;
1308 Node *m = n->in(i); // Get ith input
1309 assert( m, "expect non-null children" );
1310 if( m->is_Load() ) {
1311 if( input_mem == NULL ) {
1312 input_mem = m->in(MemNode::Memory);
1313 } else if( input_mem != m->in(MemNode::Memory) ) {
1314 input_mem = NodeSentinel;
1315 }
1316 }
1317 }
1318
1319 for( i = 1; i < cnt; i++ ){// For my children
1320 if( !n->match_edge(i) ) continue;
1321 Node *m = n->in(i); // Get ith input
1322 // Allocate states out of a private arena
1323 State *s = new (&_states_arena) State;
1324 svec->_kids[care++] = s;
1325 assert( care <= 2, "binary only for now" );
1326
1327 // Recursively label the State tree.
1328 s->_kids[0] = NULL;
1329 s->_kids[1] = NULL;
1330 s->_leaf = m;
1331
1332 // Check for leaves of the State Tree; things that cannot be a part of
1333 // the current tree. If it finds any, that value is matched as a
1334 // register operand. If not, then the normal matching is used.
1335 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1336 //
1337 // Stop recursion if this is LoadNode and the root of this tree is a
1338 // StoreNode and the load & store have different memories.
1339 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1340 // Can NOT include the match of a subtree when its memory state
1341 // is used by any of the other subtrees
1342 (input_mem == NodeSentinel) ) {
1343 #ifndef PRODUCT
1344 // Print when we exclude matching due to different memory states at input-loads
1345 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1346 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1347 tty->print_cr("invalid input_mem");
1348 }
1349 #endif
1350 // Switch to a register-only opcode; this value must be in a register
1351 // and cannot be subsumed as part of a larger instruction.
1352 s->DFA( m->ideal_reg(), m );
1353
1354 } else {
1355 // If match tree has no control and we do, adopt it for entire tree
1356 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1357 control = m->in(0); // Pick up control
1358 // Else match as a normal part of the match tree.
1359 control = Label_Root(m,s,control,mem);
1360 if (C->failing()) return NULL;
1361 }
1362 }
1363
1364
1365 // Call DFA to match this node, and return
1366 svec->DFA( n->Opcode(), n );
1367
1368 #ifdef ASSERT
1369 uint x;
1370 for( x = 0; x < _LAST_MACH_OPER; x++ )
1371 if( svec->valid(x) )
1372 break;
1373
1374 if (x >= _LAST_MACH_OPER) {
1375 n->dump();
1376 svec->dump();
1377 assert( false, "bad AD file" );
1378 }
1379 #endif
1380 return control;
1381 }
1382
1383
1384 // Con nodes reduced using the same rule can share their MachNode
1385 // which reduces the number of copies of a constant in the final
1386 // program. The register allocator is free to split uses later to
1387 // split live ranges.
1388 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1389 if (!leaf->is_Con() && !leaf->is_DecodeN()) return NULL;
1390
1391 // See if this Con has already been reduced using this rule.
1392 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1393 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1394 if (last != NULL && rule == last->rule()) {
1395 // Don't expect control change for DecodeN
1396 if (leaf->is_DecodeN())
1397 return last;
1398 // Get the new space root.
1399 Node* xroot = new_node(C->root());
1400 if (xroot == NULL) {
1401 // This shouldn't happen give the order of matching.
1402 return NULL;
1403 }
1404
1405 // Shared constants need to have their control be root so they
1406 // can be scheduled properly.
1407 Node* control = last->in(0);
1408 if (control != xroot) {
1409 if (control == NULL || control == C->root()) {
1410 last->set_req(0, xroot);
1411 } else {
1412 assert(false, "unexpected control");
1413 return NULL;
1414 }
1415 }
1416 return last;
1417 }
1418 return NULL;
1419 }
1420
1421
1422 //------------------------------ReduceInst-------------------------------------
1423 // Reduce a State tree (with given Control) into a tree of MachNodes.
1424 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1425 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1426 // Each MachNode has a number of complicated MachOper operands; each
1427 // MachOper also covers a further tree of Ideal Nodes.
1428
1429 // The root of the Ideal match tree is always an instruction, so we enter
1430 // the recursion here. After building the MachNode, we need to recurse
1431 // the tree checking for these cases:
1432 // (1) Child is an instruction -
1433 // Build the instruction (recursively), add it as an edge.
1434 // Build a simple operand (register) to hold the result of the instruction.
1435 // (2) Child is an interior part of an instruction -
1436 // Skip over it (do nothing)
1437 // (3) Child is the start of a operand -
1438 // Build the operand, place it inside the instruction
1439 // Call ReduceOper.
1440 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1441 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1442
1443 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1444 if (shared_node != NULL) {
1445 return shared_node;
1446 }
1447
1448 // Build the object to represent this state & prepare for recursive calls
1449 MachNode *mach = s->MachNodeGenerator( rule, C );
1450 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1451 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1452 Node *leaf = s->_leaf;
1453 // Check for instruction or instruction chain rule
1454 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1455 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1456 "duplicating node that's already been matched");
1457 // Instruction
1458 mach->add_req( leaf->in(0) ); // Set initial control
1459 // Reduce interior of complex instruction
1460 ReduceInst_Interior( s, rule, mem, mach, 1 );
1461 } else {
1462 // Instruction chain rules are data-dependent on their inputs
1463 mach->add_req(0); // Set initial control to none
1464 ReduceInst_Chain_Rule( s, rule, mem, mach );
1465 }
1466
1467 // If a Memory was used, insert a Memory edge
1468 if( mem != (Node*)1 ) {
1469 mach->ins_req(MemNode::Memory,mem);
1470 #ifdef ASSERT
1471 // Verify adr type after matching memory operation
1472 const MachOper* oper = mach->memory_operand();
1473 if (oper != NULL && oper != (MachOper*)-1 &&
1474 mach->adr_type() != TypeRawPtr::BOTTOM) { // non-direct addressing mode
1475 // It has a unique memory operand. Find corresponding ideal mem node.
1476 Node* m = NULL;
1477 if (leaf->is_Mem()) {
1478 m = leaf;
1479 } else {
1480 m = _mem_node;
1481 assert(m != NULL && m->is_Mem(), "expecting memory node");
1482 }
1483 const Type* mach_at = mach->adr_type();
1484 // DecodeN node consumed by an address may have different type
1485 // then its input. Don't compare types for such case.
1486 if (m->adr_type() != mach_at &&
1487 (m->in(MemNode::Address)->is_DecodeN() ||
1488 m->in(MemNode::Address)->is_AddP() &&
1489 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeN() ||
1490 m->in(MemNode::Address)->is_AddP() &&
1491 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1492 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeN())) {
1493 mach_at = m->adr_type();
1494 }
1495 if (m->adr_type() != mach_at) {
1496 m->dump();
1497 tty->print_cr("mach:");
1498 mach->dump(1);
1499 }
1500 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1501 }
1502 #endif
1503 }
1504
1505 // If the _leaf is an AddP, insert the base edge
1506 if( leaf->is_AddP() )
1507 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1508
1509 uint num_proj = _proj_list.size();
1510
1511 // Perform any 1-to-many expansions required
1512 MachNode *ex = mach->Expand(s,_proj_list);
1513 if( ex != mach ) {
1514 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1515 if( ex->in(1)->is_Con() )
1516 ex->in(1)->set_req(0, C->root());
1517 // Remove old node from the graph
1518 for( uint i=0; i<mach->req(); i++ ) {
1519 mach->set_req(i,NULL);
1520 }
1521 #ifdef ASSERT
1522 _new2old_map.map(ex->_idx, s->_leaf);
1523 #endif
1524 }
1525
1526 // PhaseChaitin::fixup_spills will sometimes generate spill code
1527 // via the matcher. By the time, nodes have been wired into the CFG,
1528 // and any further nodes generated by expand rules will be left hanging
1529 // in space, and will not get emitted as output code. Catch this.
1530 // Also, catch any new register allocation constraints ("projections")
1531 // generated belatedly during spill code generation.
1532 if (_allocation_started) {
1533 guarantee(ex == mach, "no expand rules during spill generation");
1534 guarantee(_proj_list.size() == num_proj, "no allocation during spill generation");
1535 }
1536
1537 if (leaf->is_Con() || leaf->is_DecodeN()) {
1538 // Record the con for sharing
1539 _shared_nodes.map(leaf->_idx, ex);
1540 }
1541
1542 return ex;
1543 }
1544
1545 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1546 // 'op' is what I am expecting to receive
1547 int op = _leftOp[rule];
1548 // Operand type to catch childs result
1549 // This is what my child will give me.
1550 int opnd_class_instance = s->_rule[op];
1551 // Choose between operand class or not.
1552 // This is what I will receive.
1553 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1554 // New rule for child. Chase operand classes to get the actual rule.
1555 int newrule = s->_rule[catch_op];
1556
1557 if( newrule < NUM_OPERANDS ) {
1558 // Chain from operand or operand class, may be output of shared node
1559 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1560 "Bad AD file: Instruction chain rule must chain from operand");
1561 // Insert operand into array of operands for this instruction
1562 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1563
1564 ReduceOper( s, newrule, mem, mach );
1565 } else {
1566 // Chain from the result of an instruction
1567 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1568 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1569 Node *mem1 = (Node*)1;
1570 debug_only(Node *save_mem_node = _mem_node;)
1571 mach->add_req( ReduceInst(s, newrule, mem1) );
1572 debug_only(_mem_node = save_mem_node;)
1573 }
1574 return;
1575 }
1576
1577
1578 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1579 if( s->_leaf->is_Load() ) {
1580 Node *mem2 = s->_leaf->in(MemNode::Memory);
1581 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1582 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1583 mem = mem2;
1584 }
1585 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1586 if( mach->in(0) == NULL )
1587 mach->set_req(0, s->_leaf->in(0));
1588 }
1589
1590 // Now recursively walk the state tree & add operand list.
1591 for( uint i=0; i<2; i++ ) { // binary tree
1592 State *newstate = s->_kids[i];
1593 if( newstate == NULL ) break; // Might only have 1 child
1594 // 'op' is what I am expecting to receive
1595 int op;
1596 if( i == 0 ) {
1597 op = _leftOp[rule];
1598 } else {
1599 op = _rightOp[rule];
1600 }
1601 // Operand type to catch childs result
1602 // This is what my child will give me.
1603 int opnd_class_instance = newstate->_rule[op];
1604 // Choose between operand class or not.
1605 // This is what I will receive.
1606 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1607 // New rule for child. Chase operand classes to get the actual rule.
1608 int newrule = newstate->_rule[catch_op];
1609
1610 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1611 // Operand/operandClass
1612 // Insert operand into array of operands for this instruction
1613 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1614 ReduceOper( newstate, newrule, mem, mach );
1615
1616 } else { // Child is internal operand or new instruction
1617 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1618 // internal operand --> call ReduceInst_Interior
1619 // Interior of complex instruction. Do nothing but recurse.
1620 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1621 } else {
1622 // instruction --> call build operand( ) to catch result
1623 // --> ReduceInst( newrule )
1624 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1625 Node *mem1 = (Node*)1;
1626 debug_only(Node *save_mem_node = _mem_node;)
1627 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1628 debug_only(_mem_node = save_mem_node;)
1629 }
1630 }
1631 assert( mach->_opnds[num_opnds-1], "" );
1632 }
1633 return num_opnds;
1634 }
1635
1636 // This routine walks the interior of possible complex operands.
1637 // At each point we check our children in the match tree:
1638 // (1) No children -
1639 // We are a leaf; add _leaf field as an input to the MachNode
1640 // (2) Child is an internal operand -
1641 // Skip over it ( do nothing )
1642 // (3) Child is an instruction -
1643 // Call ReduceInst recursively and
1644 // and instruction as an input to the MachNode
1645 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1646 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1647 State *kid = s->_kids[0];
1648 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1649
1650 // Leaf? And not subsumed?
1651 if( kid == NULL && !_swallowed[rule] ) {
1652 mach->add_req( s->_leaf ); // Add leaf pointer
1653 return; // Bail out
1654 }
1655
1656 if( s->_leaf->is_Load() ) {
1657 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1658 mem = s->_leaf->in(MemNode::Memory);
1659 debug_only(_mem_node = s->_leaf;)
1660 }
1661 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1662 if( !mach->in(0) )
1663 mach->set_req(0,s->_leaf->in(0));
1664 else {
1665 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1666 }
1667 }
1668
1669 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1670 int newrule;
1671 if( i == 0 )
1672 newrule = kid->_rule[_leftOp[rule]];
1673 else
1674 newrule = kid->_rule[_rightOp[rule]];
1675
1676 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1677 // Internal operand; recurse but do nothing else
1678 ReduceOper( kid, newrule, mem, mach );
1679
1680 } else { // Child is a new instruction
1681 // Reduce the instruction, and add a direct pointer from this
1682 // machine instruction to the newly reduced one.
1683 Node *mem1 = (Node*)1;
1684 debug_only(Node *save_mem_node = _mem_node;)
1685 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1686 debug_only(_mem_node = save_mem_node;)
1687 }
1688 }
1689 }
1690
1691
1692 // -------------------------------------------------------------------------
1693 // Java-Java calling convention
1694 // (what you use when Java calls Java)
1695
1696 //------------------------------find_receiver----------------------------------
1697 // For a given signature, return the OptoReg for parameter 0.
1698 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1699 VMRegPair regs;
1700 BasicType sig_bt = T_OBJECT;
1701 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1702 // Return argument 0 register. In the LP64 build pointers
1703 // take 2 registers, but the VM wants only the 'main' name.
1704 return OptoReg::as_OptoReg(regs.first());
1705 }
1706
1707 // A method-klass-holder may be passed in the inline_cache_reg
1708 // and then expanded into the inline_cache_reg and a method_oop register
1709 // defined in ad_<arch>.cpp
1710
1711
1712 //------------------------------find_shared------------------------------------
1713 // Set bits if Node is shared or otherwise a root
1714 void Matcher::find_shared( Node *n ) {
1715 // Allocate stack of size C->unique() * 2 to avoid frequent realloc
1716 MStack mstack(C->unique() * 2);
1717 // Mark nodes as address_visited if they are inputs to an address expression
1718 VectorSet address_visited(Thread::current()->resource_area());
1719 mstack.push(n, Visit); // Don't need to pre-visit root node
1720 while (mstack.is_nonempty()) {
1721 n = mstack.node(); // Leave node on stack
1722 Node_State nstate = mstack.state();
1723 uint nop = n->Opcode();
1724 if (nstate == Pre_Visit) {
1725 if (address_visited.test(n->_idx)) { // Visited in address already?
1726 // Flag as visited and shared now.
1727 set_visited(n);
1728 }
1729 if (is_visited(n)) { // Visited already?
1730 // Node is shared and has no reason to clone. Flag it as shared.
1731 // This causes it to match into a register for the sharing.
1732 set_shared(n); // Flag as shared and
1733 mstack.pop(); // remove node from stack
1734 continue;
1735 }
1736 nstate = Visit; // Not already visited; so visit now
1737 }
1738 if (nstate == Visit) {
1739 mstack.set_state(Post_Visit);
1740 set_visited(n); // Flag as visited now
1741 bool mem_op = false;
1742
1743 switch( nop ) { // Handle some opcodes special
1744 case Op_Phi: // Treat Phis as shared roots
1745 case Op_Parm:
1746 case Op_Proj: // All handled specially during matching
1747 case Op_SafePointScalarObject:
1748 set_shared(n);
1749 set_dontcare(n);
1750 break;
1751 case Op_If:
1752 case Op_CountedLoopEnd:
1753 mstack.set_state(Alt_Post_Visit); // Alternative way
1754 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
1755 // with matching cmp/branch in 1 instruction. The Matcher needs the
1756 // Bool and CmpX side-by-side, because it can only get at constants
1757 // that are at the leaves of Match trees, and the Bool's condition acts
1758 // as a constant here.
1759 mstack.push(n->in(1), Visit); // Clone the Bool
1760 mstack.push(n->in(0), Pre_Visit); // Visit control input
1761 continue; // while (mstack.is_nonempty())
1762 case Op_ConvI2D: // These forms efficiently match with a prior
1763 case Op_ConvI2F: // Load but not a following Store
1764 if( n->in(1)->is_Load() && // Prior load
1765 n->outcnt() == 1 && // Not already shared
1766 n->unique_out()->is_Store() ) // Following store
1767 set_shared(n); // Force it to be a root
1768 break;
1769 case Op_ReverseBytesI:
1770 case Op_ReverseBytesL:
1771 if( n->in(1)->is_Load() && // Prior load
1772 n->outcnt() == 1 ) // Not already shared
1773 set_shared(n); // Force it to be a root
1774 break;
1775 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
1776 case Op_IfFalse:
1777 case Op_IfTrue:
1778 case Op_MachProj:
1779 case Op_MergeMem:
1780 case Op_Catch:
1781 case Op_CatchProj:
1782 case Op_CProj:
1783 case Op_JumpProj:
1784 case Op_JProj:
1785 case Op_NeverBranch:
1786 set_dontcare(n);
1787 break;
1788 case Op_Jump:
1789 mstack.push(n->in(1), Visit); // Switch Value
1790 mstack.push(n->in(0), Pre_Visit); // Visit Control input
1791 continue; // while (mstack.is_nonempty())
1792 case Op_StrComp:
1793 case Op_StrEquals:
1794 case Op_StrIndexOf:
1795 case Op_AryEq:
1796 set_shared(n); // Force result into register (it will be anyways)
1797 break;
1798 case Op_ConP: { // Convert pointers above the centerline to NUL
1799 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1800 const TypePtr* tp = tn->type()->is_ptr();
1801 if (tp->_ptr == TypePtr::AnyNull) {
1802 tn->set_type(TypePtr::NULL_PTR);
1803 }
1804 break;
1805 }
1806 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
1807 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1808 const TypePtr* tp = tn->type()->make_ptr();
1809 if (tp && tp->_ptr == TypePtr::AnyNull) {
1810 tn->set_type(TypeNarrowOop::NULL_PTR);
1811 }
1812 break;
1813 }
1814 case Op_Binary: // These are introduced in the Post_Visit state.
1815 ShouldNotReachHere();
1816 break;
1817 case Op_StoreB: // Do match these, despite no ideal reg
1818 case Op_StoreC:
1819 case Op_StoreCM:
1820 case Op_StoreD:
1821 case Op_StoreF:
1822 case Op_StoreI:
1823 case Op_StoreL:
1824 case Op_StoreP:
1825 case Op_StoreN:
1826 case Op_Store16B:
1827 case Op_Store8B:
1828 case Op_Store4B:
1829 case Op_Store8C:
1830 case Op_Store4C:
1831 case Op_Store2C:
1832 case Op_Store4I:
1833 case Op_Store2I:
1834 case Op_Store2L:
1835 case Op_Store4F:
1836 case Op_Store2F:
1837 case Op_Store2D:
1838 case Op_ClearArray:
1839 case Op_SafePoint:
1840 mem_op = true;
1841 break;
1842 case Op_LoadB:
1843 case Op_LoadUS:
1844 case Op_LoadD:
1845 case Op_LoadF:
1846 case Op_LoadI:
1847 case Op_LoadKlass:
1848 case Op_LoadNKlass:
1849 case Op_LoadL:
1850 case Op_LoadS:
1851 case Op_LoadP:
1852 case Op_LoadN:
1853 case Op_LoadRange:
1854 case Op_LoadD_unaligned:
1855 case Op_LoadL_unaligned:
1856 case Op_Load16B:
1857 case Op_Load8B:
1858 case Op_Load4B:
1859 case Op_Load4C:
1860 case Op_Load2C:
1861 case Op_Load8C:
1862 case Op_Load8S:
1863 case Op_Load4S:
1864 case Op_Load2S:
1865 case Op_Load4I:
1866 case Op_Load2I:
1867 case Op_Load2L:
1868 case Op_Load4F:
1869 case Op_Load2F:
1870 case Op_Load2D:
1871 mem_op = true;
1872 // Must be root of match tree due to prior load conflict
1873 if( C->subsume_loads() == false ) {
1874 set_shared(n);
1875 }
1876 // Fall into default case
1877 default:
1878 if( !n->ideal_reg() )
1879 set_dontcare(n); // Unmatchable Nodes
1880 } // end_switch
1881
1882 for(int i = n->req() - 1; i >= 0; --i) { // For my children
1883 Node *m = n->in(i); // Get ith input
1884 if (m == NULL) continue; // Ignore NULLs
1885 uint mop = m->Opcode();
1886
1887 // Must clone all producers of flags, or we will not match correctly.
1888 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
1889 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
1890 // are also there, so we may match a float-branch to int-flags and
1891 // expect the allocator to haul the flags from the int-side to the
1892 // fp-side. No can do.
1893 if( _must_clone[mop] ) {
1894 mstack.push(m, Visit);
1895 continue; // for(int i = ...)
1896 }
1897
1898 // Clone addressing expressions as they are "free" in most instructions
1899 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
1900 if (m->in(AddPNode::Base)->Opcode() == Op_DecodeN) {
1901 // Bases used in addresses must be shared but since
1902 // they are shared through a DecodeN they may appear
1903 // to have a single use so force sharing here.
1904 set_shared(m->in(AddPNode::Base)->in(1));
1905 }
1906
1907 // Some inputs for address expression are not put on stack
1908 // to avoid marking them as shared and forcing them into register
1909 // if they are used only in address expressions.
1910 // But they should be marked as shared if there are other uses
1911 // besides address expressions.
1912
1913 Node *off = m->in(AddPNode::Offset);
1914 if( off->is_Con() &&
1915 // When there are other uses besides address expressions
1916 // put it on stack and mark as shared.
1917 !is_visited(m) ) {
1918 address_visited.test_set(m->_idx); // Flag as address_visited
1919 Node *adr = m->in(AddPNode::Address);
1920
1921 // Intel, ARM and friends can handle 2 adds in addressing mode
1922 if( clone_shift_expressions && adr->is_AddP() &&
1923 // AtomicAdd is not an addressing expression.
1924 // Cheap to find it by looking for screwy base.
1925 !adr->in(AddPNode::Base)->is_top() &&
1926 // Are there other uses besides address expressions?
1927 !is_visited(adr) ) {
1928 address_visited.set(adr->_idx); // Flag as address_visited
1929 Node *shift = adr->in(AddPNode::Offset);
1930 // Check for shift by small constant as well
1931 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
1932 shift->in(2)->get_int() <= 3 &&
1933 // Are there other uses besides address expressions?
1934 !is_visited(shift) ) {
1935 address_visited.set(shift->_idx); // Flag as address_visited
1936 mstack.push(shift->in(2), Visit);
1937 Node *conv = shift->in(1);
1938 #ifdef _LP64
1939 // Allow Matcher to match the rule which bypass
1940 // ConvI2L operation for an array index on LP64
1941 // if the index value is positive.
1942 if( conv->Opcode() == Op_ConvI2L &&
1943 conv->as_Type()->type()->is_long()->_lo >= 0 &&
1944 // Are there other uses besides address expressions?
1945 !is_visited(conv) ) {
1946 address_visited.set(conv->_idx); // Flag as address_visited
1947 mstack.push(conv->in(1), Pre_Visit);
1948 } else
1949 #endif
1950 mstack.push(conv, Pre_Visit);
1951 } else {
1952 mstack.push(shift, Pre_Visit);
1953 }
1954 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
1955 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
1956 } else { // Sparc, Alpha, PPC and friends
1957 mstack.push(adr, Pre_Visit);
1958 }
1959
1960 // Clone X+offset as it also folds into most addressing expressions
1961 mstack.push(off, Visit);
1962 mstack.push(m->in(AddPNode::Base), Pre_Visit);
1963 continue; // for(int i = ...)
1964 } // if( off->is_Con() )
1965 } // if( mem_op &&
1966 mstack.push(m, Pre_Visit);
1967 } // for(int i = ...)
1968 }
1969 else if (nstate == Alt_Post_Visit) {
1970 mstack.pop(); // Remove node from stack
1971 // We cannot remove the Cmp input from the Bool here, as the Bool may be
1972 // shared and all users of the Bool need to move the Cmp in parallel.
1973 // This leaves both the Bool and the If pointing at the Cmp. To
1974 // prevent the Matcher from trying to Match the Cmp along both paths
1975 // BoolNode::match_edge always returns a zero.
1976
1977 // We reorder the Op_If in a pre-order manner, so we can visit without
1978 // accidentally sharing the Cmp (the Bool and the If make 2 users).
1979 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
1980 }
1981 else if (nstate == Post_Visit) {
1982 mstack.pop(); // Remove node from stack
1983
1984 // Now hack a few special opcodes
1985 switch( n->Opcode() ) { // Handle some opcodes special
1986 case Op_StorePConditional:
1987 case Op_StoreIConditional:
1988 case Op_StoreLConditional:
1989 case Op_CompareAndSwapI:
1990 case Op_CompareAndSwapL:
1991 case Op_CompareAndSwapP:
1992 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
1993 Node *newval = n->in(MemNode::ValueIn );
1994 Node *oldval = n->in(LoadStoreNode::ExpectedIn);
1995 Node *pair = new (C, 3) BinaryNode( oldval, newval );
1996 n->set_req(MemNode::ValueIn,pair);
1997 n->del_req(LoadStoreNode::ExpectedIn);
1998 break;
1999 }
2000 case Op_CMoveD: // Convert trinary to binary-tree
2001 case Op_CMoveF:
2002 case Op_CMoveI:
2003 case Op_CMoveL:
2004 case Op_CMoveN:
2005 case Op_CMoveP: {
2006 // Restructure into a binary tree for Matching. It's possible that
2007 // we could move this code up next to the graph reshaping for IfNodes
2008 // or vice-versa, but I do not want to debug this for Ladybird.
2009 // 10/2/2000 CNC.
2010 Node *pair1 = new (C, 3) BinaryNode(n->in(1),n->in(1)->in(1));
2011 n->set_req(1,pair1);
2012 Node *pair2 = new (C, 3) BinaryNode(n->in(2),n->in(3));
2013 n->set_req(2,pair2);
2014 n->del_req(3);
2015 break;
2016 }
2017 default:
2018 break;
2019 }
2020 }
2021 else {
2022 ShouldNotReachHere();
2023 }
2024 } // end of while (mstack.is_nonempty())
2025 }
2026
2027 #ifdef ASSERT
2028 // machine-independent root to machine-dependent root
2029 void Matcher::dump_old2new_map() {
2030 _old2new_map.dump();
2031 }
2032 #endif
2033
2034 //---------------------------collect_null_checks-------------------------------
2035 // Find null checks in the ideal graph; write a machine-specific node for
2036 // it. Used by later implicit-null-check handling. Actually collects
2037 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2038 // value being tested.
2039 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2040 Node *iff = proj->in(0);
2041 if( iff->Opcode() == Op_If ) {
2042 // During matching If's have Bool & Cmp side-by-side
2043 BoolNode *b = iff->in(1)->as_Bool();
2044 Node *cmp = iff->in(2);
2045 int opc = cmp->Opcode();
2046 if (opc != Op_CmpP && opc != Op_CmpN) return;
2047
2048 const Type* ct = cmp->in(2)->bottom_type();
2049 if (ct == TypePtr::NULL_PTR ||
2050 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2051
2052 bool push_it = false;
2053 if( proj->Opcode() == Op_IfTrue ) {
2054 extern int all_null_checks_found;
2055 all_null_checks_found++;
2056 if( b->_test._test == BoolTest::ne ) {
2057 push_it = true;
2058 }
2059 } else {
2060 assert( proj->Opcode() == Op_IfFalse, "" );
2061 if( b->_test._test == BoolTest::eq ) {
2062 push_it = true;
2063 }
2064 }
2065 if( push_it ) {
2066 _null_check_tests.push(proj);
2067 Node* val = cmp->in(1);
2068 #ifdef _LP64
2069 if (UseCompressedOops && !Matcher::clone_shift_expressions &&
2070 val->bottom_type()->isa_narrowoop()) {
2071 //
2072 // Look for DecodeN node which should be pinned to orig_proj.
2073 // On platforms (Sparc) which can not handle 2 adds
2074 // in addressing mode we have to keep a DecodeN node and
2075 // use it to do implicit NULL check in address.
2076 //
2077 // DecodeN node was pinned to non-null path (orig_proj) during
2078 // CastPP transformation in final_graph_reshaping_impl().
2079 //
2080 uint cnt = orig_proj->outcnt();
2081 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2082 Node* d = orig_proj->raw_out(i);
2083 if (d->is_DecodeN() && d->in(1) == val) {
2084 val = d;
2085 val->set_req(0, NULL); // Unpin now.
2086 break;
2087 }
2088 }
2089 }
2090 #endif
2091 _null_check_tests.push(val);
2092 }
2093 }
2094 }
2095 }
2096
2097 //---------------------------validate_null_checks------------------------------
2098 // Its possible that the value being NULL checked is not the root of a match
2099 // tree. If so, I cannot use the value in an implicit null check.
2100 void Matcher::validate_null_checks( ) {
2101 uint cnt = _null_check_tests.size();
2102 for( uint i=0; i < cnt; i+=2 ) {
2103 Node *test = _null_check_tests[i];
2104 Node *val = _null_check_tests[i+1];
2105 if (has_new_node(val)) {
2106 // Is a match-tree root, so replace with the matched value
2107 _null_check_tests.map(i+1, new_node(val));
2108 } else {
2109 // Yank from candidate list
2110 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2111 _null_check_tests.map(i,_null_check_tests[--cnt]);
2112 _null_check_tests.pop();
2113 _null_check_tests.pop();
2114 i-=2;
2115 }
2116 }
2117 }
2118
2119
2120 // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock
2121 // acting as an Acquire and thus we don't need an Acquire here. We
2122 // retain the Node to act as a compiler ordering barrier.
2123 bool Matcher::prior_fast_lock( const Node *acq ) {
2124 Node *r = acq->in(0);
2125 if( !r->is_Region() || r->req() <= 1 ) return false;
2126 Node *proj = r->in(1);
2127 if( !proj->is_Proj() ) return false;
2128 Node *call = proj->in(0);
2129 if( !call->is_Call() || call->as_Call()->entry_point() != OptoRuntime::complete_monitor_locking_Java() )
2130 return false;
2131
2132 return true;
2133 }
2134
2135 // Used by the DFA in dfa_sparc.cpp. Check for a following FastUnLock
2136 // acting as a Release and thus we don't need a Release here. We
2137 // retain the Node to act as a compiler ordering barrier.
2138 bool Matcher::post_fast_unlock( const Node *rel ) {
2139 Compile *C = Compile::current();
2140 assert( rel->Opcode() == Op_MemBarRelease, "" );
2141 const MemBarReleaseNode *mem = (const MemBarReleaseNode*)rel;
2142 DUIterator_Fast imax, i = mem->fast_outs(imax);
2143 Node *ctrl = NULL;
2144 while( true ) {
2145 ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found
2146 assert( ctrl->is_Proj(), "only projections here" );
2147 ProjNode *proj = (ProjNode*)ctrl;
2148 if( proj->_con == TypeFunc::Control &&
2149 !C->node_arena()->contains(ctrl) ) // Unmatched old-space only
2150 break;
2151 i++;
2152 }
2153 Node *iff = NULL;
2154 for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) {
2155 Node *x = ctrl->fast_out(j);
2156 if( x->is_If() && x->req() > 1 &&
2157 !C->node_arena()->contains(x) ) { // Unmatched old-space only
2158 iff = x;
2159 break;
2160 }
2161 }
2162 if( !iff ) return false;
2163 Node *bol = iff->in(1);
2164 // The iff might be some random subclass of If or bol might be Con-Top
2165 if (!bol->is_Bool()) return false;
2166 assert( bol->req() > 1, "" );
2167 return (bol->in(1)->Opcode() == Op_FastUnlock);
2168 }
2169
2170 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2171 // atomic instruction acting as a store_load barrier without any
2172 // intervening volatile load, and thus we don't need a barrier here.
2173 // We retain the Node to act as a compiler ordering barrier.
2174 bool Matcher::post_store_load_barrier(const Node *vmb) {
2175 Compile *C = Compile::current();
2176 assert( vmb->is_MemBar(), "" );
2177 assert( vmb->Opcode() != Op_MemBarAcquire, "" );
2178 const MemBarNode *mem = (const MemBarNode*)vmb;
2179
2180 // Get the Proj node, ctrl, that can be used to iterate forward
2181 Node *ctrl = NULL;
2182 DUIterator_Fast imax, i = mem->fast_outs(imax);
2183 while( true ) {
2184 ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found
2185 assert( ctrl->is_Proj(), "only projections here" );
2186 ProjNode *proj = (ProjNode*)ctrl;
2187 if( proj->_con == TypeFunc::Control &&
2188 !C->node_arena()->contains(ctrl) ) // Unmatched old-space only
2189 break;
2190 i++;
2191 }
2192
2193 for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) {
2194 Node *x = ctrl->fast_out(j);
2195 int xop = x->Opcode();
2196
2197 // We don't need current barrier if we see another or a lock
2198 // before seeing volatile load.
2199 //
2200 // Op_Fastunlock previously appeared in the Op_* list below.
2201 // With the advent of 1-0 lock operations we're no longer guaranteed
2202 // that a monitor exit operation contains a serializing instruction.
2203
2204 if (xop == Op_MemBarVolatile ||
2205 xop == Op_FastLock ||
2206 xop == Op_CompareAndSwapL ||
2207 xop == Op_CompareAndSwapP ||
2208 xop == Op_CompareAndSwapN ||
2209 xop == Op_CompareAndSwapI)
2210 return true;
2211
2212 if (x->is_MemBar()) {
2213 // We must retain this membar if there is an upcoming volatile
2214 // load, which will be preceded by acquire membar.
2215 if (xop == Op_MemBarAcquire)
2216 return false;
2217 // For other kinds of barriers, check by pretending we
2218 // are them, and seeing if we can be removed.
2219 else
2220 return post_store_load_barrier((const MemBarNode*)x);
2221 }
2222
2223 // Delicate code to detect case of an upcoming fastlock block
2224 if( x->is_If() && x->req() > 1 &&
2225 !C->node_arena()->contains(x) ) { // Unmatched old-space only
2226 Node *iff = x;
2227 Node *bol = iff->in(1);
2228 // The iff might be some random subclass of If or bol might be Con-Top
2229 if (!bol->is_Bool()) return false;
2230 assert( bol->req() > 1, "" );
2231 return (bol->in(1)->Opcode() == Op_FastUnlock);
2232 }
2233 // probably not necessary to check for these
2234 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj())
2235 return false;
2236 }
2237 return false;
2238 }
2239
2240 //=============================================================================
2241 //---------------------------State---------------------------------------------
2242 State::State(void) {
2243 #ifdef ASSERT
2244 _id = 0;
2245 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2246 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2247 //memset(_cost, -1, sizeof(_cost));
2248 //memset(_rule, -1, sizeof(_rule));
2249 #endif
2250 memset(_valid, 0, sizeof(_valid));
2251 }
2252
2253 #ifdef ASSERT
2254 State::~State() {
2255 _id = 99;
2256 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2257 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2258 memset(_cost, -3, sizeof(_cost));
2259 memset(_rule, -3, sizeof(_rule));
2260 }
2261 #endif
2262
2263 #ifndef PRODUCT
2264 //---------------------------dump----------------------------------------------
2265 void State::dump() {
2266 tty->print("\n");
2267 dump(0);
2268 }
2269
2270 void State::dump(int depth) {
2271 for( int j = 0; j < depth; j++ )
2272 tty->print(" ");
2273 tty->print("--N: ");
2274 _leaf->dump();
2275 uint i;
2276 for( i = 0; i < _LAST_MACH_OPER; i++ )
2277 // Check for valid entry
2278 if( valid(i) ) {
2279 for( int j = 0; j < depth; j++ )
2280 tty->print(" ");
2281 assert(_cost[i] != max_juint, "cost must be a valid value");
2282 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2283 tty->print_cr("%s %d %s",
2284 ruleName[i], _cost[i], ruleName[_rule[i]] );
2285 }
2286 tty->print_cr("");
2287
2288 for( i=0; i<2; i++ )
2289 if( _kids[i] )
2290 _kids[i]->dump(depth+1);
2291 }
2292 #endif