1 /*
2 * Copyright 1997-2009 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 #include "incls/_precompiled.incl"
26 #include "incls/_assembler_sparc.cpp.incl"
27
28 // Convert the raw encoding form into the form expected by the
29 // constructor for Address.
30 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) {
31 assert(scale == 0, "not supported");
32 RelocationHolder rspec;
33 if (disp_is_oop) {
34 rspec = Relocation::spec_simple(relocInfo::oop_type);
35 }
36
37 Register rindex = as_Register(index);
38 if (rindex != G0) {
39 Address madr(as_Register(base), rindex);
40 madr._rspec = rspec;
41 return madr;
42 } else {
43 Address madr(as_Register(base), disp);
44 madr._rspec = rspec;
45 return madr;
46 }
47 }
48
49 Address Argument::address_in_frame() const {
50 // Warning: In LP64 mode disp will occupy more than 10 bits, but
51 // op codes such as ld or ldx, only access disp() to get
52 // their simm13 argument.
53 int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS;
54 if (is_in())
55 return Address(FP, disp); // In argument.
56 else
57 return Address(SP, disp); // Out argument.
58 }
59
60 static const char* argumentNames[][2] = {
61 {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"},
62 {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"},
63 {"A(n>9)","P(n>9)"}
64 };
65
66 const char* Argument::name() const {
67 int nofArgs = sizeof argumentNames / sizeof argumentNames[0];
68 int num = number();
69 if (num >= nofArgs) num = nofArgs - 1;
70 return argumentNames[num][is_in() ? 1 : 0];
71 }
72
73 void Assembler::print_instruction(int inst) {
74 const char* s;
75 switch (inv_op(inst)) {
76 default: s = "????"; break;
77 case call_op: s = "call"; break;
78 case branch_op:
79 switch (inv_op2(inst)) {
80 case bpr_op2: s = "bpr"; break;
81 case fb_op2: s = "fb"; break;
82 case fbp_op2: s = "fbp"; break;
83 case br_op2: s = "br"; break;
84 case bp_op2: s = "bp"; break;
85 case cb_op2: s = "cb"; break;
86 default: s = "????"; break;
87 }
88 }
89 ::tty->print("%s", s);
90 }
91
92
93 // Patch instruction inst at offset inst_pos to refer to dest_pos
94 // and return the resulting instruction.
95 // We should have pcs, not offsets, but since all is relative, it will work out
96 // OK.
97 int Assembler::patched_branch(int dest_pos, int inst, int inst_pos) {
98
99 int m; // mask for displacement field
100 int v; // new value for displacement field
101 const int word_aligned_ones = -4;
102 switch (inv_op(inst)) {
103 default: ShouldNotReachHere();
104 case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break;
105 case branch_op:
106 switch (inv_op2(inst)) {
107 case bpr_op2: m = wdisp16(word_aligned_ones, 0); v = wdisp16(dest_pos, inst_pos); break;
108 case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break;
109 case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break;
110 case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
111 case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
112 case cb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break;
113 default: ShouldNotReachHere();
114 }
115 }
116 return inst & ~m | v;
117 }
118
119 // Return the offset of the branch destionation of instruction inst
120 // at offset pos.
121 // Should have pcs, but since all is relative, it works out.
122 int Assembler::branch_destination(int inst, int pos) {
123 int r;
124 switch (inv_op(inst)) {
125 default: ShouldNotReachHere();
126 case call_op: r = inv_wdisp(inst, pos, 30); break;
127 case branch_op:
128 switch (inv_op2(inst)) {
129 case bpr_op2: r = inv_wdisp16(inst, pos); break;
130 case fbp_op2: r = inv_wdisp( inst, pos, 19); break;
131 case bp_op2: r = inv_wdisp( inst, pos, 19); break;
132 case fb_op2: r = inv_wdisp( inst, pos, 22); break;
133 case br_op2: r = inv_wdisp( inst, pos, 22); break;
134 case cb_op2: r = inv_wdisp( inst, pos, 22); break;
135 default: ShouldNotReachHere();
136 }
137 }
138 return r;
139 }
140
141 int AbstractAssembler::code_fill_byte() {
142 return 0x00; // illegal instruction 0x00000000
143 }
144
145 Assembler::Condition Assembler::reg_cond_to_cc_cond(Assembler::RCondition in) {
146 switch (in) {
147 case rc_z: return equal;
148 case rc_lez: return lessEqual;
149 case rc_lz: return less;
150 case rc_nz: return notEqual;
151 case rc_gz: return greater;
152 case rc_gez: return greaterEqual;
153 default:
154 ShouldNotReachHere();
155 }
156 return equal;
157 }
158
159 // Generate a bunch 'o stuff (including v9's
160 #ifndef PRODUCT
161 void Assembler::test_v9() {
162 add( G0, G1, G2 );
163 add( G3, 0, G4 );
164
165 addcc( G5, G6, G7 );
166 addcc( I0, 1, I1 );
167 addc( I2, I3, I4 );
168 addc( I5, -1, I6 );
169 addccc( I7, L0, L1 );
170 addccc( L2, (1 << 12) - 2, L3 );
171
172 Label lbl1, lbl2, lbl3;
173
174 bind(lbl1);
175
176 bpr( rc_z, true, pn, L4, pc(), relocInfo::oop_type );
177 delayed()->nop();
178 bpr( rc_lez, false, pt, L5, lbl1);
179 delayed()->nop();
180
181 fb( f_never, true, pc() + 4, relocInfo::none);
182 delayed()->nop();
183 fb( f_notEqual, false, lbl2 );
184 delayed()->nop();
185
186 fbp( f_notZero, true, fcc0, pn, pc() - 4, relocInfo::none);
187 delayed()->nop();
188 fbp( f_lessOrGreater, false, fcc1, pt, lbl3 );
189 delayed()->nop();
190
191 br( equal, true, pc() + 1024, relocInfo::none);
192 delayed()->nop();
193 br( lessEqual, false, lbl1 );
194 delayed()->nop();
195 br( never, false, lbl1 );
196 delayed()->nop();
197
198 bp( less, true, icc, pn, pc(), relocInfo::none);
199 delayed()->nop();
200 bp( lessEqualUnsigned, false, xcc, pt, lbl2 );
201 delayed()->nop();
202
203 call( pc(), relocInfo::none);
204 delayed()->nop();
205 call( lbl3 );
206 delayed()->nop();
207
208
209 casa( L6, L7, O0 );
210 casxa( O1, O2, O3, 0 );
211
212 udiv( O4, O5, O7 );
213 udiv( G0, (1 << 12) - 1, G1 );
214 sdiv( G1, G2, G3 );
215 sdiv( G4, -((1 << 12) - 1), G5 );
216 udivcc( G6, G7, I0 );
217 udivcc( I1, -((1 << 12) - 2), I2 );
218 sdivcc( I3, I4, I5 );
219 sdivcc( I6, -((1 << 12) - 0), I7 );
220
221 done();
222 retry();
223
224 fadd( FloatRegisterImpl::S, F0, F1, F2 );
225 fsub( FloatRegisterImpl::D, F34, F0, F62 );
226
227 fcmp( FloatRegisterImpl::Q, fcc0, F0, F60);
228 fcmpe( FloatRegisterImpl::S, fcc1, F31, F30);
229
230 ftox( FloatRegisterImpl::D, F2, F4 );
231 ftoi( FloatRegisterImpl::Q, F4, F8 );
232
233 ftof( FloatRegisterImpl::S, FloatRegisterImpl::Q, F3, F12 );
234
235 fxtof( FloatRegisterImpl::S, F4, F5 );
236 fitof( FloatRegisterImpl::D, F6, F8 );
237
238 fmov( FloatRegisterImpl::Q, F16, F20 );
239 fneg( FloatRegisterImpl::S, F6, F7 );
240 fabs( FloatRegisterImpl::D, F10, F12 );
241
242 fmul( FloatRegisterImpl::Q, F24, F28, F32 );
243 fmul( FloatRegisterImpl::S, FloatRegisterImpl::D, F8, F9, F14 );
244 fdiv( FloatRegisterImpl::S, F10, F11, F12 );
245
246 fsqrt( FloatRegisterImpl::S, F13, F14 );
247
248 flush( L0, L1 );
249 flush( L2, -1 );
250
251 flushw();
252
253 illtrap( (1 << 22) - 2);
254
255 impdep1( 17, (1 << 19) - 1 );
256 impdep2( 3, 0 );
257
258 jmpl( L3, L4, L5 );
259 delayed()->nop();
260 jmpl( L6, -1, L7, Relocation::spec_simple(relocInfo::none));
261 delayed()->nop();
262
263
264 ldf( FloatRegisterImpl::S, O0, O1, F15 );
265 ldf( FloatRegisterImpl::D, O2, -1, F14 );
266
267
268 ldfsr( O3, O4 );
269 ldfsr( O5, -1 );
270 ldxfsr( O6, O7 );
271 ldxfsr( I0, -1 );
272
273 ldfa( FloatRegisterImpl::D, I1, I2, 1, F16 );
274 ldfa( FloatRegisterImpl::Q, I3, -1, F36 );
275
276 ldsb( I4, I5, I6 );
277 ldsb( I7, -1, G0 );
278 ldsh( G1, G3, G4 );
279 ldsh( G5, -1, G6 );
280 ldsw( G7, L0, L1 );
281 ldsw( L2, -1, L3 );
282 ldub( L4, L5, L6 );
283 ldub( L7, -1, O0 );
284 lduh( O1, O2, O3 );
285 lduh( O4, -1, O5 );
286 lduw( O6, O7, G0 );
287 lduw( G1, -1, G2 );
288 ldx( G3, G4, G5 );
289 ldx( G6, -1, G7 );
290 ldd( I0, I1, I2 );
291 ldd( I3, -1, I4 );
292
293 ldsba( I5, I6, 2, I7 );
294 ldsba( L0, -1, L1 );
295 ldsha( L2, L3, 3, L4 );
296 ldsha( L5, -1, L6 );
297 ldswa( L7, O0, (1 << 8) - 1, O1 );
298 ldswa( O2, -1, O3 );
299 lduba( O4, O5, 0, O6 );
300 lduba( O7, -1, I0 );
301 lduha( I1, I2, 1, I3 );
302 lduha( I4, -1, I5 );
303 lduwa( I6, I7, 2, L0 );
304 lduwa( L1, -1, L2 );
305 ldxa( L3, L4, 3, L5 );
306 ldxa( L6, -1, L7 );
307 ldda( G0, G1, 4, G2 );
308 ldda( G3, -1, G4 );
309
310 ldstub( G5, G6, G7 );
311 ldstub( O0, -1, O1 );
312
313 ldstuba( O2, O3, 5, O4 );
314 ldstuba( O5, -1, O6 );
315
316 and3( I0, L0, O0 );
317 and3( G7, -1, O7 );
318 andcc( L2, I2, G2 );
319 andcc( L4, -1, G4 );
320 andn( I5, I6, I7 );
321 andn( I6, -1, I7 );
322 andncc( I5, I6, I7 );
323 andncc( I7, -1, I6 );
324 or3( I5, I6, I7 );
325 or3( I7, -1, I6 );
326 orcc( I5, I6, I7 );
327 orcc( I7, -1, I6 );
328 orn( I5, I6, I7 );
329 orn( I7, -1, I6 );
330 orncc( I5, I6, I7 );
331 orncc( I7, -1, I6 );
332 xor3( I5, I6, I7 );
333 xor3( I7, -1, I6 );
334 xorcc( I5, I6, I7 );
335 xorcc( I7, -1, I6 );
336 xnor( I5, I6, I7 );
337 xnor( I7, -1, I6 );
338 xnorcc( I5, I6, I7 );
339 xnorcc( I7, -1, I6 );
340
341 membar( Membar_mask_bits(StoreStore | LoadStore | StoreLoad | LoadLoad | Sync | MemIssue | Lookaside ) );
342 membar( StoreStore );
343 membar( LoadStore );
344 membar( StoreLoad );
345 membar( LoadLoad );
346 membar( Sync );
347 membar( MemIssue );
348 membar( Lookaside );
349
350 fmov( FloatRegisterImpl::S, f_ordered, true, fcc2, F16, F17 );
351 fmov( FloatRegisterImpl::D, rc_lz, L5, F18, F20 );
352
353 movcc( overflowClear, false, icc, I6, L4 );
354 movcc( f_unorderedOrEqual, true, fcc2, (1 << 10) - 1, O0 );
355
356 movr( rc_nz, I5, I6, I7 );
357 movr( rc_gz, L1, -1, L2 );
358
359 mulx( I5, I6, I7 );
360 mulx( I7, -1, I6 );
361 sdivx( I5, I6, I7 );
362 sdivx( I7, -1, I6 );
363 udivx( I5, I6, I7 );
364 udivx( I7, -1, I6 );
365
366 umul( I5, I6, I7 );
367 umul( I7, -1, I6 );
368 smul( I5, I6, I7 );
369 smul( I7, -1, I6 );
370 umulcc( I5, I6, I7 );
371 umulcc( I7, -1, I6 );
372 smulcc( I5, I6, I7 );
373 smulcc( I7, -1, I6 );
374
375 mulscc( I5, I6, I7 );
376 mulscc( I7, -1, I6 );
377
378 nop();
379
380
381 popc( G0, G1);
382 popc( -1, G2);
383
384 prefetch( L1, L2, severalReads );
385 prefetch( L3, -1, oneRead );
386 prefetcha( O3, O2, 6, severalWritesAndPossiblyReads );
387 prefetcha( G2, -1, oneWrite );
388
389 rett( I7, I7);
390 delayed()->nop();
391 rett( G0, -1, relocInfo::none);
392 delayed()->nop();
393
394 save( I5, I6, I7 );
395 save( I7, -1, I6 );
396 restore( I5, I6, I7 );
397 restore( I7, -1, I6 );
398
399 saved();
400 restored();
401
402 sethi( 0xaaaaaaaa, I3, Relocation::spec_simple(relocInfo::none));
403
404 sll( I5, I6, I7 );
405 sll( I7, 31, I6 );
406 srl( I5, I6, I7 );
407 srl( I7, 0, I6 );
408 sra( I5, I6, I7 );
409 sra( I7, 30, I6 );
410 sllx( I5, I6, I7 );
411 sllx( I7, 63, I6 );
412 srlx( I5, I6, I7 );
413 srlx( I7, 0, I6 );
414 srax( I5, I6, I7 );
415 srax( I7, 62, I6 );
416
417 sir( -1 );
418
419 stbar();
420
421 stf( FloatRegisterImpl::Q, F40, G0, I7 );
422 stf( FloatRegisterImpl::S, F18, I3, -1 );
423
424 stfsr( L1, L2 );
425 stfsr( I7, -1 );
426 stxfsr( I6, I5 );
427 stxfsr( L4, -1 );
428
429 stfa( FloatRegisterImpl::D, F22, I6, I7, 7 );
430 stfa( FloatRegisterImpl::Q, F44, G0, -1 );
431
432 stb( L5, O2, I7 );
433 stb( I7, I6, -1 );
434 sth( L5, O2, I7 );
435 sth( I7, I6, -1 );
436 stw( L5, O2, I7 );
437 stw( I7, I6, -1 );
438 stx( L5, O2, I7 );
439 stx( I7, I6, -1 );
440 std( L5, O2, I7 );
441 std( I7, I6, -1 );
442
443 stba( L5, O2, I7, 8 );
444 stba( I7, I6, -1 );
445 stha( L5, O2, I7, 9 );
446 stha( I7, I6, -1 );
447 stwa( L5, O2, I7, 0 );
448 stwa( I7, I6, -1 );
449 stxa( L5, O2, I7, 11 );
450 stxa( I7, I6, -1 );
451 stda( L5, O2, I7, 12 );
452 stda( I7, I6, -1 );
453
454 sub( I5, I6, I7 );
455 sub( I7, -1, I6 );
456 subcc( I5, I6, I7 );
457 subcc( I7, -1, I6 );
458 subc( I5, I6, I7 );
459 subc( I7, -1, I6 );
460 subccc( I5, I6, I7 );
461 subccc( I7, -1, I6 );
462
463 swap( I5, I6, I7 );
464 swap( I7, -1, I6 );
465
466 swapa( G0, G1, 13, G2 );
467 swapa( I7, -1, I6 );
468
469 taddcc( I5, I6, I7 );
470 taddcc( I7, -1, I6 );
471 taddcctv( I5, I6, I7 );
472 taddcctv( I7, -1, I6 );
473
474 tsubcc( I5, I6, I7 );
475 tsubcc( I7, -1, I6 );
476 tsubcctv( I5, I6, I7 );
477 tsubcctv( I7, -1, I6 );
478
479 trap( overflowClear, xcc, G0, G1 );
480 trap( lessEqual, icc, I7, 17 );
481
482 bind(lbl2);
483 bind(lbl3);
484
485 code()->decode();
486 }
487
488 // Generate a bunch 'o stuff unique to V8
489 void Assembler::test_v8_onlys() {
490 Label lbl1;
491
492 cb( cp_0or1or2, false, pc() - 4, relocInfo::none);
493 delayed()->nop();
494 cb( cp_never, true, lbl1);
495 delayed()->nop();
496
497 cpop1(1, 2, 3, 4);
498 cpop2(5, 6, 7, 8);
499
500 ldc( I0, I1, 31);
501 ldc( I2, -1, 0);
502
503 lddc( I4, I4, 30);
504 lddc( I6, 0, 1 );
505
506 ldcsr( L0, L1, 0);
507 ldcsr( L1, (1 << 12) - 1, 17 );
508
509 stc( 31, L4, L5);
510 stc( 30, L6, -(1 << 12) );
511
512 stdc( 0, L7, G0);
513 stdc( 1, G1, 0 );
514
515 stcsr( 16, G2, G3);
516 stcsr( 17, G4, 1 );
517
518 stdcq( 4, G5, G6);
519 stdcq( 5, G7, -1 );
520
521 bind(lbl1);
522
523 code()->decode();
524 }
525 #endif
526
527 // Implementation of MacroAssembler
528
529 void MacroAssembler::null_check(Register reg, int offset) {
530 if (needs_explicit_null_check((intptr_t)offset)) {
531 // provoke OS NULL exception if reg = NULL by
532 // accessing M[reg] w/o changing any registers
533 ld_ptr(reg, 0, G0);
534 }
535 else {
536 // nothing to do, (later) access of M[reg + offset]
537 // will provoke OS NULL exception if reg = NULL
538 }
539 }
540
541 // Ring buffer jumps
542
543 #ifndef PRODUCT
544 void MacroAssembler::ret( bool trace ) { if (trace) {
545 mov(I7, O7); // traceable register
546 JMP(O7, 2 * BytesPerInstWord);
547 } else {
548 jmpl( I7, 2 * BytesPerInstWord, G0 );
549 }
550 }
551
552 void MacroAssembler::retl( bool trace ) { if (trace) JMP(O7, 2 * BytesPerInstWord);
553 else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
554 #endif /* PRODUCT */
555
556
557 void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) {
558 assert_not_delayed();
559 // This can only be traceable if r1 & r2 are visible after a window save
560 if (TraceJumps) {
561 #ifndef PRODUCT
562 save_frame(0);
563 verify_thread();
564 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
565 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
566 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
567 add(O2, O1, O1);
568
569 add(r1->after_save(), r2->after_save(), O2);
570 set((intptr_t)file, O3);
571 set(line, O4);
572 Label L;
573 // get nearby pc, store jmp target
574 call(L, relocInfo::none); // No relocation for call to pc+0x8
575 delayed()->st(O2, O1, 0);
576 bind(L);
577
578 // store nearby pc
579 st(O7, O1, sizeof(intptr_t));
580 // store file
581 st(O3, O1, 2*sizeof(intptr_t));
582 // store line
583 st(O4, O1, 3*sizeof(intptr_t));
584 add(O0, 1, O0);
585 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
586 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
587 restore();
588 #endif /* PRODUCT */
589 }
590 jmpl(r1, r2, G0);
591 }
592 void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) {
593 assert_not_delayed();
594 // This can only be traceable if r1 is visible after a window save
595 if (TraceJumps) {
596 #ifndef PRODUCT
597 save_frame(0);
598 verify_thread();
599 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
600 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
601 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
602 add(O2, O1, O1);
603
604 add(r1->after_save(), offset, O2);
605 set((intptr_t)file, O3);
606 set(line, O4);
607 Label L;
608 // get nearby pc, store jmp target
609 call(L, relocInfo::none); // No relocation for call to pc+0x8
610 delayed()->st(O2, O1, 0);
611 bind(L);
612
613 // store nearby pc
614 st(O7, O1, sizeof(intptr_t));
615 // store file
616 st(O3, O1, 2*sizeof(intptr_t));
617 // store line
618 st(O4, O1, 3*sizeof(intptr_t));
619 add(O0, 1, O0);
620 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
621 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
622 restore();
623 #endif /* PRODUCT */
624 }
625 jmp(r1, offset);
626 }
627
628 // This code sequence is relocatable to any address, even on LP64.
629 void MacroAssembler::jumpl(AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line) {
630 assert_not_delayed();
631 // Force fixed length sethi because NativeJump and NativeFarCall don't handle
632 // variable length instruction streams.
633 patchable_sethi(addrlit, temp);
634 Address a(temp, addrlit.low10() + offset); // Add the offset to the displacement.
635 if (TraceJumps) {
636 #ifndef PRODUCT
637 // Must do the add here so relocation can find the remainder of the
638 // value to be relocated.
639 add(a.base(), a.disp(), a.base(), addrlit.rspec(offset));
640 save_frame(0);
641 verify_thread();
642 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0);
643 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1);
644 sll(O0, exact_log2(4*sizeof(intptr_t)), O2);
645 add(O2, O1, O1);
646
647 set((intptr_t)file, O3);
648 set(line, O4);
649 Label L;
650
651 // get nearby pc, store jmp target
652 call(L, relocInfo::none); // No relocation for call to pc+0x8
653 delayed()->st(a.base()->after_save(), O1, 0);
654 bind(L);
655
656 // store nearby pc
657 st(O7, O1, sizeof(intptr_t));
658 // store file
659 st(O3, O1, 2*sizeof(intptr_t));
660 // store line
661 st(O4, O1, 3*sizeof(intptr_t));
662 add(O0, 1, O0);
663 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0);
664 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()));
665 restore();
666 jmpl(a.base(), G0, d);
667 #else
668 jmpl(a.base(), a.disp(), d);
669 #endif /* PRODUCT */
670 } else {
671 jmpl(a.base(), a.disp(), d);
672 }
673 }
674
675 void MacroAssembler::jump(AddressLiteral& addrlit, Register temp, int offset, const char* file, int line) {
676 jumpl(addrlit, temp, G0, offset, file, line);
677 }
678
679
680 // Convert to C varargs format
681 void MacroAssembler::set_varargs( Argument inArg, Register d ) {
682 // spill register-resident args to their memory slots
683 // (SPARC calling convention requires callers to have already preallocated these)
684 // Note that the inArg might in fact be an outgoing argument,
685 // if a leaf routine or stub does some tricky argument shuffling.
686 // This routine must work even though one of the saved arguments
687 // is in the d register (e.g., set_varargs(Argument(0, false), O0)).
688 for (Argument savePtr = inArg;
689 savePtr.is_register();
690 savePtr = savePtr.successor()) {
691 st_ptr(savePtr.as_register(), savePtr.address_in_frame());
692 }
693 // return the address of the first memory slot
694 Address a = inArg.address_in_frame();
695 add(a.base(), a.disp(), d);
696 }
697
698 // Conditional breakpoint (for assertion checks in assembly code)
699 void MacroAssembler::breakpoint_trap(Condition c, CC cc) {
700 trap(c, cc, G0, ST_RESERVED_FOR_USER_0);
701 }
702
703 // We want to use ST_BREAKPOINT here, but the debugger is confused by it.
704 void MacroAssembler::breakpoint_trap() {
705 trap(ST_RESERVED_FOR_USER_0);
706 }
707
708 // flush windows (except current) using flushw instruction if avail.
709 void MacroAssembler::flush_windows() {
710 if (VM_Version::v9_instructions_work()) flushw();
711 else flush_windows_trap();
712 }
713
714 // Write serialization page so VM thread can do a pseudo remote membar
715 // We use the current thread pointer to calculate a thread specific
716 // offset to write to within the page. This minimizes bus traffic
717 // due to cache line collision.
718 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {
719 srl(thread, os::get_serialize_page_shift_count(), tmp2);
720 if (Assembler::is_simm13(os::vm_page_size())) {
721 and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2);
722 }
723 else {
724 set((os::vm_page_size() - sizeof(int)), tmp1);
725 and3(tmp2, tmp1, tmp2);
726 }
727 set(os::get_memory_serialize_page(), tmp1);
728 st(G0, tmp1, tmp2);
729 }
730
731
732
733 void MacroAssembler::enter() {
734 Unimplemented();
735 }
736
737 void MacroAssembler::leave() {
738 Unimplemented();
739 }
740
741 void MacroAssembler::mult(Register s1, Register s2, Register d) {
742 if(VM_Version::v9_instructions_work()) {
743 mulx (s1, s2, d);
744 } else {
745 smul (s1, s2, d);
746 }
747 }
748
749 void MacroAssembler::mult(Register s1, int simm13a, Register d) {
750 if(VM_Version::v9_instructions_work()) {
751 mulx (s1, simm13a, d);
752 } else {
753 smul (s1, simm13a, d);
754 }
755 }
756
757
758 #ifdef ASSERT
759 void MacroAssembler::read_ccr_v8_assert(Register ccr_save) {
760 const Register s1 = G3_scratch;
761 const Register s2 = G4_scratch;
762 Label get_psr_test;
763 // Get the condition codes the V8 way.
764 read_ccr_trap(s1);
765 mov(ccr_save, s2);
766 // This is a test of V8 which has icc but not xcc
767 // so mask off the xcc bits
768 and3(s2, 0xf, s2);
769 // Compare condition codes from the V8 and V9 ways.
770 subcc(s2, s1, G0);
771 br(Assembler::notEqual, true, Assembler::pt, get_psr_test);
772 delayed()->breakpoint_trap();
773 bind(get_psr_test);
774 }
775
776 void MacroAssembler::write_ccr_v8_assert(Register ccr_save) {
777 const Register s1 = G3_scratch;
778 const Register s2 = G4_scratch;
779 Label set_psr_test;
780 // Write out the saved condition codes the V8 way
781 write_ccr_trap(ccr_save, s1, s2);
782 // Read back the condition codes using the V9 instruction
783 rdccr(s1);
784 mov(ccr_save, s2);
785 // This is a test of V8 which has icc but not xcc
786 // so mask off the xcc bits
787 and3(s2, 0xf, s2);
788 and3(s1, 0xf, s1);
789 // Compare the V8 way with the V9 way.
790 subcc(s2, s1, G0);
791 br(Assembler::notEqual, true, Assembler::pt, set_psr_test);
792 delayed()->breakpoint_trap();
793 bind(set_psr_test);
794 }
795 #else
796 #define read_ccr_v8_assert(x)
797 #define write_ccr_v8_assert(x)
798 #endif // ASSERT
799
800 void MacroAssembler::read_ccr(Register ccr_save) {
801 if (VM_Version::v9_instructions_work()) {
802 rdccr(ccr_save);
803 // Test code sequence used on V8. Do not move above rdccr.
804 read_ccr_v8_assert(ccr_save);
805 } else {
806 read_ccr_trap(ccr_save);
807 }
808 }
809
810 void MacroAssembler::write_ccr(Register ccr_save) {
811 if (VM_Version::v9_instructions_work()) {
812 // Test code sequence used on V8. Do not move below wrccr.
813 write_ccr_v8_assert(ccr_save);
814 wrccr(ccr_save);
815 } else {
816 const Register temp_reg1 = G3_scratch;
817 const Register temp_reg2 = G4_scratch;
818 write_ccr_trap(ccr_save, temp_reg1, temp_reg2);
819 }
820 }
821
822
823 // Calls to C land
824
825 #ifdef ASSERT
826 // a hook for debugging
827 static Thread* reinitialize_thread() {
828 return ThreadLocalStorage::thread();
829 }
830 #else
831 #define reinitialize_thread ThreadLocalStorage::thread
832 #endif
833
834 #ifdef ASSERT
835 address last_get_thread = NULL;
836 #endif
837
838 // call this when G2_thread is not known to be valid
839 void MacroAssembler::get_thread() {
840 save_frame(0); // to avoid clobbering O0
841 mov(G1, L0); // avoid clobbering G1
842 mov(G5_method, L1); // avoid clobbering G5
843 mov(G3, L2); // avoid clobbering G3 also
844 mov(G4, L5); // avoid clobbering G4
845 #ifdef ASSERT
846 AddressLiteral last_get_thread_addrlit(&last_get_thread);
847 set(last_get_thread_addrlit, L3);
848 inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call
849 st_ptr(L4, L3, 0);
850 #endif
851 call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type);
852 delayed()->nop();
853 mov(L0, G1);
854 mov(L1, G5_method);
855 mov(L2, G3);
856 mov(L5, G4);
857 restore(O0, 0, G2_thread);
858 }
859
860 static Thread* verify_thread_subroutine(Thread* gthread_value) {
861 Thread* correct_value = ThreadLocalStorage::thread();
862 guarantee(gthread_value == correct_value, "G2_thread value must be the thread");
863 return correct_value;
864 }
865
866 void MacroAssembler::verify_thread() {
867 if (VerifyThread) {
868 // NOTE: this chops off the heads of the 64-bit O registers.
869 #ifdef CC_INTERP
870 save_frame(0);
871 #else
872 // make sure G2_thread contains the right value
873 save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof)
874 mov(G1, L1); // avoid clobbering G1
875 // G2 saved below
876 mov(G3, L3); // avoid clobbering G3
877 mov(G4, L4); // avoid clobbering G4
878 mov(G5_method, L5); // avoid clobbering G5_method
879 #endif /* CC_INTERP */
880 #if defined(COMPILER2) && !defined(_LP64)
881 // Save & restore possible 64-bit Long arguments in G-regs
882 srlx(G1,32,L0);
883 srlx(G4,32,L6);
884 #endif
885 call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type);
886 delayed()->mov(G2_thread, O0);
887
888 mov(L1, G1); // Restore G1
889 // G2 restored below
890 mov(L3, G3); // restore G3
891 mov(L4, G4); // restore G4
892 mov(L5, G5_method); // restore G5_method
893 #if defined(COMPILER2) && !defined(_LP64)
894 // Save & restore possible 64-bit Long arguments in G-regs
895 sllx(L0,32,G2); // Move old high G1 bits high in G2
896 sllx(G1, 0,G1); // Clear current high G1 bits
897 or3 (G1,G2,G1); // Recover 64-bit G1
898 sllx(L6,32,G2); // Move old high G4 bits high in G2
899 sllx(G4, 0,G4); // Clear current high G4 bits
900 or3 (G4,G2,G4); // Recover 64-bit G4
901 #endif
902 restore(O0, 0, G2_thread);
903 }
904 }
905
906
907 void MacroAssembler::save_thread(const Register thread_cache) {
908 verify_thread();
909 if (thread_cache->is_valid()) {
910 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");
911 mov(G2_thread, thread_cache);
912 }
913 if (VerifyThread) {
914 // smash G2_thread, as if the VM were about to anyway
915 set(0x67676767, G2_thread);
916 }
917 }
918
919
920 void MacroAssembler::restore_thread(const Register thread_cache) {
921 if (thread_cache->is_valid()) {
922 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile");
923 mov(thread_cache, G2_thread);
924 verify_thread();
925 } else {
926 // do it the slow way
927 get_thread();
928 }
929 }
930
931
932 // %%% maybe get rid of [re]set_last_Java_frame
933 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) {
934 assert_not_delayed();
935 Address flags(G2_thread, JavaThread::frame_anchor_offset() +
936 JavaFrameAnchor::flags_offset());
937 Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset());
938
939 // Always set last_Java_pc and flags first because once last_Java_sp is visible
940 // has_last_Java_frame is true and users will look at the rest of the fields.
941 // (Note: flags should always be zero before we get here so doesn't need to be set.)
942
943 #ifdef ASSERT
944 // Verify that flags was zeroed on return to Java
945 Label PcOk;
946 save_frame(0); // to avoid clobbering O0
947 ld_ptr(pc_addr, L0);
948 tst(L0);
949 #ifdef _LP64
950 brx(Assembler::zero, false, Assembler::pt, PcOk);
951 #else
952 br(Assembler::zero, false, Assembler::pt, PcOk);
953 #endif // _LP64
954 delayed() -> nop();
955 stop("last_Java_pc not zeroed before leaving Java");
956 bind(PcOk);
957
958 // Verify that flags was zeroed on return to Java
959 Label FlagsOk;
960 ld(flags, L0);
961 tst(L0);
962 br(Assembler::zero, false, Assembler::pt, FlagsOk);
963 delayed() -> restore();
964 stop("flags not zeroed before leaving Java");
965 bind(FlagsOk);
966 #endif /* ASSERT */
967 //
968 // When returning from calling out from Java mode the frame anchor's last_Java_pc
969 // will always be set to NULL. It is set here so that if we are doing a call to
970 // native (not VM) that we capture the known pc and don't have to rely on the
971 // native call having a standard frame linkage where we can find the pc.
972
973 if (last_Java_pc->is_valid()) {
974 st_ptr(last_Java_pc, pc_addr);
975 }
976
977 #ifdef _LP64
978 #ifdef ASSERT
979 // Make sure that we have an odd stack
980 Label StackOk;
981 andcc(last_java_sp, 0x01, G0);
982 br(Assembler::notZero, false, Assembler::pt, StackOk);
983 delayed() -> nop();
984 stop("Stack Not Biased in set_last_Java_frame");
985 bind(StackOk);
986 #endif // ASSERT
987 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame");
988 add( last_java_sp, STACK_BIAS, G4_scratch );
989 st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset());
990 #else
991 st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset());
992 #endif // _LP64
993 }
994
995 void MacroAssembler::reset_last_Java_frame(void) {
996 assert_not_delayed();
997
998 Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset());
999 Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
1000 Address flags (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
1001
1002 #ifdef ASSERT
1003 // check that it WAS previously set
1004 #ifdef CC_INTERP
1005 save_frame(0);
1006 #else
1007 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof
1008 #endif /* CC_INTERP */
1009 ld_ptr(sp_addr, L0);
1010 tst(L0);
1011 breakpoint_trap(Assembler::zero, Assembler::ptr_cc);
1012 restore();
1013 #endif // ASSERT
1014
1015 st_ptr(G0, sp_addr);
1016 // Always return last_Java_pc to zero
1017 st_ptr(G0, pc_addr);
1018 // Always null flags after return to Java
1019 st(G0, flags);
1020 }
1021
1022
1023 void MacroAssembler::call_VM_base(
1024 Register oop_result,
1025 Register thread_cache,
1026 Register last_java_sp,
1027 address entry_point,
1028 int number_of_arguments,
1029 bool check_exceptions)
1030 {
1031 assert_not_delayed();
1032
1033 // determine last_java_sp register
1034 if (!last_java_sp->is_valid()) {
1035 last_java_sp = SP;
1036 }
1037 // debugging support
1038 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1039
1040 // 64-bit last_java_sp is biased!
1041 set_last_Java_frame(last_java_sp, noreg);
1042 if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early
1043 save_thread(thread_cache);
1044 // do the call
1045 call(entry_point, relocInfo::runtime_call_type);
1046 if (!VerifyThread)
1047 delayed()->mov(G2_thread, O0); // pass thread as first argument
1048 else
1049 delayed()->nop(); // (thread already passed)
1050 restore_thread(thread_cache);
1051 reset_last_Java_frame();
1052
1053 // check for pending exceptions. use Gtemp as scratch register.
1054 if (check_exceptions) {
1055 check_and_forward_exception(Gtemp);
1056 }
1057
1058 // get oop result if there is one and reset the value in the thread
1059 if (oop_result->is_valid()) {
1060 get_vm_result(oop_result);
1061 }
1062 }
1063
1064 void MacroAssembler::check_and_forward_exception(Register scratch_reg)
1065 {
1066 Label L;
1067
1068 check_and_handle_popframe(scratch_reg);
1069 check_and_handle_earlyret(scratch_reg);
1070
1071 Address exception_addr(G2_thread, Thread::pending_exception_offset());
1072 ld_ptr(exception_addr, scratch_reg);
1073 br_null(scratch_reg,false,pt,L);
1074 delayed()->nop();
1075 // we use O7 linkage so that forward_exception_entry has the issuing PC
1076 call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type);
1077 delayed()->nop();
1078 bind(L);
1079 }
1080
1081
1082 void MacroAssembler::check_and_handle_popframe(Register scratch_reg) {
1083 }
1084
1085
1086 void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) {
1087 }
1088
1089
1090 void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1091 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
1092 }
1093
1094
1095 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {
1096 // O0 is reserved for the thread
1097 mov(arg_1, O1);
1098 call_VM(oop_result, entry_point, 1, check_exceptions);
1099 }
1100
1101
1102 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
1103 // O0 is reserved for the thread
1104 mov(arg_1, O1);
1105 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
1106 call_VM(oop_result, entry_point, 2, check_exceptions);
1107 }
1108
1109
1110 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
1111 // O0 is reserved for the thread
1112 mov(arg_1, O1);
1113 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
1114 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");
1115 call_VM(oop_result, entry_point, 3, check_exceptions);
1116 }
1117
1118
1119
1120 // Note: The following call_VM overloadings are useful when a "save"
1121 // has already been performed by a stub, and the last Java frame is
1122 // the previous one. In that case, last_java_sp must be passed as FP
1123 // instead of SP.
1124
1125
1126 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) {
1127 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1128 }
1129
1130
1131 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {
1132 // O0 is reserved for the thread
1133 mov(arg_1, O1);
1134 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1135 }
1136
1137
1138 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
1139 // O0 is reserved for the thread
1140 mov(arg_1, O1);
1141 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
1142 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1143 }
1144
1145
1146 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
1147 // O0 is reserved for the thread
1148 mov(arg_1, O1);
1149 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument");
1150 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument");
1151 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1152 }
1153
1154
1155
1156 void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) {
1157 assert_not_delayed();
1158 save_thread(thread_cache);
1159 // do the call
1160 call(entry_point, relocInfo::runtime_call_type);
1161 delayed()->nop();
1162 restore_thread(thread_cache);
1163 }
1164
1165
1166 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) {
1167 call_VM_leaf_base(thread_cache, entry_point, number_of_arguments);
1168 }
1169
1170
1171 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) {
1172 mov(arg_1, O0);
1173 call_VM_leaf(thread_cache, entry_point, 1);
1174 }
1175
1176
1177 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) {
1178 mov(arg_1, O0);
1179 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument");
1180 call_VM_leaf(thread_cache, entry_point, 2);
1181 }
1182
1183
1184 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) {
1185 mov(arg_1, O0);
1186 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument");
1187 mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument");
1188 call_VM_leaf(thread_cache, entry_point, 3);
1189 }
1190
1191
1192 void MacroAssembler::get_vm_result(Register oop_result) {
1193 verify_thread();
1194 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
1195 ld_ptr( vm_result_addr, oop_result);
1196 st_ptr(G0, vm_result_addr);
1197 verify_oop(oop_result);
1198 }
1199
1200
1201 void MacroAssembler::get_vm_result_2(Register oop_result) {
1202 verify_thread();
1203 Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset());
1204 ld_ptr(vm_result_addr_2, oop_result);
1205 st_ptr(G0, vm_result_addr_2);
1206 verify_oop(oop_result);
1207 }
1208
1209
1210 // We require that C code which does not return a value in vm_result will
1211 // leave it undisturbed.
1212 void MacroAssembler::set_vm_result(Register oop_result) {
1213 verify_thread();
1214 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset());
1215 verify_oop(oop_result);
1216
1217 # ifdef ASSERT
1218 // Check that we are not overwriting any other oop.
1219 #ifdef CC_INTERP
1220 save_frame(0);
1221 #else
1222 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof
1223 #endif /* CC_INTERP */
1224 ld_ptr(vm_result_addr, L0);
1225 tst(L0);
1226 restore();
1227 breakpoint_trap(notZero, Assembler::ptr_cc);
1228 // }
1229 # endif
1230
1231 st_ptr(oop_result, vm_result_addr);
1232 }
1233
1234
1235 void MacroAssembler::card_table_write(jbyte* byte_map_base,
1236 Register tmp, Register obj) {
1237 #ifdef _LP64
1238 srlx(obj, CardTableModRefBS::card_shift, obj);
1239 #else
1240 srl(obj, CardTableModRefBS::card_shift, obj);
1241 #endif
1242 assert(tmp != obj, "need separate temp reg");
1243 set((address) byte_map_base, tmp);
1244 stb(G0, tmp, obj);
1245 }
1246
1247
1248 void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
1249 address save_pc;
1250 int shiftcnt;
1251 #ifdef _LP64
1252 # ifdef CHECK_DELAY
1253 assert_not_delayed((char*) "cannot put two instructions in delay slot");
1254 # endif
1255 v9_dep();
1256 save_pc = pc();
1257
1258 int msb32 = (int) (addrlit.value() >> 32);
1259 int lsb32 = (int) (addrlit.value());
1260
1261 if (msb32 == 0 && lsb32 >= 0) {
1262 Assembler::sethi(lsb32, d, addrlit.rspec());
1263 }
1264 else if (msb32 == -1) {
1265 Assembler::sethi(~lsb32, d, addrlit.rspec());
1266 xor3(d, ~low10(~0), d);
1267 }
1268 else {
1269 Assembler::sethi(msb32, d, addrlit.rspec()); // msb 22-bits
1270 if (msb32 & 0x3ff) // Any bits?
1271 or3(d, msb32 & 0x3ff, d); // msb 32-bits are now in lsb 32
1272 if (lsb32 & 0xFFFFFC00) { // done?
1273 if ((lsb32 >> 20) & 0xfff) { // Any bits set?
1274 sllx(d, 12, d); // Make room for next 12 bits
1275 or3(d, (lsb32 >> 20) & 0xfff, d); // Or in next 12
1276 shiftcnt = 0; // We already shifted
1277 }
1278 else
1279 shiftcnt = 12;
1280 if ((lsb32 >> 10) & 0x3ff) {
1281 sllx(d, shiftcnt + 10, d); // Make room for last 10 bits
1282 or3(d, (lsb32 >> 10) & 0x3ff, d); // Or in next 10
1283 shiftcnt = 0;
1284 }
1285 else
1286 shiftcnt = 10;
1287 sllx(d, shiftcnt + 10, d); // Shift leaving disp field 0'd
1288 }
1289 else
1290 sllx(d, 32, d);
1291 }
1292 // Pad out the instruction sequence so it can be patched later.
1293 if (ForceRelocatable || (addrlit.rtype() != relocInfo::none &&
1294 addrlit.rtype() != relocInfo::runtime_call_type)) {
1295 while (pc() < (save_pc + (7 * BytesPerInstWord)))
1296 nop();
1297 }
1298 #else
1299 Assembler::sethi(addrlit.value(), d, addrlit.rspec());
1300 #endif
1301 }
1302
1303
1304 void MacroAssembler::sethi(const AddressLiteral& addrlit, Register d) {
1305 internal_sethi(addrlit, d, false);
1306 }
1307
1308
1309 void MacroAssembler::patchable_sethi(const AddressLiteral& addrlit, Register d) {
1310 internal_sethi(addrlit, d, true);
1311 }
1312
1313
1314 int MacroAssembler::size_of_sethi(address a, bool worst_case) {
1315 #ifdef _LP64
1316 if (worst_case) return 7;
1317 intptr_t iaddr = (intptr_t)a;
1318 int hi32 = (int)(iaddr >> 32);
1319 int lo32 = (int)(iaddr);
1320 int inst_count;
1321 if (hi32 == 0 && lo32 >= 0)
1322 inst_count = 1;
1323 else if (hi32 == -1)
1324 inst_count = 2;
1325 else {
1326 inst_count = 2;
1327 if ( hi32 & 0x3ff )
1328 inst_count++;
1329 if ( lo32 & 0xFFFFFC00 ) {
1330 if( (lo32 >> 20) & 0xfff ) inst_count += 2;
1331 if( (lo32 >> 10) & 0x3ff ) inst_count += 2;
1332 }
1333 }
1334 return BytesPerInstWord * inst_count;
1335 #else
1336 return BytesPerInstWord;
1337 #endif
1338 }
1339
1340 int MacroAssembler::worst_case_size_of_set() {
1341 return size_of_sethi(NULL, true) + 1;
1342 }
1343
1344
1345 void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) {
1346 intptr_t value = addrlit.value();
1347
1348 if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) {
1349 // can optimize
1350 if (-4096 <= value && value <= 4095) {
1351 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended)
1352 return;
1353 }
1354 if (inv_hi22(hi22(value)) == value) {
1355 sethi(addrlit, d);
1356 return;
1357 }
1358 }
1359 assert_not_delayed((char*) "cannot put two instructions in delay slot");
1360 internal_sethi(addrlit, d, ForceRelocatable);
1361 if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) {
1362 add(d, addrlit.low10(), d, addrlit.rspec());
1363 }
1364 }
1365
1366 void MacroAssembler::set(const AddressLiteral& al, Register d) {
1367 internal_set(al, d, false);
1368 }
1369
1370 void MacroAssembler::set(intptr_t value, Register d) {
1371 AddressLiteral al(value);
1372 internal_set(al, d, false);
1373 }
1374
1375 void MacroAssembler::set(address addr, Register d, RelocationHolder const& rspec) {
1376 AddressLiteral al(addr, rspec);
1377 internal_set(al, d, false);
1378 }
1379
1380 void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) {
1381 internal_set(al, d, true);
1382 }
1383
1384 void MacroAssembler::patchable_set(intptr_t value, Register d) {
1385 AddressLiteral al(value);
1386 internal_set(al, d, true);
1387 }
1388
1389
1390 void MacroAssembler::set64(jlong value, Register d, Register tmp) {
1391 assert_not_delayed();
1392 v9_dep();
1393
1394 int hi = (int)(value >> 32);
1395 int lo = (int)(value & ~0);
1396 // (Matcher::isSimpleConstant64 knows about the following optimizations.)
1397 if (Assembler::is_simm13(lo) && value == lo) {
1398 or3(G0, lo, d);
1399 } else if (hi == 0) {
1400 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32
1401 if (low10(lo) != 0)
1402 or3(d, low10(lo), d);
1403 }
1404 else if (hi == -1) {
1405 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32
1406 xor3(d, low10(lo) ^ ~low10(~0), d);
1407 }
1408 else if (lo == 0) {
1409 if (Assembler::is_simm13(hi)) {
1410 or3(G0, hi, d);
1411 } else {
1412 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32
1413 if (low10(hi) != 0)
1414 or3(d, low10(hi), d);
1415 }
1416 sllx(d, 32, d);
1417 }
1418 else {
1419 Assembler::sethi(hi, tmp);
1420 Assembler::sethi(lo, d); // macro assembler version sign-extends
1421 if (low10(hi) != 0)
1422 or3 (tmp, low10(hi), tmp);
1423 if (low10(lo) != 0)
1424 or3 ( d, low10(lo), d);
1425 sllx(tmp, 32, tmp);
1426 or3 (d, tmp, d);
1427 }
1428 }
1429
1430 // compute size in bytes of sparc frame, given
1431 // number of extraWords
1432 int MacroAssembler::total_frame_size_in_bytes(int extraWords) {
1433
1434 int nWords = frame::memory_parameter_word_sp_offset;
1435
1436 nWords += extraWords;
1437
1438 if (nWords & 1) ++nWords; // round up to double-word
1439
1440 return nWords * BytesPerWord;
1441 }
1442
1443
1444 // save_frame: given number of "extra" words in frame,
1445 // issue approp. save instruction (p 200, v8 manual)
1446
1447 void MacroAssembler::save_frame(int extraWords = 0) {
1448 int delta = -total_frame_size_in_bytes(extraWords);
1449 if (is_simm13(delta)) {
1450 save(SP, delta, SP);
1451 } else {
1452 set(delta, G3_scratch);
1453 save(SP, G3_scratch, SP);
1454 }
1455 }
1456
1457
1458 void MacroAssembler::save_frame_c1(int size_in_bytes) {
1459 if (is_simm13(-size_in_bytes)) {
1460 save(SP, -size_in_bytes, SP);
1461 } else {
1462 set(-size_in_bytes, G3_scratch);
1463 save(SP, G3_scratch, SP);
1464 }
1465 }
1466
1467
1468 void MacroAssembler::save_frame_and_mov(int extraWords,
1469 Register s1, Register d1,
1470 Register s2, Register d2) {
1471 assert_not_delayed();
1472
1473 // The trick here is to use precisely the same memory word
1474 // that trap handlers also use to save the register.
1475 // This word cannot be used for any other purpose, but
1476 // it works fine to save the register's value, whether or not
1477 // an interrupt flushes register windows at any given moment!
1478 Address s1_addr;
1479 if (s1->is_valid() && (s1->is_in() || s1->is_local())) {
1480 s1_addr = s1->address_in_saved_window();
1481 st_ptr(s1, s1_addr);
1482 }
1483
1484 Address s2_addr;
1485 if (s2->is_valid() && (s2->is_in() || s2->is_local())) {
1486 s2_addr = s2->address_in_saved_window();
1487 st_ptr(s2, s2_addr);
1488 }
1489
1490 save_frame(extraWords);
1491
1492 if (s1_addr.base() == SP) {
1493 ld_ptr(s1_addr.after_save(), d1);
1494 } else if (s1->is_valid()) {
1495 mov(s1->after_save(), d1);
1496 }
1497
1498 if (s2_addr.base() == SP) {
1499 ld_ptr(s2_addr.after_save(), d2);
1500 } else if (s2->is_valid()) {
1501 mov(s2->after_save(), d2);
1502 }
1503 }
1504
1505
1506 AddressLiteral MacroAssembler::allocate_oop_address(jobject obj) {
1507 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1508 int oop_index = oop_recorder()->allocate_index(obj);
1509 return AddressLiteral(obj, oop_Relocation::spec(oop_index));
1510 }
1511
1512
1513 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) {
1514 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1515 int oop_index = oop_recorder()->find_index(obj);
1516 return AddressLiteral(obj, oop_Relocation::spec(oop_index));
1517 }
1518
1519 void MacroAssembler::set_narrow_oop(jobject obj, Register d) {
1520 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1521 int oop_index = oop_recorder()->find_index(obj);
1522 RelocationHolder rspec = oop_Relocation::spec(oop_index);
1523
1524 assert_not_delayed();
1525 // Relocation with special format (see relocInfo_sparc.hpp).
1526 relocate(rspec, 1);
1527 // Assembler::sethi(0x3fffff, d);
1528 emit_long( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(0x3fffff) );
1529 // Don't add relocation for 'add'. Do patching during 'sethi' processing.
1530 add(d, 0x3ff, d);
1531
1532 }
1533
1534
1535 void MacroAssembler::align(int modulus) {
1536 while (offset() % modulus != 0) nop();
1537 }
1538
1539
1540 void MacroAssembler::safepoint() {
1541 relocate(breakpoint_Relocation::spec(breakpoint_Relocation::safepoint));
1542 }
1543
1544
1545 void RegistersForDebugging::print(outputStream* s) {
1546 int j;
1547 for ( j = 0; j < 8; ++j )
1548 if ( j != 6 ) s->print_cr("i%d = 0x%.16lx", j, i[j]);
1549 else s->print_cr( "fp = 0x%.16lx", i[j]);
1550 s->cr();
1551
1552 for ( j = 0; j < 8; ++j )
1553 s->print_cr("l%d = 0x%.16lx", j, l[j]);
1554 s->cr();
1555
1556 for ( j = 0; j < 8; ++j )
1557 if ( j != 6 ) s->print_cr("o%d = 0x%.16lx", j, o[j]);
1558 else s->print_cr( "sp = 0x%.16lx", o[j]);
1559 s->cr();
1560
1561 for ( j = 0; j < 8; ++j )
1562 s->print_cr("g%d = 0x%.16lx", j, g[j]);
1563 s->cr();
1564
1565 // print out floats with compression
1566 for (j = 0; j < 32; ) {
1567 jfloat val = f[j];
1568 int last = j;
1569 for ( ; last+1 < 32; ++last ) {
1570 char b1[1024], b2[1024];
1571 sprintf(b1, "%f", val);
1572 sprintf(b2, "%f", f[last+1]);
1573 if (strcmp(b1, b2))
1574 break;
1575 }
1576 s->print("f%d", j);
1577 if ( j != last ) s->print(" - f%d", last);
1578 s->print(" = %f", val);
1579 s->fill_to(25);
1580 s->print_cr(" (0x%x)", val);
1581 j = last + 1;
1582 }
1583 s->cr();
1584
1585 // and doubles (evens only)
1586 for (j = 0; j < 32; ) {
1587 jdouble val = d[j];
1588 int last = j;
1589 for ( ; last+1 < 32; ++last ) {
1590 char b1[1024], b2[1024];
1591 sprintf(b1, "%f", val);
1592 sprintf(b2, "%f", d[last+1]);
1593 if (strcmp(b1, b2))
1594 break;
1595 }
1596 s->print("d%d", 2 * j);
1597 if ( j != last ) s->print(" - d%d", last);
1598 s->print(" = %f", val);
1599 s->fill_to(30);
1600 s->print("(0x%x)", *(int*)&val);
1601 s->fill_to(42);
1602 s->print_cr("(0x%x)", *(1 + (int*)&val));
1603 j = last + 1;
1604 }
1605 s->cr();
1606 }
1607
1608 void RegistersForDebugging::save_registers(MacroAssembler* a) {
1609 a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0);
1610 a->flush_windows();
1611 int i;
1612 for (i = 0; i < 8; ++i) {
1613 a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i));
1614 a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i));
1615 a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i));
1616 a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i));
1617 }
1618 for (i = 0; i < 32; ++i) {
1619 a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i));
1620 }
1621 for (i = 0; i < (VM_Version::v9_instructions_work() ? 64 : 32); i += 2) {
1622 a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i));
1623 }
1624 }
1625
1626 void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) {
1627 for (int i = 1; i < 8; ++i) {
1628 a->ld_ptr(r, g_offset(i), as_gRegister(i));
1629 }
1630 for (int j = 0; j < 32; ++j) {
1631 a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j));
1632 }
1633 for (int k = 0; k < (VM_Version::v9_instructions_work() ? 64 : 32); k += 2) {
1634 a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k));
1635 }
1636 }
1637
1638
1639 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1640 void MacroAssembler::push_fTOS() {
1641 // %%%%%% need to implement this
1642 }
1643
1644 // pops double TOS element from CPU stack and pushes on FPU stack
1645 void MacroAssembler::pop_fTOS() {
1646 // %%%%%% need to implement this
1647 }
1648
1649 void MacroAssembler::empty_FPU_stack() {
1650 // %%%%%% need to implement this
1651 }
1652
1653 void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) {
1654 // plausibility check for oops
1655 if (!VerifyOops) return;
1656
1657 if (reg == G0) return; // always NULL, which is always an oop
1658
1659 char buffer[64];
1660 #ifdef COMPILER1
1661 if (CommentedAssembly) {
1662 snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset());
1663 block_comment(buffer);
1664 }
1665 #endif
1666
1667 int len = strlen(file) + strlen(msg) + 1 + 4;
1668 sprintf(buffer, "%d", line);
1669 len += strlen(buffer);
1670 sprintf(buffer, " at offset %d ", offset());
1671 len += strlen(buffer);
1672 char * real_msg = new char[len];
1673 sprintf(real_msg, "%s%s(%s:%d)", msg, buffer, file, line);
1674
1675 // Call indirectly to solve generation ordering problem
1676 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());
1677
1678 // Make some space on stack above the current register window.
1679 // Enough to hold 8 64-bit registers.
1680 add(SP,-8*8,SP);
1681
1682 // Save some 64-bit registers; a normal 'save' chops the heads off
1683 // of 64-bit longs in the 32-bit build.
1684 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);
1685 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);
1686 mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed
1687 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);
1688
1689 set((intptr_t)real_msg, O1);
1690 // Load address to call to into O7
1691 load_ptr_contents(a, O7);
1692 // Register call to verify_oop_subroutine
1693 callr(O7, G0);
1694 delayed()->nop();
1695 // recover frame size
1696 add(SP, 8*8,SP);
1697 }
1698
1699 void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) {
1700 // plausibility check for oops
1701 if (!VerifyOops) return;
1702
1703 char buffer[64];
1704 sprintf(buffer, "%d", line);
1705 int len = strlen(file) + strlen(msg) + 1 + 4 + strlen(buffer);
1706 sprintf(buffer, " at SP+%d ", addr.disp());
1707 len += strlen(buffer);
1708 char * real_msg = new char[len];
1709 sprintf(real_msg, "%s at SP+%d (%s:%d)", msg, addr.disp(), file, line);
1710
1711 // Call indirectly to solve generation ordering problem
1712 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address());
1713
1714 // Make some space on stack above the current register window.
1715 // Enough to hold 8 64-bit registers.
1716 add(SP,-8*8,SP);
1717
1718 // Save some 64-bit registers; a normal 'save' chops the heads off
1719 // of 64-bit longs in the 32-bit build.
1720 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8);
1721 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8);
1722 ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed
1723 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8);
1724
1725 set((intptr_t)real_msg, O1);
1726 // Load address to call to into O7
1727 load_ptr_contents(a, O7);
1728 // Register call to verify_oop_subroutine
1729 callr(O7, G0);
1730 delayed()->nop();
1731 // recover frame size
1732 add(SP, 8*8,SP);
1733 }
1734
1735 // side-door communication with signalHandler in os_solaris.cpp
1736 address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL };
1737
1738 // This macro is expanded just once; it creates shared code. Contract:
1739 // receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY
1740 // registers, including flags. May not use a register 'save', as this blows
1741 // the high bits of the O-regs if they contain Long values. Acts as a 'leaf'
1742 // call.
1743 void MacroAssembler::verify_oop_subroutine() {
1744 assert( VM_Version::v9_instructions_work(), "VerifyOops not supported for V8" );
1745
1746 // Leaf call; no frame.
1747 Label succeed, fail, null_or_fail;
1748
1749 // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home).
1750 // O0 is now the oop to be checked. O7 is the return address.
1751 Register O0_obj = O0;
1752
1753 // Save some more registers for temps.
1754 stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8);
1755 stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8);
1756 stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8);
1757 stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8);
1758
1759 // Save flags
1760 Register O5_save_flags = O5;
1761 rdccr( O5_save_flags );
1762
1763 { // count number of verifies
1764 Register O2_adr = O2;
1765 Register O3_accum = O3;
1766 inc_counter(StubRoutines::verify_oop_count_addr(), O2_adr, O3_accum);
1767 }
1768
1769 Register O2_mask = O2;
1770 Register O3_bits = O3;
1771 Register O4_temp = O4;
1772
1773 // mark lower end of faulting range
1774 assert(_verify_oop_implicit_branch[0] == NULL, "set once");
1775 _verify_oop_implicit_branch[0] = pc();
1776
1777 // We can't check the mark oop because it could be in the process of
1778 // locking or unlocking while this is running.
1779 set(Universe::verify_oop_mask (), O2_mask);
1780 set(Universe::verify_oop_bits (), O3_bits);
1781
1782 // assert((obj & oop_mask) == oop_bits);
1783 and3(O0_obj, O2_mask, O4_temp);
1784 cmp(O4_temp, O3_bits);
1785 brx(notEqual, false, pn, null_or_fail);
1786 delayed()->nop();
1787
1788 if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) {
1789 // the null_or_fail case is useless; must test for null separately
1790 br_null(O0_obj, false, pn, succeed);
1791 delayed()->nop();
1792 }
1793
1794 // Check the klassOop of this object for being in the right area of memory.
1795 // Cannot do the load in the delay above slot in case O0 is null
1796 load_klass(O0_obj, O0_obj);
1797 // assert((klass & klass_mask) == klass_bits);
1798 if( Universe::verify_klass_mask() != Universe::verify_oop_mask() )
1799 set(Universe::verify_klass_mask(), O2_mask);
1800 if( Universe::verify_klass_bits() != Universe::verify_oop_bits() )
1801 set(Universe::verify_klass_bits(), O3_bits);
1802 and3(O0_obj, O2_mask, O4_temp);
1803 cmp(O4_temp, O3_bits);
1804 brx(notEqual, false, pn, fail);
1805 delayed()->nop();
1806 // Check the klass's klass
1807 load_klass(O0_obj, O0_obj);
1808 and3(O0_obj, O2_mask, O4_temp);
1809 cmp(O4_temp, O3_bits);
1810 brx(notEqual, false, pn, fail);
1811 delayed()->wrccr( O5_save_flags ); // Restore CCR's
1812
1813 // mark upper end of faulting range
1814 _verify_oop_implicit_branch[1] = pc();
1815
1816 //-----------------------
1817 // all tests pass
1818 bind(succeed);
1819
1820 // Restore prior 64-bit registers
1821 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0);
1822 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1);
1823 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2);
1824 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3);
1825 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4);
1826 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5);
1827
1828 retl(); // Leaf return; restore prior O7 in delay slot
1829 delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7);
1830
1831 //-----------------------
1832 bind(null_or_fail); // nulls are less common but OK
1833 br_null(O0_obj, false, pt, succeed);
1834 delayed()->wrccr( O5_save_flags ); // Restore CCR's
1835
1836 //-----------------------
1837 // report failure:
1838 bind(fail);
1839 _verify_oop_implicit_branch[2] = pc();
1840
1841 wrccr( O5_save_flags ); // Restore CCR's
1842
1843 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
1844
1845 // stop_subroutine expects message pointer in I1.
1846 mov(I1, O1);
1847
1848 // Restore prior 64-bit registers
1849 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0);
1850 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1);
1851 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2);
1852 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3);
1853 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4);
1854 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5);
1855
1856 // factor long stop-sequence into subroutine to save space
1857 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");
1858
1859 // call indirectly to solve generation ordering problem
1860 AddressLiteral al(StubRoutines::Sparc::stop_subroutine_entry_address());
1861 load_ptr_contents(al, O5);
1862 jmpl(O5, 0, O7);
1863 delayed()->nop();
1864 }
1865
1866
1867 void MacroAssembler::stop(const char* msg) {
1868 // save frame first to get O7 for return address
1869 // add one word to size in case struct is odd number of words long
1870 // It must be doubleword-aligned for storing doubles into it.
1871
1872 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
1873
1874 // stop_subroutine expects message pointer in I1.
1875 set((intptr_t)msg, O1);
1876
1877 // factor long stop-sequence into subroutine to save space
1878 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet");
1879
1880 // call indirectly to solve generation ordering problem
1881 AddressLiteral a(StubRoutines::Sparc::stop_subroutine_entry_address());
1882 load_ptr_contents(a, O5);
1883 jmpl(O5, 0, O7);
1884 delayed()->nop();
1885
1886 breakpoint_trap(); // make stop actually stop rather than writing
1887 // unnoticeable results in the output files.
1888
1889 // restore(); done in callee to save space!
1890 }
1891
1892
1893 void MacroAssembler::warn(const char* msg) {
1894 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2));
1895 RegistersForDebugging::save_registers(this);
1896 mov(O0, L0);
1897 set((intptr_t)msg, O0);
1898 call( CAST_FROM_FN_PTR(address, warning) );
1899 delayed()->nop();
1900 // ret();
1901 // delayed()->restore();
1902 RegistersForDebugging::restore_registers(this, L0);
1903 restore();
1904 }
1905
1906
1907 void MacroAssembler::untested(const char* what) {
1908 // We must be able to turn interactive prompting off
1909 // in order to run automated test scripts on the VM
1910 // Use the flag ShowMessageBoxOnError
1911
1912 char* b = new char[1024];
1913 sprintf(b, "untested: %s", what);
1914
1915 if ( ShowMessageBoxOnError ) stop(b);
1916 else warn(b);
1917 }
1918
1919
1920 void MacroAssembler::stop_subroutine() {
1921 RegistersForDebugging::save_registers(this);
1922
1923 // for the sake of the debugger, stick a PC on the current frame
1924 // (this assumes that the caller has performed an extra "save")
1925 mov(I7, L7);
1926 add(O7, -7 * BytesPerInt, I7);
1927
1928 save_frame(); // one more save to free up another O7 register
1929 mov(I0, O1); // addr of reg save area
1930
1931 // We expect pointer to message in I1. Caller must set it up in O1
1932 mov(I1, O0); // get msg
1933 call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type);
1934 delayed()->nop();
1935
1936 restore();
1937
1938 RegistersForDebugging::restore_registers(this, O0);
1939
1940 save_frame(0);
1941 call(CAST_FROM_FN_PTR(address,breakpoint));
1942 delayed()->nop();
1943 restore();
1944
1945 mov(L7, I7);
1946 retl();
1947 delayed()->restore(); // see stop above
1948 }
1949
1950
1951 void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) {
1952 if ( ShowMessageBoxOnError ) {
1953 JavaThreadState saved_state = JavaThread::current()->thread_state();
1954 JavaThread::current()->set_thread_state(_thread_in_vm);
1955 {
1956 // In order to get locks work, we need to fake a in_VM state
1957 ttyLocker ttyl;
1958 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg);
1959 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
1960 ::tty->print_cr("Interpreter::bytecode_counter = %d", BytecodeCounter::counter_value());
1961 }
1962 if (os::message_box(msg, "Execution stopped, print registers?"))
1963 regs->print(::tty);
1964 }
1965 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state);
1966 }
1967 else
1968 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
1969 assert(false, "error");
1970 }
1971
1972
1973 #ifndef PRODUCT
1974 void MacroAssembler::test() {
1975 ResourceMark rm;
1976
1977 CodeBuffer cb("test", 10000, 10000);
1978 MacroAssembler* a = new MacroAssembler(&cb);
1979 VM_Version::allow_all();
1980 a->test_v9();
1981 a->test_v8_onlys();
1982 VM_Version::revert();
1983
1984 StubRoutines::Sparc::test_stop_entry()();
1985 }
1986 #endif
1987
1988
1989 void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) {
1990 subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words?
1991 Label no_extras;
1992 br( negative, true, pt, no_extras ); // if neg, clear reg
1993 delayed()->set(0, Rresult); // annuled, so only if taken
1994 bind( no_extras );
1995 }
1996
1997
1998 void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) {
1999 #ifdef _LP64
2000 add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult);
2001 #else
2002 add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult);
2003 #endif
2004 bclr(1, Rresult);
2005 sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes
2006 }
2007
2008
2009 void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) {
2010 calc_frame_size(Rextra_words, Rresult);
2011 neg(Rresult);
2012 save(SP, Rresult, SP);
2013 }
2014
2015
2016 // ---------------------------------------------------------
2017 Assembler::RCondition cond2rcond(Assembler::Condition c) {
2018 switch (c) {
2019 /*case zero: */
2020 case Assembler::equal: return Assembler::rc_z;
2021 case Assembler::lessEqual: return Assembler::rc_lez;
2022 case Assembler::less: return Assembler::rc_lz;
2023 /*case notZero:*/
2024 case Assembler::notEqual: return Assembler::rc_nz;
2025 case Assembler::greater: return Assembler::rc_gz;
2026 case Assembler::greaterEqual: return Assembler::rc_gez;
2027 }
2028 ShouldNotReachHere();
2029 return Assembler::rc_z;
2030 }
2031
2032 // compares register with zero and branches. NOT FOR USE WITH 64-bit POINTERS
2033 void MacroAssembler::br_zero( Condition c, bool a, Predict p, Register s1, Label& L) {
2034 tst(s1);
2035 br (c, a, p, L);
2036 }
2037
2038
2039 // Compares a pointer register with zero and branches on null.
2040 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
2041 void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) {
2042 assert_not_delayed();
2043 #ifdef _LP64
2044 bpr( rc_z, a, p, s1, L );
2045 #else
2046 tst(s1);
2047 br ( zero, a, p, L );
2048 #endif
2049 }
2050
2051 void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) {
2052 assert_not_delayed();
2053 #ifdef _LP64
2054 bpr( rc_nz, a, p, s1, L );
2055 #else
2056 tst(s1);
2057 br ( notZero, a, p, L );
2058 #endif
2059 }
2060
2061 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p,
2062 Register s1, address d,
2063 relocInfo::relocType rt ) {
2064 if (VM_Version::v9_instructions_work()) {
2065 bpr(rc, a, p, s1, d, rt);
2066 } else {
2067 tst(s1);
2068 br(reg_cond_to_cc_cond(rc), a, p, d, rt);
2069 }
2070 }
2071
2072 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p,
2073 Register s1, Label& L ) {
2074 if (VM_Version::v9_instructions_work()) {
2075 bpr(rc, a, p, s1, L);
2076 } else {
2077 tst(s1);
2078 br(reg_cond_to_cc_cond(rc), a, p, L);
2079 }
2080 }
2081
2082
2083 // instruction sequences factored across compiler & interpreter
2084
2085
2086 void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low,
2087 Register Rb_hi, Register Rb_low,
2088 Register Rresult) {
2089
2090 Label check_low_parts, done;
2091
2092 cmp(Ra_hi, Rb_hi ); // compare hi parts
2093 br(equal, true, pt, check_low_parts);
2094 delayed()->cmp(Ra_low, Rb_low); // test low parts
2095
2096 // And, with an unsigned comparison, it does not matter if the numbers
2097 // are negative or not.
2098 // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff.
2099 // The second one is bigger (unsignedly).
2100
2101 // Other notes: The first move in each triplet can be unconditional
2102 // (and therefore probably prefetchable).
2103 // And the equals case for the high part does not need testing,
2104 // since that triplet is reached only after finding the high halves differ.
2105
2106 if (VM_Version::v9_instructions_work()) {
2107
2108 mov ( -1, Rresult);
2109 ba( false, done ); delayed()-> movcc(greater, false, icc, 1, Rresult);
2110 }
2111 else {
2112 br(less, true, pt, done); delayed()-> set(-1, Rresult);
2113 br(greater, true, pt, done); delayed()-> set( 1, Rresult);
2114 }
2115
2116 bind( check_low_parts );
2117
2118 if (VM_Version::v9_instructions_work()) {
2119 mov( -1, Rresult);
2120 movcc(equal, false, icc, 0, Rresult);
2121 movcc(greaterUnsigned, false, icc, 1, Rresult);
2122 }
2123 else {
2124 set(-1, Rresult);
2125 br(equal, true, pt, done); delayed()->set( 0, Rresult);
2126 br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult);
2127 }
2128 bind( done );
2129 }
2130
2131 void MacroAssembler::lneg( Register Rhi, Register Rlow ) {
2132 subcc( G0, Rlow, Rlow );
2133 subc( G0, Rhi, Rhi );
2134 }
2135
2136 void MacroAssembler::lshl( Register Rin_high, Register Rin_low,
2137 Register Rcount,
2138 Register Rout_high, Register Rout_low,
2139 Register Rtemp ) {
2140
2141
2142 Register Ralt_count = Rtemp;
2143 Register Rxfer_bits = Rtemp;
2144
2145 assert( Ralt_count != Rin_high
2146 && Ralt_count != Rin_low
2147 && Ralt_count != Rcount
2148 && Rxfer_bits != Rin_low
2149 && Rxfer_bits != Rin_high
2150 && Rxfer_bits != Rcount
2151 && Rxfer_bits != Rout_low
2152 && Rout_low != Rin_high,
2153 "register alias checks");
2154
2155 Label big_shift, done;
2156
2157 // This code can be optimized to use the 64 bit shifts in V9.
2158 // Here we use the 32 bit shifts.
2159
2160 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
2161 subcc(Rcount, 31, Ralt_count);
2162 br(greater, true, pn, big_shift);
2163 delayed()->
2164 dec(Ralt_count);
2165
2166 // shift < 32 bits, Ralt_count = Rcount-31
2167
2168 // We get the transfer bits by shifting right by 32-count the low
2169 // register. This is done by shifting right by 31-count and then by one
2170 // more to take care of the special (rare) case where count is zero
2171 // (shifting by 32 would not work).
2172
2173 neg( Ralt_count );
2174
2175 // The order of the next two instructions is critical in the case where
2176 // Rin and Rout are the same and should not be reversed.
2177
2178 srl( Rin_low, Ralt_count, Rxfer_bits ); // shift right by 31-count
2179 if (Rcount != Rout_low) {
2180 sll( Rin_low, Rcount, Rout_low ); // low half
2181 }
2182 sll( Rin_high, Rcount, Rout_high );
2183 if (Rcount == Rout_low) {
2184 sll( Rin_low, Rcount, Rout_low ); // low half
2185 }
2186 srl( Rxfer_bits, 1, Rxfer_bits ); // shift right by one more
2187 ba (false, done);
2188 delayed()->
2189 or3( Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low
2190
2191 // shift >= 32 bits, Ralt_count = Rcount-32
2192 bind(big_shift);
2193 sll( Rin_low, Ralt_count, Rout_high );
2194 clr( Rout_low );
2195
2196 bind(done);
2197 }
2198
2199
2200 void MacroAssembler::lshr( Register Rin_high, Register Rin_low,
2201 Register Rcount,
2202 Register Rout_high, Register Rout_low,
2203 Register Rtemp ) {
2204
2205 Register Ralt_count = Rtemp;
2206 Register Rxfer_bits = Rtemp;
2207
2208 assert( Ralt_count != Rin_high
2209 && Ralt_count != Rin_low
2210 && Ralt_count != Rcount
2211 && Rxfer_bits != Rin_low
2212 && Rxfer_bits != Rin_high
2213 && Rxfer_bits != Rcount
2214 && Rxfer_bits != Rout_high
2215 && Rout_high != Rin_low,
2216 "register alias checks");
2217
2218 Label big_shift, done;
2219
2220 // This code can be optimized to use the 64 bit shifts in V9.
2221 // Here we use the 32 bit shifts.
2222
2223 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
2224 subcc(Rcount, 31, Ralt_count);
2225 br(greater, true, pn, big_shift);
2226 delayed()->dec(Ralt_count);
2227
2228 // shift < 32 bits, Ralt_count = Rcount-31
2229
2230 // We get the transfer bits by shifting left by 32-count the high
2231 // register. This is done by shifting left by 31-count and then by one
2232 // more to take care of the special (rare) case where count is zero
2233 // (shifting by 32 would not work).
2234
2235 neg( Ralt_count );
2236 if (Rcount != Rout_low) {
2237 srl( Rin_low, Rcount, Rout_low );
2238 }
2239
2240 // The order of the next two instructions is critical in the case where
2241 // Rin and Rout are the same and should not be reversed.
2242
2243 sll( Rin_high, Ralt_count, Rxfer_bits ); // shift left by 31-count
2244 sra( Rin_high, Rcount, Rout_high ); // high half
2245 sll( Rxfer_bits, 1, Rxfer_bits ); // shift left by one more
2246 if (Rcount == Rout_low) {
2247 srl( Rin_low, Rcount, Rout_low );
2248 }
2249 ba (false, done);
2250 delayed()->
2251 or3( Rout_low, Rxfer_bits, Rout_low ); // new low value: or shifted old low part and xfer from high
2252
2253 // shift >= 32 bits, Ralt_count = Rcount-32
2254 bind(big_shift);
2255
2256 sra( Rin_high, Ralt_count, Rout_low );
2257 sra( Rin_high, 31, Rout_high ); // sign into hi
2258
2259 bind( done );
2260 }
2261
2262
2263
2264 void MacroAssembler::lushr( Register Rin_high, Register Rin_low,
2265 Register Rcount,
2266 Register Rout_high, Register Rout_low,
2267 Register Rtemp ) {
2268
2269 Register Ralt_count = Rtemp;
2270 Register Rxfer_bits = Rtemp;
2271
2272 assert( Ralt_count != Rin_high
2273 && Ralt_count != Rin_low
2274 && Ralt_count != Rcount
2275 && Rxfer_bits != Rin_low
2276 && Rxfer_bits != Rin_high
2277 && Rxfer_bits != Rcount
2278 && Rxfer_bits != Rout_high
2279 && Rout_high != Rin_low,
2280 "register alias checks");
2281
2282 Label big_shift, done;
2283
2284 // This code can be optimized to use the 64 bit shifts in V9.
2285 // Here we use the 32 bit shifts.
2286
2287 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits
2288 subcc(Rcount, 31, Ralt_count);
2289 br(greater, true, pn, big_shift);
2290 delayed()->dec(Ralt_count);
2291
2292 // shift < 32 bits, Ralt_count = Rcount-31
2293
2294 // We get the transfer bits by shifting left by 32-count the high
2295 // register. This is done by shifting left by 31-count and then by one
2296 // more to take care of the special (rare) case where count is zero
2297 // (shifting by 32 would not work).
2298
2299 neg( Ralt_count );
2300 if (Rcount != Rout_low) {
2301 srl( Rin_low, Rcount, Rout_low );
2302 }
2303
2304 // The order of the next two instructions is critical in the case where
2305 // Rin and Rout are the same and should not be reversed.
2306
2307 sll( Rin_high, Ralt_count, Rxfer_bits ); // shift left by 31-count
2308 srl( Rin_high, Rcount, Rout_high ); // high half
2309 sll( Rxfer_bits, 1, Rxfer_bits ); // shift left by one more
2310 if (Rcount == Rout_low) {
2311 srl( Rin_low, Rcount, Rout_low );
2312 }
2313 ba (false, done);
2314 delayed()->
2315 or3( Rout_low, Rxfer_bits, Rout_low ); // new low value: or shifted old low part and xfer from high
2316
2317 // shift >= 32 bits, Ralt_count = Rcount-32
2318 bind(big_shift);
2319
2320 srl( Rin_high, Ralt_count, Rout_low );
2321 clr( Rout_high );
2322
2323 bind( done );
2324 }
2325
2326 #ifdef _LP64
2327 void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) {
2328 cmp(Ra, Rb);
2329 mov( -1, Rresult);
2330 movcc(equal, false, xcc, 0, Rresult);
2331 movcc(greater, false, xcc, 1, Rresult);
2332 }
2333 #endif
2334
2335
2336 void MacroAssembler::float_cmp( bool is_float, int unordered_result,
2337 FloatRegister Fa, FloatRegister Fb,
2338 Register Rresult) {
2339
2340 fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb);
2341
2342 Condition lt = unordered_result == -1 ? f_unorderedOrLess : f_less;
2343 Condition eq = f_equal;
2344 Condition gt = unordered_result == 1 ? f_unorderedOrGreater : f_greater;
2345
2346 if (VM_Version::v9_instructions_work()) {
2347
2348 mov( -1, Rresult );
2349 movcc( eq, true, fcc0, 0, Rresult );
2350 movcc( gt, true, fcc0, 1, Rresult );
2351
2352 } else {
2353 Label done;
2354
2355 set( -1, Rresult );
2356 //fb(lt, true, pn, done); delayed()->set( -1, Rresult );
2357 fb( eq, true, pn, done); delayed()->set( 0, Rresult );
2358 fb( gt, true, pn, done); delayed()->set( 1, Rresult );
2359
2360 bind (done);
2361 }
2362 }
2363
2364
2365 void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
2366 {
2367 if (VM_Version::v9_instructions_work()) {
2368 Assembler::fneg(w, s, d);
2369 } else {
2370 if (w == FloatRegisterImpl::S) {
2371 Assembler::fneg(w, s, d);
2372 } else if (w == FloatRegisterImpl::D) {
2373 // number() does a sanity check on the alignment.
2374 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
2375 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
2376
2377 Assembler::fneg(FloatRegisterImpl::S, s, d);
2378 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2379 } else {
2380 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
2381
2382 // number() does a sanity check on the alignment.
2383 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
2384 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
2385
2386 Assembler::fneg(FloatRegisterImpl::S, s, d);
2387 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2388 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
2389 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
2390 }
2391 }
2392 }
2393
2394 void MacroAssembler::fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
2395 {
2396 if (VM_Version::v9_instructions_work()) {
2397 Assembler::fmov(w, s, d);
2398 } else {
2399 if (w == FloatRegisterImpl::S) {
2400 Assembler::fmov(w, s, d);
2401 } else if (w == FloatRegisterImpl::D) {
2402 // number() does a sanity check on the alignment.
2403 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
2404 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
2405
2406 Assembler::fmov(FloatRegisterImpl::S, s, d);
2407 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2408 } else {
2409 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
2410
2411 // number() does a sanity check on the alignment.
2412 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
2413 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
2414
2415 Assembler::fmov(FloatRegisterImpl::S, s, d);
2416 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2417 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
2418 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
2419 }
2420 }
2421 }
2422
2423 void MacroAssembler::fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d)
2424 {
2425 if (VM_Version::v9_instructions_work()) {
2426 Assembler::fabs(w, s, d);
2427 } else {
2428 if (w == FloatRegisterImpl::S) {
2429 Assembler::fabs(w, s, d);
2430 } else if (w == FloatRegisterImpl::D) {
2431 // number() does a sanity check on the alignment.
2432 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) &&
2433 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check");
2434
2435 Assembler::fabs(FloatRegisterImpl::S, s, d);
2436 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2437 } else {
2438 assert(w == FloatRegisterImpl::Q, "Invalid float register width");
2439
2440 // number() does a sanity check on the alignment.
2441 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) &&
2442 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check");
2443
2444 Assembler::fabs(FloatRegisterImpl::S, s, d);
2445 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor());
2446 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor());
2447 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor());
2448 }
2449 }
2450 }
2451
2452 void MacroAssembler::save_all_globals_into_locals() {
2453 mov(G1,L1);
2454 mov(G2,L2);
2455 mov(G3,L3);
2456 mov(G4,L4);
2457 mov(G5,L5);
2458 mov(G6,L6);
2459 mov(G7,L7);
2460 }
2461
2462 void MacroAssembler::restore_globals_from_locals() {
2463 mov(L1,G1);
2464 mov(L2,G2);
2465 mov(L3,G3);
2466 mov(L4,G4);
2467 mov(L5,G5);
2468 mov(L6,G6);
2469 mov(L7,G7);
2470 }
2471
2472 // Use for 64 bit operation.
2473 void MacroAssembler::casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm)
2474 {
2475 // store ptr_reg as the new top value
2476 #ifdef _LP64
2477 casx(top_ptr_reg, top_reg, ptr_reg);
2478 #else
2479 cas_under_lock(top_ptr_reg, top_reg, ptr_reg, lock_addr, use_call_vm);
2480 #endif // _LP64
2481 }
2482
2483 // [RGV] This routine does not handle 64 bit operations.
2484 // use casx_under_lock() or casx directly!!!
2485 void MacroAssembler::cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm)
2486 {
2487 // store ptr_reg as the new top value
2488 if (VM_Version::v9_instructions_work()) {
2489 cas(top_ptr_reg, top_reg, ptr_reg);
2490 } else {
2491
2492 // If the register is not an out nor global, it is not visible
2493 // after the save. Allocate a register for it, save its
2494 // value in the register save area (the save may not flush
2495 // registers to the save area).
2496
2497 Register top_ptr_reg_after_save;
2498 Register top_reg_after_save;
2499 Register ptr_reg_after_save;
2500
2501 if (top_ptr_reg->is_out() || top_ptr_reg->is_global()) {
2502 top_ptr_reg_after_save = top_ptr_reg->after_save();
2503 } else {
2504 Address reg_save_addr = top_ptr_reg->address_in_saved_window();
2505 top_ptr_reg_after_save = L0;
2506 st(top_ptr_reg, reg_save_addr);
2507 }
2508
2509 if (top_reg->is_out() || top_reg->is_global()) {
2510 top_reg_after_save = top_reg->after_save();
2511 } else {
2512 Address reg_save_addr = top_reg->address_in_saved_window();
2513 top_reg_after_save = L1;
2514 st(top_reg, reg_save_addr);
2515 }
2516
2517 if (ptr_reg->is_out() || ptr_reg->is_global()) {
2518 ptr_reg_after_save = ptr_reg->after_save();
2519 } else {
2520 Address reg_save_addr = ptr_reg->address_in_saved_window();
2521 ptr_reg_after_save = L2;
2522 st(ptr_reg, reg_save_addr);
2523 }
2524
2525 const Register& lock_reg = L3;
2526 const Register& lock_ptr_reg = L4;
2527 const Register& value_reg = L5;
2528 const Register& yield_reg = L6;
2529 const Register& yieldall_reg = L7;
2530
2531 save_frame();
2532
2533 if (top_ptr_reg_after_save == L0) {
2534 ld(top_ptr_reg->address_in_saved_window().after_save(), top_ptr_reg_after_save);
2535 }
2536
2537 if (top_reg_after_save == L1) {
2538 ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save);
2539 }
2540
2541 if (ptr_reg_after_save == L2) {
2542 ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save);
2543 }
2544
2545 Label(retry_get_lock);
2546 Label(not_same);
2547 Label(dont_yield);
2548
2549 assert(lock_addr, "lock_address should be non null for v8");
2550 set((intptr_t)lock_addr, lock_ptr_reg);
2551 // Initialize yield counter
2552 mov(G0,yield_reg);
2553 mov(G0, yieldall_reg);
2554 set(StubRoutines::Sparc::locked, lock_reg);
2555
2556 bind(retry_get_lock);
2557 cmp(yield_reg, V8AtomicOperationUnderLockSpinCount);
2558 br(Assembler::less, false, Assembler::pt, dont_yield);
2559 delayed()->nop();
2560
2561 if(use_call_vm) {
2562 Untested("Need to verify global reg consistancy");
2563 call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::yield_all), yieldall_reg);
2564 } else {
2565 // Save the regs and make space for a C call
2566 save(SP, -96, SP);
2567 save_all_globals_into_locals();
2568 call(CAST_FROM_FN_PTR(address,os::yield_all));
2569 delayed()->mov(yieldall_reg, O0);
2570 restore_globals_from_locals();
2571 restore();
2572 }
2573
2574 // reset the counter
2575 mov(G0,yield_reg);
2576 add(yieldall_reg, 1, yieldall_reg);
2577
2578 bind(dont_yield);
2579 // try to get lock
2580 swap(lock_ptr_reg, 0, lock_reg);
2581
2582 // did we get the lock?
2583 cmp(lock_reg, StubRoutines::Sparc::unlocked);
2584 br(Assembler::notEqual, true, Assembler::pn, retry_get_lock);
2585 delayed()->add(yield_reg,1,yield_reg);
2586
2587 // yes, got lock. do we have the same top?
2588 ld(top_ptr_reg_after_save, 0, value_reg);
2589 cmp(value_reg, top_reg_after_save);
2590 br(Assembler::notEqual, false, Assembler::pn, not_same);
2591 delayed()->nop();
2592
2593 // yes, same top.
2594 st(ptr_reg_after_save, top_ptr_reg_after_save, 0);
2595 membar(Assembler::StoreStore);
2596
2597 bind(not_same);
2598 mov(value_reg, ptr_reg_after_save);
2599 st(lock_reg, lock_ptr_reg, 0); // unlock
2600
2601 restore();
2602 }
2603 }
2604
2605 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
2606 Register tmp,
2607 int offset) {
2608 intptr_t value = *delayed_value_addr;
2609 if (value != 0)
2610 return RegisterOrConstant(value + offset);
2611
2612 // load indirectly to solve generation ordering problem
2613 AddressLiteral a(delayed_value_addr);
2614 load_ptr_contents(a, tmp);
2615
2616 #ifdef ASSERT
2617 tst(tmp);
2618 breakpoint_trap(zero, xcc);
2619 #endif
2620
2621 if (offset != 0)
2622 add(tmp, offset, tmp);
2623
2624 return RegisterOrConstant(tmp);
2625 }
2626
2627
2628 void MacroAssembler::regcon_inc_ptr( RegisterOrConstant& dest, RegisterOrConstant src, Register temp ) {
2629 assert(dest.register_or_noreg() != G0, "lost side effect");
2630 if ((src.is_constant() && src.as_constant() == 0) ||
2631 (src.is_register() && src.as_register() == G0)) {
2632 // do nothing
2633 } else if (dest.is_register()) {
2634 add(dest.as_register(), ensure_rs2(src, temp), dest.as_register());
2635 } else if (src.is_constant()) {
2636 intptr_t res = dest.as_constant() + src.as_constant();
2637 dest = RegisterOrConstant(res); // side effect seen by caller
2638 } else {
2639 assert(temp != noreg, "cannot handle constant += register");
2640 add(src.as_register(), ensure_rs2(dest, temp), temp);
2641 dest = RegisterOrConstant(temp); // side effect seen by caller
2642 }
2643 }
2644
2645 void MacroAssembler::regcon_sll_ptr( RegisterOrConstant& dest, RegisterOrConstant src, Register temp ) {
2646 assert(dest.register_or_noreg() != G0, "lost side effect");
2647 if (!is_simm13(src.constant_or_zero()))
2648 src = (src.as_constant() & 0xFF);
2649 if ((src.is_constant() && src.as_constant() == 0) ||
2650 (src.is_register() && src.as_register() == G0)) {
2651 // do nothing
2652 } else if (dest.is_register()) {
2653 sll_ptr(dest.as_register(), src, dest.as_register());
2654 } else if (src.is_constant()) {
2655 intptr_t res = dest.as_constant() << src.as_constant();
2656 dest = RegisterOrConstant(res); // side effect seen by caller
2657 } else {
2658 assert(temp != noreg, "cannot handle constant <<= register");
2659 set(dest.as_constant(), temp);
2660 sll_ptr(temp, src, temp);
2661 dest = RegisterOrConstant(temp); // side effect seen by caller
2662 }
2663 }
2664
2665
2666 // Look up the method for a megamorphic invokeinterface call.
2667 // The target method is determined by <intf_klass, itable_index>.
2668 // The receiver klass is in recv_klass.
2669 // On success, the result will be in method_result, and execution falls through.
2670 // On failure, execution transfers to the given label.
2671 void MacroAssembler::lookup_interface_method(Register recv_klass,
2672 Register intf_klass,
2673 RegisterOrConstant itable_index,
2674 Register method_result,
2675 Register scan_temp,
2676 Register sethi_temp,
2677 Label& L_no_such_interface) {
2678 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
2679 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
2680 "caller must use same register for non-constant itable index as for method");
2681
2682 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
2683 int vtable_base = instanceKlass::vtable_start_offset() * wordSize;
2684 int scan_step = itableOffsetEntry::size() * wordSize;
2685 int vte_size = vtableEntry::size() * wordSize;
2686
2687 lduw(recv_klass, instanceKlass::vtable_length_offset() * wordSize, scan_temp);
2688 // %%% We should store the aligned, prescaled offset in the klassoop.
2689 // Then the next several instructions would fold away.
2690
2691 int round_to_unit = ((HeapWordsPerLong > 1) ? BytesPerLong : 0);
2692 int itb_offset = vtable_base;
2693 if (round_to_unit != 0) {
2694 // hoist first instruction of round_to(scan_temp, BytesPerLong):
2695 itb_offset += round_to_unit - wordSize;
2696 }
2697 int itb_scale = exact_log2(vtableEntry::size() * wordSize);
2698 sll(scan_temp, itb_scale, scan_temp);
2699 add(scan_temp, itb_offset, scan_temp);
2700 if (round_to_unit != 0) {
2701 // Round up to align_object_offset boundary
2702 // see code for instanceKlass::start_of_itable!
2703 // Was: round_to(scan_temp, BytesPerLong);
2704 // Hoisted: add(scan_temp, BytesPerLong-1, scan_temp);
2705 and3(scan_temp, -round_to_unit, scan_temp);
2706 }
2707 add(recv_klass, scan_temp, scan_temp);
2708
2709 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
2710 RegisterOrConstant itable_offset = itable_index;
2711 regcon_sll_ptr(itable_offset, exact_log2(itableMethodEntry::size() * wordSize));
2712 regcon_inc_ptr(itable_offset, itableMethodEntry::method_offset_in_bytes());
2713 add(recv_klass, ensure_rs2(itable_offset, sethi_temp), recv_klass);
2714
2715 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
2716 // if (scan->interface() == intf) {
2717 // result = (klass + scan->offset() + itable_index);
2718 // }
2719 // }
2720 Label search, found_method;
2721
2722 for (int peel = 1; peel >= 0; peel--) {
2723 // %%%% Could load both offset and interface in one ldx, if they were
2724 // in the opposite order. This would save a load.
2725 ld_ptr(scan_temp, itableOffsetEntry::interface_offset_in_bytes(), method_result);
2726
2727 // Check that this entry is non-null. A null entry means that
2728 // the receiver class doesn't implement the interface, and wasn't the
2729 // same as when the caller was compiled.
2730 bpr(Assembler::rc_z, false, Assembler::pn, method_result, L_no_such_interface);
2731 delayed()->cmp(method_result, intf_klass);
2732
2733 if (peel) {
2734 brx(Assembler::equal, false, Assembler::pt, found_method);
2735 } else {
2736 brx(Assembler::notEqual, false, Assembler::pn, search);
2737 // (invert the test to fall through to found_method...)
2738 }
2739 delayed()->add(scan_temp, scan_step, scan_temp);
2740
2741 if (!peel) break;
2742
2743 bind(search);
2744 }
2745
2746 bind(found_method);
2747
2748 // Got a hit.
2749 int ito_offset = itableOffsetEntry::offset_offset_in_bytes();
2750 // scan_temp[-scan_step] points to the vtable offset we need
2751 ito_offset -= scan_step;
2752 lduw(scan_temp, ito_offset, scan_temp);
2753 ld_ptr(recv_klass, scan_temp, method_result);
2754 }
2755
2756
2757 void MacroAssembler::check_klass_subtype(Register sub_klass,
2758 Register super_klass,
2759 Register temp_reg,
2760 Register temp2_reg,
2761 Label& L_success) {
2762 Label L_failure, L_pop_to_failure;
2763 check_klass_subtype_fast_path(sub_klass, super_klass,
2764 temp_reg, temp2_reg,
2765 &L_success, &L_failure, NULL);
2766 Register sub_2 = sub_klass;
2767 Register sup_2 = super_klass;
2768 if (!sub_2->is_global()) sub_2 = L0;
2769 if (!sup_2->is_global()) sup_2 = L1;
2770
2771 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2);
2772 check_klass_subtype_slow_path(sub_2, sup_2,
2773 L2, L3, L4, L5,
2774 NULL, &L_pop_to_failure);
2775
2776 // on success:
2777 restore();
2778 ba(false, L_success);
2779 delayed()->nop();
2780
2781 // on failure:
2782 bind(L_pop_to_failure);
2783 restore();
2784 bind(L_failure);
2785 }
2786
2787
2788 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
2789 Register super_klass,
2790 Register temp_reg,
2791 Register temp2_reg,
2792 Label* L_success,
2793 Label* L_failure,
2794 Label* L_slow_path,
2795 RegisterOrConstant super_check_offset,
2796 Register instanceof_hack) {
2797 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
2798 Klass::secondary_super_cache_offset_in_bytes());
2799 int sco_offset = (klassOopDesc::header_size() * HeapWordSize +
2800 Klass::super_check_offset_offset_in_bytes());
2801
2802 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
2803 bool need_slow_path = (must_load_sco ||
2804 super_check_offset.constant_or_zero() == sco_offset);
2805
2806 assert_different_registers(sub_klass, super_klass, temp_reg);
2807 if (super_check_offset.is_register()) {
2808 assert_different_registers(sub_klass, super_klass,
2809 super_check_offset.as_register());
2810 } else if (must_load_sco) {
2811 assert(temp2_reg != noreg, "supply either a temp or a register offset");
2812 }
2813
2814 Label L_fallthrough;
2815 int label_nulls = 0;
2816 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
2817 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
2818 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
2819 assert(label_nulls <= 1 || instanceof_hack != noreg ||
2820 (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path),
2821 "at most one NULL in the batch, usually");
2822
2823 // Support for the instanceof hack, which uses delay slots to
2824 // set a destination register to zero or one.
2825 bool do_bool_sets = (instanceof_hack != noreg);
2826 #define BOOL_SET(bool_value) \
2827 if (do_bool_sets && bool_value >= 0) \
2828 set(bool_value, instanceof_hack)
2829 #define DELAYED_BOOL_SET(bool_value) \
2830 if (do_bool_sets && bool_value >= 0) \
2831 delayed()->set(bool_value, instanceof_hack); \
2832 else delayed()->nop()
2833 // Hacked ba(), which may only be used just before L_fallthrough.
2834 #define FINAL_JUMP(label, bool_value) \
2835 if (&(label) == &L_fallthrough) { \
2836 BOOL_SET(bool_value); \
2837 } else { \
2838 ba((do_bool_sets && bool_value >= 0), label); \
2839 DELAYED_BOOL_SET(bool_value); \
2840 }
2841
2842 // If the pointers are equal, we are done (e.g., String[] elements).
2843 // This self-check enables sharing of secondary supertype arrays among
2844 // non-primary types such as array-of-interface. Otherwise, each such
2845 // type would need its own customized SSA.
2846 // We move this check to the front of the fast path because many
2847 // type checks are in fact trivially successful in this manner,
2848 // so we get a nicely predicted branch right at the start of the check.
2849 cmp(super_klass, sub_klass);
2850 brx(Assembler::equal, do_bool_sets, Assembler::pn, *L_success);
2851 DELAYED_BOOL_SET(1);
2852
2853 // Check the supertype display:
2854 if (must_load_sco) {
2855 // The super check offset is always positive...
2856 lduw(super_klass, sco_offset, temp2_reg);
2857 super_check_offset = RegisterOrConstant(temp2_reg);
2858 }
2859 ld_ptr(sub_klass, super_check_offset, temp_reg);
2860 cmp(super_klass, temp_reg);
2861
2862 // This check has worked decisively for primary supers.
2863 // Secondary supers are sought in the super_cache ('super_cache_addr').
2864 // (Secondary supers are interfaces and very deeply nested subtypes.)
2865 // This works in the same check above because of a tricky aliasing
2866 // between the super_cache and the primary super display elements.
2867 // (The 'super_check_addr' can address either, as the case requires.)
2868 // Note that the cache is updated below if it does not help us find
2869 // what we need immediately.
2870 // So if it was a primary super, we can just fail immediately.
2871 // Otherwise, it's the slow path for us (no success at this point).
2872
2873 if (super_check_offset.is_register()) {
2874 brx(Assembler::equal, do_bool_sets, Assembler::pn, *L_success);
2875 delayed(); if (do_bool_sets) BOOL_SET(1);
2876 // if !do_bool_sets, sneak the next cmp into the delay slot:
2877 cmp(super_check_offset.as_register(), sc_offset);
2878
2879 if (L_failure == &L_fallthrough) {
2880 brx(Assembler::equal, do_bool_sets, Assembler::pt, *L_slow_path);
2881 delayed()->nop();
2882 BOOL_SET(0); // fallthrough on failure
2883 } else {
2884 brx(Assembler::notEqual, do_bool_sets, Assembler::pn, *L_failure);
2885 DELAYED_BOOL_SET(0);
2886 FINAL_JUMP(*L_slow_path, -1); // -1 => vanilla delay slot
2887 }
2888 } else if (super_check_offset.as_constant() == sc_offset) {
2889 // Need a slow path; fast failure is impossible.
2890 if (L_slow_path == &L_fallthrough) {
2891 brx(Assembler::equal, do_bool_sets, Assembler::pt, *L_success);
2892 DELAYED_BOOL_SET(1);
2893 } else {
2894 brx(Assembler::notEqual, false, Assembler::pn, *L_slow_path);
2895 delayed()->nop();
2896 FINAL_JUMP(*L_success, 1);
2897 }
2898 } else {
2899 // No slow path; it's a fast decision.
2900 if (L_failure == &L_fallthrough) {
2901 brx(Assembler::equal, do_bool_sets, Assembler::pt, *L_success);
2902 DELAYED_BOOL_SET(1);
2903 BOOL_SET(0);
2904 } else {
2905 brx(Assembler::notEqual, do_bool_sets, Assembler::pn, *L_failure);
2906 DELAYED_BOOL_SET(0);
2907 FINAL_JUMP(*L_success, 1);
2908 }
2909 }
2910
2911 bind(L_fallthrough);
2912
2913 #undef final_jump
2914 #undef bool_set
2915 #undef DELAYED_BOOL_SET
2916 #undef final_jump
2917 }
2918
2919
2920 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
2921 Register super_klass,
2922 Register count_temp,
2923 Register scan_temp,
2924 Register scratch_reg,
2925 Register coop_reg,
2926 Label* L_success,
2927 Label* L_failure) {
2928 assert_different_registers(sub_klass, super_klass,
2929 count_temp, scan_temp, scratch_reg, coop_reg);
2930
2931 Label L_fallthrough, L_loop;
2932 int label_nulls = 0;
2933 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
2934 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
2935 assert(label_nulls <= 1, "at most one NULL in the batch");
2936
2937 // a couple of useful fields in sub_klass:
2938 int ss_offset = (klassOopDesc::header_size() * HeapWordSize +
2939 Klass::secondary_supers_offset_in_bytes());
2940 int sc_offset = (klassOopDesc::header_size() * HeapWordSize +
2941 Klass::secondary_super_cache_offset_in_bytes());
2942
2943 // Do a linear scan of the secondary super-klass chain.
2944 // This code is rarely used, so simplicity is a virtue here.
2945
2946 #ifndef PRODUCT
2947 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
2948 inc_counter((address) pst_counter, count_temp, scan_temp);
2949 #endif
2950
2951 // We will consult the secondary-super array.
2952 ld_ptr(sub_klass, ss_offset, scan_temp);
2953
2954 // Compress superclass if necessary.
2955 Register search_key = super_klass;
2956 bool decode_super_klass = false;
2957 if (UseCompressedOops) {
2958 if (coop_reg != noreg) {
2959 encode_heap_oop_not_null(super_klass, coop_reg);
2960 search_key = coop_reg;
2961 } else {
2962 encode_heap_oop_not_null(super_klass);
2963 decode_super_klass = true; // scarce temps!
2964 }
2965 // The superclass is never null; it would be a basic system error if a null
2966 // pointer were to sneak in here. Note that we have already loaded the
2967 // Klass::super_check_offset from the super_klass in the fast path,
2968 // so if there is a null in that register, we are already in the afterlife.
2969 }
2970
2971 // Load the array length. (Positive movl does right thing on LP64.)
2972 lduw(scan_temp, arrayOopDesc::length_offset_in_bytes(), count_temp);
2973
2974 // Check for empty secondary super list
2975 tst(count_temp);
2976
2977 // Top of search loop
2978 bind(L_loop);
2979 br(Assembler::equal, false, Assembler::pn, *L_failure);
2980 delayed()->add(scan_temp, heapOopSize, scan_temp);
2981 assert(heapOopSize != 0, "heapOopSize should be initialized");
2982
2983 // Skip the array header in all array accesses.
2984 int elem_offset = arrayOopDesc::base_offset_in_bytes(T_OBJECT);
2985 elem_offset -= heapOopSize; // the scan pointer was pre-incremented also
2986
2987 // Load next super to check
2988 if (UseCompressedOops) {
2989 // Don't use load_heap_oop; we don't want to decode the element.
2990 lduw( scan_temp, elem_offset, scratch_reg );
2991 } else {
2992 ld_ptr( scan_temp, elem_offset, scratch_reg );
2993 }
2994
2995 // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list
2996 cmp(scratch_reg, search_key);
2997
2998 // A miss means we are NOT a subtype and need to keep looping
2999 brx(Assembler::notEqual, false, Assembler::pn, L_loop);
3000 delayed()->deccc(count_temp); // decrement trip counter in delay slot
3001
3002 // Falling out the bottom means we found a hit; we ARE a subtype
3003 if (decode_super_klass) decode_heap_oop(super_klass);
3004
3005 // Success. Cache the super we found and proceed in triumph.
3006 st_ptr(super_klass, sub_klass, sc_offset);
3007
3008 if (L_success != &L_fallthrough) {
3009 ba(false, *L_success);
3010 delayed()->nop();
3011 }
3012
3013 bind(L_fallthrough);
3014 }
3015
3016
3017
3018
3019 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg,
3020 Register temp_reg,
3021 Label& wrong_method_type) {
3022 assert_different_registers(mtype_reg, mh_reg, temp_reg);
3023 // compare method type against that of the receiver
3024 RegisterOrConstant mhtype_offset = delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg);
3025 ld_ptr(mh_reg, mhtype_offset, temp_reg);
3026 cmp(temp_reg, mtype_reg);
3027 br(Assembler::notEqual, false, Assembler::pn, wrong_method_type);
3028 delayed()->nop();
3029 }
3030
3031
3032 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg) {
3033 assert(mh_reg == G3_method_handle, "caller must put MH object in G3");
3034 assert_different_registers(mh_reg, temp_reg);
3035
3036 // pick out the interpreted side of the handler
3037 ld_ptr(mh_reg, delayed_value(java_dyn_MethodHandle::vmentry_offset_in_bytes, temp_reg), temp_reg);
3038
3039 // off we go...
3040 ld_ptr(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes(), temp_reg);
3041 jmp(temp_reg, 0);
3042
3043 // for the various stubs which take control at this point,
3044 // see MethodHandles::generate_method_handle_stub
3045
3046 // (Can any caller use this delay slot? If so, add an option for supression.)
3047 delayed()->nop();
3048 }
3049
3050 RegisterOrConstant MacroAssembler::argument_offset(RegisterOrConstant arg_slot,
3051 int extra_slot_offset) {
3052 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
3053 int stackElementSize = Interpreter::stackElementWords() * wordSize;
3054 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
3055 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
3056 assert(offset1 - offset == stackElementSize, "correct arithmetic");
3057 if (arg_slot.is_constant()) {
3058 offset += arg_slot.as_constant() * stackElementSize;
3059 return offset;
3060 } else {
3061 Register temp = arg_slot.as_register();
3062 sll_ptr(temp, exact_log2(stackElementSize), temp);
3063 if (offset != 0)
3064 add(temp, offset, temp);
3065 return temp;
3066 }
3067 }
3068
3069
3070
3071 void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg,
3072 Register temp_reg,
3073 Label& done, Label* slow_case,
3074 BiasedLockingCounters* counters) {
3075 assert(UseBiasedLocking, "why call this otherwise?");
3076
3077 if (PrintBiasedLockingStatistics) {
3078 assert_different_registers(obj_reg, mark_reg, temp_reg, O7);
3079 if (counters == NULL)
3080 counters = BiasedLocking::counters();
3081 }
3082
3083 Label cas_label;
3084
3085 // Biased locking
3086 // See whether the lock is currently biased toward our thread and
3087 // whether the epoch is still valid
3088 // Note that the runtime guarantees sufficient alignment of JavaThread
3089 // pointers to allow age to be placed into low bits
3090 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
3091 and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
3092 cmp(temp_reg, markOopDesc::biased_lock_pattern);
3093 brx(Assembler::notEqual, false, Assembler::pn, cas_label);
3094 delayed()->nop();
3095
3096 load_klass(obj_reg, temp_reg);
3097 ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg);
3098 or3(G2_thread, temp_reg, temp_reg);
3099 xor3(mark_reg, temp_reg, temp_reg);
3100 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg);
3101 if (counters != NULL) {
3102 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg);
3103 // Reload mark_reg as we may need it later
3104 ld_ptr(Address(obj_reg, oopDesc::mark_offset_in_bytes()), mark_reg);
3105 }
3106 brx(Assembler::equal, true, Assembler::pt, done);
3107 delayed()->nop();
3108
3109 Label try_revoke_bias;
3110 Label try_rebias;
3111 Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes());
3112 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3113
3114 // At this point we know that the header has the bias pattern and
3115 // that we are not the bias owner in the current epoch. We need to
3116 // figure out more details about the state of the header in order to
3117 // know what operations can be legally performed on the object's
3118 // header.
3119
3120 // If the low three bits in the xor result aren't clear, that means
3121 // the prototype header is no longer biased and we have to revoke
3122 // the bias on this object.
3123 btst(markOopDesc::biased_lock_mask_in_place, temp_reg);
3124 brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias);
3125
3126 // Biasing is still enabled for this data type. See whether the
3127 // epoch of the current bias is still valid, meaning that the epoch
3128 // bits of the mark word are equal to the epoch bits of the
3129 // prototype header. (Note that the prototype header's epoch bits
3130 // only change at a safepoint.) If not, attempt to rebias the object
3131 // toward the current thread. Note that we must be absolutely sure
3132 // that the current epoch is invalid in order to do this because
3133 // otherwise the manipulations it performs on the mark word are
3134 // illegal.
3135 delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg);
3136 brx(Assembler::notZero, false, Assembler::pn, try_rebias);
3137
3138 // The epoch of the current bias is still valid but we know nothing
3139 // about the owner; it might be set or it might be clear. Try to
3140 // acquire the bias of the object using an atomic operation. If this
3141 // fails we will go in to the runtime to revoke the object's bias.
3142 // Note that we first construct the presumed unbiased header so we
3143 // don't accidentally blow away another thread's valid bias.
3144 delayed()->and3(mark_reg,
3145 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place,
3146 mark_reg);
3147 or3(G2_thread, mark_reg, temp_reg);
3148 casn(mark_addr.base(), mark_reg, temp_reg);
3149 // If the biasing toward our thread failed, this means that
3150 // another thread succeeded in biasing it toward itself and we
3151 // need to revoke that bias. The revocation will occur in the
3152 // interpreter runtime in the slow case.
3153 cmp(mark_reg, temp_reg);
3154 if (counters != NULL) {
3155 cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg);
3156 }
3157 if (slow_case != NULL) {
3158 brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
3159 delayed()->nop();
3160 }
3161 br(Assembler::always, false, Assembler::pt, done);
3162 delayed()->nop();
3163
3164 bind(try_rebias);
3165 // At this point we know the epoch has expired, meaning that the
3166 // current "bias owner", if any, is actually invalid. Under these
3167 // circumstances _only_, we are allowed to use the current header's
3168 // value as the comparison value when doing the cas to acquire the
3169 // bias in the current epoch. In other words, we allow transfer of
3170 // the bias from one thread to another directly in this situation.
3171 //
3172 // FIXME: due to a lack of registers we currently blow away the age
3173 // bits in this situation. Should attempt to preserve them.
3174 load_klass(obj_reg, temp_reg);
3175 ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg);
3176 or3(G2_thread, temp_reg, temp_reg);
3177 casn(mark_addr.base(), mark_reg, temp_reg);
3178 // If the biasing toward our thread failed, this means that
3179 // another thread succeeded in biasing it toward itself and we
3180 // need to revoke that bias. The revocation will occur in the
3181 // interpreter runtime in the slow case.
3182 cmp(mark_reg, temp_reg);
3183 if (counters != NULL) {
3184 cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg);
3185 }
3186 if (slow_case != NULL) {
3187 brx(Assembler::notEqual, true, Assembler::pn, *slow_case);
3188 delayed()->nop();
3189 }
3190 br(Assembler::always, false, Assembler::pt, done);
3191 delayed()->nop();
3192
3193 bind(try_revoke_bias);
3194 // The prototype mark in the klass doesn't have the bias bit set any
3195 // more, indicating that objects of this data type are not supposed
3196 // to be biased any more. We are going to try to reset the mark of
3197 // this object to the prototype value and fall through to the
3198 // CAS-based locking scheme. Note that if our CAS fails, it means
3199 // that another thread raced us for the privilege of revoking the
3200 // bias of this particular object, so it's okay to continue in the
3201 // normal locking code.
3202 //
3203 // FIXME: due to a lack of registers we currently blow away the age
3204 // bits in this situation. Should attempt to preserve them.
3205 load_klass(obj_reg, temp_reg);
3206 ld_ptr(Address(temp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg);
3207 casn(mark_addr.base(), mark_reg, temp_reg);
3208 // Fall through to the normal CAS-based lock, because no matter what
3209 // the result of the above CAS, some thread must have succeeded in
3210 // removing the bias bit from the object's header.
3211 if (counters != NULL) {
3212 cmp(mark_reg, temp_reg);
3213 cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg);
3214 }
3215
3216 bind(cas_label);
3217 }
3218
3219 void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done,
3220 bool allow_delay_slot_filling) {
3221 // Check for biased locking unlock case, which is a no-op
3222 // Note: we do not have to check the thread ID for two reasons.
3223 // First, the interpreter checks for IllegalMonitorStateException at
3224 // a higher level. Second, if the bias was revoked while we held the
3225 // lock, the object could not be rebiased toward another thread, so
3226 // the bias bit would be clear.
3227 ld_ptr(mark_addr, temp_reg);
3228 and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg);
3229 cmp(temp_reg, markOopDesc::biased_lock_pattern);
3230 brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done);
3231 delayed();
3232 if (!allow_delay_slot_filling) {
3233 nop();
3234 }
3235 }
3236
3237
3238 // CASN -- 32-64 bit switch hitter similar to the synthetic CASN provided by
3239 // Solaris/SPARC's "as". Another apt name would be cas_ptr()
3240
3241 void MacroAssembler::casn (Register addr_reg, Register cmp_reg, Register set_reg ) {
3242 casx_under_lock (addr_reg, cmp_reg, set_reg, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()) ;
3243 }
3244
3245
3246
3247 // compiler_lock_object() and compiler_unlock_object() are direct transliterations
3248 // of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments.
3249 // The code could be tightened up considerably.
3250 //
3251 // box->dhw disposition - post-conditions at DONE_LABEL.
3252 // - Successful inflated lock: box->dhw != 0.
3253 // Any non-zero value suffices.
3254 // Consider G2_thread, rsp, boxReg, or unused_mark()
3255 // - Successful Stack-lock: box->dhw == mark.
3256 // box->dhw must contain the displaced mark word value
3257 // - Failure -- icc.ZFlag == 0 and box->dhw is undefined.
3258 // The slow-path fast_enter() and slow_enter() operators
3259 // are responsible for setting box->dhw = NonZero (typically ::unused_mark).
3260 // - Biased: box->dhw is undefined
3261 //
3262 // SPARC refworkload performance - specifically jetstream and scimark - are
3263 // extremely sensitive to the size of the code emitted by compiler_lock_object
3264 // and compiler_unlock_object. Critically, the key factor is code size, not path
3265 // length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the
3266 // effect).
3267
3268
3269 void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark,
3270 Register Rbox, Register Rscratch,
3271 BiasedLockingCounters* counters,
3272 bool try_bias) {
3273 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
3274
3275 verify_oop(Roop);
3276 Label done ;
3277
3278 if (counters != NULL) {
3279 inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch);
3280 }
3281
3282 if (EmitSync & 1) {
3283 mov (3, Rscratch) ;
3284 st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3285 cmp (SP, G0) ;
3286 return ;
3287 }
3288
3289 if (EmitSync & 2) {
3290
3291 // Fetch object's markword
3292 ld_ptr(mark_addr, Rmark);
3293
3294 if (try_bias) {
3295 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3296 }
3297
3298 // Save Rbox in Rscratch to be used for the cas operation
3299 mov(Rbox, Rscratch);
3300
3301 // set Rmark to markOop | markOopDesc::unlocked_value
3302 or3(Rmark, markOopDesc::unlocked_value, Rmark);
3303
3304 // Initialize the box. (Must happen before we update the object mark!)
3305 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3306
3307 // compare object markOop with Rmark and if equal exchange Rscratch with object markOop
3308 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3309 casx_under_lock(mark_addr.base(), Rmark, Rscratch,
3310 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3311
3312 // if compare/exchange succeeded we found an unlocked object and we now have locked it
3313 // hence we are done
3314 cmp(Rmark, Rscratch);
3315 #ifdef _LP64
3316 sub(Rscratch, STACK_BIAS, Rscratch);
3317 #endif
3318 brx(Assembler::equal, false, Assembler::pt, done);
3319 delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot
3320
3321 // we did not find an unlocked object so see if this is a recursive case
3322 // sub(Rscratch, SP, Rscratch);
3323 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3324 andcc(Rscratch, 0xfffff003, Rscratch);
3325 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3326 bind (done) ;
3327 return ;
3328 }
3329
3330 Label Egress ;
3331
3332 if (EmitSync & 256) {
3333 Label IsInflated ;
3334
3335 ld_ptr (mark_addr, Rmark); // fetch obj->mark
3336 // Triage: biased, stack-locked, neutral, inflated
3337 if (try_bias) {
3338 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3339 // Invariant: if control reaches this point in the emitted stream
3340 // then Rmark has not been modified.
3341 }
3342
3343 // Store mark into displaced mark field in the on-stack basic-lock "box"
3344 // Critically, this must happen before the CAS
3345 // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty.
3346 st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3347 andcc (Rmark, 2, G0) ;
3348 brx (Assembler::notZero, false, Assembler::pn, IsInflated) ;
3349 delayed() ->
3350
3351 // Try stack-lock acquisition.
3352 // Beware: the 1st instruction is in a delay slot
3353 mov (Rbox, Rscratch);
3354 or3 (Rmark, markOopDesc::unlocked_value, Rmark);
3355 assert (mark_addr.disp() == 0, "cas must take a zero displacement");
3356 casn (mark_addr.base(), Rmark, Rscratch) ;
3357 cmp (Rmark, Rscratch);
3358 brx (Assembler::equal, false, Assembler::pt, done);
3359 delayed()->sub(Rscratch, SP, Rscratch);
3360
3361 // Stack-lock attempt failed - check for recursive stack-lock.
3362 // See the comments below about how we might remove this case.
3363 #ifdef _LP64
3364 sub (Rscratch, STACK_BIAS, Rscratch);
3365 #endif
3366 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3367 andcc (Rscratch, 0xfffff003, Rscratch);
3368 br (Assembler::always, false, Assembler::pt, done) ;
3369 delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3370
3371 bind (IsInflated) ;
3372 if (EmitSync & 64) {
3373 // If m->owner != null goto IsLocked
3374 // Pessimistic form: Test-and-CAS vs CAS
3375 // The optimistic form avoids RTS->RTO cache line upgrades.
3376 ld_ptr (Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3377 andcc (Rscratch, Rscratch, G0) ;
3378 brx (Assembler::notZero, false, Assembler::pn, done) ;
3379 delayed()->nop() ;
3380 // m->owner == null : it's unlocked.
3381 }
3382
3383 // Try to CAS m->owner from null to Self
3384 // Invariant: if we acquire the lock then _recursions should be 0.
3385 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ;
3386 mov (G2_thread, Rscratch) ;
3387 casn (Rmark, G0, Rscratch) ;
3388 cmp (Rscratch, G0) ;
3389 // Intentional fall-through into done
3390 } else {
3391 // Aggressively avoid the Store-before-CAS penalty
3392 // Defer the store into box->dhw until after the CAS
3393 Label IsInflated, Recursive ;
3394
3395 // Anticipate CAS -- Avoid RTS->RTO upgrade
3396 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ;
3397
3398 ld_ptr (mark_addr, Rmark); // fetch obj->mark
3399 // Triage: biased, stack-locked, neutral, inflated
3400
3401 if (try_bias) {
3402 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters);
3403 // Invariant: if control reaches this point in the emitted stream
3404 // then Rmark has not been modified.
3405 }
3406 andcc (Rmark, 2, G0) ;
3407 brx (Assembler::notZero, false, Assembler::pn, IsInflated) ;
3408 delayed()-> // Beware - dangling delay-slot
3409
3410 // Try stack-lock acquisition.
3411 // Transiently install BUSY (0) encoding in the mark word.
3412 // if the CAS of 0 into the mark was successful then we execute:
3413 // ST box->dhw = mark -- save fetched mark in on-stack basiclock box
3414 // ST obj->mark = box -- overwrite transient 0 value
3415 // This presumes TSO, of course.
3416
3417 mov (0, Rscratch) ;
3418 or3 (Rmark, markOopDesc::unlocked_value, Rmark);
3419 assert (mark_addr.disp() == 0, "cas must take a zero displacement");
3420 casn (mark_addr.base(), Rmark, Rscratch) ;
3421 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ;
3422 cmp (Rscratch, Rmark) ;
3423 brx (Assembler::notZero, false, Assembler::pn, Recursive) ;
3424 delayed() ->
3425 st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes());
3426 if (counters != NULL) {
3427 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
3428 }
3429 br (Assembler::always, false, Assembler::pt, done);
3430 delayed() ->
3431 st_ptr (Rbox, mark_addr) ;
3432
3433 bind (Recursive) ;
3434 // Stack-lock attempt failed - check for recursive stack-lock.
3435 // Tests show that we can remove the recursive case with no impact
3436 // on refworkload 0.83. If we need to reduce the size of the code
3437 // emitted by compiler_lock_object() the recursive case is perfect
3438 // candidate.
3439 //
3440 // A more extreme idea is to always inflate on stack-lock recursion.
3441 // This lets us eliminate the recursive checks in compiler_lock_object
3442 // and compiler_unlock_object and the (box->dhw == 0) encoding.
3443 // A brief experiment - requiring changes to synchronizer.cpp, interpreter,
3444 // and showed a performance *increase*. In the same experiment I eliminated
3445 // the fast-path stack-lock code from the interpreter and always passed
3446 // control to the "slow" operators in synchronizer.cpp.
3447
3448 // RScratch contains the fetched obj->mark value from the failed CASN.
3449 #ifdef _LP64
3450 sub (Rscratch, STACK_BIAS, Rscratch);
3451 #endif
3452 sub(Rscratch, SP, Rscratch);
3453 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant");
3454 andcc (Rscratch, 0xfffff003, Rscratch);
3455 if (counters != NULL) {
3456 // Accounting needs the Rscratch register
3457 st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3458 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch);
3459 br (Assembler::always, false, Assembler::pt, done) ;
3460 delayed()->nop() ;
3461 } else {
3462 br (Assembler::always, false, Assembler::pt, done) ;
3463 delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes());
3464 }
3465
3466 bind (IsInflated) ;
3467 if (EmitSync & 64) {
3468 // If m->owner != null goto IsLocked
3469 // Test-and-CAS vs CAS
3470 // Pessimistic form avoids futile (doomed) CAS attempts
3471 // The optimistic form avoids RTS->RTO cache line upgrades.
3472 ld_ptr (Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3473 andcc (Rscratch, Rscratch, G0) ;
3474 brx (Assembler::notZero, false, Assembler::pn, done) ;
3475 delayed()->nop() ;
3476 // m->owner == null : it's unlocked.
3477 }
3478
3479 // Try to CAS m->owner from null to Self
3480 // Invariant: if we acquire the lock then _recursions should be 0.
3481 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ;
3482 mov (G2_thread, Rscratch) ;
3483 casn (Rmark, G0, Rscratch) ;
3484 cmp (Rscratch, G0) ;
3485 // ST box->displaced_header = NonZero.
3486 // Any non-zero value suffices:
3487 // unused_mark(), G2_thread, RBox, RScratch, rsp, etc.
3488 st_ptr (Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes());
3489 // Intentional fall-through into done
3490 }
3491
3492 bind (done) ;
3493 }
3494
3495 void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark,
3496 Register Rbox, Register Rscratch,
3497 bool try_bias) {
3498 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes());
3499
3500 Label done ;
3501
3502 if (EmitSync & 4) {
3503 cmp (SP, G0) ;
3504 return ;
3505 }
3506
3507 if (EmitSync & 8) {
3508 if (try_bias) {
3509 biased_locking_exit(mark_addr, Rscratch, done);
3510 }
3511
3512 // Test first if it is a fast recursive unlock
3513 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark);
3514 cmp(Rmark, G0);
3515 brx(Assembler::equal, false, Assembler::pt, done);
3516 delayed()->nop();
3517
3518 // Check if it is still a light weight lock, this is is true if we see
3519 // the stack address of the basicLock in the markOop of the object
3520 assert(mark_addr.disp() == 0, "cas must take a zero displacement");
3521 casx_under_lock(mark_addr.base(), Rbox, Rmark,
3522 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3523 br (Assembler::always, false, Assembler::pt, done);
3524 delayed()->cmp(Rbox, Rmark);
3525 bind (done) ;
3526 return ;
3527 }
3528
3529 // Beware ... If the aggregate size of the code emitted by CLO and CUO is
3530 // is too large performance rolls abruptly off a cliff.
3531 // This could be related to inlining policies, code cache management, or
3532 // I$ effects.
3533 Label LStacked ;
3534
3535 if (try_bias) {
3536 // TODO: eliminate redundant LDs of obj->mark
3537 biased_locking_exit(mark_addr, Rscratch, done);
3538 }
3539
3540 ld_ptr (Roop, oopDesc::mark_offset_in_bytes(), Rmark) ;
3541 ld_ptr (Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch);
3542 andcc (Rscratch, Rscratch, G0);
3543 brx (Assembler::zero, false, Assembler::pn, done);
3544 delayed()-> nop() ; // consider: relocate fetch of mark, above, into this DS
3545 andcc (Rmark, 2, G0) ;
3546 brx (Assembler::zero, false, Assembler::pt, LStacked) ;
3547 delayed()-> nop() ;
3548
3549 // It's inflated
3550 // Conceptually we need a #loadstore|#storestore "release" MEMBAR before
3551 // the ST of 0 into _owner which releases the lock. This prevents loads
3552 // and stores within the critical section from reordering (floating)
3553 // past the store that releases the lock. But TSO is a strong memory model
3554 // and that particular flavor of barrier is a noop, so we can safely elide it.
3555 // Note that we use 1-0 locking by default for the inflated case. We
3556 // close the resultant (and rare) race by having contented threads in
3557 // monitorenter periodically poll _owner.
3558 ld_ptr (Rmark, ObjectMonitor::owner_offset_in_bytes() - 2, Rscratch);
3559 ld_ptr (Rmark, ObjectMonitor::recursions_offset_in_bytes() - 2, Rbox);
3560 xor3 (Rscratch, G2_thread, Rscratch) ;
3561 orcc (Rbox, Rscratch, Rbox) ;
3562 brx (Assembler::notZero, false, Assembler::pn, done) ;
3563 delayed()->
3564 ld_ptr (Rmark, ObjectMonitor::EntryList_offset_in_bytes() - 2, Rscratch);
3565 ld_ptr (Rmark, ObjectMonitor::cxq_offset_in_bytes() - 2, Rbox);
3566 orcc (Rbox, Rscratch, G0) ;
3567 if (EmitSync & 65536) {
3568 Label LSucc ;
3569 brx (Assembler::notZero, false, Assembler::pn, LSucc) ;
3570 delayed()->nop() ;
3571 br (Assembler::always, false, Assembler::pt, done) ;
3572 delayed()->
3573 st_ptr (G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3574
3575 bind (LSucc) ;
3576 st_ptr (G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3577 if (os::is_MP()) { membar (StoreLoad) ; }
3578 ld_ptr (Rmark, ObjectMonitor::succ_offset_in_bytes() - 2, Rscratch);
3579 andcc (Rscratch, Rscratch, G0) ;
3580 brx (Assembler::notZero, false, Assembler::pt, done) ;
3581 delayed()-> andcc (G0, G0, G0) ;
3582 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ;
3583 mov (G2_thread, Rscratch) ;
3584 casn (Rmark, G0, Rscratch) ;
3585 cmp (Rscratch, G0) ;
3586 // invert icc.zf and goto done
3587 brx (Assembler::notZero, false, Assembler::pt, done) ;
3588 delayed() -> cmp (G0, G0) ;
3589 br (Assembler::always, false, Assembler::pt, done);
3590 delayed() -> cmp (G0, 1) ;
3591 } else {
3592 brx (Assembler::notZero, false, Assembler::pn, done) ;
3593 delayed()->nop() ;
3594 br (Assembler::always, false, Assembler::pt, done) ;
3595 delayed()->
3596 st_ptr (G0, Rmark, ObjectMonitor::owner_offset_in_bytes() - 2);
3597 }
3598
3599 bind (LStacked) ;
3600 // Consider: we could replace the expensive CAS in the exit
3601 // path with a simple ST of the displaced mark value fetched from
3602 // the on-stack basiclock box. That admits a race where a thread T2
3603 // in the slow lock path -- inflating with monitor M -- could race a
3604 // thread T1 in the fast unlock path, resulting in a missed wakeup for T2.
3605 // More precisely T1 in the stack-lock unlock path could "stomp" the
3606 // inflated mark value M installed by T2, resulting in an orphan
3607 // object monitor M and T2 becoming stranded. We can remedy that situation
3608 // by having T2 periodically poll the object's mark word using timed wait
3609 // operations. If T2 discovers that a stomp has occurred it vacates
3610 // the monitor M and wakes any other threads stranded on the now-orphan M.
3611 // In addition the monitor scavenger, which performs deflation,
3612 // would also need to check for orpan monitors and stranded threads.
3613 //
3614 // Finally, inflation is also used when T2 needs to assign a hashCode
3615 // to O and O is stack-locked by T1. The "stomp" race could cause
3616 // an assigned hashCode value to be lost. We can avoid that condition
3617 // and provide the necessary hashCode stability invariants by ensuring
3618 // that hashCode generation is idempotent between copying GCs.
3619 // For example we could compute the hashCode of an object O as
3620 // O's heap address XOR some high quality RNG value that is refreshed
3621 // at GC-time. The monitor scavenger would install the hashCode
3622 // found in any orphan monitors. Again, the mechanism admits a
3623 // lost-update "stomp" WAW race but detects and recovers as needed.
3624 //
3625 // A prototype implementation showed excellent results, although
3626 // the scavenger and timeout code was rather involved.
3627
3628 casn (mark_addr.base(), Rbox, Rscratch) ;
3629 cmp (Rbox, Rscratch);
3630 // Intentional fall through into done ...
3631
3632 bind (done) ;
3633 }
3634
3635
3636
3637 void MacroAssembler::print_CPU_state() {
3638 // %%%%% need to implement this
3639 }
3640
3641 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
3642 // %%%%% need to implement this
3643 }
3644
3645 void MacroAssembler::push_IU_state() {
3646 // %%%%% need to implement this
3647 }
3648
3649
3650 void MacroAssembler::pop_IU_state() {
3651 // %%%%% need to implement this
3652 }
3653
3654
3655 void MacroAssembler::push_FPU_state() {
3656 // %%%%% need to implement this
3657 }
3658
3659
3660 void MacroAssembler::pop_FPU_state() {
3661 // %%%%% need to implement this
3662 }
3663
3664
3665 void MacroAssembler::push_CPU_state() {
3666 // %%%%% need to implement this
3667 }
3668
3669
3670 void MacroAssembler::pop_CPU_state() {
3671 // %%%%% need to implement this
3672 }
3673
3674
3675
3676 void MacroAssembler::verify_tlab() {
3677 #ifdef ASSERT
3678 if (UseTLAB && VerifyOops) {
3679 Label next, next2, ok;
3680 Register t1 = L0;
3681 Register t2 = L1;
3682 Register t3 = L2;
3683
3684 save_frame(0);
3685 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
3686 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2);
3687 or3(t1, t2, t3);
3688 cmp(t1, t2);
3689 br(Assembler::greaterEqual, false, Assembler::pn, next);
3690 delayed()->nop();
3691 stop("assert(top >= start)");
3692 should_not_reach_here();
3693
3694 bind(next);
3695 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1);
3696 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2);
3697 or3(t3, t2, t3);
3698 cmp(t1, t2);
3699 br(Assembler::lessEqual, false, Assembler::pn, next2);
3700 delayed()->nop();
3701 stop("assert(top <= end)");
3702 should_not_reach_here();
3703
3704 bind(next2);
3705 and3(t3, MinObjAlignmentInBytesMask, t3);
3706 cmp(t3, 0);
3707 br(Assembler::lessEqual, false, Assembler::pn, ok);
3708 delayed()->nop();
3709 stop("assert(aligned)");
3710 should_not_reach_here();
3711
3712 bind(ok);
3713 restore();
3714 }
3715 #endif
3716 }
3717
3718
3719 void MacroAssembler::eden_allocate(
3720 Register obj, // result: pointer to object after successful allocation
3721 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
3722 int con_size_in_bytes, // object size in bytes if known at compile time
3723 Register t1, // temp register
3724 Register t2, // temp register
3725 Label& slow_case // continuation point if fast allocation fails
3726 ){
3727 // make sure arguments make sense
3728 assert_different_registers(obj, var_size_in_bytes, t1, t2);
3729 assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size");
3730 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
3731
3732 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
3733 // No allocation in the shared eden.
3734 br(Assembler::always, false, Assembler::pt, slow_case);
3735 delayed()->nop();
3736 } else {
3737 // get eden boundaries
3738 // note: we need both top & top_addr!
3739 const Register top_addr = t1;
3740 const Register end = t2;
3741
3742 CollectedHeap* ch = Universe::heap();
3743 set((intx)ch->top_addr(), top_addr);
3744 intx delta = (intx)ch->end_addr() - (intx)ch->top_addr();
3745 ld_ptr(top_addr, delta, end);
3746 ld_ptr(top_addr, 0, obj);
3747
3748 // try to allocate
3749 Label retry;
3750 bind(retry);
3751 #ifdef ASSERT
3752 // make sure eden top is properly aligned
3753 {
3754 Label L;
3755 btst(MinObjAlignmentInBytesMask, obj);
3756 br(Assembler::zero, false, Assembler::pt, L);
3757 delayed()->nop();
3758 stop("eden top is not properly aligned");
3759 bind(L);
3760 }
3761 #endif // ASSERT
3762 const Register free = end;
3763 sub(end, obj, free); // compute amount of free space
3764 if (var_size_in_bytes->is_valid()) {
3765 // size is unknown at compile time
3766 cmp(free, var_size_in_bytes);
3767 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case
3768 delayed()->add(obj, var_size_in_bytes, end);
3769 } else {
3770 // size is known at compile time
3771 cmp(free, con_size_in_bytes);
3772 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case
3773 delayed()->add(obj, con_size_in_bytes, end);
3774 }
3775 // Compare obj with the value at top_addr; if still equal, swap the value of
3776 // end with the value at top_addr. If not equal, read the value at top_addr
3777 // into end.
3778 casx_under_lock(top_addr, obj, end, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr());
3779 // if someone beat us on the allocation, try again, otherwise continue
3780 cmp(obj, end);
3781 brx(Assembler::notEqual, false, Assembler::pn, retry);
3782 delayed()->mov(end, obj); // nop if successfull since obj == end
3783
3784 #ifdef ASSERT
3785 // make sure eden top is properly aligned
3786 {
3787 Label L;
3788 const Register top_addr = t1;
3789
3790 set((intx)ch->top_addr(), top_addr);
3791 ld_ptr(top_addr, 0, top_addr);
3792 btst(MinObjAlignmentInBytesMask, top_addr);
3793 br(Assembler::zero, false, Assembler::pt, L);
3794 delayed()->nop();
3795 stop("eden top is not properly aligned");
3796 bind(L);
3797 }
3798 #endif // ASSERT
3799 }
3800 }
3801
3802
3803 void MacroAssembler::tlab_allocate(
3804 Register obj, // result: pointer to object after successful allocation
3805 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
3806 int con_size_in_bytes, // object size in bytes if known at compile time
3807 Register t1, // temp register
3808 Label& slow_case // continuation point if fast allocation fails
3809 ){
3810 // make sure arguments make sense
3811 assert_different_registers(obj, var_size_in_bytes, t1);
3812 assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size");
3813 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment");
3814
3815 const Register free = t1;
3816
3817 verify_tlab();
3818
3819 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj);
3820
3821 // calculate amount of free space
3822 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free);
3823 sub(free, obj, free);
3824
3825 Label done;
3826 if (var_size_in_bytes == noreg) {
3827 cmp(free, con_size_in_bytes);
3828 } else {
3829 cmp(free, var_size_in_bytes);
3830 }
3831 br(Assembler::less, false, Assembler::pn, slow_case);
3832 // calculate the new top pointer
3833 if (var_size_in_bytes == noreg) {
3834 delayed()->add(obj, con_size_in_bytes, free);
3835 } else {
3836 delayed()->add(obj, var_size_in_bytes, free);
3837 }
3838
3839 bind(done);
3840
3841 #ifdef ASSERT
3842 // make sure new free pointer is properly aligned
3843 {
3844 Label L;
3845 btst(MinObjAlignmentInBytesMask, free);
3846 br(Assembler::zero, false, Assembler::pt, L);
3847 delayed()->nop();
3848 stop("updated TLAB free is not properly aligned");
3849 bind(L);
3850 }
3851 #endif // ASSERT
3852
3853 // update the tlab top pointer
3854 st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
3855 verify_tlab();
3856 }
3857
3858
3859 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
3860 Register top = O0;
3861 Register t1 = G1;
3862 Register t2 = G3;
3863 Register t3 = O1;
3864 assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */);
3865 Label do_refill, discard_tlab;
3866
3867 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
3868 // No allocation in the shared eden.
3869 br(Assembler::always, false, Assembler::pt, slow_case);
3870 delayed()->nop();
3871 }
3872
3873 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top);
3874 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1);
3875 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2);
3876
3877 // calculate amount of free space
3878 sub(t1, top, t1);
3879 srl_ptr(t1, LogHeapWordSize, t1);
3880
3881 // Retain tlab and allocate object in shared space if
3882 // the amount free in the tlab is too large to discard.
3883 cmp(t1, t2);
3884 brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab);
3885
3886 // increment waste limit to prevent getting stuck on this slow path
3887 delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2);
3888 st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()));
3889 if (TLABStats) {
3890 // increment number of slow_allocations
3891 ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2);
3892 add(t2, 1, t2);
3893 stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()));
3894 }
3895 br(Assembler::always, false, Assembler::pt, try_eden);
3896 delayed()->nop();
3897
3898 bind(discard_tlab);
3899 if (TLABStats) {
3900 // increment number of refills
3901 ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2);
3902 add(t2, 1, t2);
3903 stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()));
3904 // accumulate wastage
3905 ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2);
3906 add(t2, t1, t2);
3907 stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()));
3908 }
3909
3910 // if tlab is currently allocated (top or end != null) then
3911 // fill [top, end + alignment_reserve) with array object
3912 br_null(top, false, Assembler::pn, do_refill);
3913 delayed()->nop();
3914
3915 set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2);
3916 st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word
3917 // set klass to intArrayKlass
3918 sub(t1, typeArrayOopDesc::header_size(T_INT), t1);
3919 add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1);
3920 sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1);
3921 st(t1, top, arrayOopDesc::length_offset_in_bytes());
3922 set((intptr_t)Universe::intArrayKlassObj_addr(), t2);
3923 ld_ptr(t2, 0, t2);
3924 // store klass last. concurrent gcs assumes klass length is valid if
3925 // klass field is not null.
3926 store_klass(t2, top);
3927 verify_oop(top);
3928
3929 // refill the tlab with an eden allocation
3930 bind(do_refill);
3931 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1);
3932 sll_ptr(t1, LogHeapWordSize, t1);
3933 // add object_size ??
3934 eden_allocate(top, t1, 0, t2, t3, slow_case);
3935
3936 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset()));
3937 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset()));
3938 #ifdef ASSERT
3939 // check that tlab_size (t1) is still valid
3940 {
3941 Label ok;
3942 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2);
3943 sll_ptr(t2, LogHeapWordSize, t2);
3944 cmp(t1, t2);
3945 br(Assembler::equal, false, Assembler::pt, ok);
3946 delayed()->nop();
3947 stop("assert(t1 == tlab_size)");
3948 should_not_reach_here();
3949
3950 bind(ok);
3951 }
3952 #endif // ASSERT
3953 add(top, t1, top); // t1 is tlab_size
3954 sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top);
3955 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset()));
3956 verify_tlab();
3957 br(Assembler::always, false, Assembler::pt, retry);
3958 delayed()->nop();
3959 }
3960
3961 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
3962 switch (cond) {
3963 // Note some conditions are synonyms for others
3964 case Assembler::never: return Assembler::always;
3965 case Assembler::zero: return Assembler::notZero;
3966 case Assembler::lessEqual: return Assembler::greater;
3967 case Assembler::less: return Assembler::greaterEqual;
3968 case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned;
3969 case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned;
3970 case Assembler::negative: return Assembler::positive;
3971 case Assembler::overflowSet: return Assembler::overflowClear;
3972 case Assembler::always: return Assembler::never;
3973 case Assembler::notZero: return Assembler::zero;
3974 case Assembler::greater: return Assembler::lessEqual;
3975 case Assembler::greaterEqual: return Assembler::less;
3976 case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned;
3977 case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned;
3978 case Assembler::positive: return Assembler::negative;
3979 case Assembler::overflowClear: return Assembler::overflowSet;
3980 }
3981
3982 ShouldNotReachHere(); return Assembler::overflowClear;
3983 }
3984
3985 void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr,
3986 Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) {
3987 Condition negated_cond = negate_condition(cond);
3988 Label L;
3989 brx(negated_cond, false, Assembler::pt, L);
3990 delayed()->nop();
3991 inc_counter(counter_ptr, Rtmp1, Rtmp2);
3992 bind(L);
3993 }
3994
3995 void MacroAssembler::inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2) {
3996 AddressLiteral addrlit(counter_addr);
3997 sethi(addrlit, Rtmp1); // Move hi22 bits into temporary register.
3998 Address addr(Rtmp1, addrlit.low10()); // Build an address with low10 bits.
3999 ld(addr, Rtmp2);
4000 inc(Rtmp2);
4001 st(Rtmp2, addr);
4002 }
4003
4004 void MacroAssembler::inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2) {
4005 inc_counter((address) counter_addr, Rtmp1, Rtmp2);
4006 }
4007
4008 SkipIfEqual::SkipIfEqual(
4009 MacroAssembler* masm, Register temp, const bool* flag_addr,
4010 Assembler::Condition condition) {
4011 _masm = masm;
4012 AddressLiteral flag(flag_addr);
4013 _masm->sethi(flag, temp);
4014 _masm->ldub(temp, flag.low10(), temp);
4015 _masm->tst(temp);
4016 _masm->br(condition, false, Assembler::pt, _label);
4017 _masm->delayed()->nop();
4018 }
4019
4020 SkipIfEqual::~SkipIfEqual() {
4021 _masm->bind(_label);
4022 }
4023
4024
4025 // Writes to stack successive pages until offset reached to check for
4026 // stack overflow + shadow pages. This clobbers tsp and scratch.
4027 void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp,
4028 Register Rscratch) {
4029 // Use stack pointer in temp stack pointer
4030 mov(SP, Rtsp);
4031
4032 // Bang stack for total size given plus stack shadow page size.
4033 // Bang one page at a time because a large size can overflow yellow and
4034 // red zones (the bang will fail but stack overflow handling can't tell that
4035 // it was a stack overflow bang vs a regular segv).
4036 int offset = os::vm_page_size();
4037 Register Roffset = Rscratch;
4038
4039 Label loop;
4040 bind(loop);
4041 set((-offset)+STACK_BIAS, Rscratch);
4042 st(G0, Rtsp, Rscratch);
4043 set(offset, Roffset);
4044 sub(Rsize, Roffset, Rsize);
4045 cmp(Rsize, G0);
4046 br(Assembler::greater, false, Assembler::pn, loop);
4047 delayed()->sub(Rtsp, Roffset, Rtsp);
4048
4049 // Bang down shadow pages too.
4050 // The -1 because we already subtracted 1 page.
4051 for (int i = 0; i< StackShadowPages-1; i++) {
4052 set((-i*offset)+STACK_BIAS, Rscratch);
4053 st(G0, Rtsp, Rscratch);
4054 }
4055 }
4056
4057 ///////////////////////////////////////////////////////////////////////////////////
4058 #ifndef SERIALGC
4059
4060 static uint num_stores = 0;
4061 static uint num_null_pre_stores = 0;
4062
4063 static void count_null_pre_vals(void* pre_val) {
4064 num_stores++;
4065 if (pre_val == NULL) num_null_pre_stores++;
4066 if ((num_stores % 1000000) == 0) {
4067 tty->print_cr(UINT32_FORMAT " stores, " UINT32_FORMAT " (%5.2f%%) with null pre-vals.",
4068 num_stores, num_null_pre_stores,
4069 100.0*(float)num_null_pre_stores/(float)num_stores);
4070 }
4071 }
4072
4073 static address satb_log_enqueue_with_frame = 0;
4074 static u_char* satb_log_enqueue_with_frame_end = 0;
4075
4076 static address satb_log_enqueue_frameless = 0;
4077 static u_char* satb_log_enqueue_frameless_end = 0;
4078
4079 static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions?
4080
4081 // The calls to this don't work. We'd need to do a fair amount of work to
4082 // make it work.
4083 static void check_index(int ind) {
4084 assert(0 <= ind && ind <= 64*K && ((ind % oopSize) == 0),
4085 "Invariants.")
4086 }
4087
4088 static void generate_satb_log_enqueue(bool with_frame) {
4089 BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize);
4090 CodeBuffer buf(bb->instructions_begin(), bb->instructions_size());
4091 MacroAssembler masm(&buf);
4092 address start = masm.pc();
4093 Register pre_val;
4094
4095 Label refill, restart;
4096 if (with_frame) {
4097 masm.save_frame(0);
4098 pre_val = I0; // Was O0 before the save.
4099 } else {
4100 pre_val = O0;
4101 }
4102 int satb_q_index_byte_offset =
4103 in_bytes(JavaThread::satb_mark_queue_offset() +
4104 PtrQueue::byte_offset_of_index());
4105 int satb_q_buf_byte_offset =
4106 in_bytes(JavaThread::satb_mark_queue_offset() +
4107 PtrQueue::byte_offset_of_buf());
4108 assert(in_bytes(PtrQueue::byte_width_of_index()) == sizeof(intptr_t) &&
4109 in_bytes(PtrQueue::byte_width_of_buf()) == sizeof(intptr_t),
4110 "check sizes in assembly below");
4111
4112 masm.bind(restart);
4113 masm.ld_ptr(G2_thread, satb_q_index_byte_offset, L0);
4114
4115 masm.br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn, L0, refill);
4116 // If the branch is taken, no harm in executing this in the delay slot.
4117 masm.delayed()->ld_ptr(G2_thread, satb_q_buf_byte_offset, L1);
4118 masm.sub(L0, oopSize, L0);
4119
4120 masm.st_ptr(pre_val, L1, L0); // [_buf + index] := I0
4121 if (!with_frame) {
4122 // Use return-from-leaf
4123 masm.retl();
4124 masm.delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset);
4125 } else {
4126 // Not delayed.
4127 masm.st_ptr(L0, G2_thread, satb_q_index_byte_offset);
4128 }
4129 if (with_frame) {
4130 masm.ret();
4131 masm.delayed()->restore();
4132 }
4133 masm.bind(refill);
4134
4135 address handle_zero =
4136 CAST_FROM_FN_PTR(address,
4137 &SATBMarkQueueSet::handle_zero_index_for_thread);
4138 // This should be rare enough that we can afford to save all the
4139 // scratch registers that the calling context might be using.
4140 masm.mov(G1_scratch, L0);
4141 masm.mov(G3_scratch, L1);
4142 masm.mov(G4, L2);
4143 // We need the value of O0 above (for the write into the buffer), so we
4144 // save and restore it.
4145 masm.mov(O0, L3);
4146 // Since the call will overwrite O7, we save and restore that, as well.
4147 masm.mov(O7, L4);
4148 masm.call_VM_leaf(L5, handle_zero, G2_thread);
4149 masm.mov(L0, G1_scratch);
4150 masm.mov(L1, G3_scratch);
4151 masm.mov(L2, G4);
4152 masm.mov(L3, O0);
4153 masm.br(Assembler::always, /*annul*/false, Assembler::pt, restart);
4154 masm.delayed()->mov(L4, O7);
4155
4156 if (with_frame) {
4157 satb_log_enqueue_with_frame = start;
4158 satb_log_enqueue_with_frame_end = masm.pc();
4159 } else {
4160 satb_log_enqueue_frameless = start;
4161 satb_log_enqueue_frameless_end = masm.pc();
4162 }
4163 }
4164
4165 static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) {
4166 if (with_frame) {
4167 if (satb_log_enqueue_with_frame == 0) {
4168 generate_satb_log_enqueue(with_frame);
4169 assert(satb_log_enqueue_with_frame != 0, "postcondition.");
4170 if (G1SATBPrintStubs) {
4171 tty->print_cr("Generated with-frame satb enqueue:");
4172 Disassembler::decode((u_char*)satb_log_enqueue_with_frame,
4173 satb_log_enqueue_with_frame_end,
4174 tty);
4175 }
4176 }
4177 } else {
4178 if (satb_log_enqueue_frameless == 0) {
4179 generate_satb_log_enqueue(with_frame);
4180 assert(satb_log_enqueue_frameless != 0, "postcondition.");
4181 if (G1SATBPrintStubs) {
4182 tty->print_cr("Generated frameless satb enqueue:");
4183 Disassembler::decode((u_char*)satb_log_enqueue_frameless,
4184 satb_log_enqueue_frameless_end,
4185 tty);
4186 }
4187 }
4188 }
4189 }
4190
4191 void MacroAssembler::g1_write_barrier_pre(Register obj, Register index, int offset, Register tmp, bool preserve_o_regs) {
4192 assert(offset == 0 || index == noreg, "choose one");
4193
4194 if (G1DisablePreBarrier) return;
4195 // satb_log_barrier(tmp, obj, offset, preserve_o_regs);
4196 Label filtered;
4197 // satb_log_barrier_work0(tmp, filtered);
4198 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4199 ld(G2,
4200 in_bytes(JavaThread::satb_mark_queue_offset() +
4201 PtrQueue::byte_offset_of_active()),
4202 tmp);
4203 } else {
4204 guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1,
4205 "Assumption");
4206 ldsb(G2,
4207 in_bytes(JavaThread::satb_mark_queue_offset() +
4208 PtrQueue::byte_offset_of_active()),
4209 tmp);
4210 }
4211
4212 // Check on whether to annul.
4213 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered);
4214 delayed() -> nop();
4215
4216 // satb_log_barrier_work1(tmp, offset);
4217 if (index == noreg) {
4218 if (Assembler::is_simm13(offset)) {
4219 load_heap_oop(obj, offset, tmp);
4220 } else {
4221 set(offset, tmp);
4222 load_heap_oop(obj, tmp, tmp);
4223 }
4224 } else {
4225 load_heap_oop(obj, index, tmp);
4226 }
4227
4228 // satb_log_barrier_work2(obj, tmp, offset);
4229
4230 // satb_log_barrier_work3(tmp, filtered, preserve_o_regs);
4231
4232 const Register pre_val = tmp;
4233
4234 if (G1SATBBarrierPrintNullPreVals) {
4235 save_frame(0);
4236 mov(pre_val, O0);
4237 // Save G-regs that target may use.
4238 mov(G1, L1);
4239 mov(G2, L2);
4240 mov(G3, L3);
4241 mov(G4, L4);
4242 mov(G5, L5);
4243 call(CAST_FROM_FN_PTR(address, &count_null_pre_vals));
4244 delayed()->nop();
4245 // Restore G-regs that target may have used.
4246 mov(L1, G1);
4247 mov(L2, G2);
4248 mov(L3, G3);
4249 mov(L4, G4);
4250 mov(L5, G5);
4251 restore(G0, G0, G0);
4252 }
4253
4254 // Check on whether to annul.
4255 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, pre_val, filtered);
4256 delayed() -> nop();
4257
4258 // OK, it's not filtered, so we'll need to call enqueue. In the normal
4259 // case, pre_val will be a scratch G-reg, but there's some cases in which
4260 // it's an O-reg. In the first case, do a normal call. In the latter,
4261 // do a save here and call the frameless version.
4262
4263 guarantee(pre_val->is_global() || pre_val->is_out(),
4264 "Or we need to think harder.");
4265 if (pre_val->is_global() && !preserve_o_regs) {
4266 generate_satb_log_enqueue_if_necessary(true); // with frame.
4267 call(satb_log_enqueue_with_frame);
4268 delayed()->mov(pre_val, O0);
4269 } else {
4270 generate_satb_log_enqueue_if_necessary(false); // with frameless.
4271 save_frame(0);
4272 call(satb_log_enqueue_frameless);
4273 delayed()->mov(pre_val->after_save(), O0);
4274 restore();
4275 }
4276
4277 bind(filtered);
4278 }
4279
4280 static jint num_ct_writes = 0;
4281 static jint num_ct_writes_filtered_in_hr = 0;
4282 static jint num_ct_writes_filtered_null = 0;
4283 static G1CollectedHeap* g1 = NULL;
4284
4285 static Thread* count_ct_writes(void* filter_val, void* new_val) {
4286 Atomic::inc(&num_ct_writes);
4287 if (filter_val == NULL) {
4288 Atomic::inc(&num_ct_writes_filtered_in_hr);
4289 } else if (new_val == NULL) {
4290 Atomic::inc(&num_ct_writes_filtered_null);
4291 } else {
4292 if (g1 == NULL) {
4293 g1 = G1CollectedHeap::heap();
4294 }
4295 }
4296 if ((num_ct_writes % 1000000) == 0) {
4297 jint num_ct_writes_filtered =
4298 num_ct_writes_filtered_in_hr +
4299 num_ct_writes_filtered_null;
4300
4301 tty->print_cr("%d potential CT writes: %5.2f%% filtered\n"
4302 " (%5.2f%% intra-HR, %5.2f%% null).",
4303 num_ct_writes,
4304 100.0*(float)num_ct_writes_filtered/(float)num_ct_writes,
4305 100.0*(float)num_ct_writes_filtered_in_hr/
4306 (float)num_ct_writes,
4307 100.0*(float)num_ct_writes_filtered_null/
4308 (float)num_ct_writes);
4309 }
4310 return Thread::current();
4311 }
4312
4313 static address dirty_card_log_enqueue = 0;
4314 static u_char* dirty_card_log_enqueue_end = 0;
4315
4316 // This gets to assume that o0 contains the object address.
4317 static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) {
4318 BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2);
4319 CodeBuffer buf(bb->instructions_begin(), bb->instructions_size());
4320 MacroAssembler masm(&buf);
4321 address start = masm.pc();
4322
4323 Label not_already_dirty, restart, refill;
4324
4325 #ifdef _LP64
4326 masm.srlx(O0, CardTableModRefBS::card_shift, O0);
4327 #else
4328 masm.srl(O0, CardTableModRefBS::card_shift, O0);
4329 #endif
4330 AddressLiteral addrlit(byte_map_base);
4331 masm.set(addrlit, O1); // O1 := <card table base>
4332 masm.ldub(O0, O1, O2); // O2 := [O0 + O1]
4333
4334 masm.br_on_reg_cond(Assembler::rc_nz, /*annul*/false, Assembler::pt,
4335 O2, not_already_dirty);
4336 // Get O1 + O2 into a reg by itself -- useful in the take-the-branch
4337 // case, harmless if not.
4338 masm.delayed()->add(O0, O1, O3);
4339
4340 // We didn't take the branch, so we're already dirty: return.
4341 // Use return-from-leaf
4342 masm.retl();
4343 masm.delayed()->nop();
4344
4345 // Not dirty.
4346 masm.bind(not_already_dirty);
4347 // First, dirty it.
4348 masm.stb(G0, O3, G0); // [cardPtr] := 0 (i.e., dirty).
4349 int dirty_card_q_index_byte_offset =
4350 in_bytes(JavaThread::dirty_card_queue_offset() +
4351 PtrQueue::byte_offset_of_index());
4352 int dirty_card_q_buf_byte_offset =
4353 in_bytes(JavaThread::dirty_card_queue_offset() +
4354 PtrQueue::byte_offset_of_buf());
4355 masm.bind(restart);
4356 masm.ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0);
4357
4358 masm.br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn,
4359 L0, refill);
4360 // If the branch is taken, no harm in executing this in the delay slot.
4361 masm.delayed()->ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1);
4362 masm.sub(L0, oopSize, L0);
4363
4364 masm.st_ptr(O3, L1, L0); // [_buf + index] := I0
4365 // Use return-from-leaf
4366 masm.retl();
4367 masm.delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset);
4368
4369 masm.bind(refill);
4370 address handle_zero =
4371 CAST_FROM_FN_PTR(address,
4372 &DirtyCardQueueSet::handle_zero_index_for_thread);
4373 // This should be rare enough that we can afford to save all the
4374 // scratch registers that the calling context might be using.
4375 masm.mov(G1_scratch, L3);
4376 masm.mov(G3_scratch, L5);
4377 // We need the value of O3 above (for the write into the buffer), so we
4378 // save and restore it.
4379 masm.mov(O3, L6);
4380 // Since the call will overwrite O7, we save and restore that, as well.
4381 masm.mov(O7, L4);
4382
4383 masm.call_VM_leaf(L7_thread_cache, handle_zero, G2_thread);
4384 masm.mov(L3, G1_scratch);
4385 masm.mov(L5, G3_scratch);
4386 masm.mov(L6, O3);
4387 masm.br(Assembler::always, /*annul*/false, Assembler::pt, restart);
4388 masm.delayed()->mov(L4, O7);
4389
4390 dirty_card_log_enqueue = start;
4391 dirty_card_log_enqueue_end = masm.pc();
4392 // XXX Should have a guarantee here about not going off the end!
4393 // Does it already do so? Do an experiment...
4394 }
4395
4396 static inline void
4397 generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) {
4398 if (dirty_card_log_enqueue == 0) {
4399 generate_dirty_card_log_enqueue(byte_map_base);
4400 assert(dirty_card_log_enqueue != 0, "postcondition.");
4401 if (G1SATBPrintStubs) {
4402 tty->print_cr("Generated dirty_card enqueue:");
4403 Disassembler::decode((u_char*)dirty_card_log_enqueue,
4404 dirty_card_log_enqueue_end,
4405 tty);
4406 }
4407 }
4408 }
4409
4410
4411 void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
4412
4413 Label filtered;
4414 MacroAssembler* post_filter_masm = this;
4415
4416 if (new_val == G0) return;
4417 if (G1DisablePostBarrier) return;
4418
4419 G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set();
4420 assert(bs->kind() == BarrierSet::G1SATBCT ||
4421 bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier");
4422 if (G1RSBarrierRegionFilter) {
4423 xor3(store_addr, new_val, tmp);
4424 #ifdef _LP64
4425 srlx(tmp, HeapRegion::LogOfHRGrainBytes, tmp);
4426 #else
4427 srl(tmp, HeapRegion::LogOfHRGrainBytes, tmp);
4428 #endif
4429 if (G1PrintCTFilterStats) {
4430 guarantee(tmp->is_global(), "Or stats won't work...");
4431 // This is a sleazy hack: I'm temporarily hijacking G2, which I
4432 // promise to restore.
4433 mov(new_val, G2);
4434 save_frame(0);
4435 mov(tmp, O0);
4436 mov(G2, O1);
4437 // Save G-regs that target may use.
4438 mov(G1, L1);
4439 mov(G2, L2);
4440 mov(G3, L3);
4441 mov(G4, L4);
4442 mov(G5, L5);
4443 call(CAST_FROM_FN_PTR(address, &count_ct_writes));
4444 delayed()->nop();
4445 mov(O0, G2);
4446 // Restore G-regs that target may have used.
4447 mov(L1, G1);
4448 mov(L3, G3);
4449 mov(L4, G4);
4450 mov(L5, G5);
4451 restore(G0, G0, G0);
4452 }
4453 // XXX Should I predict this taken or not? Does it mattern?
4454 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered);
4455 delayed()->nop();
4456 }
4457
4458 // If the "store_addr" register is an "in" or "local" register, move it to
4459 // a scratch reg so we can pass it as an argument.
4460 bool use_scr = !(store_addr->is_global() || store_addr->is_out());
4461 // Pick a scratch register different from "tmp".
4462 Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch);
4463 // Make sure we use up the delay slot!
4464 if (use_scr) {
4465 post_filter_masm->mov(store_addr, scr);
4466 } else {
4467 post_filter_masm->nop();
4468 }
4469 generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base);
4470 save_frame(0);
4471 call(dirty_card_log_enqueue);
4472 if (use_scr) {
4473 delayed()->mov(scr, O0);
4474 } else {
4475 delayed()->mov(store_addr->after_save(), O0);
4476 }
4477 restore();
4478
4479 bind(filtered);
4480
4481 }
4482
4483 #endif // SERIALGC
4484 ///////////////////////////////////////////////////////////////////////////////////
4485
4486 void MacroAssembler::card_write_barrier_post(Register store_addr, Register new_val, Register tmp) {
4487 // If we're writing constant NULL, we can skip the write barrier.
4488 if (new_val == G0) return;
4489 CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set();
4490 assert(bs->kind() == BarrierSet::CardTableModRef ||
4491 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier");
4492 card_table_write(bs->byte_map_base, tmp, store_addr);
4493 }
4494
4495 void MacroAssembler::load_klass(Register src_oop, Register klass) {
4496 // The number of bytes in this code is used by
4497 // MachCallDynamicJavaNode::ret_addr_offset()
4498 // if this changes, change that.
4499 if (UseCompressedOops) {
4500 lduw(src_oop, oopDesc::klass_offset_in_bytes(), klass);
4501 decode_heap_oop_not_null(klass);
4502 } else {
4503 ld_ptr(src_oop, oopDesc::klass_offset_in_bytes(), klass);
4504 }
4505 }
4506
4507 void MacroAssembler::store_klass(Register klass, Register dst_oop) {
4508 if (UseCompressedOops) {
4509 assert(dst_oop != klass, "not enough registers");
4510 encode_heap_oop_not_null(klass);
4511 st(klass, dst_oop, oopDesc::klass_offset_in_bytes());
4512 } else {
4513 st_ptr(klass, dst_oop, oopDesc::klass_offset_in_bytes());
4514 }
4515 }
4516
4517 void MacroAssembler::store_klass_gap(Register s, Register d) {
4518 if (UseCompressedOops) {
4519 assert(s != d, "not enough registers");
4520 st(s, d, oopDesc::klass_gap_offset_in_bytes());
4521 }
4522 }
4523
4524 void MacroAssembler::load_heap_oop(const Address& s, Register d) {
4525 if (UseCompressedOops) {
4526 lduw(s, d);
4527 decode_heap_oop(d);
4528 } else {
4529 ld_ptr(s, d);
4530 }
4531 }
4532
4533 void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) {
4534 if (UseCompressedOops) {
4535 lduw(s1, s2, d);
4536 decode_heap_oop(d, d);
4537 } else {
4538 ld_ptr(s1, s2, d);
4539 }
4540 }
4541
4542 void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) {
4543 if (UseCompressedOops) {
4544 lduw(s1, simm13a, d);
4545 decode_heap_oop(d, d);
4546 } else {
4547 ld_ptr(s1, simm13a, d);
4548 }
4549 }
4550
4551 void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) {
4552 if (UseCompressedOops) {
4553 assert(s1 != d && s2 != d, "not enough registers");
4554 encode_heap_oop(d);
4555 st(d, s1, s2);
4556 } else {
4557 st_ptr(d, s1, s2);
4558 }
4559 }
4560
4561 void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) {
4562 if (UseCompressedOops) {
4563 assert(s1 != d, "not enough registers");
4564 encode_heap_oop(d);
4565 st(d, s1, simm13a);
4566 } else {
4567 st_ptr(d, s1, simm13a);
4568 }
4569 }
4570
4571 void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) {
4572 if (UseCompressedOops) {
4573 assert(a.base() != d, "not enough registers");
4574 encode_heap_oop(d);
4575 st(d, a, offset);
4576 } else {
4577 st_ptr(d, a, offset);
4578 }
4579 }
4580
4581
4582 void MacroAssembler::encode_heap_oop(Register src, Register dst) {
4583 assert (UseCompressedOops, "must be compressed");
4584 assert (Universe::heap() != NULL, "java heap should be initialized");
4585 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4586 verify_oop(src);
4587 if (Universe::narrow_oop_base() == NULL) {
4588 srlx(src, LogMinObjAlignmentInBytes, dst);
4589 return;
4590 }
4591 Label done;
4592 if (src == dst) {
4593 // optimize for frequent case src == dst
4594 bpr(rc_nz, true, Assembler::pt, src, done);
4595 delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken
4596 bind(done);
4597 srlx(src, LogMinObjAlignmentInBytes, dst);
4598 } else {
4599 bpr(rc_z, false, Assembler::pn, src, done);
4600 delayed() -> mov(G0, dst);
4601 // could be moved before branch, and annulate delay,
4602 // but may add some unneeded work decoding null
4603 sub(src, G6_heapbase, dst);
4604 srlx(dst, LogMinObjAlignmentInBytes, dst);
4605 bind(done);
4606 }
4607 }
4608
4609
4610 void MacroAssembler::encode_heap_oop_not_null(Register r) {
4611 assert (UseCompressedOops, "must be compressed");
4612 assert (Universe::heap() != NULL, "java heap should be initialized");
4613 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4614 verify_oop(r);
4615 if (Universe::narrow_oop_base() != NULL)
4616 sub(r, G6_heapbase, r);
4617 srlx(r, LogMinObjAlignmentInBytes, r);
4618 }
4619
4620 void MacroAssembler::encode_heap_oop_not_null(Register src, Register dst) {
4621 assert (UseCompressedOops, "must be compressed");
4622 assert (Universe::heap() != NULL, "java heap should be initialized");
4623 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4624 verify_oop(src);
4625 if (Universe::narrow_oop_base() == NULL) {
4626 srlx(src, LogMinObjAlignmentInBytes, dst);
4627 } else {
4628 sub(src, G6_heapbase, dst);
4629 srlx(dst, LogMinObjAlignmentInBytes, dst);
4630 }
4631 }
4632
4633 // Same algorithm as oops.inline.hpp decode_heap_oop.
4634 void MacroAssembler::decode_heap_oop(Register src, Register dst) {
4635 assert (UseCompressedOops, "must be compressed");
4636 assert (Universe::heap() != NULL, "java heap should be initialized");
4637 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4638 sllx(src, LogMinObjAlignmentInBytes, dst);
4639 if (Universe::narrow_oop_base() != NULL) {
4640 Label done;
4641 bpr(rc_nz, true, Assembler::pt, dst, done);
4642 delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken
4643 bind(done);
4644 }
4645 verify_oop(dst);
4646 }
4647
4648 void MacroAssembler::decode_heap_oop_not_null(Register r) {
4649 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
4650 // pd_code_size_limit.
4651 // Also do not verify_oop as this is called by verify_oop.
4652 assert (UseCompressedOops, "must be compressed");
4653 assert (Universe::heap() != NULL, "java heap should be initialized");
4654 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4655 sllx(r, LogMinObjAlignmentInBytes, r);
4656 if (Universe::narrow_oop_base() != NULL)
4657 add(r, G6_heapbase, r);
4658 }
4659
4660 void MacroAssembler::decode_heap_oop_not_null(Register src, Register dst) {
4661 // Do not add assert code to this unless you change vtableStubs_sparc.cpp
4662 // pd_code_size_limit.
4663 // Also do not verify_oop as this is called by verify_oop.
4664 assert (UseCompressedOops, "must be compressed");
4665 assert (Universe::heap() != NULL, "java heap should be initialized");
4666 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
4667 sllx(src, LogMinObjAlignmentInBytes, dst);
4668 if (Universe::narrow_oop_base() != NULL)
4669 add(dst, G6_heapbase, dst);
4670 }
4671
4672 void MacroAssembler::reinit_heapbase() {
4673 if (UseCompressedOops) {
4674 // call indirectly to solve generation ordering problem
4675 AddressLiteral base(Universe::narrow_oop_base_addr());
4676 load_ptr_contents(base, G6_heapbase);
4677 }
4678 }
4679
4680 // Compare char[] arrays aligned to 4 bytes.
4681 void MacroAssembler::char_arrays_equals(Register ary1, Register ary2,
4682 Register limit, Register result,
4683 Register chr1, Register chr2, Label& Ldone) {
4684 Label Lvector, Lloop;
4685 assert(chr1 == result, "should be the same");
4686
4687 // Note: limit contains number of bytes (2*char_elements) != 0.
4688 andcc(limit, 0x2, chr1); // trailing character ?
4689 br(Assembler::zero, false, Assembler::pt, Lvector);
4690 delayed()->nop();
4691
4692 // compare the trailing char
4693 sub(limit, sizeof(jchar), limit);
4694 lduh(ary1, limit, chr1);
4695 lduh(ary2, limit, chr2);
4696 cmp(chr1, chr2);
4697 br(Assembler::notEqual, true, Assembler::pt, Ldone);
4698 delayed()->mov(G0, result); // not equal
4699
4700 // only one char ?
4701 br_on_reg_cond(rc_z, true, Assembler::pn, limit, Ldone);
4702 delayed()->add(G0, 1, result); // zero-length arrays are equal
4703
4704 // word by word compare, dont't need alignment check
4705 bind(Lvector);
4706 // Shift ary1 and ary2 to the end of the arrays, negate limit
4707 add(ary1, limit, ary1);
4708 add(ary2, limit, ary2);
4709 neg(limit, limit);
4710
4711 lduw(ary1, limit, chr1);
4712 bind(Lloop);
4713 lduw(ary2, limit, chr2);
4714 cmp(chr1, chr2);
4715 br(Assembler::notEqual, true, Assembler::pt, Ldone);
4716 delayed()->mov(G0, result); // not equal
4717 inccc(limit, 2*sizeof(jchar));
4718 // annul LDUW if branch is not taken to prevent access past end of array
4719 br(Assembler::notZero, true, Assembler::pt, Lloop);
4720 delayed()->lduw(ary1, limit, chr1); // hoisted
4721
4722 // Caller should set it:
4723 // add(G0, 1, result); // equals
4724 }
4725