src/share/vm/opto/compile.hpp
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src/share/vm/opto/compile.hpp

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*** 221,231 **** // Matching, CFG layout, allocation, code generation PhaseCFG* _cfg; // Results of CFG finding bool _select_24_bit_instr; // We selected an instruction with a 24-bit result bool _in_24_bit_fp_mode; // We are emitting instructions with 24-bit results ! bool _has_java_calls; // True if the method has java calls Matcher* _matcher; // Engine to map ideal to machine instructions PhaseRegAlloc* _regalloc; // Results of register allocation. int _frame_slots; // Size of total frame in stack slots CodeOffsets _code_offsets; // Offsets into the code for various interesting entries RegMask _FIRST_STACK_mask; // All stack slots usable for spills (depends on frame layout) --- 221,232 ---- // Matching, CFG layout, allocation, code generation PhaseCFG* _cfg; // Results of CFG finding bool _select_24_bit_instr; // We selected an instruction with a 24-bit result bool _in_24_bit_fp_mode; // We are emitting instructions with 24-bit results ! int _java_calls; // Number of java calls in the method ! int _inner_loops; // Number of inner loops in the method Matcher* _matcher; // Engine to map ideal to machine instructions PhaseRegAlloc* _regalloc; // Results of register allocation. int _frame_slots; // Size of total frame in stack slots CodeOffsets _code_offsets; // Offsets into the code for various interesting entries RegMask _FIRST_STACK_mask; // All stack slots usable for spills (depends on frame layout)
*** 503,513 **** // Matching, CFG layout, allocation, code generation PhaseCFG* cfg() { return _cfg; } bool select_24_bit_instr() const { return _select_24_bit_instr; } bool in_24_bit_fp_mode() const { return _in_24_bit_fp_mode; } ! bool has_java_calls() const { return _has_java_calls; } Matcher* matcher() { return _matcher; } PhaseRegAlloc* regalloc() { return _regalloc; } int frame_slots() const { return _frame_slots; } int frame_size_in_words() const; // frame_slots in units of the polymorphic 'words' RegMask& FIRST_STACK_mask() { return _FIRST_STACK_mask; } --- 504,516 ---- // Matching, CFG layout, allocation, code generation PhaseCFG* cfg() { return _cfg; } bool select_24_bit_instr() const { return _select_24_bit_instr; } bool in_24_bit_fp_mode() const { return _in_24_bit_fp_mode; } ! bool has_java_calls() const { return _java_calls > 0; } ! int java_calls() const { return _java_calls; } ! int inner_loops() const { return _inner_loops; } Matcher* matcher() { return _matcher; } PhaseRegAlloc* regalloc() { return _regalloc; } int frame_slots() const { return _frame_slots; } int frame_size_in_words() const; // frame_slots in units of the polymorphic 'words' RegMask& FIRST_STACK_mask() { return _FIRST_STACK_mask; }
*** 530,540 **** void set_24_bit_selection_and_mode(bool selection, bool mode) { _select_24_bit_instr = selection; _in_24_bit_fp_mode = mode; } ! void set_has_java_calls(bool z) { _has_java_calls = z; } // Instruction bits passed off to the VM int code_size() { return _method_size; } CodeBuffer* code_buffer() { return &_code_buffer; } int first_block_size() { return _first_block_size; } --- 533,544 ---- void set_24_bit_selection_and_mode(bool selection, bool mode) { _select_24_bit_instr = selection; _in_24_bit_fp_mode = mode; } ! void set_java_calls(int z) { _java_calls = z; } ! void set_inner_loops(int z) { _inner_loops = z; } // Instruction bits passed off to the VM int code_size() { return _method_size; } CodeBuffer* code_buffer() { return &_code_buffer; } int first_block_size() { return _first_block_size; }
src/share/vm/opto/compile.hpp
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