1 /*
2 * Copyright 2003-2010 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 #include "incls/_precompiled.incl"
26 #include "incls/_sharedRuntime_x86_64.cpp.incl"
27
28 DeoptimizationBlob *SharedRuntime::_deopt_blob;
29 #ifdef COMPILER2
30 UncommonTrapBlob *SharedRuntime::_uncommon_trap_blob;
31 ExceptionBlob *OptoRuntime::_exception_blob;
32 #endif // COMPILER2
33
34 SafepointBlob *SharedRuntime::_polling_page_safepoint_handler_blob;
35 SafepointBlob *SharedRuntime::_polling_page_return_handler_blob;
36 RuntimeStub* SharedRuntime::_wrong_method_blob;
37 RuntimeStub* SharedRuntime::_ic_miss_blob;
38 RuntimeStub* SharedRuntime::_resolve_opt_virtual_call_blob;
39 RuntimeStub* SharedRuntime::_resolve_virtual_call_blob;
40 RuntimeStub* SharedRuntime::_resolve_static_call_blob;
41
42 const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size;
43
44 #define __ masm->
45
46 class SimpleRuntimeFrame {
47
48 public:
49
50 // Most of the runtime stubs have this simple frame layout.
51 // This class exists to make the layout shared in one place.
52 // Offsets are for compiler stack slots, which are jints.
53 enum layout {
54 // The frame sender code expects that rbp will be in the "natural" place and
55 // will override any oopMap setting for it. We must therefore force the layout
56 // so that it agrees with the frame sender code.
57 rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt,
58 rbp_off2,
59 return_off, return_off2,
60 framesize
61 };
62 };
63
64 class RegisterSaver {
65 // Capture info about frame layout. Layout offsets are in jint
66 // units because compiler frame slots are jints.
67 #define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off
68 enum layout {
69 fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area
70 xmm_off = fpu_state_off + 160/BytesPerInt, // offset in fxsave save area
71 DEF_XMM_OFFS(0),
72 DEF_XMM_OFFS(1),
73 DEF_XMM_OFFS(2),
74 DEF_XMM_OFFS(3),
75 DEF_XMM_OFFS(4),
76 DEF_XMM_OFFS(5),
77 DEF_XMM_OFFS(6),
78 DEF_XMM_OFFS(7),
79 DEF_XMM_OFFS(8),
80 DEF_XMM_OFFS(9),
81 DEF_XMM_OFFS(10),
82 DEF_XMM_OFFS(11),
83 DEF_XMM_OFFS(12),
84 DEF_XMM_OFFS(13),
85 DEF_XMM_OFFS(14),
86 DEF_XMM_OFFS(15),
87 fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt),
88 fpu_stateH_end,
89 r15_off, r15H_off,
90 r14_off, r14H_off,
91 r13_off, r13H_off,
92 r12_off, r12H_off,
93 r11_off, r11H_off,
94 r10_off, r10H_off,
95 r9_off, r9H_off,
96 r8_off, r8H_off,
97 rdi_off, rdiH_off,
98 rsi_off, rsiH_off,
99 ignore_off, ignoreH_off, // extra copy of rbp
100 rsp_off, rspH_off,
101 rbx_off, rbxH_off,
102 rdx_off, rdxH_off,
103 rcx_off, rcxH_off,
104 rax_off, raxH_off,
105 // 16-byte stack alignment fill word: see MacroAssembler::push/pop_IU_state
106 align_off, alignH_off,
107 flags_off, flagsH_off,
108 // The frame sender code expects that rbp will be in the "natural" place and
109 // will override any oopMap setting for it. We must therefore force the layout
110 // so that it agrees with the frame sender code.
111 rbp_off, rbpH_off, // copy of rbp we will restore
112 return_off, returnH_off, // slot for return address
113 reg_save_size // size in compiler stack slots
114 };
115
116 public:
117 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
118 static void restore_live_registers(MacroAssembler* masm);
119
120 // Offsets into the register save area
121 // Used by deoptimization when it is managing result register
122 // values on its own
123
124 static int rax_offset_in_bytes(void) { return BytesPerInt * rax_off; }
125 static int rdx_offset_in_bytes(void) { return BytesPerInt * rdx_off; }
126 static int rbx_offset_in_bytes(void) { return BytesPerInt * rbx_off; }
127 static int xmm0_offset_in_bytes(void) { return BytesPerInt * xmm0_off; }
128 static int return_offset_in_bytes(void) { return BytesPerInt * return_off; }
129
130 // During deoptimization only the result registers need to be restored,
131 // all the other values have already been extracted.
132 static void restore_result_registers(MacroAssembler* masm);
133 };
134
135 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
136
137 // Always make the frame size 16-byte aligned
138 int frame_size_in_bytes = round_to(additional_frame_words*wordSize +
139 reg_save_size*BytesPerInt, 16);
140 // OopMap frame size is in compiler stack slots (jint's) not bytes or words
141 int frame_size_in_slots = frame_size_in_bytes / BytesPerInt;
142 // The caller will allocate additional_frame_words
143 int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt;
144 // CodeBlob frame size is in words.
145 int frame_size_in_words = frame_size_in_bytes / wordSize;
146 *total_frame_words = frame_size_in_words;
147
148 // Save registers, fpu state, and flags.
149 // We assume caller has already pushed the return address onto the
150 // stack, so rsp is 8-byte aligned here.
151 // We push rpb twice in this sequence because we want the real rbp
152 // to be under the return like a normal enter.
153
154 __ enter(); // rsp becomes 16-byte aligned here
155 __ push_CPU_state(); // Push a multiple of 16 bytes
156 if (frame::arg_reg_save_area_bytes != 0) {
157 // Allocate argument register save area
158 __ subptr(rsp, frame::arg_reg_save_area_bytes);
159 }
160
161 // Set an oopmap for the call site. This oopmap will map all
162 // oop-registers and debug-info registers as callee-saved. This
163 // will allow deoptimization at this safepoint to find all possible
164 // debug-info recordings, as well as let GC find all oops.
165
166 OopMapSet *oop_maps = new OopMapSet();
167 OopMap* map = new OopMap(frame_size_in_slots, 0);
168 map->set_callee_saved(VMRegImpl::stack2reg( rax_off + additional_frame_slots), rax->as_VMReg());
169 map->set_callee_saved(VMRegImpl::stack2reg( rcx_off + additional_frame_slots), rcx->as_VMReg());
170 map->set_callee_saved(VMRegImpl::stack2reg( rdx_off + additional_frame_slots), rdx->as_VMReg());
171 map->set_callee_saved(VMRegImpl::stack2reg( rbx_off + additional_frame_slots), rbx->as_VMReg());
172 // rbp location is known implicitly by the frame sender code, needs no oopmap
173 // and the location where rbp was saved by is ignored
174 map->set_callee_saved(VMRegImpl::stack2reg( rsi_off + additional_frame_slots), rsi->as_VMReg());
175 map->set_callee_saved(VMRegImpl::stack2reg( rdi_off + additional_frame_slots), rdi->as_VMReg());
176 map->set_callee_saved(VMRegImpl::stack2reg( r8_off + additional_frame_slots), r8->as_VMReg());
177 map->set_callee_saved(VMRegImpl::stack2reg( r9_off + additional_frame_slots), r9->as_VMReg());
178 map->set_callee_saved(VMRegImpl::stack2reg( r10_off + additional_frame_slots), r10->as_VMReg());
179 map->set_callee_saved(VMRegImpl::stack2reg( r11_off + additional_frame_slots), r11->as_VMReg());
180 map->set_callee_saved(VMRegImpl::stack2reg( r12_off + additional_frame_slots), r12->as_VMReg());
181 map->set_callee_saved(VMRegImpl::stack2reg( r13_off + additional_frame_slots), r13->as_VMReg());
182 map->set_callee_saved(VMRegImpl::stack2reg( r14_off + additional_frame_slots), r14->as_VMReg());
183 map->set_callee_saved(VMRegImpl::stack2reg( r15_off + additional_frame_slots), r15->as_VMReg());
184 map->set_callee_saved(VMRegImpl::stack2reg(xmm0_off + additional_frame_slots), xmm0->as_VMReg());
185 map->set_callee_saved(VMRegImpl::stack2reg(xmm1_off + additional_frame_slots), xmm1->as_VMReg());
186 map->set_callee_saved(VMRegImpl::stack2reg(xmm2_off + additional_frame_slots), xmm2->as_VMReg());
187 map->set_callee_saved(VMRegImpl::stack2reg(xmm3_off + additional_frame_slots), xmm3->as_VMReg());
188 map->set_callee_saved(VMRegImpl::stack2reg(xmm4_off + additional_frame_slots), xmm4->as_VMReg());
189 map->set_callee_saved(VMRegImpl::stack2reg(xmm5_off + additional_frame_slots), xmm5->as_VMReg());
190 map->set_callee_saved(VMRegImpl::stack2reg(xmm6_off + additional_frame_slots), xmm6->as_VMReg());
191 map->set_callee_saved(VMRegImpl::stack2reg(xmm7_off + additional_frame_slots), xmm7->as_VMReg());
192 map->set_callee_saved(VMRegImpl::stack2reg(xmm8_off + additional_frame_slots), xmm8->as_VMReg());
193 map->set_callee_saved(VMRegImpl::stack2reg(xmm9_off + additional_frame_slots), xmm9->as_VMReg());
194 map->set_callee_saved(VMRegImpl::stack2reg(xmm10_off + additional_frame_slots), xmm10->as_VMReg());
195 map->set_callee_saved(VMRegImpl::stack2reg(xmm11_off + additional_frame_slots), xmm11->as_VMReg());
196 map->set_callee_saved(VMRegImpl::stack2reg(xmm12_off + additional_frame_slots), xmm12->as_VMReg());
197 map->set_callee_saved(VMRegImpl::stack2reg(xmm13_off + additional_frame_slots), xmm13->as_VMReg());
198 map->set_callee_saved(VMRegImpl::stack2reg(xmm14_off + additional_frame_slots), xmm14->as_VMReg());
199 map->set_callee_saved(VMRegImpl::stack2reg(xmm15_off + additional_frame_slots), xmm15->as_VMReg());
200
201 // %%% These should all be a waste but we'll keep things as they were for now
202 if (true) {
203 map->set_callee_saved(VMRegImpl::stack2reg( raxH_off + additional_frame_slots),
204 rax->as_VMReg()->next());
205 map->set_callee_saved(VMRegImpl::stack2reg( rcxH_off + additional_frame_slots),
206 rcx->as_VMReg()->next());
207 map->set_callee_saved(VMRegImpl::stack2reg( rdxH_off + additional_frame_slots),
208 rdx->as_VMReg()->next());
209 map->set_callee_saved(VMRegImpl::stack2reg( rbxH_off + additional_frame_slots),
210 rbx->as_VMReg()->next());
211 // rbp location is known implicitly by the frame sender code, needs no oopmap
212 map->set_callee_saved(VMRegImpl::stack2reg( rsiH_off + additional_frame_slots),
213 rsi->as_VMReg()->next());
214 map->set_callee_saved(VMRegImpl::stack2reg( rdiH_off + additional_frame_slots),
215 rdi->as_VMReg()->next());
216 map->set_callee_saved(VMRegImpl::stack2reg( r8H_off + additional_frame_slots),
217 r8->as_VMReg()->next());
218 map->set_callee_saved(VMRegImpl::stack2reg( r9H_off + additional_frame_slots),
219 r9->as_VMReg()->next());
220 map->set_callee_saved(VMRegImpl::stack2reg( r10H_off + additional_frame_slots),
221 r10->as_VMReg()->next());
222 map->set_callee_saved(VMRegImpl::stack2reg( r11H_off + additional_frame_slots),
223 r11->as_VMReg()->next());
224 map->set_callee_saved(VMRegImpl::stack2reg( r12H_off + additional_frame_slots),
225 r12->as_VMReg()->next());
226 map->set_callee_saved(VMRegImpl::stack2reg( r13H_off + additional_frame_slots),
227 r13->as_VMReg()->next());
228 map->set_callee_saved(VMRegImpl::stack2reg( r14H_off + additional_frame_slots),
229 r14->as_VMReg()->next());
230 map->set_callee_saved(VMRegImpl::stack2reg( r15H_off + additional_frame_slots),
231 r15->as_VMReg()->next());
232 map->set_callee_saved(VMRegImpl::stack2reg(xmm0H_off + additional_frame_slots),
233 xmm0->as_VMReg()->next());
234 map->set_callee_saved(VMRegImpl::stack2reg(xmm1H_off + additional_frame_slots),
235 xmm1->as_VMReg()->next());
236 map->set_callee_saved(VMRegImpl::stack2reg(xmm2H_off + additional_frame_slots),
237 xmm2->as_VMReg()->next());
238 map->set_callee_saved(VMRegImpl::stack2reg(xmm3H_off + additional_frame_slots),
239 xmm3->as_VMReg()->next());
240 map->set_callee_saved(VMRegImpl::stack2reg(xmm4H_off + additional_frame_slots),
241 xmm4->as_VMReg()->next());
242 map->set_callee_saved(VMRegImpl::stack2reg(xmm5H_off + additional_frame_slots),
243 xmm5->as_VMReg()->next());
244 map->set_callee_saved(VMRegImpl::stack2reg(xmm6H_off + additional_frame_slots),
245 xmm6->as_VMReg()->next());
246 map->set_callee_saved(VMRegImpl::stack2reg(xmm7H_off + additional_frame_slots),
247 xmm7->as_VMReg()->next());
248 map->set_callee_saved(VMRegImpl::stack2reg(xmm8H_off + additional_frame_slots),
249 xmm8->as_VMReg()->next());
250 map->set_callee_saved(VMRegImpl::stack2reg(xmm9H_off + additional_frame_slots),
251 xmm9->as_VMReg()->next());
252 map->set_callee_saved(VMRegImpl::stack2reg(xmm10H_off + additional_frame_slots),
253 xmm10->as_VMReg()->next());
254 map->set_callee_saved(VMRegImpl::stack2reg(xmm11H_off + additional_frame_slots),
255 xmm11->as_VMReg()->next());
256 map->set_callee_saved(VMRegImpl::stack2reg(xmm12H_off + additional_frame_slots),
257 xmm12->as_VMReg()->next());
258 map->set_callee_saved(VMRegImpl::stack2reg(xmm13H_off + additional_frame_slots),
259 xmm13->as_VMReg()->next());
260 map->set_callee_saved(VMRegImpl::stack2reg(xmm14H_off + additional_frame_slots),
261 xmm14->as_VMReg()->next());
262 map->set_callee_saved(VMRegImpl::stack2reg(xmm15H_off + additional_frame_slots),
263 xmm15->as_VMReg()->next());
264 }
265
266 return map;
267 }
268
269 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
270 if (frame::arg_reg_save_area_bytes != 0) {
271 // Pop arg register save area
272 __ addptr(rsp, frame::arg_reg_save_area_bytes);
273 }
274 // Recover CPU state
275 __ pop_CPU_state();
276 // Get the rbp described implicitly by the calling convention (no oopMap)
277 __ pop(rbp);
278 }
279
280 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
281
282 // Just restore result register. Only used by deoptimization. By
283 // now any callee save register that needs to be restored to a c2
284 // caller of the deoptee has been extracted into the vframeArray
285 // and will be stuffed into the c2i adapter we create for later
286 // restoration so only result registers need to be restored here.
287
288 // Restore fp result register
289 __ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes()));
290 // Restore integer result register
291 __ movptr(rax, Address(rsp, rax_offset_in_bytes()));
292 __ movptr(rdx, Address(rsp, rdx_offset_in_bytes()));
293
294 // Pop all of the register save are off the stack except the return address
295 __ addptr(rsp, return_offset_in_bytes());
296 }
297
298 // The java_calling_convention describes stack locations as ideal slots on
299 // a frame with no abi restrictions. Since we must observe abi restrictions
300 // (like the placement of the register window) the slots must be biased by
301 // the following value.
302 static int reg2offset_in(VMReg r) {
303 // Account for saved rbp and return address
304 // This should really be in_preserve_stack_slots
305 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
306 }
307
308 static int reg2offset_out(VMReg r) {
309 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
310 }
311
312 // ---------------------------------------------------------------------------
313 // Read the array of BasicTypes from a signature, and compute where the
314 // arguments should go. Values in the VMRegPair regs array refer to 4-byte
315 // quantities. Values less than VMRegImpl::stack0 are registers, those above
316 // refer to 4-byte stack slots. All stack slots are based off of the stack pointer
317 // as framesizes are fixed.
318 // VMRegImpl::stack0 refers to the first slot 0(sp).
319 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
320 // up to RegisterImpl::number_of_registers) are the 64-bit
321 // integer registers.
322
323 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
324 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
325 // units regardless of build. Of course for i486 there is no 64 bit build
326
327 // The Java calling convention is a "shifted" version of the C ABI.
328 // By skipping the first C ABI register we can call non-static jni methods
329 // with small numbers of arguments without having to shuffle the arguments
330 // at all. Since we control the java ABI we ought to at least get some
331 // advantage out of it.
332
333 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
334 VMRegPair *regs,
335 int total_args_passed,
336 int is_outgoing) {
337
338 // Create the mapping between argument positions and
339 // registers.
340 static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = {
341 j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5
342 };
343 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_j] = {
344 j_farg0, j_farg1, j_farg2, j_farg3,
345 j_farg4, j_farg5, j_farg6, j_farg7
346 };
347
348
349 uint int_args = 0;
350 uint fp_args = 0;
351 uint stk_args = 0; // inc by 2 each time
352
353 for (int i = 0; i < total_args_passed; i++) {
354 switch (sig_bt[i]) {
355 case T_BOOLEAN:
356 case T_CHAR:
357 case T_BYTE:
358 case T_SHORT:
359 case T_INT:
360 if (int_args < Argument::n_int_register_parameters_j) {
361 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
362 } else {
363 regs[i].set1(VMRegImpl::stack2reg(stk_args));
364 stk_args += 2;
365 }
366 break;
367 case T_VOID:
368 // halves of T_LONG or T_DOUBLE
369 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
370 regs[i].set_bad();
371 break;
372 case T_LONG:
373 assert(sig_bt[i + 1] == T_VOID, "expecting half");
374 // fall through
375 case T_OBJECT:
376 case T_ARRAY:
377 case T_ADDRESS:
378 if (int_args < Argument::n_int_register_parameters_j) {
379 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
380 } else {
381 regs[i].set2(VMRegImpl::stack2reg(stk_args));
382 stk_args += 2;
383 }
384 break;
385 case T_FLOAT:
386 if (fp_args < Argument::n_float_register_parameters_j) {
387 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
388 } else {
389 regs[i].set1(VMRegImpl::stack2reg(stk_args));
390 stk_args += 2;
391 }
392 break;
393 case T_DOUBLE:
394 assert(sig_bt[i + 1] == T_VOID, "expecting half");
395 if (fp_args < Argument::n_float_register_parameters_j) {
396 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
397 } else {
398 regs[i].set2(VMRegImpl::stack2reg(stk_args));
399 stk_args += 2;
400 }
401 break;
402 default:
403 ShouldNotReachHere();
404 break;
405 }
406 }
407
408 return round_to(stk_args, 2);
409 }
410
411 // Patch the callers callsite with entry to compiled code if it exists.
412 static void patch_callers_callsite(MacroAssembler *masm) {
413 Label L;
414 __ verify_oop(rbx);
415 __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
416 __ jcc(Assembler::equal, L);
417
418 // Save the current stack pointer
419 __ mov(r13, rsp);
420 // Schedule the branch target address early.
421 // Call into the VM to patch the caller, then jump to compiled callee
422 // rax isn't live so capture return address while we easily can
423 __ movptr(rax, Address(rsp, 0));
424
425 // align stack so push_CPU_state doesn't fault
426 __ andptr(rsp, -(StackAlignmentInBytes));
427 __ push_CPU_state();
428
429
430 __ verify_oop(rbx);
431 // VM needs caller's callsite
432 // VM needs target method
433 // This needs to be a long call since we will relocate this adapter to
434 // the codeBuffer and it may not reach
435
436 // Allocate argument register save area
437 if (frame::arg_reg_save_area_bytes != 0) {
438 __ subptr(rsp, frame::arg_reg_save_area_bytes);
439 }
440 __ mov(c_rarg0, rbx);
441 __ mov(c_rarg1, rax);
442 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
443
444 // De-allocate argument register save area
445 if (frame::arg_reg_save_area_bytes != 0) {
446 __ addptr(rsp, frame::arg_reg_save_area_bytes);
447 }
448
449 __ pop_CPU_state();
450 // restore sp
451 __ mov(rsp, r13);
452 __ bind(L);
453 }
454
455 // Helper function to put tags in interpreter stack.
456 static void tag_stack(MacroAssembler *masm, const BasicType sig, int st_off) {
457 if (TaggedStackInterpreter) {
458 int tag_offset = st_off + Interpreter::expr_tag_offset_in_bytes(0);
459 if (sig == T_OBJECT || sig == T_ARRAY) {
460 __ movptr(Address(rsp, tag_offset), (int32_t) frame::TagReference);
461 } else if (sig == T_LONG || sig == T_DOUBLE) {
462 int next_tag_offset = st_off + Interpreter::expr_tag_offset_in_bytes(1);
463 __ movptr(Address(rsp, next_tag_offset), (int32_t) frame::TagValue);
464 __ movptr(Address(rsp, tag_offset), (int32_t) frame::TagValue);
465 } else {
466 __ movptr(Address(rsp, tag_offset), (int32_t) frame::TagValue);
467 }
468 }
469 }
470
471
472 static void gen_c2i_adapter(MacroAssembler *masm,
473 int total_args_passed,
474 int comp_args_on_stack,
475 const BasicType *sig_bt,
476 const VMRegPair *regs,
477 Label& skip_fixup) {
478 // Before we get into the guts of the C2I adapter, see if we should be here
479 // at all. We've come from compiled code and are attempting to jump to the
480 // interpreter, which means the caller made a static call to get here
481 // (vcalls always get a compiled target if there is one). Check for a
482 // compiled target. If there is one, we need to patch the caller's call.
483 patch_callers_callsite(masm);
484
485 __ bind(skip_fixup);
486
487 // Since all args are passed on the stack, total_args_passed *
488 // Interpreter::stackElementSize is the space we need. Plus 1 because
489 // we also account for the return address location since
490 // we store it first rather than hold it in rax across all the shuffling
491
492 int extraspace = (total_args_passed * Interpreter::stackElementSize()) + wordSize;
493
494 // stack is aligned, keep it that way
495 extraspace = round_to(extraspace, 2*wordSize);
496
497 // Get return address
498 __ pop(rax);
499
500 // set senderSP value
501 __ mov(r13, rsp);
502
503 __ subptr(rsp, extraspace);
504
505 // Store the return address in the expected location
506 __ movptr(Address(rsp, 0), rax);
507
508 // Now write the args into the outgoing interpreter space
509 for (int i = 0; i < total_args_passed; i++) {
510 if (sig_bt[i] == T_VOID) {
511 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
512 continue;
513 }
514
515 // offset to start parameters
516 int st_off = (total_args_passed - i) * Interpreter::stackElementSize() +
517 Interpreter::value_offset_in_bytes();
518 int next_off = st_off - Interpreter::stackElementSize();
519
520 // Say 4 args:
521 // i st_off
522 // 0 32 T_LONG
523 // 1 24 T_VOID
524 // 2 16 T_OBJECT
525 // 3 8 T_BOOL
526 // - 0 return address
527 //
528 // However to make thing extra confusing. Because we can fit a long/double in
529 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
530 // leaves one slot empty and only stores to a single slot. In this case the
531 // slot that is occupied is the T_VOID slot. See I said it was confusing.
532
533 VMReg r_1 = regs[i].first();
534 VMReg r_2 = regs[i].second();
535 if (!r_1->is_valid()) {
536 assert(!r_2->is_valid(), "");
537 continue;
538 }
539 if (r_1->is_stack()) {
540 // memory to memory use rax
541 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
542 if (!r_2->is_valid()) {
543 // sign extend??
544 __ movl(rax, Address(rsp, ld_off));
545 __ movptr(Address(rsp, st_off), rax);
546 tag_stack(masm, sig_bt[i], st_off);
547
548 } else {
549
550 __ movq(rax, Address(rsp, ld_off));
551
552 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
553 // T_DOUBLE and T_LONG use two slots in the interpreter
554 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
555 // ld_off == LSW, ld_off+wordSize == MSW
556 // st_off == MSW, next_off == LSW
557 __ movq(Address(rsp, next_off), rax);
558 #ifdef ASSERT
559 // Overwrite the unused slot with known junk
560 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
561 __ movptr(Address(rsp, st_off), rax);
562 #endif /* ASSERT */
563 tag_stack(masm, sig_bt[i], next_off);
564 } else {
565 __ movq(Address(rsp, st_off), rax);
566 tag_stack(masm, sig_bt[i], st_off);
567 }
568 }
569 } else if (r_1->is_Register()) {
570 Register r = r_1->as_Register();
571 if (!r_2->is_valid()) {
572 // must be only an int (or less ) so move only 32bits to slot
573 // why not sign extend??
574 __ movl(Address(rsp, st_off), r);
575 tag_stack(masm, sig_bt[i], st_off);
576 } else {
577 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
578 // T_DOUBLE and T_LONG use two slots in the interpreter
579 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
580 // long/double in gpr
581 #ifdef ASSERT
582 // Overwrite the unused slot with known junk
583 __ mov64(rax, CONST64(0xdeadffffdeadaaab));
584 __ movptr(Address(rsp, st_off), rax);
585 #endif /* ASSERT */
586 __ movq(Address(rsp, next_off), r);
587 tag_stack(masm, sig_bt[i], next_off);
588 } else {
589 __ movptr(Address(rsp, st_off), r);
590 tag_stack(masm, sig_bt[i], st_off);
591 }
592 }
593 } else {
594 assert(r_1->is_XMMRegister(), "");
595 if (!r_2->is_valid()) {
596 // only a float use just part of the slot
597 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
598 tag_stack(masm, sig_bt[i], st_off);
599 } else {
600 #ifdef ASSERT
601 // Overwrite the unused slot with known junk
602 __ mov64(rax, CONST64(0xdeadffffdeadaaac));
603 __ movptr(Address(rsp, st_off), rax);
604 #endif /* ASSERT */
605 __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister());
606 tag_stack(masm, sig_bt[i], next_off);
607 }
608 }
609 }
610
611 // Schedule the branch target address early.
612 __ movptr(rcx, Address(rbx, in_bytes(methodOopDesc::interpreter_entry_offset())));
613 __ jmp(rcx);
614 }
615
616 static void gen_i2c_adapter(MacroAssembler *masm,
617 int total_args_passed,
618 int comp_args_on_stack,
619 const BasicType *sig_bt,
620 const VMRegPair *regs) {
621
622 //
623 // We will only enter here from an interpreted frame and never from after
624 // passing thru a c2i. Azul allowed this but we do not. If we lose the
625 // race and use a c2i we will remain interpreted for the race loser(s).
626 // This removes all sorts of headaches on the x86 side and also eliminates
627 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
628
629
630 // Note: r13 contains the senderSP on entry. We must preserve it since
631 // we may do a i2c -> c2i transition if we lose a race where compiled
632 // code goes non-entrant while we get args ready.
633 // In addition we use r13 to locate all the interpreter args as
634 // we must align the stack to 16 bytes on an i2c entry else we
635 // lose alignment we expect in all compiled code and register
636 // save code can segv when fxsave instructions find improperly
637 // aligned stack pointer.
638
639 __ movptr(rax, Address(rsp, 0));
640
641 // Must preserve original SP for loading incoming arguments because
642 // we need to align the outgoing SP for compiled code.
643 __ movptr(r11, rsp);
644
645 // Cut-out for having no stack args. Since up to 2 int/oop args are passed
646 // in registers, we will occasionally have no stack args.
647 int comp_words_on_stack = 0;
648 if (comp_args_on_stack) {
649 // Sig words on the stack are greater-than VMRegImpl::stack0. Those in
650 // registers are below. By subtracting stack0, we either get a negative
651 // number (all values in registers) or the maximum stack slot accessed.
652
653 // Convert 4-byte c2 stack slots to words.
654 comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
655 // Round up to miminum stack alignment, in wordSize
656 comp_words_on_stack = round_to(comp_words_on_stack, 2);
657 __ subptr(rsp, comp_words_on_stack * wordSize);
658 }
659
660
661 // Ensure compiled code always sees stack at proper alignment
662 __ andptr(rsp, -16);
663
664 // push the return address and misalign the stack that youngest frame always sees
665 // as far as the placement of the call instruction
666 __ push(rax);
667
668 // Put saved SP in another register
669 const Register saved_sp = rax;
670 __ movptr(saved_sp, r11);
671
672 // Will jump to the compiled code just as if compiled code was doing it.
673 // Pre-load the register-jump target early, to schedule it better.
674 __ movptr(r11, Address(rbx, in_bytes(methodOopDesc::from_compiled_offset())));
675
676 // Now generate the shuffle code. Pick up all register args and move the
677 // rest through the floating point stack top.
678 for (int i = 0; i < total_args_passed; i++) {
679 if (sig_bt[i] == T_VOID) {
680 // Longs and doubles are passed in native word order, but misaligned
681 // in the 32-bit build.
682 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
683 continue;
684 }
685
686 // Pick up 0, 1 or 2 words from SP+offset.
687
688 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
689 "scrambled load targets?");
690 // Load in argument order going down.
691 int ld_off = (total_args_passed - i)*Interpreter::stackElementSize() + Interpreter::value_offset_in_bytes();
692 // Point to interpreter value (vs. tag)
693 int next_off = ld_off - Interpreter::stackElementSize();
694 //
695 //
696 //
697 VMReg r_1 = regs[i].first();
698 VMReg r_2 = regs[i].second();
699 if (!r_1->is_valid()) {
700 assert(!r_2->is_valid(), "");
701 continue;
702 }
703 if (r_1->is_stack()) {
704 // Convert stack slot to an SP offset (+ wordSize to account for return address )
705 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
706
707 // We can use r13 as a temp here because compiled code doesn't need r13 as an input
708 // and if we end up going thru a c2i because of a miss a reasonable value of r13
709 // will be generated.
710 if (!r_2->is_valid()) {
711 // sign extend???
712 __ movl(r13, Address(saved_sp, ld_off));
713 __ movptr(Address(rsp, st_off), r13);
714 } else {
715 //
716 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
717 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
718 // So we must adjust where to pick up the data to match the interpreter.
719 //
720 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
721 // are accessed as negative so LSW is at LOW address
722
723 // ld_off is MSW so get LSW
724 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
725 next_off : ld_off;
726 __ movq(r13, Address(saved_sp, offset));
727 // st_off is LSW (i.e. reg.first())
728 __ movq(Address(rsp, st_off), r13);
729 }
730 } else if (r_1->is_Register()) { // Register argument
731 Register r = r_1->as_Register();
732 assert(r != rax, "must be different");
733 if (r_2->is_valid()) {
734 //
735 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
736 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
737 // So we must adjust where to pick up the data to match the interpreter.
738
739 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
740 next_off : ld_off;
741
742 // this can be a misaligned move
743 __ movq(r, Address(saved_sp, offset));
744 } else {
745 // sign extend and use a full word?
746 __ movl(r, Address(saved_sp, ld_off));
747 }
748 } else {
749 if (!r_2->is_valid()) {
750 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
751 } else {
752 __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off));
753 }
754 }
755 }
756
757 // 6243940 We might end up in handle_wrong_method if
758 // the callee is deoptimized as we race thru here. If that
759 // happens we don't want to take a safepoint because the
760 // caller frame will look interpreted and arguments are now
761 // "compiled" so it is much better to make this transition
762 // invisible to the stack walking code. Unfortunately if
763 // we try and find the callee by normal means a safepoint
764 // is possible. So we stash the desired callee in the thread
765 // and the vm will find there should this case occur.
766
767 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
768
769 // put methodOop where a c2i would expect should we end up there
770 // only needed becaus eof c2 resolve stubs return methodOop as a result in
771 // rax
772 __ mov(rax, rbx);
773 __ jmp(r11);
774 }
775
776 // ---------------------------------------------------------------
777 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
778 int total_args_passed,
779 int comp_args_on_stack,
780 const BasicType *sig_bt,
781 const VMRegPair *regs,
782 AdapterFingerPrint* fingerprint) {
783 address i2c_entry = __ pc();
784
785 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
786
787 // -------------------------------------------------------------------------
788 // Generate a C2I adapter. On entry we know rbx holds the methodOop during calls
789 // to the interpreter. The args start out packed in the compiled layout. They
790 // need to be unpacked into the interpreter layout. This will almost always
791 // require some stack space. We grow the current (compiled) stack, then repack
792 // the args. We finally end in a jump to the generic interpreter entry point.
793 // On exit from the interpreter, the interpreter will restore our SP (lest the
794 // compiled code, which relys solely on SP and not RBP, get sick).
795
796 address c2i_unverified_entry = __ pc();
797 Label skip_fixup;
798 Label ok;
799
800 Register holder = rax;
801 Register receiver = j_rarg0;
802 Register temp = rbx;
803
804 {
805 __ verify_oop(holder);
806 __ load_klass(temp, receiver);
807 __ verify_oop(temp);
808
809 __ cmpptr(temp, Address(holder, compiledICHolderOopDesc::holder_klass_offset()));
810 __ movptr(rbx, Address(holder, compiledICHolderOopDesc::holder_method_offset()));
811 __ jcc(Assembler::equal, ok);
812 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
813
814 __ bind(ok);
815 // Method might have been compiled since the call site was patched to
816 // interpreted if that is the case treat it as a miss so we can get
817 // the call site corrected.
818 __ cmpptr(Address(rbx, in_bytes(methodOopDesc::code_offset())), (int32_t)NULL_WORD);
819 __ jcc(Assembler::equal, skip_fixup);
820 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
821 }
822
823 address c2i_entry = __ pc();
824
825 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
826
827 __ flush();
828 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
829 }
830
831 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
832 VMRegPair *regs,
833 int total_args_passed) {
834 // We return the amount of VMRegImpl stack slots we need to reserve for all
835 // the arguments NOT counting out_preserve_stack_slots.
836
837 // NOTE: These arrays will have to change when c1 is ported
838 #ifdef _WIN64
839 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
840 c_rarg0, c_rarg1, c_rarg2, c_rarg3
841 };
842 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
843 c_farg0, c_farg1, c_farg2, c_farg3
844 };
845 #else
846 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
847 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5
848 };
849 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
850 c_farg0, c_farg1, c_farg2, c_farg3,
851 c_farg4, c_farg5, c_farg6, c_farg7
852 };
853 #endif // _WIN64
854
855
856 uint int_args = 0;
857 uint fp_args = 0;
858 uint stk_args = 0; // inc by 2 each time
859
860 for (int i = 0; i < total_args_passed; i++) {
861 switch (sig_bt[i]) {
862 case T_BOOLEAN:
863 case T_CHAR:
864 case T_BYTE:
865 case T_SHORT:
866 case T_INT:
867 if (int_args < Argument::n_int_register_parameters_c) {
868 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
869 #ifdef _WIN64
870 fp_args++;
871 // Allocate slots for callee to stuff register args the stack.
872 stk_args += 2;
873 #endif
874 } else {
875 regs[i].set1(VMRegImpl::stack2reg(stk_args));
876 stk_args += 2;
877 }
878 break;
879 case T_LONG:
880 assert(sig_bt[i + 1] == T_VOID, "expecting half");
881 // fall through
882 case T_OBJECT:
883 case T_ARRAY:
884 case T_ADDRESS:
885 if (int_args < Argument::n_int_register_parameters_c) {
886 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
887 #ifdef _WIN64
888 fp_args++;
889 stk_args += 2;
890 #endif
891 } else {
892 regs[i].set2(VMRegImpl::stack2reg(stk_args));
893 stk_args += 2;
894 }
895 break;
896 case T_FLOAT:
897 if (fp_args < Argument::n_float_register_parameters_c) {
898 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
899 #ifdef _WIN64
900 int_args++;
901 // Allocate slots for callee to stuff register args the stack.
902 stk_args += 2;
903 #endif
904 } else {
905 regs[i].set1(VMRegImpl::stack2reg(stk_args));
906 stk_args += 2;
907 }
908 break;
909 case T_DOUBLE:
910 assert(sig_bt[i + 1] == T_VOID, "expecting half");
911 if (fp_args < Argument::n_float_register_parameters_c) {
912 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
913 #ifdef _WIN64
914 int_args++;
915 // Allocate slots for callee to stuff register args the stack.
916 stk_args += 2;
917 #endif
918 } else {
919 regs[i].set2(VMRegImpl::stack2reg(stk_args));
920 stk_args += 2;
921 }
922 break;
923 case T_VOID: // Halves of longs and doubles
924 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
925 regs[i].set_bad();
926 break;
927 default:
928 ShouldNotReachHere();
929 break;
930 }
931 }
932 #ifdef _WIN64
933 // windows abi requires that we always allocate enough stack space
934 // for 4 64bit registers to be stored down.
935 if (stk_args < 8) {
936 stk_args = 8;
937 }
938 #endif // _WIN64
939
940 return stk_args;
941 }
942
943 // On 64 bit we will store integer like items to the stack as
944 // 64 bits items (sparc abi) even though java would only store
945 // 32bits for a parameter. On 32bit it will simply be 32 bits
946 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
947 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
948 if (src.first()->is_stack()) {
949 if (dst.first()->is_stack()) {
950 // stack to stack
951 __ movslq(rax, Address(rbp, reg2offset_in(src.first())));
952 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
953 } else {
954 // stack to reg
955 __ movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
956 }
957 } else if (dst.first()->is_stack()) {
958 // reg to stack
959 // Do we really have to sign extend???
960 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
961 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
962 } else {
963 // Do we really have to sign extend???
964 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
965 if (dst.first() != src.first()) {
966 __ movq(dst.first()->as_Register(), src.first()->as_Register());
967 }
968 }
969 }
970
971
972 // An oop arg. Must pass a handle not the oop itself
973 static void object_move(MacroAssembler* masm,
974 OopMap* map,
975 int oop_handle_offset,
976 int framesize_in_slots,
977 VMRegPair src,
978 VMRegPair dst,
979 bool is_receiver,
980 int* receiver_offset) {
981
982 // must pass a handle. First figure out the location we use as a handle
983
984 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
985
986 // See if oop is NULL if it is we need no handle
987
988 if (src.first()->is_stack()) {
989
990 // Oop is already on the stack as an argument
991 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
992 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
993 if (is_receiver) {
994 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
995 }
996
997 __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
998 __ lea(rHandle, Address(rbp, reg2offset_in(src.first())));
999 // conditionally move a NULL
1000 __ cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1001 } else {
1002
1003 // Oop is in an a register we must store it to the space we reserve
1004 // on the stack for oop_handles and pass a handle if oop is non-NULL
1005
1006 const Register rOop = src.first()->as_Register();
1007 int oop_slot;
1008 if (rOop == j_rarg0)
1009 oop_slot = 0;
1010 else if (rOop == j_rarg1)
1011 oop_slot = 1;
1012 else if (rOop == j_rarg2)
1013 oop_slot = 2;
1014 else if (rOop == j_rarg3)
1015 oop_slot = 3;
1016 else if (rOop == j_rarg4)
1017 oop_slot = 4;
1018 else {
1019 assert(rOop == j_rarg5, "wrong register");
1020 oop_slot = 5;
1021 }
1022
1023 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1024 int offset = oop_slot*VMRegImpl::stack_slot_size;
1025
1026 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1027 // Store oop in handle area, may be NULL
1028 __ movptr(Address(rsp, offset), rOop);
1029 if (is_receiver) {
1030 *receiver_offset = offset;
1031 }
1032
1033 __ cmpptr(rOop, (int32_t)NULL_WORD);
1034 __ lea(rHandle, Address(rsp, offset));
1035 // conditionally move a NULL from the handle area where it was just stored
1036 __ cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1037 }
1038
1039 // If arg is on the stack then place it otherwise it is already in correct reg.
1040 if (dst.first()->is_stack()) {
1041 __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1042 }
1043 }
1044
1045 // A float arg may have to do float reg int reg conversion
1046 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1047 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1048
1049 // The calling conventions assures us that each VMregpair is either
1050 // all really one physical register or adjacent stack slots.
1051 // This greatly simplifies the cases here compared to sparc.
1052
1053 if (src.first()->is_stack()) {
1054 if (dst.first()->is_stack()) {
1055 __ movl(rax, Address(rbp, reg2offset_in(src.first())));
1056 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1057 } else {
1058 // stack to reg
1059 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1060 __ movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first())));
1061 }
1062 } else if (dst.first()->is_stack()) {
1063 // reg to stack
1064 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1065 __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1066 } else {
1067 // reg to reg
1068 // In theory these overlap but the ordering is such that this is likely a nop
1069 if ( src.first() != dst.first()) {
1070 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1071 }
1072 }
1073 }
1074
1075 // A long move
1076 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1077
1078 // The calling conventions assures us that each VMregpair is either
1079 // all really one physical register or adjacent stack slots.
1080 // This greatly simplifies the cases here compared to sparc.
1081
1082 if (src.is_single_phys_reg() ) {
1083 if (dst.is_single_phys_reg()) {
1084 if (dst.first() != src.first()) {
1085 __ mov(dst.first()->as_Register(), src.first()->as_Register());
1086 }
1087 } else {
1088 assert(dst.is_single_reg(), "not a stack pair");
1089 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1090 }
1091 } else if (dst.is_single_phys_reg()) {
1092 assert(src.is_single_reg(), "not a stack pair");
1093 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first())));
1094 } else {
1095 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1096 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1097 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1098 }
1099 }
1100
1101 // A double move
1102 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1103
1104 // The calling conventions assures us that each VMregpair is either
1105 // all really one physical register or adjacent stack slots.
1106 // This greatly simplifies the cases here compared to sparc.
1107
1108 if (src.is_single_phys_reg() ) {
1109 if (dst.is_single_phys_reg()) {
1110 // In theory these overlap but the ordering is such that this is likely a nop
1111 if ( src.first() != dst.first()) {
1112 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1113 }
1114 } else {
1115 assert(dst.is_single_reg(), "not a stack pair");
1116 __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1117 }
1118 } else if (dst.is_single_phys_reg()) {
1119 assert(src.is_single_reg(), "not a stack pair");
1120 __ movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first())));
1121 } else {
1122 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1123 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1124 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1125 }
1126 }
1127
1128
1129 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1130 // We always ignore the frame_slots arg and just use the space just below frame pointer
1131 // which by this time is free to use
1132 switch (ret_type) {
1133 case T_FLOAT:
1134 __ movflt(Address(rbp, -wordSize), xmm0);
1135 break;
1136 case T_DOUBLE:
1137 __ movdbl(Address(rbp, -wordSize), xmm0);
1138 break;
1139 case T_VOID: break;
1140 default: {
1141 __ movptr(Address(rbp, -wordSize), rax);
1142 }
1143 }
1144 }
1145
1146 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1147 // We always ignore the frame_slots arg and just use the space just below frame pointer
1148 // which by this time is free to use
1149 switch (ret_type) {
1150 case T_FLOAT:
1151 __ movflt(xmm0, Address(rbp, -wordSize));
1152 break;
1153 case T_DOUBLE:
1154 __ movdbl(xmm0, Address(rbp, -wordSize));
1155 break;
1156 case T_VOID: break;
1157 default: {
1158 __ movptr(rax, Address(rbp, -wordSize));
1159 }
1160 }
1161 }
1162
1163 static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1164 for ( int i = first_arg ; i < arg_count ; i++ ) {
1165 if (args[i].first()->is_Register()) {
1166 __ push(args[i].first()->as_Register());
1167 } else if (args[i].first()->is_XMMRegister()) {
1168 __ subptr(rsp, 2*wordSize);
1169 __ movdbl(Address(rsp, 0), args[i].first()->as_XMMRegister());
1170 }
1171 }
1172 }
1173
1174 static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1175 for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) {
1176 if (args[i].first()->is_Register()) {
1177 __ pop(args[i].first()->as_Register());
1178 } else if (args[i].first()->is_XMMRegister()) {
1179 __ movdbl(args[i].first()->as_XMMRegister(), Address(rsp, 0));
1180 __ addptr(rsp, 2*wordSize);
1181 }
1182 }
1183 }
1184
1185 // ---------------------------------------------------------------------------
1186 // Generate a native wrapper for a given method. The method takes arguments
1187 // in the Java compiled code convention, marshals them to the native
1188 // convention (handlizes oops, etc), transitions to native, makes the call,
1189 // returns to java state (possibly blocking), unhandlizes any result and
1190 // returns.
1191 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler *masm,
1192 methodHandle method,
1193 int total_in_args,
1194 int comp_args_on_stack,
1195 BasicType *in_sig_bt,
1196 VMRegPair *in_regs,
1197 BasicType ret_type) {
1198 // Native nmethod wrappers never take possesion of the oop arguments.
1199 // So the caller will gc the arguments. The only thing we need an
1200 // oopMap for is if the call is static
1201 //
1202 // An OopMap for lock (and class if static)
1203 OopMapSet *oop_maps = new OopMapSet();
1204 intptr_t start = (intptr_t)__ pc();
1205
1206 // We have received a description of where all the java arg are located
1207 // on entry to the wrapper. We need to convert these args to where
1208 // the jni function will expect them. To figure out where they go
1209 // we convert the java signature to a C signature by inserting
1210 // the hidden arguments as arg[0] and possibly arg[1] (static method)
1211
1212 int total_c_args = total_in_args + 1;
1213 if (method->is_static()) {
1214 total_c_args++;
1215 }
1216
1217 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
1218 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
1219
1220 int argc = 0;
1221 out_sig_bt[argc++] = T_ADDRESS;
1222 if (method->is_static()) {
1223 out_sig_bt[argc++] = T_OBJECT;
1224 }
1225
1226 for (int i = 0; i < total_in_args ; i++ ) {
1227 out_sig_bt[argc++] = in_sig_bt[i];
1228 }
1229
1230 // Now figure out where the args must be stored and how much stack space
1231 // they require.
1232 //
1233 int out_arg_slots;
1234 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
1235
1236 // Compute framesize for the wrapper. We need to handlize all oops in
1237 // incoming registers
1238
1239 // Calculate the total number of stack slots we will need.
1240
1241 // First count the abi requirement plus all of the outgoing args
1242 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
1243
1244 // Now the space for the inbound oop handle area
1245
1246 int oop_handle_offset = stack_slots;
1247 stack_slots += 6*VMRegImpl::slots_per_word;
1248
1249 // Now any space we need for handlizing a klass if static method
1250
1251 int oop_temp_slot_offset = 0;
1252 int klass_slot_offset = 0;
1253 int klass_offset = -1;
1254 int lock_slot_offset = 0;
1255 bool is_static = false;
1256
1257 if (method->is_static()) {
1258 klass_slot_offset = stack_slots;
1259 stack_slots += VMRegImpl::slots_per_word;
1260 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
1261 is_static = true;
1262 }
1263
1264 // Plus a lock if needed
1265
1266 if (method->is_synchronized()) {
1267 lock_slot_offset = stack_slots;
1268 stack_slots += VMRegImpl::slots_per_word;
1269 }
1270
1271 // Now a place (+2) to save return values or temp during shuffling
1272 // + 4 for return address (which we own) and saved rbp
1273 stack_slots += 6;
1274
1275 // Ok The space we have allocated will look like:
1276 //
1277 //
1278 // FP-> | |
1279 // |---------------------|
1280 // | 2 slots for moves |
1281 // |---------------------|
1282 // | lock box (if sync) |
1283 // |---------------------| <- lock_slot_offset
1284 // | klass (if static) |
1285 // |---------------------| <- klass_slot_offset
1286 // | oopHandle area |
1287 // |---------------------| <- oop_handle_offset (6 java arg registers)
1288 // | outbound memory |
1289 // | based arguments |
1290 // | |
1291 // |---------------------|
1292 // | |
1293 // SP-> | out_preserved_slots |
1294 //
1295 //
1296
1297
1298 // Now compute actual number of stack words we need rounding to make
1299 // stack properly aligned.
1300 stack_slots = round_to(stack_slots, StackAlignmentInSlots);
1301
1302 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
1303
1304
1305 // First thing make an ic check to see if we should even be here
1306
1307 // We are free to use all registers as temps without saving them and
1308 // restoring them except rbp. rbp is the only callee save register
1309 // as far as the interpreter and the compiler(s) are concerned.
1310
1311
1312 const Register ic_reg = rax;
1313 const Register receiver = j_rarg0;
1314
1315 Label ok;
1316 Label exception_pending;
1317
1318 assert_different_registers(ic_reg, receiver, rscratch1);
1319 __ verify_oop(receiver);
1320 __ load_klass(rscratch1, receiver);
1321 __ cmpq(ic_reg, rscratch1);
1322 __ jcc(Assembler::equal, ok);
1323
1324 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1325
1326 __ bind(ok);
1327
1328 // Verified entry point must be aligned
1329 __ align(8);
1330
1331 int vep_offset = ((intptr_t)__ pc()) - start;
1332
1333 // The instruction at the verified entry point must be 5 bytes or longer
1334 // because it can be patched on the fly by make_non_entrant. The stack bang
1335 // instruction fits that requirement.
1336
1337 // Generate stack overflow check
1338
1339 if (UseStackBanging) {
1340 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
1341 } else {
1342 // need a 5 byte instruction to allow MT safe patching to non-entrant
1343 __ fat_nop();
1344 }
1345
1346 // Generate a new frame for the wrapper.
1347 __ enter();
1348 // -2 because return address is already present and so is saved rbp
1349 __ subptr(rsp, stack_size - 2*wordSize);
1350
1351 // Frame is now completed as far as size and linkage.
1352
1353 int frame_complete = ((intptr_t)__ pc()) - start;
1354
1355 #ifdef ASSERT
1356 {
1357 Label L;
1358 __ mov(rax, rsp);
1359 __ andptr(rax, -16); // must be 16 byte boundary (see amd64 ABI)
1360 __ cmpptr(rax, rsp);
1361 __ jcc(Assembler::equal, L);
1362 __ stop("improperly aligned stack");
1363 __ bind(L);
1364 }
1365 #endif /* ASSERT */
1366
1367
1368 // We use r14 as the oop handle for the receiver/klass
1369 // It is callee save so it survives the call to native
1370
1371 const Register oop_handle_reg = r14;
1372
1373
1374
1375 //
1376 // We immediately shuffle the arguments so that any vm call we have to
1377 // make from here on out (sync slow path, jvmti, etc.) we will have
1378 // captured the oops from our caller and have a valid oopMap for
1379 // them.
1380
1381 // -----------------
1382 // The Grand Shuffle
1383
1384 // The Java calling convention is either equal (linux) or denser (win64) than the
1385 // c calling convention. However the because of the jni_env argument the c calling
1386 // convention always has at least one more (and two for static) arguments than Java.
1387 // Therefore if we move the args from java -> c backwards then we will never have
1388 // a register->register conflict and we don't have to build a dependency graph
1389 // and figure out how to break any cycles.
1390 //
1391
1392 // Record esp-based slot for receiver on stack for non-static methods
1393 int receiver_offset = -1;
1394
1395 // This is a trick. We double the stack slots so we can claim
1396 // the oops in the caller's frame. Since we are sure to have
1397 // more args than the caller doubling is enough to make
1398 // sure we can capture all the incoming oop args from the
1399 // caller.
1400 //
1401 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1402
1403 // Mark location of rbp (someday)
1404 // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rbp));
1405
1406 // Use eax, ebx as temporaries during any memory-memory moves we have to do
1407 // All inbound args are referenced based on rbp and all outbound args via rsp.
1408
1409
1410 #ifdef ASSERT
1411 bool reg_destroyed[RegisterImpl::number_of_registers];
1412 bool freg_destroyed[XMMRegisterImpl::number_of_registers];
1413 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
1414 reg_destroyed[r] = false;
1415 }
1416 for ( int f = 0 ; f < XMMRegisterImpl::number_of_registers ; f++ ) {
1417 freg_destroyed[f] = false;
1418 }
1419
1420 #endif /* ASSERT */
1421
1422
1423 int c_arg = total_c_args - 1;
1424 for ( int i = total_in_args - 1; i >= 0 ; i--, c_arg-- ) {
1425 #ifdef ASSERT
1426 if (in_regs[i].first()->is_Register()) {
1427 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!");
1428 } else if (in_regs[i].first()->is_XMMRegister()) {
1429 assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!");
1430 }
1431 if (out_regs[c_arg].first()->is_Register()) {
1432 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
1433 } else if (out_regs[c_arg].first()->is_XMMRegister()) {
1434 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
1435 }
1436 #endif /* ASSERT */
1437 switch (in_sig_bt[i]) {
1438 case T_ARRAY:
1439 case T_OBJECT:
1440 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
1441 ((i == 0) && (!is_static)),
1442 &receiver_offset);
1443 break;
1444 case T_VOID:
1445 break;
1446
1447 case T_FLOAT:
1448 float_move(masm, in_regs[i], out_regs[c_arg]);
1449 break;
1450
1451 case T_DOUBLE:
1452 assert( i + 1 < total_in_args &&
1453 in_sig_bt[i + 1] == T_VOID &&
1454 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
1455 double_move(masm, in_regs[i], out_regs[c_arg]);
1456 break;
1457
1458 case T_LONG :
1459 long_move(masm, in_regs[i], out_regs[c_arg]);
1460 break;
1461
1462 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
1463
1464 default:
1465 move32_64(masm, in_regs[i], out_regs[c_arg]);
1466 }
1467 }
1468
1469 // point c_arg at the first arg that is already loaded in case we
1470 // need to spill before we call out
1471 c_arg++;
1472
1473 // Pre-load a static method's oop into r14. Used both by locking code and
1474 // the normal JNI call code.
1475 if (method->is_static()) {
1476
1477 // load oop into a register
1478 __ movoop(oop_handle_reg, JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()));
1479
1480 // Now handlize the static class mirror it's known not-null.
1481 __ movptr(Address(rsp, klass_offset), oop_handle_reg);
1482 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
1483
1484 // Now get the handle
1485 __ lea(oop_handle_reg, Address(rsp, klass_offset));
1486 // store the klass handle as second argument
1487 __ movptr(c_rarg1, oop_handle_reg);
1488 // and protect the arg if we must spill
1489 c_arg--;
1490 }
1491
1492 // Change state to native (we save the return address in the thread, since it might not
1493 // be pushed on the stack when we do a a stack traversal). It is enough that the pc()
1494 // points into the right code segment. It does not have to be the correct return pc.
1495 // We use the same pc/oopMap repeatedly when we call out
1496
1497 intptr_t the_pc = (intptr_t) __ pc();
1498 oop_maps->add_gc_map(the_pc - start, map);
1499
1500 __ set_last_Java_frame(rsp, noreg, (address)the_pc);
1501
1502
1503 // We have all of the arguments setup at this point. We must not touch any register
1504 // argument registers at this point (what if we save/restore them there are no oop?
1505
1506 {
1507 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
1508 // protect the args we've loaded
1509 save_args(masm, total_c_args, c_arg, out_regs);
1510 __ movoop(c_rarg1, JNIHandles::make_local(method()));
1511 __ call_VM_leaf(
1512 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
1513 r15_thread, c_rarg1);
1514 restore_args(masm, total_c_args, c_arg, out_regs);
1515 }
1516
1517 // RedefineClasses() tracing support for obsolete method entry
1518 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
1519 // protect the args we've loaded
1520 save_args(masm, total_c_args, c_arg, out_regs);
1521 __ movoop(c_rarg1, JNIHandles::make_local(method()));
1522 __ call_VM_leaf(
1523 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
1524 r15_thread, c_rarg1);
1525 restore_args(masm, total_c_args, c_arg, out_regs);
1526 }
1527
1528 // Lock a synchronized method
1529
1530 // Register definitions used by locking and unlocking
1531
1532 const Register swap_reg = rax; // Must use rax for cmpxchg instruction
1533 const Register obj_reg = rbx; // Will contain the oop
1534 const Register lock_reg = r13; // Address of compiler lock object (BasicLock)
1535 const Register old_hdr = r13; // value of old header at unlock time
1536
1537 Label slow_path_lock;
1538 Label lock_done;
1539
1540 if (method->is_synchronized()) {
1541
1542
1543 const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
1544
1545 // Get the handle (the 2nd argument)
1546 __ mov(oop_handle_reg, c_rarg1);
1547
1548 // Get address of the box
1549
1550 __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
1551
1552 // Load the oop from the handle
1553 __ movptr(obj_reg, Address(oop_handle_reg, 0));
1554
1555 if (UseBiasedLocking) {
1556 __ biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, lock_done, &slow_path_lock);
1557 }
1558
1559 // Load immediate 1 into swap_reg %rax
1560 __ movl(swap_reg, 1);
1561
1562 // Load (object->mark() | 1) into swap_reg %rax
1563 __ orptr(swap_reg, Address(obj_reg, 0));
1564
1565 // Save (object->mark() | 1) into BasicLock's displaced header
1566 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
1567
1568 if (os::is_MP()) {
1569 __ lock();
1570 }
1571
1572 // src -> dest iff dest == rax else rax <- dest
1573 __ cmpxchgptr(lock_reg, Address(obj_reg, 0));
1574 __ jcc(Assembler::equal, lock_done);
1575
1576 // Hmm should this move to the slow path code area???
1577
1578 // Test if the oopMark is an obvious stack pointer, i.e.,
1579 // 1) (mark & 3) == 0, and
1580 // 2) rsp <= mark < mark + os::pagesize()
1581 // These 3 tests can be done by evaluating the following
1582 // expression: ((mark - rsp) & (3 - os::vm_page_size())),
1583 // assuming both stack pointer and pagesize have their
1584 // least significant 2 bits clear.
1585 // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg
1586
1587 __ subptr(swap_reg, rsp);
1588 __ andptr(swap_reg, 3 - os::vm_page_size());
1589
1590 // Save the test result, for recursive case, the result is zero
1591 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
1592 __ jcc(Assembler::notEqual, slow_path_lock);
1593
1594 // Slow path will re-enter here
1595
1596 __ bind(lock_done);
1597 }
1598
1599
1600 // Finally just about ready to make the JNI call
1601
1602
1603 // get JNIEnv* which is first argument to native
1604
1605 __ lea(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset())));
1606
1607 // Now set thread in native
1608 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native);
1609
1610 __ call(RuntimeAddress(method->native_function()));
1611
1612 // Either restore the MXCSR register after returning from the JNI Call
1613 // or verify that it wasn't changed.
1614 if (RestoreMXCSROnJNICalls) {
1615 __ ldmxcsr(ExternalAddress(StubRoutines::x86::mxcsr_std()));
1616
1617 }
1618 else if (CheckJNICalls ) {
1619 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::verify_mxcsr_entry())));
1620 }
1621
1622
1623 // Unpack native results.
1624 switch (ret_type) {
1625 case T_BOOLEAN: __ c2bool(rax); break;
1626 case T_CHAR : __ movzwl(rax, rax); break;
1627 case T_BYTE : __ sign_extend_byte (rax); break;
1628 case T_SHORT : __ sign_extend_short(rax); break;
1629 case T_INT : /* nothing to do */ break;
1630 case T_DOUBLE :
1631 case T_FLOAT :
1632 // Result is in xmm0 we'll save as needed
1633 break;
1634 case T_ARRAY: // Really a handle
1635 case T_OBJECT: // Really a handle
1636 break; // can't de-handlize until after safepoint check
1637 case T_VOID: break;
1638 case T_LONG: break;
1639 default : ShouldNotReachHere();
1640 }
1641
1642 // Switch thread to "native transition" state before reading the synchronization state.
1643 // This additional state is necessary because reading and testing the synchronization
1644 // state is not atomic w.r.t. GC, as this scenario demonstrates:
1645 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
1646 // VM thread changes sync state to synchronizing and suspends threads for GC.
1647 // Thread A is resumed to finish this native method, but doesn't block here since it
1648 // didn't see any synchronization is progress, and escapes.
1649 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
1650
1651 if(os::is_MP()) {
1652 if (UseMembar) {
1653 // Force this write out before the read below
1654 __ membar(Assembler::Membar_mask_bits(
1655 Assembler::LoadLoad | Assembler::LoadStore |
1656 Assembler::StoreLoad | Assembler::StoreStore));
1657 } else {
1658 // Write serialization page so VM thread can do a pseudo remote membar.
1659 // We use the current thread pointer to calculate a thread specific
1660 // offset to write to within the page. This minimizes bus traffic
1661 // due to cache line collision.
1662 __ serialize_memory(r15_thread, rcx);
1663 }
1664 }
1665
1666
1667 // check for safepoint operation in progress and/or pending suspend requests
1668 {
1669 Label Continue;
1670
1671 __ cmp32(ExternalAddress((address)SafepointSynchronize::address_of_state()),
1672 SafepointSynchronize::_not_synchronized);
1673
1674 Label L;
1675 __ jcc(Assembler::notEqual, L);
1676 __ cmpl(Address(r15_thread, JavaThread::suspend_flags_offset()), 0);
1677 __ jcc(Assembler::equal, Continue);
1678 __ bind(L);
1679
1680 // Don't use call_VM as it will see a possible pending exception and forward it
1681 // and never return here preventing us from clearing _last_native_pc down below.
1682 // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are
1683 // preserved and correspond to the bcp/locals pointers. So we do a runtime call
1684 // by hand.
1685 //
1686 save_native_result(masm, ret_type, stack_slots);
1687 __ mov(c_rarg0, r15_thread);
1688 __ mov(r12, rsp); // remember sp
1689 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
1690 __ andptr(rsp, -16); // align stack as required by ABI
1691 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans)));
1692 __ mov(rsp, r12); // restore sp
1693 __ reinit_heapbase();
1694 // Restore any method result value
1695 restore_native_result(masm, ret_type, stack_slots);
1696 __ bind(Continue);
1697 }
1698
1699 // change thread state
1700 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_Java);
1701
1702 Label reguard;
1703 Label reguard_done;
1704 __ cmpl(Address(r15_thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled);
1705 __ jcc(Assembler::equal, reguard);
1706 __ bind(reguard_done);
1707
1708 // native result if any is live
1709
1710 // Unlock
1711 Label unlock_done;
1712 Label slow_path_unlock;
1713 if (method->is_synchronized()) {
1714
1715 // Get locked oop from the handle we passed to jni
1716 __ movptr(obj_reg, Address(oop_handle_reg, 0));
1717
1718 Label done;
1719
1720 if (UseBiasedLocking) {
1721 __ biased_locking_exit(obj_reg, old_hdr, done);
1722 }
1723
1724 // Simple recursive lock?
1725
1726 __ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD);
1727 __ jcc(Assembler::equal, done);
1728
1729 // Must save rax if if it is live now because cmpxchg must use it
1730 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
1731 save_native_result(masm, ret_type, stack_slots);
1732 }
1733
1734
1735 // get address of the stack lock
1736 __ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
1737 // get old displaced header
1738 __ movptr(old_hdr, Address(rax, 0));
1739
1740 // Atomic swap old header if oop still contains the stack lock
1741 if (os::is_MP()) {
1742 __ lock();
1743 }
1744 __ cmpxchgptr(old_hdr, Address(obj_reg, 0));
1745 __ jcc(Assembler::notEqual, slow_path_unlock);
1746
1747 // slow path re-enters here
1748 __ bind(unlock_done);
1749 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
1750 restore_native_result(masm, ret_type, stack_slots);
1751 }
1752
1753 __ bind(done);
1754
1755 }
1756 {
1757 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
1758 save_native_result(masm, ret_type, stack_slots);
1759 __ movoop(c_rarg1, JNIHandles::make_local(method()));
1760 __ call_VM_leaf(
1761 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
1762 r15_thread, c_rarg1);
1763 restore_native_result(masm, ret_type, stack_slots);
1764 }
1765
1766 __ reset_last_Java_frame(false, true);
1767
1768 // Unpack oop result
1769 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
1770 Label L;
1771 __ testptr(rax, rax);
1772 __ jcc(Assembler::zero, L);
1773 __ movptr(rax, Address(rax, 0));
1774 __ bind(L);
1775 __ verify_oop(rax);
1776 }
1777
1778 // reset handle block
1779 __ movptr(rcx, Address(r15_thread, JavaThread::active_handles_offset()));
1780 __ movptr(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD);
1781
1782 // pop our frame
1783
1784 __ leave();
1785
1786 // Any exception pending?
1787 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
1788 __ jcc(Assembler::notEqual, exception_pending);
1789
1790 // Return
1791
1792 __ ret(0);
1793
1794 // Unexpected paths are out of line and go here
1795
1796 // forward the exception
1797 __ bind(exception_pending);
1798
1799 // and forward the exception
1800 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1801
1802
1803 // Slow path locking & unlocking
1804 if (method->is_synchronized()) {
1805
1806 // BEGIN Slow path lock
1807 __ bind(slow_path_lock);
1808
1809 // has last_Java_frame setup. No exceptions so do vanilla call not call_VM
1810 // args are (oop obj, BasicLock* lock, JavaThread* thread)
1811
1812 // protect the args we've loaded
1813 save_args(masm, total_c_args, c_arg, out_regs);
1814
1815 __ mov(c_rarg0, obj_reg);
1816 __ mov(c_rarg1, lock_reg);
1817 __ mov(c_rarg2, r15_thread);
1818
1819 // Not a leaf but we have last_Java_frame setup as we want
1820 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3);
1821 restore_args(masm, total_c_args, c_arg, out_regs);
1822
1823 #ifdef ASSERT
1824 { Label L;
1825 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
1826 __ jcc(Assembler::equal, L);
1827 __ stop("no pending exception allowed on exit from monitorenter");
1828 __ bind(L);
1829 }
1830 #endif
1831 __ jmp(lock_done);
1832
1833 // END Slow path lock
1834
1835 // BEGIN Slow path unlock
1836 __ bind(slow_path_unlock);
1837
1838 // If we haven't already saved the native result we must save it now as xmm registers
1839 // are still exposed.
1840
1841 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
1842 save_native_result(masm, ret_type, stack_slots);
1843 }
1844
1845 __ lea(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
1846
1847 __ mov(c_rarg0, obj_reg);
1848 __ mov(r12, rsp); // remember sp
1849 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
1850 __ andptr(rsp, -16); // align stack as required by ABI
1851
1852 // Save pending exception around call to VM (which contains an EXCEPTION_MARK)
1853 // NOTE that obj_reg == rbx currently
1854 __ movptr(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset())));
1855 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
1856
1857 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)));
1858 __ mov(rsp, r12); // restore sp
1859 __ reinit_heapbase();
1860 #ifdef ASSERT
1861 {
1862 Label L;
1863 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
1864 __ jcc(Assembler::equal, L);
1865 __ stop("no pending exception allowed on exit complete_monitor_unlocking_C");
1866 __ bind(L);
1867 }
1868 #endif /* ASSERT */
1869
1870 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx);
1871
1872 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
1873 restore_native_result(masm, ret_type, stack_slots);
1874 }
1875 __ jmp(unlock_done);
1876
1877 // END Slow path unlock
1878
1879 } // synchronized
1880
1881 // SLOW PATH Reguard the stack if needed
1882
1883 __ bind(reguard);
1884 save_native_result(masm, ret_type, stack_slots);
1885 __ mov(r12, rsp); // remember sp
1886 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
1887 __ andptr(rsp, -16); // align stack as required by ABI
1888 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
1889 __ mov(rsp, r12); // restore sp
1890 __ reinit_heapbase();
1891 restore_native_result(masm, ret_type, stack_slots);
1892 // and continue
1893 __ jmp(reguard_done);
1894
1895
1896
1897 __ flush();
1898
1899 nmethod *nm = nmethod::new_native_nmethod(method,
1900 masm->code(),
1901 vep_offset,
1902 frame_complete,
1903 stack_slots / VMRegImpl::slots_per_word,
1904 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
1905 in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size),
1906 oop_maps);
1907 return nm;
1908
1909 }
1910
1911 #ifdef HAVE_DTRACE_H
1912 // ---------------------------------------------------------------------------
1913 // Generate a dtrace nmethod for a given signature. The method takes arguments
1914 // in the Java compiled code convention, marshals them to the native
1915 // abi and then leaves nops at the position you would expect to call a native
1916 // function. When the probe is enabled the nops are replaced with a trap
1917 // instruction that dtrace inserts and the trace will cause a notification
1918 // to dtrace.
1919 //
1920 // The probes are only able to take primitive types and java/lang/String as
1921 // arguments. No other java types are allowed. Strings are converted to utf8
1922 // strings so that from dtrace point of view java strings are converted to C
1923 // strings. There is an arbitrary fixed limit on the total space that a method
1924 // can use for converting the strings. (256 chars per string in the signature).
1925 // So any java string larger then this is truncated.
1926
1927 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
1928 static bool offsets_initialized = false;
1929
1930
1931 nmethod *SharedRuntime::generate_dtrace_nmethod(MacroAssembler *masm,
1932 methodHandle method) {
1933
1934
1935 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
1936 // be single threaded in this method.
1937 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
1938
1939 if (!offsets_initialized) {
1940 fp_offset[c_rarg0->as_VMReg()->value()] = -1 * wordSize;
1941 fp_offset[c_rarg1->as_VMReg()->value()] = -2 * wordSize;
1942 fp_offset[c_rarg2->as_VMReg()->value()] = -3 * wordSize;
1943 fp_offset[c_rarg3->as_VMReg()->value()] = -4 * wordSize;
1944 fp_offset[c_rarg4->as_VMReg()->value()] = -5 * wordSize;
1945 fp_offset[c_rarg5->as_VMReg()->value()] = -6 * wordSize;
1946
1947 fp_offset[c_farg0->as_VMReg()->value()] = -7 * wordSize;
1948 fp_offset[c_farg1->as_VMReg()->value()] = -8 * wordSize;
1949 fp_offset[c_farg2->as_VMReg()->value()] = -9 * wordSize;
1950 fp_offset[c_farg3->as_VMReg()->value()] = -10 * wordSize;
1951 fp_offset[c_farg4->as_VMReg()->value()] = -11 * wordSize;
1952 fp_offset[c_farg5->as_VMReg()->value()] = -12 * wordSize;
1953 fp_offset[c_farg6->as_VMReg()->value()] = -13 * wordSize;
1954 fp_offset[c_farg7->as_VMReg()->value()] = -14 * wordSize;
1955
1956 offsets_initialized = true;
1957 }
1958 // Fill in the signature array, for the calling-convention call.
1959 int total_args_passed = method->size_of_parameters();
1960
1961 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
1962 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
1963
1964 // The signature we are going to use for the trap that dtrace will see
1965 // java/lang/String is converted. We drop "this" and any other object
1966 // is converted to NULL. (A one-slot java/lang/Long object reference
1967 // is converted to a two-slot long, which is why we double the allocation).
1968 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
1969 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
1970
1971 int i=0;
1972 int total_strings = 0;
1973 int first_arg_to_pass = 0;
1974 int total_c_args = 0;
1975
1976 // Skip the receiver as dtrace doesn't want to see it
1977 if( !method->is_static() ) {
1978 in_sig_bt[i++] = T_OBJECT;
1979 first_arg_to_pass = 1;
1980 }
1981
1982 // We need to convert the java args to where a native (non-jni) function
1983 // would expect them. To figure out where they go we convert the java
1984 // signature to a C signature.
1985
1986 SignatureStream ss(method->signature());
1987 for ( ; !ss.at_return_type(); ss.next()) {
1988 BasicType bt = ss.type();
1989 in_sig_bt[i++] = bt; // Collect remaining bits of signature
1990 out_sig_bt[total_c_args++] = bt;
1991 if( bt == T_OBJECT) {
1992 symbolOop s = ss.as_symbol_or_null();
1993 if (s == vmSymbols::java_lang_String()) {
1994 total_strings++;
1995 out_sig_bt[total_c_args-1] = T_ADDRESS;
1996 } else if (s == vmSymbols::java_lang_Boolean() ||
1997 s == vmSymbols::java_lang_Character() ||
1998 s == vmSymbols::java_lang_Byte() ||
1999 s == vmSymbols::java_lang_Short() ||
2000 s == vmSymbols::java_lang_Integer() ||
2001 s == vmSymbols::java_lang_Float()) {
2002 out_sig_bt[total_c_args-1] = T_INT;
2003 } else if (s == vmSymbols::java_lang_Long() ||
2004 s == vmSymbols::java_lang_Double()) {
2005 out_sig_bt[total_c_args-1] = T_LONG;
2006 out_sig_bt[total_c_args++] = T_VOID;
2007 }
2008 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
2009 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
2010 // We convert double to long
2011 out_sig_bt[total_c_args-1] = T_LONG;
2012 out_sig_bt[total_c_args++] = T_VOID;
2013 } else if ( bt == T_FLOAT) {
2014 // We convert float to int
2015 out_sig_bt[total_c_args-1] = T_INT;
2016 }
2017 }
2018
2019 assert(i==total_args_passed, "validly parsed signature");
2020
2021 // Now get the compiled-Java layout as input arguments
2022 int comp_args_on_stack;
2023 comp_args_on_stack = SharedRuntime::java_calling_convention(
2024 in_sig_bt, in_regs, total_args_passed, false);
2025
2026 // Now figure out where the args must be stored and how much stack space
2027 // they require (neglecting out_preserve_stack_slots but space for storing
2028 // the 1st six register arguments). It's weird see int_stk_helper.
2029
2030 int out_arg_slots;
2031 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
2032
2033 // Calculate the total number of stack slots we will need.
2034
2035 // First count the abi requirement plus all of the outgoing args
2036 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2037
2038 // Now space for the string(s) we must convert
2039 int* string_locs = NEW_RESOURCE_ARRAY(int, total_strings + 1);
2040 for (i = 0; i < total_strings ; i++) {
2041 string_locs[i] = stack_slots;
2042 stack_slots += max_dtrace_string_size / VMRegImpl::stack_slot_size;
2043 }
2044
2045 // Plus the temps we might need to juggle register args
2046 // regs take two slots each
2047 stack_slots += (Argument::n_int_register_parameters_c +
2048 Argument::n_float_register_parameters_c) * 2;
2049
2050
2051 // + 4 for return address (which we own) and saved rbp,
2052
2053 stack_slots += 4;
2054
2055 // Ok The space we have allocated will look like:
2056 //
2057 //
2058 // FP-> | |
2059 // |---------------------|
2060 // | string[n] |
2061 // |---------------------| <- string_locs[n]
2062 // | string[n-1] |
2063 // |---------------------| <- string_locs[n-1]
2064 // | ... |
2065 // | ... |
2066 // |---------------------| <- string_locs[1]
2067 // | string[0] |
2068 // |---------------------| <- string_locs[0]
2069 // | outbound memory |
2070 // | based arguments |
2071 // | |
2072 // |---------------------|
2073 // | |
2074 // SP-> | out_preserved_slots |
2075 //
2076 //
2077
2078 // Now compute actual number of stack words we need rounding to make
2079 // stack properly aligned.
2080 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
2081
2082 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2083
2084 intptr_t start = (intptr_t)__ pc();
2085
2086 // First thing make an ic check to see if we should even be here
2087
2088 // We are free to use all registers as temps without saving them and
2089 // restoring them except rbp. rbp, is the only callee save register
2090 // as far as the interpreter and the compiler(s) are concerned.
2091
2092 const Register ic_reg = rax;
2093 const Register receiver = rcx;
2094 Label hit;
2095 Label exception_pending;
2096
2097
2098 __ verify_oop(receiver);
2099 __ cmpl(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes()));
2100 __ jcc(Assembler::equal, hit);
2101
2102 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
2103
2104 // verified entry must be aligned for code patching.
2105 // and the first 5 bytes must be in the same cache line
2106 // if we align at 8 then we will be sure 5 bytes are in the same line
2107 __ align(8);
2108
2109 __ bind(hit);
2110
2111 int vep_offset = ((intptr_t)__ pc()) - start;
2112
2113
2114 // The instruction at the verified entry point must be 5 bytes or longer
2115 // because it can be patched on the fly by make_non_entrant. The stack bang
2116 // instruction fits that requirement.
2117
2118 // Generate stack overflow check
2119
2120 if (UseStackBanging) {
2121 if (stack_size <= StackShadowPages*os::vm_page_size()) {
2122 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size());
2123 } else {
2124 __ movl(rax, stack_size);
2125 __ bang_stack_size(rax, rbx);
2126 }
2127 } else {
2128 // need a 5 byte instruction to allow MT safe patching to non-entrant
2129 __ fat_nop();
2130 }
2131
2132 assert(((uintptr_t)__ pc() - start - vep_offset) >= 5,
2133 "valid size for make_non_entrant");
2134
2135 // Generate a new frame for the wrapper.
2136 __ enter();
2137
2138 // -4 because return address is already present and so is saved rbp,
2139 if (stack_size - 2*wordSize != 0) {
2140 __ subq(rsp, stack_size - 2*wordSize);
2141 }
2142
2143 // Frame is now completed as far a size and linkage.
2144
2145 int frame_complete = ((intptr_t)__ pc()) - start;
2146
2147 int c_arg, j_arg;
2148
2149 // State of input register args
2150
2151 bool live[ConcreteRegisterImpl::number_of_registers];
2152
2153 live[j_rarg0->as_VMReg()->value()] = false;
2154 live[j_rarg1->as_VMReg()->value()] = false;
2155 live[j_rarg2->as_VMReg()->value()] = false;
2156 live[j_rarg3->as_VMReg()->value()] = false;
2157 live[j_rarg4->as_VMReg()->value()] = false;
2158 live[j_rarg5->as_VMReg()->value()] = false;
2159
2160 live[j_farg0->as_VMReg()->value()] = false;
2161 live[j_farg1->as_VMReg()->value()] = false;
2162 live[j_farg2->as_VMReg()->value()] = false;
2163 live[j_farg3->as_VMReg()->value()] = false;
2164 live[j_farg4->as_VMReg()->value()] = false;
2165 live[j_farg5->as_VMReg()->value()] = false;
2166 live[j_farg6->as_VMReg()->value()] = false;
2167 live[j_farg7->as_VMReg()->value()] = false;
2168
2169
2170 bool rax_is_zero = false;
2171
2172 // All args (except strings) destined for the stack are moved first
2173 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2174 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2175 VMRegPair src = in_regs[j_arg];
2176 VMRegPair dst = out_regs[c_arg];
2177
2178 // Get the real reg value or a dummy (rsp)
2179
2180 int src_reg = src.first()->is_reg() ?
2181 src.first()->value() :
2182 rsp->as_VMReg()->value();
2183
2184 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
2185 (in_sig_bt[j_arg] == T_OBJECT &&
2186 out_sig_bt[c_arg] != T_INT &&
2187 out_sig_bt[c_arg] != T_ADDRESS &&
2188 out_sig_bt[c_arg] != T_LONG);
2189
2190 live[src_reg] = !useless;
2191
2192 if (dst.first()->is_stack()) {
2193
2194 // Even though a string arg in a register is still live after this loop
2195 // after the string conversion loop (next) it will be dead so we take
2196 // advantage of that now for simpler code to manage live.
2197
2198 live[src_reg] = false;
2199 switch (in_sig_bt[j_arg]) {
2200
2201 case T_ARRAY:
2202 case T_OBJECT:
2203 {
2204 Address stack_dst(rsp, reg2offset_out(dst.first()));
2205
2206 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2207 // need to unbox a one-word value
2208 Register in_reg = rax;
2209 if ( src.first()->is_reg() ) {
2210 in_reg = src.first()->as_Register();
2211 } else {
2212 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
2213 rax_is_zero = false;
2214 }
2215 Label skipUnbox;
2216 __ movptr(Address(rsp, reg2offset_out(dst.first())),
2217 (int32_t)NULL_WORD);
2218 __ testq(in_reg, in_reg);
2219 __ jcc(Assembler::zero, skipUnbox);
2220
2221 BasicType bt = out_sig_bt[c_arg];
2222 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2223 Address src1(in_reg, box_offset);
2224 if ( bt == T_LONG ) {
2225 __ movq(in_reg, src1);
2226 __ movq(stack_dst, in_reg);
2227 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2228 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2229 } else {
2230 __ movl(in_reg, src1);
2231 __ movl(stack_dst, in_reg);
2232 }
2233
2234 __ bind(skipUnbox);
2235 } else if (out_sig_bt[c_arg] != T_ADDRESS) {
2236 // Convert the arg to NULL
2237 if (!rax_is_zero) {
2238 __ xorq(rax, rax);
2239 rax_is_zero = true;
2240 }
2241 __ movq(stack_dst, rax);
2242 }
2243 }
2244 break;
2245
2246 case T_VOID:
2247 break;
2248
2249 case T_FLOAT:
2250 // This does the right thing since we know it is destined for the
2251 // stack
2252 float_move(masm, src, dst);
2253 break;
2254
2255 case T_DOUBLE:
2256 // This does the right thing since we know it is destined for the
2257 // stack
2258 double_move(masm, src, dst);
2259 break;
2260
2261 case T_LONG :
2262 long_move(masm, src, dst);
2263 break;
2264
2265 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2266
2267 default:
2268 move32_64(masm, src, dst);
2269 }
2270 }
2271
2272 }
2273
2274 // If we have any strings we must store any register based arg to the stack
2275 // This includes any still live xmm registers too.
2276
2277 int sid = 0;
2278
2279 if (total_strings > 0 ) {
2280 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2281 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2282 VMRegPair src = in_regs[j_arg];
2283 VMRegPair dst = out_regs[c_arg];
2284
2285 if (src.first()->is_reg()) {
2286 Address src_tmp(rbp, fp_offset[src.first()->value()]);
2287
2288 // string oops were left untouched by the previous loop even if the
2289 // eventual (converted) arg is destined for the stack so park them
2290 // away now (except for first)
2291
2292 if (out_sig_bt[c_arg] == T_ADDRESS) {
2293 Address utf8_addr = Address(
2294 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
2295 if (sid != 1) {
2296 // The first string arg won't be killed until after the utf8
2297 // conversion
2298 __ movq(utf8_addr, src.first()->as_Register());
2299 }
2300 } else if (dst.first()->is_reg()) {
2301 if (in_sig_bt[j_arg] == T_FLOAT || in_sig_bt[j_arg] == T_DOUBLE) {
2302
2303 // Convert the xmm register to an int and store it in the reserved
2304 // location for the eventual c register arg
2305 XMMRegister f = src.first()->as_XMMRegister();
2306 if (in_sig_bt[j_arg] == T_FLOAT) {
2307 __ movflt(src_tmp, f);
2308 } else {
2309 __ movdbl(src_tmp, f);
2310 }
2311 } else {
2312 // If the arg is an oop type we don't support don't bother to store
2313 // it remember string was handled above.
2314 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
2315 (in_sig_bt[j_arg] == T_OBJECT &&
2316 out_sig_bt[c_arg] != T_INT &&
2317 out_sig_bt[c_arg] != T_LONG);
2318
2319 if (!useless) {
2320 __ movq(src_tmp, src.first()->as_Register());
2321 }
2322 }
2323 }
2324 }
2325 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
2326 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2327 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2328 }
2329 }
2330
2331 // Now that the volatile registers are safe, convert all the strings
2332 sid = 0;
2333
2334 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2335 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2336 if (out_sig_bt[c_arg] == T_ADDRESS) {
2337 // It's a string
2338 Address utf8_addr = Address(
2339 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size);
2340 // The first string we find might still be in the original java arg
2341 // register
2342
2343 VMReg src = in_regs[j_arg].first();
2344
2345 // We will need to eventually save the final argument to the trap
2346 // in the von-volatile location dedicated to src. This is the offset
2347 // from fp we will use.
2348 int src_off = src->is_reg() ?
2349 fp_offset[src->value()] : reg2offset_in(src);
2350
2351 // This is where the argument will eventually reside
2352 VMRegPair dst = out_regs[c_arg];
2353
2354 if (src->is_reg()) {
2355 if (sid == 1) {
2356 __ movq(c_rarg0, src->as_Register());
2357 } else {
2358 __ movq(c_rarg0, utf8_addr);
2359 }
2360 } else {
2361 // arg is still in the original location
2362 __ movq(c_rarg0, Address(rbp, reg2offset_in(src)));
2363 }
2364 Label done, convert;
2365
2366 // see if the oop is NULL
2367 __ testq(c_rarg0, c_rarg0);
2368 __ jcc(Assembler::notEqual, convert);
2369
2370 if (dst.first()->is_reg()) {
2371 // Save the ptr to utf string in the origina src loc or the tmp
2372 // dedicated to it
2373 __ movq(Address(rbp, src_off), c_rarg0);
2374 } else {
2375 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg0);
2376 }
2377 __ jmp(done);
2378
2379 __ bind(convert);
2380
2381 __ lea(c_rarg1, utf8_addr);
2382 if (dst.first()->is_reg()) {
2383 __ movq(Address(rbp, src_off), c_rarg1);
2384 } else {
2385 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg1);
2386 }
2387 // And do the conversion
2388 __ call(RuntimeAddress(
2389 CAST_FROM_FN_PTR(address, SharedRuntime::get_utf)));
2390
2391 __ bind(done);
2392 }
2393 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
2394 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2395 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2396 }
2397 }
2398 // The get_utf call killed all the c_arg registers
2399 live[c_rarg0->as_VMReg()->value()] = false;
2400 live[c_rarg1->as_VMReg()->value()] = false;
2401 live[c_rarg2->as_VMReg()->value()] = false;
2402 live[c_rarg3->as_VMReg()->value()] = false;
2403 live[c_rarg4->as_VMReg()->value()] = false;
2404 live[c_rarg5->as_VMReg()->value()] = false;
2405
2406 live[c_farg0->as_VMReg()->value()] = false;
2407 live[c_farg1->as_VMReg()->value()] = false;
2408 live[c_farg2->as_VMReg()->value()] = false;
2409 live[c_farg3->as_VMReg()->value()] = false;
2410 live[c_farg4->as_VMReg()->value()] = false;
2411 live[c_farg5->as_VMReg()->value()] = false;
2412 live[c_farg6->as_VMReg()->value()] = false;
2413 live[c_farg7->as_VMReg()->value()] = false;
2414 }
2415
2416 // Now we can finally move the register args to their desired locations
2417
2418 rax_is_zero = false;
2419
2420 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2421 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2422
2423 VMRegPair src = in_regs[j_arg];
2424 VMRegPair dst = out_regs[c_arg];
2425
2426 // Only need to look for args destined for the interger registers (since we
2427 // convert float/double args to look like int/long outbound)
2428 if (dst.first()->is_reg()) {
2429 Register r = dst.first()->as_Register();
2430
2431 // Check if the java arg is unsupported and thereofre useless
2432 bool useless = in_sig_bt[j_arg] == T_ARRAY ||
2433 (in_sig_bt[j_arg] == T_OBJECT &&
2434 out_sig_bt[c_arg] != T_INT &&
2435 out_sig_bt[c_arg] != T_ADDRESS &&
2436 out_sig_bt[c_arg] != T_LONG);
2437
2438
2439 // If we're going to kill an existing arg save it first
2440 if (live[dst.first()->value()]) {
2441 // you can't kill yourself
2442 if (src.first() != dst.first()) {
2443 __ movq(Address(rbp, fp_offset[dst.first()->value()]), r);
2444 }
2445 }
2446 if (src.first()->is_reg()) {
2447 if (live[src.first()->value()] ) {
2448 if (in_sig_bt[j_arg] == T_FLOAT) {
2449 __ movdl(r, src.first()->as_XMMRegister());
2450 } else if (in_sig_bt[j_arg] == T_DOUBLE) {
2451 __ movdq(r, src.first()->as_XMMRegister());
2452 } else if (r != src.first()->as_Register()) {
2453 if (!useless) {
2454 __ movq(r, src.first()->as_Register());
2455 }
2456 }
2457 } else {
2458 // If the arg is an oop type we don't support don't bother to store
2459 // it
2460 if (!useless) {
2461 if (in_sig_bt[j_arg] == T_DOUBLE ||
2462 in_sig_bt[j_arg] == T_LONG ||
2463 in_sig_bt[j_arg] == T_OBJECT ) {
2464 __ movq(r, Address(rbp, fp_offset[src.first()->value()]));
2465 } else {
2466 __ movl(r, Address(rbp, fp_offset[src.first()->value()]));
2467 }
2468 }
2469 }
2470 live[src.first()->value()] = false;
2471 } else if (!useless) {
2472 // full sized move even for int should be ok
2473 __ movq(r, Address(rbp, reg2offset_in(src.first())));
2474 }
2475
2476 // At this point r has the original java arg in the final location
2477 // (assuming it wasn't useless). If the java arg was an oop
2478 // we have a bit more to do
2479
2480 if (in_sig_bt[j_arg] == T_ARRAY || in_sig_bt[j_arg] == T_OBJECT ) {
2481 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2482 // need to unbox a one-word value
2483 Label skip;
2484 __ testq(r, r);
2485 __ jcc(Assembler::equal, skip);
2486 BasicType bt = out_sig_bt[c_arg];
2487 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2488 Address src1(r, box_offset);
2489 if ( bt == T_LONG ) {
2490 __ movq(r, src1);
2491 } else {
2492 __ movl(r, src1);
2493 }
2494 __ bind(skip);
2495
2496 } else if (out_sig_bt[c_arg] != T_ADDRESS) {
2497 // Convert the arg to NULL
2498 __ xorq(r, r);
2499 }
2500 }
2501
2502 // dst can longer be holding an input value
2503 live[dst.first()->value()] = false;
2504 }
2505 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) {
2506 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2507 ++c_arg; // skip over T_VOID to keep the loop indices in sync
2508 }
2509 }
2510
2511
2512 // Ok now we are done. Need to place the nop that dtrace wants in order to
2513 // patch in the trap
2514 int patch_offset = ((intptr_t)__ pc()) - start;
2515
2516 __ nop();
2517
2518
2519 // Return
2520
2521 __ leave();
2522 __ ret(0);
2523
2524 __ flush();
2525
2526 nmethod *nm = nmethod::new_dtrace_nmethod(
2527 method, masm->code(), vep_offset, patch_offset, frame_complete,
2528 stack_slots / VMRegImpl::slots_per_word);
2529 return nm;
2530
2531 }
2532
2533 #endif // HAVE_DTRACE_H
2534
2535 // this function returns the adjust size (in number of words) to a c2i adapter
2536 // activation for use during deoptimization
2537 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) {
2538 return (callee_locals - callee_parameters) * Interpreter::stackElementWords();
2539 }
2540
2541
2542 uint SharedRuntime::out_preserve_stack_slots() {
2543 return 0;
2544 }
2545
2546
2547 //------------------------------generate_deopt_blob----------------------------
2548 void SharedRuntime::generate_deopt_blob() {
2549 // Allocate space for the code
2550 ResourceMark rm;
2551 // Setup code generation tools
2552 CodeBuffer buffer("deopt_blob", 2048, 1024);
2553 MacroAssembler* masm = new MacroAssembler(&buffer);
2554 int frame_size_in_words;
2555 OopMap* map = NULL;
2556 OopMapSet *oop_maps = new OopMapSet();
2557
2558 // -------------
2559 // This code enters when returning to a de-optimized nmethod. A return
2560 // address has been pushed on the the stack, and return values are in
2561 // registers.
2562 // If we are doing a normal deopt then we were called from the patched
2563 // nmethod from the point we returned to the nmethod. So the return
2564 // address on the stack is wrong by NativeCall::instruction_size
2565 // We will adjust the value so it looks like we have the original return
2566 // address on the stack (like when we eagerly deoptimized).
2567 // In the case of an exception pending when deoptimizing, we enter
2568 // with a return address on the stack that points after the call we patched
2569 // into the exception handler. We have the following register state from,
2570 // e.g., the forward exception stub (see stubGenerator_x86_64.cpp).
2571 // rax: exception oop
2572 // rbx: exception handler
2573 // rdx: throwing pc
2574 // So in this case we simply jam rdx into the useless return address and
2575 // the stack looks just like we want.
2576 //
2577 // At this point we need to de-opt. We save the argument return
2578 // registers. We call the first C routine, fetch_unroll_info(). This
2579 // routine captures the return values and returns a structure which
2580 // describes the current frame size and the sizes of all replacement frames.
2581 // The current frame is compiled code and may contain many inlined
2582 // functions, each with their own JVM state. We pop the current frame, then
2583 // push all the new frames. Then we call the C routine unpack_frames() to
2584 // populate these frames. Finally unpack_frames() returns us the new target
2585 // address. Notice that callee-save registers are BLOWN here; they have
2586 // already been captured in the vframeArray at the time the return PC was
2587 // patched.
2588 address start = __ pc();
2589 Label cont;
2590
2591 // Prolog for non exception case!
2592
2593 // Save everything in sight.
2594 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2595
2596 // Normal deoptimization. Save exec mode for unpack_frames.
2597 __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved
2598 __ jmp(cont);
2599
2600 int reexecute_offset = __ pc() - start;
2601
2602 // Reexecute case
2603 // return address is the pc describes what bci to do re-execute at
2604
2605 // No need to update map as each call to save_live_registers will produce identical oopmap
2606 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2607
2608 __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved
2609 __ jmp(cont);
2610
2611 int exception_offset = __ pc() - start;
2612
2613 // Prolog for exception case
2614
2615 // all registers are dead at this entry point, except for rax, and
2616 // rdx which contain the exception oop and exception pc
2617 // respectively. Set them in TLS and fall thru to the
2618 // unpack_with_exception_in_tls entry point.
2619
2620 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
2621 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), rax);
2622
2623 int exception_in_tls_offset = __ pc() - start;
2624
2625 // new implementation because exception oop is now passed in JavaThread
2626
2627 // Prolog for exception case
2628 // All registers must be preserved because they might be used by LinearScan
2629 // Exceptiop oop and throwing PC are passed in JavaThread
2630 // tos: stack at point of call to method that threw the exception (i.e. only
2631 // args are on the stack, no return address)
2632
2633 // make room on stack for the return address
2634 // It will be patched later with the throwing pc. The correct value is not
2635 // available now because loading it from memory would destroy registers.
2636 __ push(0);
2637
2638 // Save everything in sight.
2639 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2640
2641 // Now it is safe to overwrite any register
2642
2643 // Deopt during an exception. Save exec mode for unpack_frames.
2644 __ movl(r14, Deoptimization::Unpack_exception); // callee-saved
2645
2646 // load throwing pc from JavaThread and patch it as the return address
2647 // of the current frame. Then clear the field in JavaThread
2648
2649 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
2650 __ movptr(Address(rbp, wordSize), rdx);
2651 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
2652
2653 #ifdef ASSERT
2654 // verify that there is really an exception oop in JavaThread
2655 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
2656 __ verify_oop(rax);
2657
2658 // verify that there is no pending exception
2659 Label no_pending_exception;
2660 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
2661 __ testptr(rax, rax);
2662 __ jcc(Assembler::zero, no_pending_exception);
2663 __ stop("must not have pending exception here");
2664 __ bind(no_pending_exception);
2665 #endif
2666
2667 __ bind(cont);
2668
2669 // Call C code. Need thread and this frame, but NOT official VM entry
2670 // crud. We cannot block on this call, no GC can happen.
2671 //
2672 // UnrollBlock* fetch_unroll_info(JavaThread* thread)
2673
2674 // fetch_unroll_info needs to call last_java_frame().
2675
2676 __ set_last_Java_frame(noreg, noreg, NULL);
2677 #ifdef ASSERT
2678 { Label L;
2679 __ cmpptr(Address(r15_thread,
2680 JavaThread::last_Java_fp_offset()),
2681 (int32_t)0);
2682 __ jcc(Assembler::equal, L);
2683 __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared");
2684 __ bind(L);
2685 }
2686 #endif // ASSERT
2687 __ mov(c_rarg0, r15_thread);
2688 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info)));
2689
2690 // Need to have an oopmap that tells fetch_unroll_info where to
2691 // find any register it might need.
2692 oop_maps->add_gc_map(__ pc() - start, map);
2693
2694 __ reset_last_Java_frame(false, false);
2695
2696 // Load UnrollBlock* into rdi
2697 __ mov(rdi, rax);
2698
2699 Label noException;
2700 __ cmpl(r14, Deoptimization::Unpack_exception); // Was exception pending?
2701 __ jcc(Assembler::notEqual, noException);
2702 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
2703 // QQQ this is useless it was NULL above
2704 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
2705 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
2706 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
2707
2708 __ verify_oop(rax);
2709
2710 // Overwrite the result registers with the exception results.
2711 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
2712 // I think this is useless
2713 __ movptr(Address(rsp, RegisterSaver::rdx_offset_in_bytes()), rdx);
2714
2715 __ bind(noException);
2716
2717 // Only register save data is on the stack.
2718 // Now restore the result registers. Everything else is either dead
2719 // or captured in the vframeArray.
2720 RegisterSaver::restore_result_registers(masm);
2721
2722 // All of the register save area has been popped of the stack. Only the
2723 // return address remains.
2724
2725 // Pop all the frames we must move/replace.
2726 //
2727 // Frame picture (youngest to oldest)
2728 // 1: self-frame (no frame link)
2729 // 2: deopting frame (no frame link)
2730 // 3: caller of deopting frame (could be compiled/interpreted).
2731 //
2732 // Note: by leaving the return address of self-frame on the stack
2733 // and using the size of frame 2 to adjust the stack
2734 // when we are done the return to frame 3 will still be on the stack.
2735
2736 // Pop deoptimized frame
2737 __ movl(rcx, Address(rdi, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
2738 __ addptr(rsp, rcx);
2739
2740 // rsp should be pointing at the return address to the caller (3)
2741
2742 // Stack bang to make sure there's enough room for these interpreter frames.
2743 if (UseStackBanging) {
2744 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
2745 __ bang_stack_size(rbx, rcx);
2746 }
2747
2748 // Load address of array of frame pcs into rcx
2749 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
2750
2751 // Trash the old pc
2752 __ addptr(rsp, wordSize);
2753
2754 // Load address of array of frame sizes into rsi
2755 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
2756
2757 // Load counter into rdx
2758 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
2759
2760 // Pick up the initial fp we should save
2761 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_fp_offset_in_bytes()));
2762
2763 // Now adjust the caller's stack to make up for the extra locals
2764 // but record the original sp so that we can save it in the skeletal interpreter
2765 // frame and the stack walking of interpreter_sender will get the unextended sp
2766 // value and not the "real" sp value.
2767
2768 const Register sender_sp = r8;
2769
2770 __ mov(sender_sp, rsp);
2771 __ movl(rbx, Address(rdi,
2772 Deoptimization::UnrollBlock::
2773 caller_adjustment_offset_in_bytes()));
2774 __ subptr(rsp, rbx);
2775
2776 // Push interpreter frames in a loop
2777 Label loop;
2778 __ bind(loop);
2779 __ movptr(rbx, Address(rsi, 0)); // Load frame size
2780 #ifdef CC_INTERP
2781 __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and
2782 #ifdef ASSERT
2783 __ push(0xDEADDEAD); // Make a recognizable pattern
2784 __ push(0xDEADDEAD);
2785 #else /* ASSERT */
2786 __ subptr(rsp, 2*wordSize); // skip the "static long no_param"
2787 #endif /* ASSERT */
2788 #else
2789 __ subptr(rbx, 2*wordSize); // We'll push pc and ebp by hand
2790 #endif // CC_INTERP
2791 __ pushptr(Address(rcx, 0)); // Save return address
2792 __ enter(); // Save old & set new ebp
2793 __ subptr(rsp, rbx); // Prolog
2794 #ifdef CC_INTERP
2795 __ movptr(Address(rbp,
2796 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
2797 sender_sp); // Make it walkable
2798 #else /* CC_INTERP */
2799 // This value is corrected by layout_activation_impl
2800 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
2801 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), sender_sp); // Make it walkable
2802 #endif /* CC_INTERP */
2803 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
2804 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
2805 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
2806 __ decrementl(rdx); // Decrement counter
2807 __ jcc(Assembler::notZero, loop);
2808 __ pushptr(Address(rcx, 0)); // Save final return address
2809
2810 // Re-push self-frame
2811 __ enter(); // Save old & set new ebp
2812
2813 // Allocate a full sized register save area.
2814 // Return address and rbp are in place, so we allocate two less words.
2815 __ subptr(rsp, (frame_size_in_words - 2) * wordSize);
2816
2817 // Restore frame locals after moving the frame
2818 __ movdbl(Address(rsp, RegisterSaver::xmm0_offset_in_bytes()), xmm0);
2819 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
2820
2821 // Call C code. Need thread but NOT official VM entry
2822 // crud. We cannot block on this call, no GC can happen. Call should
2823 // restore return values to their stack-slots with the new SP.
2824 //
2825 // void Deoptimization::unpack_frames(JavaThread* thread, int exec_mode)
2826
2827 // Use rbp because the frames look interpreted now
2828 __ set_last_Java_frame(noreg, rbp, NULL);
2829
2830 __ mov(c_rarg0, r15_thread);
2831 __ movl(c_rarg1, r14); // second arg: exec_mode
2832 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
2833
2834 // Set an oopmap for the call site
2835 oop_maps->add_gc_map(__ pc() - start,
2836 new OopMap( frame_size_in_words, 0 ));
2837
2838 __ reset_last_Java_frame(true, false);
2839
2840 // Collect return values
2841 __ movdbl(xmm0, Address(rsp, RegisterSaver::xmm0_offset_in_bytes()));
2842 __ movptr(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes()));
2843 // I think this is useless (throwing pc?)
2844 __ movptr(rdx, Address(rsp, RegisterSaver::rdx_offset_in_bytes()));
2845
2846 // Pop self-frame.
2847 __ leave(); // Epilog
2848
2849 // Jump to interpreter
2850 __ ret(0);
2851
2852 // Make sure all code is generated
2853 masm->flush();
2854
2855 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words);
2856 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
2857 }
2858
2859 #ifdef COMPILER2
2860 //------------------------------generate_uncommon_trap_blob--------------------
2861 void SharedRuntime::generate_uncommon_trap_blob() {
2862 // Allocate space for the code
2863 ResourceMark rm;
2864 // Setup code generation tools
2865 CodeBuffer buffer("uncommon_trap_blob", 2048, 1024);
2866 MacroAssembler* masm = new MacroAssembler(&buffer);
2867
2868 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
2869
2870 address start = __ pc();
2871
2872 // Push self-frame. We get here with a return address on the
2873 // stack, so rsp is 8-byte aligned until we allocate our frame.
2874 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog!
2875
2876 // No callee saved registers. rbp is assumed implicitly saved
2877 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
2878
2879 // compiler left unloaded_class_index in j_rarg0 move to where the
2880 // runtime expects it.
2881 __ movl(c_rarg1, j_rarg0);
2882
2883 __ set_last_Java_frame(noreg, noreg, NULL);
2884
2885 // Call C code. Need thread but NOT official VM entry
2886 // crud. We cannot block on this call, no GC can happen. Call should
2887 // capture callee-saved registers as well as return values.
2888 // Thread is in rdi already.
2889 //
2890 // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index);
2891
2892 __ mov(c_rarg0, r15_thread);
2893 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
2894
2895 // Set an oopmap for the call site
2896 OopMapSet* oop_maps = new OopMapSet();
2897 OopMap* map = new OopMap(SimpleRuntimeFrame::framesize, 0);
2898
2899 // location of rbp is known implicitly by the frame sender code
2900
2901 oop_maps->add_gc_map(__ pc() - start, map);
2902
2903 __ reset_last_Java_frame(false, false);
2904
2905 // Load UnrollBlock* into rdi
2906 __ mov(rdi, rax);
2907
2908 // Pop all the frames we must move/replace.
2909 //
2910 // Frame picture (youngest to oldest)
2911 // 1: self-frame (no frame link)
2912 // 2: deopting frame (no frame link)
2913 // 3: caller of deopting frame (could be compiled/interpreted).
2914
2915 // Pop self-frame. We have no frame, and must rely only on rax and rsp.
2916 __ addptr(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog!
2917
2918 // Pop deoptimized frame (int)
2919 __ movl(rcx, Address(rdi,
2920 Deoptimization::UnrollBlock::
2921 size_of_deoptimized_frame_offset_in_bytes()));
2922 __ addptr(rsp, rcx);
2923
2924 // rsp should be pointing at the return address to the caller (3)
2925
2926 // Stack bang to make sure there's enough room for these interpreter frames.
2927 if (UseStackBanging) {
2928 __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
2929 __ bang_stack_size(rbx, rcx);
2930 }
2931
2932 // Load address of array of frame pcs into rcx (address*)
2933 __ movptr(rcx,
2934 Address(rdi,
2935 Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
2936
2937 // Trash the return pc
2938 __ addptr(rsp, wordSize);
2939
2940 // Load address of array of frame sizes into rsi (intptr_t*)
2941 __ movptr(rsi, Address(rdi,
2942 Deoptimization::UnrollBlock::
2943 frame_sizes_offset_in_bytes()));
2944
2945 // Counter
2946 __ movl(rdx, Address(rdi,
2947 Deoptimization::UnrollBlock::
2948 number_of_frames_offset_in_bytes())); // (int)
2949
2950 // Pick up the initial fp we should save
2951 __ movptr(rbp,
2952 Address(rdi,
2953 Deoptimization::UnrollBlock::initial_fp_offset_in_bytes()));
2954
2955 // Now adjust the caller's stack to make up for the extra locals but
2956 // record the original sp so that we can save it in the skeletal
2957 // interpreter frame and the stack walking of interpreter_sender
2958 // will get the unextended sp value and not the "real" sp value.
2959
2960 const Register sender_sp = r8;
2961
2962 __ mov(sender_sp, rsp);
2963 __ movl(rbx, Address(rdi,
2964 Deoptimization::UnrollBlock::
2965 caller_adjustment_offset_in_bytes())); // (int)
2966 __ subptr(rsp, rbx);
2967
2968 // Push interpreter frames in a loop
2969 Label loop;
2970 __ bind(loop);
2971 __ movptr(rbx, Address(rsi, 0)); // Load frame size
2972 __ subptr(rbx, 2 * wordSize); // We'll push pc and rbp by hand
2973 __ pushptr(Address(rcx, 0)); // Save return address
2974 __ enter(); // Save old & set new rbp
2975 __ subptr(rsp, rbx); // Prolog
2976 #ifdef CC_INTERP
2977 __ movptr(Address(rbp,
2978 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))),
2979 sender_sp); // Make it walkable
2980 #else // CC_INTERP
2981 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize),
2982 sender_sp); // Make it walkable
2983 // This value is corrected by layout_activation_impl
2984 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
2985 #endif // CC_INTERP
2986 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
2987 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
2988 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
2989 __ decrementl(rdx); // Decrement counter
2990 __ jcc(Assembler::notZero, loop);
2991 __ pushptr(Address(rcx, 0)); // Save final return address
2992
2993 // Re-push self-frame
2994 __ enter(); // Save old & set new rbp
2995 __ subptr(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt);
2996 // Prolog
2997
2998 // Use rbp because the frames look interpreted now
2999 __ set_last_Java_frame(noreg, rbp, NULL);
3000
3001 // Call C code. Need thread but NOT official VM entry
3002 // crud. We cannot block on this call, no GC can happen. Call should
3003 // restore return values to their stack-slots with the new SP.
3004 // Thread is in rdi already.
3005 //
3006 // BasicType unpack_frames(JavaThread* thread, int exec_mode);
3007
3008 __ mov(c_rarg0, r15_thread);
3009 __ movl(c_rarg1, Deoptimization::Unpack_uncommon_trap);
3010 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3011
3012 // Set an oopmap for the call site
3013 oop_maps->add_gc_map(__ pc() - start, new OopMap(SimpleRuntimeFrame::framesize, 0));
3014
3015 __ reset_last_Java_frame(true, false);
3016
3017 // Pop self-frame.
3018 __ leave(); // Epilog
3019
3020 // Jump to interpreter
3021 __ ret(0);
3022
3023 // Make sure all code is generated
3024 masm->flush();
3025
3026 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps,
3027 SimpleRuntimeFrame::framesize >> 1);
3028 }
3029 #endif // COMPILER2
3030
3031
3032 //------------------------------generate_handler_blob------
3033 //
3034 // Generate a special Compile2Runtime blob that saves all registers,
3035 // and setup oopmap.
3036 //
3037 static SafepointBlob* generate_handler_blob(address call_ptr, bool cause_return) {
3038 assert(StubRoutines::forward_exception_entry() != NULL,
3039 "must be generated before");
3040
3041 ResourceMark rm;
3042 OopMapSet *oop_maps = new OopMapSet();
3043 OopMap* map;
3044
3045 // Allocate space for the code. Setup code generation tools.
3046 CodeBuffer buffer("handler_blob", 2048, 1024);
3047 MacroAssembler* masm = new MacroAssembler(&buffer);
3048
3049 address start = __ pc();
3050 address call_pc = NULL;
3051 int frame_size_in_words;
3052
3053 // Make room for return address (or push it again)
3054 if (!cause_return) {
3055 __ push(rbx);
3056 }
3057
3058 // Save registers, fpu state, and flags
3059 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3060
3061 // The following is basically a call_VM. However, we need the precise
3062 // address of the call in order to generate an oopmap. Hence, we do all the
3063 // work outselves.
3064
3065 __ set_last_Java_frame(noreg, noreg, NULL);
3066
3067 // The return address must always be correct so that frame constructor never
3068 // sees an invalid pc.
3069
3070 if (!cause_return) {
3071 // overwrite the dummy value we pushed on entry
3072 __ movptr(c_rarg0, Address(r15_thread, JavaThread::saved_exception_pc_offset()));
3073 __ movptr(Address(rbp, wordSize), c_rarg0);
3074 }
3075
3076 // Do the call
3077 __ mov(c_rarg0, r15_thread);
3078 __ call(RuntimeAddress(call_ptr));
3079
3080 // Set an oopmap for the call site. This oopmap will map all
3081 // oop-registers and debug-info registers as callee-saved. This
3082 // will allow deoptimization at this safepoint to find all possible
3083 // debug-info recordings, as well as let GC find all oops.
3084
3085 oop_maps->add_gc_map( __ pc() - start, map);
3086
3087 Label noException;
3088
3089 __ reset_last_Java_frame(false, false);
3090
3091 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3092 __ jcc(Assembler::equal, noException);
3093
3094 // Exception pending
3095
3096 RegisterSaver::restore_live_registers(masm);
3097
3098 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3099
3100 // No exception case
3101 __ bind(noException);
3102
3103 // Normal exit, restore registers and exit.
3104 RegisterSaver::restore_live_registers(masm);
3105
3106 __ ret(0);
3107
3108 // Make sure all code is generated
3109 masm->flush();
3110
3111 // Fill-out other meta info
3112 return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words);
3113 }
3114
3115 //
3116 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
3117 //
3118 // Generate a stub that calls into vm to find out the proper destination
3119 // of a java call. All the argument registers are live at this point
3120 // but since this is generic code we don't know what they are and the caller
3121 // must do any gc of the args.
3122 //
3123 static RuntimeStub* generate_resolve_blob(address destination, const char* name) {
3124 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3125
3126 // allocate space for the code
3127 ResourceMark rm;
3128
3129 CodeBuffer buffer(name, 1000, 512);
3130 MacroAssembler* masm = new MacroAssembler(&buffer);
3131
3132 int frame_size_in_words;
3133
3134 OopMapSet *oop_maps = new OopMapSet();
3135 OopMap* map = NULL;
3136
3137 int start = __ offset();
3138
3139 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3140
3141 int frame_complete = __ offset();
3142
3143 __ set_last_Java_frame(noreg, noreg, NULL);
3144
3145 __ mov(c_rarg0, r15_thread);
3146
3147 __ call(RuntimeAddress(destination));
3148
3149
3150 // Set an oopmap for the call site.
3151 // We need this not only for callee-saved registers, but also for volatile
3152 // registers that the compiler might be keeping live across a safepoint.
3153
3154 oop_maps->add_gc_map( __ offset() - start, map);
3155
3156 // rax contains the address we are going to jump to assuming no exception got installed
3157
3158 // clear last_Java_sp
3159 __ reset_last_Java_frame(false, false);
3160 // check for pending exceptions
3161 Label pending;
3162 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3163 __ jcc(Assembler::notEqual, pending);
3164
3165 // get the returned methodOop
3166 __ movptr(rbx, Address(r15_thread, JavaThread::vm_result_offset()));
3167 __ movptr(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx);
3168
3169 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3170
3171 RegisterSaver::restore_live_registers(masm);
3172
3173 // We are back the the original state on entry and ready to go.
3174
3175 __ jmp(rax);
3176
3177 // Pending exception after the safepoint
3178
3179 __ bind(pending);
3180
3181 RegisterSaver::restore_live_registers(masm);
3182
3183 // exception pending => remove activation and forward to exception handler
3184
3185 __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD);
3186
3187 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
3188 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3189
3190 // -------------
3191 // make sure all code is generated
3192 masm->flush();
3193
3194 // return the blob
3195 // frame_size_words or bytes??
3196 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_in_words, oop_maps, true);
3197 }
3198
3199
3200 void SharedRuntime::generate_stubs() {
3201
3202 _wrong_method_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::handle_wrong_method),
3203 "wrong_method_stub");
3204 _ic_miss_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::handle_wrong_method_ic_miss),
3205 "ic_miss_stub");
3206 _resolve_opt_virtual_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_opt_virtual_call_C),
3207 "resolve_opt_virtual_call");
3208
3209 _resolve_virtual_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_virtual_call_C),
3210 "resolve_virtual_call");
3211
3212 _resolve_static_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_static_call_C),
3213 "resolve_static_call");
3214 _polling_page_safepoint_handler_blob =
3215 generate_handler_blob(CAST_FROM_FN_PTR(address,
3216 SafepointSynchronize::handle_polling_page_exception), false);
3217
3218 _polling_page_return_handler_blob =
3219 generate_handler_blob(CAST_FROM_FN_PTR(address,
3220 SafepointSynchronize::handle_polling_page_exception), true);
3221
3222 generate_deopt_blob();
3223
3224 #ifdef COMPILER2
3225 generate_uncommon_trap_blob();
3226 #endif // COMPILER2
3227 }
3228
3229
3230 #ifdef COMPILER2
3231 // This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame
3232 //
3233 //------------------------------generate_exception_blob---------------------------
3234 // creates exception blob at the end
3235 // Using exception blob, this code is jumped from a compiled method.
3236 // (see emit_exception_handler in x86_64.ad file)
3237 //
3238 // Given an exception pc at a call we call into the runtime for the
3239 // handler in this method. This handler might merely restore state
3240 // (i.e. callee save registers) unwind the frame and jump to the
3241 // exception handler for the nmethod if there is no Java level handler
3242 // for the nmethod.
3243 //
3244 // This code is entered with a jmp.
3245 //
3246 // Arguments:
3247 // rax: exception oop
3248 // rdx: exception pc
3249 //
3250 // Results:
3251 // rax: exception oop
3252 // rdx: exception pc in caller or ???
3253 // destination: exception handler of caller
3254 //
3255 // Note: the exception pc MUST be at a call (precise debug information)
3256 // Registers rax, rdx, rcx, rsi, rdi, r8-r11 are not callee saved.
3257 //
3258
3259 void OptoRuntime::generate_exception_blob() {
3260 assert(!OptoRuntime::is_callee_saved_register(RDX_num), "");
3261 assert(!OptoRuntime::is_callee_saved_register(RAX_num), "");
3262 assert(!OptoRuntime::is_callee_saved_register(RCX_num), "");
3263
3264 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
3265
3266 // Allocate space for the code
3267 ResourceMark rm;
3268 // Setup code generation tools
3269 CodeBuffer buffer("exception_blob", 2048, 1024);
3270 MacroAssembler* masm = new MacroAssembler(&buffer);
3271
3272
3273 address start = __ pc();
3274
3275 // Exception pc is 'return address' for stack walker
3276 __ push(rdx);
3277 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog
3278
3279 // Save callee-saved registers. See x86_64.ad.
3280
3281 // rbp is an implicitly saved callee saved register (i.e. the calling
3282 // convention will save restore it in prolog/epilog) Other than that
3283 // there are no callee save registers now that adapter frames are gone.
3284
3285 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
3286
3287 // Store exception in Thread object. We cannot pass any arguments to the
3288 // handle_exception call, since we do not want to make any assumption
3289 // about the size of the frame where the exception happened in.
3290 // c_rarg0 is either rdi (Linux) or rcx (Windows).
3291 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()),rax);
3292 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
3293
3294 // This call does all the hard work. It checks if an exception handler
3295 // exists in the method.
3296 // If so, it returns the handler address.
3297 // If not, it prepares for stack-unwinding, restoring the callee-save
3298 // registers of the frame being removed.
3299 //
3300 // address OptoRuntime::handle_exception_C(JavaThread* thread)
3301
3302 __ set_last_Java_frame(noreg, noreg, NULL);
3303 __ mov(c_rarg0, r15_thread);
3304 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C)));
3305
3306 // Set an oopmap for the call site. This oopmap will only be used if we
3307 // are unwinding the stack. Hence, all locations will be dead.
3308 // Callee-saved registers will be the same as the frame above (i.e.,
3309 // handle_exception_stub), since they were restored when we got the
3310 // exception.
3311
3312 OopMapSet* oop_maps = new OopMapSet();
3313
3314 oop_maps->add_gc_map( __ pc()-start, new OopMap(SimpleRuntimeFrame::framesize, 0));
3315
3316 __ reset_last_Java_frame(false, false);
3317
3318 // Restore callee-saved registers
3319
3320 // rbp is an implicitly saved callee saved register (i.e. the calling
3321 // convention will save restore it in prolog/epilog) Other than that
3322 // there are no callee save registers no that adapter frames are gone.
3323
3324 __ movptr(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt));
3325
3326 __ addptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog
3327 __ pop(rdx); // No need for exception pc anymore
3328
3329 // rax: exception handler
3330
3331 // Restore SP from BP if the exception PC is a MethodHandle call.
3332 __ cmpl(Address(r15_thread, JavaThread::is_method_handle_exception_offset()), 0);
3333 __ cmovptr(Assembler::notEqual, rsp, rbp);
3334
3335 // We have a handler in rax (could be deopt blob).
3336 __ mov(r8, rax);
3337
3338 // Get the exception oop
3339 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
3340 // Get the exception pc in case we are deoptimized
3341 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
3342 #ifdef ASSERT
3343 __ movptr(Address(r15_thread, JavaThread::exception_handler_pc_offset()), (int)NULL_WORD);
3344 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int)NULL_WORD);
3345 #endif
3346 // Clear the exception oop so GC no longer processes it as a root.
3347 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int)NULL_WORD);
3348
3349 // rax: exception oop
3350 // r8: exception handler
3351 // rdx: exception pc
3352 // Jump to handler
3353
3354 __ jmp(r8);
3355
3356 // Make sure all code is generated
3357 masm->flush();
3358
3359 // Set exception blob
3360 _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1);
3361 }
3362 #endif // COMPILER2