103   for (DUIterator i = val->outs(); val->has_out(i); i++) {
 104     Node *m = val->out(i);
 105     if( !m->is_Mach() ) continue;
 106     MachNode *mach = m->as_Mach();
 107     was_store = false;
 108     switch( mach->ideal_Opcode() ) {
 109     case Op_LoadB:
 110     case Op_LoadUS:
 111     case Op_LoadD:
 112     case Op_LoadF:
 113     case Op_LoadI:
 114     case Op_LoadL:
 115     case Op_LoadP:
 116     case Op_LoadN:
 117     case Op_LoadS:
 118     case Op_LoadKlass:
 119     case Op_LoadNKlass:
 120     case Op_LoadRange:
 121     case Op_LoadD_unaligned:
 122     case Op_LoadL_unaligned:

 123       break;
 124     case Op_StoreB:
 125     case Op_StoreC:
 126     case Op_StoreCM:
 127     case Op_StoreD:
 128     case Op_StoreF:
 129     case Op_StoreI:
 130     case Op_StoreL:
 131     case Op_StoreP:
 132     case Op_StoreN:
 133       was_store = true;         // Memory op is a store op
 134       // Stores will have their address in slot 2 (memory in slot 1).
 135       // If the value being nul-checked is in another slot, it means we
 136       // are storing the checked value, which does NOT check the value!
 137       if( mach->in(2) != val ) continue;
 138       break;                    // Found a memory op?
 139     case Op_StrComp:
 140     case Op_StrEquals:
 141     case Op_StrIndexOf:
 142     case Op_AryEq:
 143       // Not a legit memory op for implicit null check regardless of
 144       // embedded loads
 145       continue;
 146     default:                    // Also check for embedded loads
 147       if( !mach->needs_anti_dependence_check() )
 148         continue;               // Not an memory op; skip it













 149       break;
 150     }
 151     // check if the offset is not too high for implicit exception
 152     {
 153       intptr_t offset = 0;
 154       const TypePtr *adr_type = NULL;  // Do not need this return value here
 155       const Node* base = mach->get_base_and_disp(offset, adr_type);
 156       if (base == NULL || base == NodeSentinel) {
 157         // Narrow oop address doesn't have base, only index
 158         if( val->bottom_type()->isa_narrowoop() &&
 159             MacroAssembler::needs_explicit_null_check(offset) )
 160           continue;             // Give up if offset is beyond page size
 161         // cannot reason about it; is probably not implicit null exception
 162       } else {
 163         const TypePtr* tptr;
 164         if (UseCompressedOops && Universe::narrow_oop_shift() == 0) {
 165           // 32-bits narrow oop can be the base of address expressions
 166           tptr = base->bottom_type()->make_ptr();
 167         } else {
 168           // only regular oops are expected here

 103   for (DUIterator i = val->outs(); val->has_out(i); i++) {
 104     Node *m = val->out(i);
 105     if( !m->is_Mach() ) continue;
 106     MachNode *mach = m->as_Mach();
 107     was_store = false;
 108     switch( mach->ideal_Opcode() ) {
 109     case Op_LoadB:
 110     case Op_LoadUS:
 111     case Op_LoadD:
 112     case Op_LoadF:
 113     case Op_LoadI:
 114     case Op_LoadL:
 115     case Op_LoadP:
 116     case Op_LoadN:
 117     case Op_LoadS:
 118     case Op_LoadKlass:
 119     case Op_LoadNKlass:
 120     case Op_LoadRange:
 121     case Op_LoadD_unaligned:
 122     case Op_LoadL_unaligned:
 123       assert(mach->in(2) == val, "should be address");
 124       break;
 125     case Op_StoreB:
 126     case Op_StoreC:
 127     case Op_StoreCM:
 128     case Op_StoreD:
 129     case Op_StoreF:
 130     case Op_StoreI:
 131     case Op_StoreL:
 132     case Op_StoreP:
 133     case Op_StoreN:
 134       was_store = true;         // Memory op is a store op
 135       // Stores will have their address in slot 2 (memory in slot 1).
 136       // If the value being nul-checked is in another slot, it means we
 137       // are storing the checked value, which does NOT check the value!
 138       if( mach->in(2) != val ) continue;
 139       break;                    // Found a memory op?
 140     case Op_StrComp:
 141     case Op_StrEquals:
 142     case Op_StrIndexOf:
 143     case Op_AryEq:
 144       // Not a legit memory op for implicit null check regardless of
 145       // embedded loads
 146       continue;
 147     default:                    // Also check for embedded loads
 148       if( !mach->needs_anti_dependence_check() )
 149         continue;               // Not an memory op; skip it
 150       {
 151         // Check that value is used in memory address.
 152         Node* base;
 153         Node* index;
 154         const MachOper* oper = mach->memory_inputs(base, index);
 155         if (oper == NULL || oper == (MachOper*)-1)
 156           continue;             // Not an memory op; skip it
 157         if (val == base ||
 158             val == index && val->bottom_type()->isa_narrowoop())
 159           break;                // Found it
 160         else
 161           continue;             // Skip it
 162       }
 163       break;
 164     }
 165     // check if the offset is not too high for implicit exception
 166     {
 167       intptr_t offset = 0;
 168       const TypePtr *adr_type = NULL;  // Do not need this return value here
 169       const Node* base = mach->get_base_and_disp(offset, adr_type);
 170       if (base == NULL || base == NodeSentinel) {
 171         // Narrow oop address doesn't have base, only index
 172         if( val->bottom_type()->isa_narrowoop() &&
 173             MacroAssembler::needs_explicit_null_check(offset) )
 174           continue;             // Give up if offset is beyond page size
 175         // cannot reason about it; is probably not implicit null exception
 176       } else {
 177         const TypePtr* tptr;
 178         if (UseCompressedOops && Universe::narrow_oop_shift() == 0) {
 179           // 32-bits narrow oop can be the base of address expressions
 180           tptr = base->bottom_type()->make_ptr();
 181         } else {
 182           // only regular oops are expected here